LLVM/project 8d2d8bellvm/include/llvm/IR MDBuilder.h, llvm/lib/IR MDBuilder.cpp

[profcheck] Expose likely/unlikely weights as constants in MDBuilder (#183252)

Define `kLikelyBranchWeight` and `kUnlikelyBranchWeight` as static
constexpr members in MDBuilder.h and use them in
createLikelyBranchWeights and createUnlikelyBranchWeights. This makes
the weights used for likely/unlikely branches more discoverable and
reusable.

Co-authored-by: Jin Huang <jingold at google.com>
DeltaFile
+14-0llvm/include/llvm/IR/MDBuilder.h
+2-2llvm/lib/IR/MDBuilder.cpp
+16-22 files

LLVM/project 19128bfutils/bazel/llvm-project-overlay/libc BUILD.bazel libc_build_rules.bzl

[bazel][libc] Add some deps for layering_check (#183235)

This adds a whole bunch of deps to get things _mostly_ building w/
`layering_check` enabled. It does not yet enable `layering_check`.

I used some tools to add deps to all these targets that break when
enabling the layering check feature, and a few things were added in
between when I ran the script and where trunk is at now. Since this is a
large change, I plan to do a second (and possibly third) pass later to
catch those new changes, at which point it would be safer to actually
enable `layering_check` for this package.
DeltaFile
+1,288-141utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+5-1utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
+1,293-1422 files

LLVM/project a450e16clang/lib/CodeGen/TargetBuiltins ARM.cpp

[clang][ARM] Refactor argument handling in `EmitAArch64BuiltinExpr` (3/N) (NFC)

Remove the outstanding calls to `EmitScalarExpr` in
`EmitAArch64BuiltinExpr` that are no longer required.

This is a follow-up for #181794 and #181974 - please refer to that PR
for more context.
DeltaFile
+32-65clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+32-651 files

LLVM/project d46089dclang/docs ReleaseNotes.rst, clang/lib/AST ASTContext.cpp

[clang] allow canonicalizing assumed template names

Assumed template names are part of error recovery and encode just a
declaration name, making them always canonical. This patch allows
them to be canonicalized, which is trivial.

Fixes #183075
DeltaFile
+13-0clang/test/SemaTemplate/GH183075.cpp
+5-2clang/lib/AST/ASTContext.cpp
+1-0clang/docs/ReleaseNotes.rst
+19-23 files

LLVM/project 5eb307eclang/include/clang/AST Decl.h, clang/lib/AST Decl.cpp

[clang][TypePrinter][NFC] Extract logic that handles AnonymousTagNameStyle::SourceLocation into helper function (#183304)

In https://github.com/llvm/llvm-project/pull/168533 we're adding a new
`AnonymousTagMode` and will be handled in `printAnonymousTagDecl`.

This patch extracts the logic that handles
`AnonymousTagNameStyle::SourceLocation` into a helper function to make
`printAnonymousTagDecl` easier to follow.

Drive-by changes:
* While copying the code into the helper I changed it to use
early-return style.
DeltaFile
+26-22clang/lib/AST/Decl.cpp
+3-0clang/include/clang/AST/Decl.h
+29-222 files

LLVM/project 787ba24clang/docs ReleaseNotes.rst, clang/lib/Sema SemaTemplateDeduction.cpp

[clang] create local instantiation scope for matching template template parameters (#183219)

This fixes a bug where a partial substitution from the enclosing scope
is used to prepopulate an unrelated template argument deduction.

Fixes #181166
DeltaFile
+7-0clang/test/SemaTemplate/temp_arg_template_p0522.cpp
+4-2clang/docs/ReleaseNotes.rst
+2-0clang/lib/Sema/SemaTemplateDeduction.cpp
+13-23 files

LLVM/project 3d25128lldb/docs index.rst, lldb/source/Plugins/Process/FreeBSD-Kernel-Core RegisterContextFreeBSDKernelCore_arm.cpp RegisterContextFreeBSDKernelCore_arm.h

[lldb][Process/FreeBSDKernel] Add arm support (#180674)

This is LLDB version of
https://cgit.freebsd.org/ports/tree/devel/gdb/files/kgdb/arm-fbsd-kern.c.
This enables selecting arm and reading registers from PCB structure on
core dump and live kernel debugging while trapframe unwinding support
will be implemented in future. Test files using core dump from arm will
be implemented once other kernel debugging improvements are done.

---------

Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>
DeltaFile
+102-0lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp
+41-0lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h
+7-0lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp
+1-1lldb/docs/index.rst
+1-0lldb/source/Plugins/Process/FreeBSD-Kernel-Core/CMakeLists.txt
+1-0llvm/docs/ReleaseNotes.md
+153-16 files

LLVM/project e77f11cllvm/include/llvm/CodeGen TargetRegisterInfo.h, llvm/lib/CodeGen TargetRegisterInfo.cpp

[NFC][RegisterInfoEmitter] Add target name prefix for a few variables (#183074)

Add target name prefix for a few static global variables in the
generated code. Also rework the TargetRegisterInfo constructor a bit to
use a ArrayRef for array of register classes and rename a few
constructor arguments to match the member names they initialize.
DeltaFile
+38-43llvm/utils/TableGen/RegisterInfoEmitter.cpp
+14-11llvm/lib/CodeGen/TargetRegisterInfo.cpp
+8-6llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+4-4llvm/test/TableGen/RegisterInfoEmitter-regcost-list.td
+4-4llvm/test/TableGen/RegisterInfoEmitter-regcost.td
+2-5llvm/unittests/CodeGen/MFCommon.inc
+70-731 files not shown
+73-767 files

LLVM/project 9d98151llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp

Capitalize again
DeltaFile
+63-61llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+63-611 files

LLVM/project de75b41llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

Capitalize
DeltaFile
+41-41llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+41-411 files

LLVM/project 829cde3llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll

AMDGPU: Implement expansion for f64 exp

I asked AI to port the device libs reference implementation.
It mostly worked, though it got the compares wrong and also
missed a fold that happened in compiler. With that fixed I get
identical DAG output, and almost the same globalisel output (differing
by an inverted compare and select). Also adjusted some stylistic choices.
DeltaFile
+11,178-0llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+10,242-0llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+9,987-0llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+117-9llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+116-1llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+31-7llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+31,671-176 files not shown
+31,729-6512 files

LLVM/project 5b7a906clang/lib/CodeGen/TargetBuiltins ARM.cpp

[clang][ARM] Refactor argument handling in `EmitAArch64BuiltinExpr` (3/N) (NFC)

Remove the outstanding calls to `EmitScalarExpr` in
`EmitAArch64BuiltinExpr` that are no longer required.

This is a follow-up for #181794 and #181974 - please refer to that PR
for more context.
DeltaFile
+34-65clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+34-651 files

LLVM/project cb9f3eellvm/lib/Target/SPIRV SPIRVSubtarget.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_relaxed_printf_string_address_space non-constant-printf.ll

[SPIRV] Enable SPV_EXT_relaxed_printf_string_address_space by default for Intel (#183103)

It's easy to hit the address space limitation when using printf locally,
so just enable the extension by default for Intel.

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+4-1llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
+1-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_relaxed_printf_string_address_space/non-constant-printf.ll
+5-12 files

LLVM/project 8bbb24ecompiler-rt/lib/builtins/arm/thumb1 fcmp.h cmpsf2.S

Rename Thumb1 SetResultRegister to ReturnResult

Also remove the return instructions following it in the main macro,
which aren't needed, since it does the returning itself.
DeltaFile
+10-14compiler-rt/lib/builtins/arm/thumb1/fcmp.h
+1-1compiler-rt/lib/builtins/arm/thumb1/cmpsf2.S
+1-1compiler-rt/lib/builtins/arm/thumb1/gesf2.S
+12-163 files

LLVM/project a498580clang/docs LifetimeSafety.rst index.rst

Apply changes from code browser

Apply changes from code browser
DeltaFile
+296-154clang/docs/LifetimeSafety.rst
+1-0clang/docs/index.rst
+297-1542 files

LLVM/project 6e9fdd3llvm/lib/Transforms/InstCombine InstCombineLoadStoreAlloca.cpp, llvm/lib/Transforms/Utils Local.cpp

[InstCombine] Replace alloca with undef size with poison instead of null

When an alloca instruction has an undef (or poison) array size, InstCombine
was previously replacing all uses of the alloca with a null pointer. This
caused invalid IR when the alloca was used by @llvm.lifetime intrinsics.

According to the @llvm.lifetime intrinsic specification, the pointer
argument must be either:
  - A pointer to an alloca instruction, or
  - A poison value

Since null is neither an alloca pointer nor poison, the previous
transformation violated the intrinsic's requirements and produced
invalid IR.

Fix by replacing the alloca with a poison value instead of null, which
satisfies the @llvm.lifetime requirements and produces valid IR.
DeltaFile
+32-0llvm/test/Transforms/InstCombine/alloca-poison-size.ll
+0-30llvm/test/Transforms/InstCombine/invalid-alloca-poison-size.ll
+0-4llvm/lib/Transforms/Utils/Local.cpp
+1-1llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+33-354 files

LLVM/project ab2c26dcompiler-rt/lib/builtins/arm/thumb1 dcmp.h cmpdf2.S

Rename Thumb1 SetResultRegister to ReturnResult

Also remove the return instructions following it in the main macro,
which aren't needed, since it does the returning itself.
DeltaFile
+13-20compiler-rt/lib/builtins/arm/thumb1/dcmp.h
+1-1compiler-rt/lib/builtins/arm/thumb1/cmpdf2.S
+1-1compiler-rt/lib/builtins/arm/thumb1/gedf2.S
+15-223 files

LLVM/project 92ac9aeutils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix Bazel build for 9d5574d (#183312)

Co-authored-by: Pranav Kant <prka at google.com>
DeltaFile
+0-31utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+0-311 files

LLVM/project 084a62dclang/docs LifetimeSafety.rst

Apply changes from code browser

Apply changes from code browser
DeltaFile
+296-154clang/docs/LifetimeSafety.rst
+296-1541 files

LLVM/project 368b884openmp/runtime/test/parallel bug63197.c

[openmp] Fix bug63197.c test with 3 cores (#183269)

This test assumes that the number of available threads is not 3,
otherwise `#pragma omp parallel` and `#pragma omp parallel
num_thread(3)` are naturally going to do the same thing.

Instead use `omp_get_max_threads() - 1` as the number of threads in the
initial `omp parallel num_thread(N)` and then check that the number of
threads does not match the value in the later `omp parallel`.
DeltaFile
+3-2openmp/runtime/test/parallel/bug63197.c
+3-21 files

LLVM/project 351ae0cmlir/cmake/modules AddMLIR.cmake, mlir/lib/ExecutionEngine CMakeLists.txt

[MLIR][CMake] Fix runtime libraries with PCH (#182850)

Some MLIR libraries are intended to be dlopen-ed, but currently all MLIR
libraries link against LLVMSupport. After the recent PCH introduction,
this causes these libraries to implicitly use the LLVMSupport PCH, which
results in the definition of llvm::*ABIBreakingChecks, which results in
a ODR violation when loaded with dlopen.

Conceptually, libraries that are designed to be dlopen-ed should not
simply link against LLVM libraries in non-dylib builds for this reason.
(This apparently was a problem before with mlir_apfloat_wrappers.)

To fix builds, remove LLVMSupport from runtime libraries that don't need
it and, as a workaround, disable PCH for libraries that are in a weird
state (use LLVMSupport but happen to not export symbols currently).
DeltaFile
+55-3mlir/lib/ExecutionEngine/CMakeLists.txt
+7-3mlir/cmake/modules/AddMLIR.cmake
+2-0mlir/lib/ExecutionEngine/SparseTensor/CMakeLists.txt
+64-63 files

LLVM/project 51260bfmlir/test/Analysis/DataFlow test-liveness-analysis.mlir, mlir/test/lib/Analysis/DataFlow TestLivenessAnalysis.cpp

[mlir][Analysis] Print all blocks in `-test-liveness-analysis`
DeltaFile
+26-3mlir/test/Analysis/DataFlow/test-liveness-analysis.mlir
+10-7mlir/test/lib/Analysis/DataFlow/TestLivenessAnalysis.cpp
+36-102 files

LLVM/project 5aa1c38llvm/lib/Target/AMDGPU SIInstructions.td

[NFCI] Make all SI_KILL* convergent (#183100)

Add convergent property to SI_KILL*TERMINATOR. Now all SI_KILL* are
convergent. SI_KILL*TERMINATOR were already terminators so they could
not be sunk by machine-sink. Thus, this is probably a NFC.

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+7-9llvm/lib/Target/AMDGPU/SIInstructions.td
+7-91 files

LLVM/project 8bf0b36llvm/lib/Transforms/InstCombine InstCombineLoadStoreAlloca.cpp, llvm/lib/Transforms/Utils Local.cpp

[InstCombine] Replace alloca with undef size with poison instead of null

When an alloca instruction has an undef (or poison) array size, InstCombine
was previously replacing all uses of the alloca with a null pointer. This
caused invalid IR when the alloca was used by @llvm.lifetime intrinsics.

According to the @llvm.lifetime intrinsic specification, the pointer
argument must be either:
  - A pointer to an alloca instruction, or
  - A poison value

Since null is neither an alloca pointer nor poison, the previous
transformation violated the intrinsic's requirements and produced
invalid IR.

Fix by replacing the alloca with a poison value instead of null, which
satisfies the @llvm.lifetime requirements and produces valid IR.
DeltaFile
+34-0llvm/test/Transforms/InstCombine/alloca-poison-size.ll
+0-30llvm/test/Transforms/InstCombine/invalid-alloca-poison-size.ll
+0-4llvm/lib/Transforms/Utils/Local.cpp
+1-1llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+35-354 files

LLVM/project dd37cd9llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor/AMDGPU nofpclass-amdgcn-trig-preop.ll

AMDGPU: llvm.amdgcn.trig.preop cannot return negative values

This returns a positive value less than 1.
DeltaFile
+2-2llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll
+2-1llvm/lib/Analysis/ValueTracking.cpp
+4-32 files

LLVM/project 1e5936bllvm/lib/CodeGen PrologEpilogInserter.cpp

Revert "[CodeGen] Workaround for compiler crash"

This reverts commit 23582905a37659bebf6a15c413b209ad0bbbd6c4.
DeltaFile
+1-9llvm/lib/CodeGen/PrologEpilogInserter.cpp
+1-91 files

LLVM/project bf4705cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlan.h, llvm/test/Transforms/LoopVectorize predicated-single-exit.ll early_exit_legality.ll

[VPlan] Supported conditionally executed single early exits. (#182395)

Add support for a single early exit that is executed conditionally. To
make sure the mask from any non-exiting control flow is combined with
the early exit condition.

To do so, introduce a MaskedCond VPInstruction, which is inserted as
user of the early-exit condition, at the point of the early-exit branch.
The VPInstruction will get masked automatically if needed by the
predicator, ensuring that we properly account for it when checking
whether the early exit has been taken.

Note that this does not allow for instructions that require predication
after the early exit. This requires additional work in progress:
https://github.com/llvm/llvm-project/pull/172454

As an alternative to MaskedCond, we could also predicate before handling
early exiting blocks: https://github.com/llvm/llvm-project/pull/181830

PR: https://github.com/llvm/llvm-project/pull/182395
DeltaFile
+100-57llvm/test/Transforms/LoopVectorize/predicated-single-exit.ll
+1-37llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
+26-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-1llvm/lib/Transforms/Vectorize/VPlan.h
+5-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+3-1llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+140-994 files not shown
+146-10110 files

LLVM/project ab360b1llvm/lib/Analysis TargetTransformInfo.cpp, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[LLVM][TTI] Remove the isVScaleKnownToBeAPowerOfTwo hook. (#183292)

After https://github.com/llvm/llvm-project/pull/183080 this is no longer
a configurable property.

NOTE: No test changes expected beyond
llvm/test/Transforms/LoopVectorize/scalable-predication.ll which has
been removed because it only existed to verfiy the now unsupported
functionality.
DeltaFile
+0-114llvm/test/Transforms/LoopVectorize/scalable-predication.ll
+3-24llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+0-12llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+3-5llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+0-4llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+0-4llvm/lib/Analysis/TargetTransformInfo.cpp
+6-1637 files not shown
+6-17713 files

LLVM/project b7c056aclang-tools-extra/clang-tidy/modernize UseEqualsDeleteCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix erroneous warning to make deleted function public (#182577)

This PR fixes #54276 and fixes #135249 by only matching private deleted
functions with a public overload or special member functions.
DeltaFile
+66-21clang-tools-extra/test/clang-tidy/checkers/modernize/use-equals-delete.cpp
+20-1clang-tools-extra/clang-tidy/modernize/UseEqualsDeleteCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+91-223 files

LLVM/project 4b25264clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CIR/CodeGenBuiltins/AArch64 acle_sve_dup.c

[CIR][AArch64] Add lowering + tests for predicated SVE svdup_lane builtins

This PR adds CIR lowering + tests for SVE `svdup_lane` builtins on
AArch64. The corresponding ACLE intrinsics are documented at:
https://developer.arm.com/architectures/instruction-sets/intrinsics
DeltaFile
+157-0clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c
+20-3clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+177-32 files