Add smtiic(4), a driver for the I2C controller found on the SpacemiT K1
SoC. This is a close relative of mviic(4), but the register layout
changed and some bits moved within the registers.
ok jca@
Bring back the PXA2X0 variant; it resurfaced in the SpacemiT K1 SoC.
Incorporate a fix inspired by NetBSD to keep the console enabled when
userland closes the device.
relayd: support TLS with multiple listeners
Fix a bug in relay_inherit() which runs only
relay_load_certfiles(conf, rb, NULL) unconditionally which isn't
alligned with logic in parser when it parses relay block, where multiple
certificates are load as relay_load_certfiles(conf, rb, NULL) only if
here no tlscerts (for default host) and otherwise it loads keypairs.
OK: rsadowski@
x509v3.h: remove pointless #ifdef HEADER_CONF_H
x509v3.h has included conf.h since June 20, 1999, OpenSSL commit ba404b5e,
so HEADER_CONF_H has been defined since then. Also since then, CONF_VALUE
(only available via conf.h) has been used outside of HEADER_CONF_H, making
that #ifdef doubly pointless.
ok bcook jsing kenjiro
cms_local.h: remove #ifdef X509V3_HEADER_H
All thirteen files including cms_local.h do that after including cms.h,
which already includes x509v3.h, so this is always defined. While here
make the cms_local.h a bit more selfstanding by including asn1.h and
x509v3.h
ok bcook jsing (who had the same diff) kenjiro
Follow the sparc64 lead and simply define curcpu in the kernel as the
special register containing its value, this is a general register (x4)
and therefore can be used directly
Diff stolen from miod@ who is on strike but agreed to let me commit
this. ok kettenis@
fix crash on invalid tags file
If the tag entry points to the line number zero, less crashes because
internally it uses that line number to imply that the tag is associated
with a pattern.
issue reported by Henry Ford (henryfordkjv at gmail), thanks!
ok kirill@
When a cell is cleared after having been moved, we cannot reuse its
extended data, because that may still be in use. Add a flag to
grid_clear_cell to indicate this. Fixes irritating problems with ICH
(CSI @) mostly visible in emacs.
Hoist mips64 CPU accounting to get multiple softnet threads on MP systems
Increment ncpus (hw.ncpu) in mips64 cpuattach() instead of octeon/loongson
hw_cpu_hatch() running before, not after MI sofnet_percpu(), respectively.
This matches what arm64, macppc and powerpc64 do.
Local traffic may now be distributed across multiple threads, while physical
drivers like cnmac(4/octeon) still lack multiqueue support to do so.
loongson was not tested, but should behave the same.
initial report Jordan Geoghegan
tests kirill bluhm Janne Johansson
feedback miod bluhm kettenis
OK kirill visa
Implement support for the Zicbom and Svpbmt extensions. Rework the cache
flushing code to operate on virtual addresses instead of physical
addresses. Seems the Zicbom implementation on the SpacemiT X60 cores
doesn't flush the caches if the mapping is non-cachable. So adjust
_pmap_kenter_pa() to use a temporary cachable mapping to clean a page we
want to map non-cachable.
ok jca@
netgroup_mkdb(8) calls abort() when _ng_parse() returns
_NG_ERROR for a malformed netgroup entry. Make this code
exit via the same paradigm as other errors (errx).
From Renaud Allard, thanks!
ok op@