When a cell is cleared after having been moved, we cannot reuse its
extended data, because that may still be in use. Add a flag to
grid_clear_cell to indicate this. Fixes irritating problems with ICH
(CSI @) mostly visible in emacs.
Hoist mips64 CPU accounting to get multiple softnet threads on MP systems
Increment ncpus (hw.ncpu) in mips64 cpuattach() instead of octeon/loongson
hw_cpu_hatch() running before, not after MI sofnet_percpu(), respectively.
This matches what arm64, macppc and powerpc64 do.
Local traffic may now be distributed across multiple threads, while physical
drivers like cnmac(4/octeon) still lack multiqueue support to do so.
loongson was not tested, but should behave the same.
initial report Jordan Geoghegan
tests kirill bluhm Janne Johansson
feedback miod bluhm kettenis
OK kirill visa
Implement support for the Zicbom and Svpbmt extensions. Rework the cache
flushing code to operate on virtual addresses instead of physical
addresses. Seems the Zicbom implementation on the SpacemiT X60 cores
doesn't flush the caches if the mapping is non-cachable. So adjust
_pmap_kenter_pa() to use a temporary cachable mapping to clean a page we
want to map non-cachable.
ok jca@
netgroup_mkdb(8) calls abort() when _ng_parse() returns
_NG_ERROR for a malformed netgroup entry. Make this code
exit via the same paradigm as other errors (errx).
From Renaud Allard, thanks!
ok op@
Clamp width to terminal width, also change calculation of end of screen
(it is OK to be outside the screen). Fixes problem reported by Dane
Jensen in GitHub issue 4969.
ksh: yank on 'change' in vi-mode
Until now, only 'delete' operations in ksh's vi-mode yank the deleted
range to the yank buffer. Make 'change' operations do the same.
This is consistent with vi(1)'s behavior.
ok tb@
sys/octeon: interrupts and barier cleanup
octciu_intr_establish() happens on autoconf where only CPU0 exists, and
on octeon we increase ncpus in cpu hatch, and not attach, which means
that ncpus is 1 at octciu_intr_establish() time.
What makes cpuid always 1 for that code and schedules all interrupts on
CPU0.
I also moved octciu_intr_barrier() to actual interrupt's cpu.
OK: visa@, kn@
Fix order of cpus in CPU_INFO_FOREACH
The cpus were put into the linked list in mostly inverted order during attach.
The linked list determines the order used by the CPU_INFO_FOREACH macros.
Order the linked list by ci_cpuid instead.
ok jca@ for most archs
"this should go in" deraadt@
Stop printing the riscv,isa string; our code to do so is broken and the
string is now deprecated. Instead change hw.model to be the CPU core
name for cpu0 like we do on other architectures.
We'll revisit printing CPU features for riscv64 in the future.
ok jca@, mlarkin@
Add hw.blockcpu support for arm64. Here we classify CPU cores based on
their "capacity". This a concept borrowed from the device tree standard
that indicates the nominal performance of a CPU core. For ACPI machines
we use similar information from ACPI's Collaborative Processor Performance
Control (CPPC). If performance is less than 30% of the fastest cores in
the same we classify them as L. Between 30% and 80% we classify them as E.
And above 80% we classify them as P. The CPU capacity is communicated to
userland though kstat(4).
ok deraadt@, jca@
fix memory leak in config_purge() when dealing CONFIG_PROTOS
original diff from CypherFox (openbsd at cypher-fox com), thanks!
slightly rearranged to be a bit smaller by me, but still equivalent.