LLVM/project 552f6c9llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

rebase

Created using spr 1.3.4
DeltaFile
+3,128-3,170llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487-2,510llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716-1,780llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343-11,6084,566 files not shown
+159,258-104,3134,572 files

LLVM/project 85e290bllvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350-4,196llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478-10,3696,999 files not shown
+425,286-177,3787,005 files

LLVM/project 2ece26fllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-024,133 files not shown
+2,356,601-721,36324,139 files

LLVM/project 9c94049llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project 05307cfllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project de23806llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,128 files not shown
+2,356,423-721,19324,134 files

LLVM/project 2c57c89llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875-9,2902,274 files not shown
+97,298-62,3572,280 files

LLVM/project 1008539llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV complex-loads.ll

[SLP]Reduce number of alternate instruction, where possible

Previous version was reviewed here https://github.com/llvm/llvm-project/pull/123360
It is mostly the same, adjusted after graph-to-tree transformation

Patch tries to remove wide alternate operations.
Currently SLP vectorizer emits something like this:
```
%0 = add i32
%1 = sub i32
%2 = add i32
%3 = sub i32
%4 = add i32
%5 = sub i32
%6 = add i32
%7 = sub i32

transformes to


    [166 lines not shown]
DeltaFile
+702-73llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+230-142llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+222-0llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
+138-26llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
+138-26llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
+86-20llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+1,516-28727 files not shown
+1,937-43433 files

LLVM/project 5ec884ellvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV complex-loads.ll

Revert "[SLP]Reduce number of alternate instruction, where possible"

This caused assertion failures:

  llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:16237:
  Value *llvm::slpvectorizer::BoUpSLP::vectorizeTree(TreeEntry *):
  Assertion `OpTE1.isSame( ArrayRef(E->Scalars).take_front(OpTE1.getVectorFactor())) && "Expected same first part of scalars."' failed.

See comment on the PR.

> Previous version was reviewed here https://github.com/llvm/llvm-project/pull/123360
> It is mostly the same, adjusted after graph-to-tree transformation

This reverts commit 7de895ff1146c17ec78877900c01c09f4140e692.
DeltaFile
+74-704llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+142-230llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+26-138llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
+26-138llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
+20-86llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+20-86llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+308-1,38226 files not shown
+435-1,71732 files

LLVM/project 79c32c1llvm/test/MC/AMDGPU gfx12_asm_sop2.s gfx12_asm_sop1.s, llvm/test/MC/Disassembler/AMDGPU gfx12_dasm_sop2.txt gfx12_dasm_sop1.txt

.

Created using spr 1.3.5-bogner
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,424-1,423llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+1,234-1,233llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+721-720llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt
+721-720llvm/test/MC/AMDGPU/gfx12_asm_sopc.s
+8,252-8,244263 files not shown
+14,950-10,040269 files

LLVM/project ed3f871llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

Merge branch 'main' into users/vitalybuka/spr/ir-optimize-cfi-in-writecombinedglobalvaluesummary
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+1,240-1,230llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+9,200-10,5201,240 files not shown
+47,494-33,1451,246 files

LLVM/project 7de895fllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV complex-loads.ll

[SLP]Reduce number of alternate instruction, where possible

Previous version was reviewed here https://github.com/llvm/llvm-project/pull/123360
It is mostly the same, adjusted after graph-to-tree transformation

Patch tries to remove wide alternate operations.
Currently SLP vectorizer emits something like this:
```
%0 = add i32
%1 = sub i32
%2 = add i32
%3 = sub i32
%4 = add i32
%5 = sub i32
%6 = add i32
%7 = sub i32

transformes to


    [166 lines not shown]
DeltaFile
+702-72llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+230-142llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+138-26llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
+138-26llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
+86-20llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+86-20llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+1,380-30626 files not shown
+1,715-43332 files

LLVM/project 9274743llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Analysis/CostModel/AArch64 arith-widening.ll sve-intrinsics.ll

release note

Created using spr 1.3.5-bogner
DeltaFile
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+741-741llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+660-658llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+545-533llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
+464-470llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+74-698llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+3,424-4,996379 files not shown
+13,173-12,743385 files

LLVM/project e858b10llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/CodeGen/AMDGPU materialize-frame-index-sgpr.gfx10.ll materialize-frame-index-sgpr.ll

Revert "[SLP]Reduce number of alternate instruction, where possible"

This caused failures such as:

  Instruction does not dominate all uses!
  %29 = insertelement <8 x i64> %28, i64 %xor6.i.5, i64 6
  %17 = shufflevector <8 x i64> %29, <8 x i64> poison, <6 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>

see comment on https://github.com/llvm/llvm-project/pull/123360

> Previous version was reviewed here https://github.com/llvm/llvm-project/pull/123360
> It is mostly the same, adjusted after graph-to-tree transformation
>
> Patch tries to remove wide alternate operations.
> Currently SLP vectorizer emits something like this:
> ```
> %0 = add i32
> %1 = sub i32
> %2 = add i32

    [29 lines not shown]
DeltaFile
+221-927llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
+74-698llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+142-230llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+137-177llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+26-138llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
+26-138llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
+626-2,30828 files not shown
+794-2,74434 files

LLVM/project 397c487llvm/test/CodeGen/AMDGPU global_atomics_scan_fadd.ll global_atomics_scan_fsub.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-cttz-vp.ll

Merge remote-tracking branch 'origin/main' into users/ccc03-08-_astmatcher_templateargumentcountis_support_functiondecl_
DeltaFile
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+726-1,509llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+7,080-8,2571,023 files not shown
+37,140-28,4421,029 files

LLVM/project 9d37e61llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV complex-loads.ll

[SLP]Reduce number of alternate instruction, where possible

Previous version was reviewed here https://github.com/llvm/llvm-project/pull/123360
It is mostly the same, adjusted after graph-to-tree transformation

Patch tries to remove wide alternate operations.
Currently SLP vectorizer emits something like this:
```
%0 = add i32
%1 = sub i32
%2 = add i32
%3 = sub i32
%4 = add i32
%5 = sub i32
%6 = add i32
%7 = sub i32

transformes to


    [166 lines not shown]
DeltaFile
+696-72llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+230-142llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+138-26llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
+138-26llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
+86-20llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+86-20llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+1,374-30625 files not shown
+1,637-43331 files

LLVM/project 57a6b05llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV complex-loads.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5
DeltaFile
+230-630llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+674-72llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+86-20llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+86-20llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+82-16llvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll
+82-16llvm/test/Transforms/SLPVectorizer/X86/alternate-fp.ll
+1,240-77425 files not shown
+1,448-90931 files

LLVM/project d9751a3llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Merge branch 'main' into users/chapuni/yaml/newgen

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-logical-mixed.cpp
        llvm/test/tools/llvm-cov/Inputs/branch-macros.cpp
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956-030,003 files not shown
+3,294,806-1,187,82230,009 files

LLVM/project 1a95648clang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

Rebase

Created using spr 1.3.5
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,778-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,582-1,5435,129 files not shown
+235,155-136,7225,135 files

LLVM/project 2f763c0clang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

Rebase on top of main

Created using spr 1.3.6-beta.1
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project 4615cceclang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project fe1b3e2clang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

Rebase on top of main

Created using spr 1.3.6-beta.1
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project 8c18c46clang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project 6883cbdclang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

Rebase on top of main

Created using spr 1.3.6-beta.1
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project cacf7fdclang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project c202534clang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

Rebase on top of main

Created using spr 1.3.6-beta.1
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project 5aad4baclang/test/AST ast-dump-templates.cpp, libcxx/test/libcxx/containers/associative tree_remove.pass.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,824-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
+3,412-0llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+1,480-1,490libcxx/test/libcxx/containers/associative/tree_remove.pass.cpp
+2,885-51llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+28,628-1,5434,718 files not shown
+222,321-128,3564,724 files

LLVM/project d00579bllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV complex-loads.ll

Revert "[SLP]Reduce number of alternate instruction, where possible"

This reverts commit d5a7a483a65f830a0c7a931781bc90046dc67ff4.

That commit triggers failed asserts, see
https://github.com/llvm/llvm-project/pull/123360 for details.
DeltaFile
+627-231llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+51-585llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+20-86llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+20-86llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+16-82llvm/test/Transforms/SLPVectorizer/X86/alternate-fp.ll
+16-82llvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll
+750-1,15216 files not shown
+854-1,32622 files

LLVM/project 3fad066llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Rebase on top of main.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956-021,151 files not shown
+2,151,133-609,87521,157 files

LLVM/project 2d88d20llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-021,151 files not shown
+2,151,133-609,87521,157 files