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[AMDGPU] Add identity_combines to RegBankCombiner

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Rebase, address comments

Created using spr 1.3.5

Merge branch 'main' into users/ylzsx/r-tls-noie

reb

Created using spr 1.3.4

Merge branch 'main' into users/meinersbur/flang_runtime_premerge

Rebase, address comments

Created using spr 1.3.5

Rebase, address comments

Created using spr 1.3.5

DAG: Use phi to create vregs instead of the constant input (#129464)

For most targets, the register class comes from the type so this
makes no difference. For AMDGPU, the selected register class depends
on the divergence of the value. For a constant phi input, this will
always be false. The heuristic for whether to treat the value as
a scalar or vector constant based on the uses would then incorrectly
think this is a scalar use, when really the phi is a copy from S to V.

This avoids an intermediate s_mov_b32 plus a copy in some cases. These
would often, but not always, fold out in mi passes.

This only adjusts the constant input case. It may make sense to do
this for the non-constant case as well.

Rebase, address comments

Created using spr 1.3.5

DAG: Use phi to create vregs instead of the constant input

For most targets, the register class comes from the type so this
makes no difference. For AMDGPU, the selected register class depends
on the divergence of the value. For a constant phi input, this will
always be false. The heuristic for whether to treat the value as
a scalar or vector constant based on the uses would then incorrectly
think this is a scalar use, when really the phi is a copy from S to V.

This avoids an intermediate s_mov_b32 plus a copy in some cases. These
would often, but not always, fold out in mi passes.

This only adjusts the constant input case. It may make sense to do
this for the non-constant case as well.

DAG: Use phi to create vregs instead of the constant input

For most targets, the register class comes from the type so this
makes no difference. For AMDGPU, the selected register class depends
on the divergence of the value. For a constant phi input, this will
always be false. The heuristic for whether to treat the value as
a scalar or vector constant based on the uses would then incorrectly
think this is a scalar use, when really the phi is a copy from S to V.

This avoids an intermediate s_mov_b32 plus a copy in some cases. These
would often, but not always, fold out in mi passes.

This only adjusts the constant input case. It may make sense to do
this for the non-constant case as well.

rebase

Created using spr 1.3.5-bogner

Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/trunk

Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/nest-base

Conflicts:
        clang/test/CoverageMapping/mcdc-single-cond.cpp

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/bitmapaddr

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/mcdcstate

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/lnot

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/expect

Merge branch 'main' into users/chapuni/mcdc/nest/tests

rebase

Created using spr 1.3.4

run 'git merge main'

Rebase, add option

Created using spr 1.3.5

AMDGPU: Do not try to commute instruction with same input register (#127562)

There's little point to trying to commute an instruction if the
two operands are already the same.

This avoids an assertion in a future patch, but this likely isn't the
correct fix. The worklist management in SIFoldOperands is dodgy, and
we should probably fix it to work like PeepholeOpt (i.e. stop looking
at use lists, and fold from users). This is an extension of the already
handled special case which it's trying to avoid folding an instruction
which is already being folded.

AMDGPU: Do not try to commute instruction with same input register

There's little point to trying to commute an instruction if the
two operands are already the same.

This avoids an assertion in a future patch, but this likely isn't the
correct fix. The worklist management in SIFoldOperands is dodgy, and
we should probably fix it to work like PeepholeOpt (i.e. stop looking
at use lists, and fold from users). This is an extension of the already
handled special case which it's trying to avoid folding an instruction
which is already being folded.

AMDGPU: Do not try to commute instruction with same input register

There's little point to trying to commute an instruction if the
two operands are already the same.

This avoids an assertion in a future patch, but this likely isn't the
correct fix. The worklist management in SIFoldOperands is dodgy, and
we should probably fix it to work like PeepholeOpt (i.e. stop looking
at use lists, and fold from users). This is an extension of the already
handled special case which it's trying to avoid folding an instruction
which is already being folded.