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Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Merge branch 'main' into users/ylzsx/r-tls-noie

Merge branch 'main' into users/meinersbur/flang_runtime_premerge

Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/trunk

Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/nest-base

Conflicts:
        clang/test/CoverageMapping/mcdc-single-cond.cpp

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/bitmapaddr

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/mcdcstate

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/lnot

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/expect

Merge branch 'main' into users/chapuni/mcdc/nest/tests

run 'git merge main'

fix order

Created using spr 1.3.4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Rebase

Created using spr 1.3.5

rebase

Created using spr 1.3.4

refactor

Created using spr 1.3.4

Address @DavidSpickett's comment

Created using spr 1.3.5-bogner

Merge branch 'main' of https://github.com/llvm/llvm-project into cbuffer-codegen5

Rebase, address comments, remove some extra graph-related code

Created using spr 1.3.5

rebase

Created using spr 1.3.4

Merge branch 'main' into obj2yaml/root-constants

apply review suggestions

Created using spr 1.3.6-beta.1

Merge branch 'main' into users/chapuni/yaml/newgen

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-logical-mixed.cpp
        llvm/test/tools/llvm-cov/Inputs/branch-macros.cpp

[LLD][ELF][ARM] Fix resolution of R_ARM_THM_JUMP8 and R_ARM_THM_JUMP11 for big endian (#126933)

These relocations apply to 16-bit Thumb instructions, so reading 16 bits
rather than 32 bits ensures the correct bits are masked and written
back. This fixes the incorrect masking and aligns the relocation logic
with the instruction encoding.

Before this patch, 32 bits were read from the ELF object. This did not
align with the instruction size of 16 bits, but the masking incidentally
made it all work nonetheless. However, this was the case only in little
endian.

In big endian mode, the read 32-bit word had to have its bytes reversed.
With this byte reordering, the masking would be applied to the wrong
bits, hence causing the incorrect encoding to be produced as a result of
the relocation resolution.

The added test checks the result for both little and big endian modes.

Merge branch 'main' into users/ylzsx/r-call36

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

use fixed size for dynamic inst count

Created using spr 1.3.6-beta.1