LLVM/project 552f6c9llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

rebase

Created using spr 1.3.4
DeltaFile
+3,128-3,170llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487-2,510llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716-1,780llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343-11,6084,566 files not shown
+159,258-104,3134,572 files

LLVM/project 85e290bllvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350-4,196llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478-10,3696,999 files not shown
+425,286-177,3787,005 files

LLVM/project 26f4359flang/include/flang/Optimizer/HLFIR HLFIROps.td, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

handle review comments
DeltaFile
+1-13flang/include/flang/Optimizer/HLFIR/HLFIROps.td
+1-1flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+2-142 files

LLVM/project 90e3c13flang/include/flang/Optimizer/HLFIR HLFIROps.td, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

[flang][hlfir] Add MLIR op for `do concurrent`

Adds new MLIR ops to model `do concurrent`. In order to make `do
concurrent` representation self-contained, a loop is modeled using 2
ops, one wrapper and one that contains the actual body of the loop. For
example, a 2D `do concurrent` loop is modeled as follows:

```mlir
  hlfir.do_concurrent {
    %i = fir.alloca i32
    %j = fir.alloca i32
    hlfir.do_concurrent.loop
      (%i_iv, %j_iv) = (%i_lb, %j_lb) to (%i_ub, %j_ub) step (%i_st, %j_st) {
      %0 = fir.convert %i_iv : (index) -> i32
      fir.store %0 to %i : !fir.ref<i32>

      %1 = fir.convert %j_iv : (index) -> i32
      fir.store %1 to %j : !fir.ref<i32>
    }

    [7 lines not shown]
DeltaFile
+163-0flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+116-0flang/include/flang/Optimizer/HLFIR/HLFIROps.td
+95-0flang/test/HLFIR/invalid.fir
+92-0flang/test/HLFIR/do_concurrent.fir
+466-04 files

LLVM/project 2ece26fllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-024,133 files not shown
+2,356,601-721,36324,139 files

LLVM/project 9c94049llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project 05307cfllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project de23806llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,128 files not shown
+2,356,423-721,19324,134 files

LLVM/project 2c57c89llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875-9,2902,274 files not shown
+97,298-62,3572,280 files

LLVM/project dcc9686flang/include/flang/Optimizer/HLFIR HLFIROps.td, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

handle review comments
DeltaFile
+1-13flang/include/flang/Optimizer/HLFIR/HLFIROps.td
+1-1flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+2-142 files

LLVM/project af84177flang/include/flang/Optimizer/HLFIR HLFIROps.td, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

[flang][hlfir] Add MLIR op for `do concurrent`

Adds new MLIR ops to model `do concurrent`. In order to make `do
concurrent` representation self-contained, a loop is modeled using 2
ops, one wrapper and one that contains the actual body of the loop. For
example, a 2D `do concurrent` loop is modeled as follows:

```mlir
  hlfir.do_concurrent {
    %i = fir.alloca i32
    %j = fir.alloca i32
    hlfir.do_concurrent.loop
      (%i_iv, %j_iv) = (%i_lb, %j_lb) to (%i_ub, %j_ub) step (%i_st, %j_st) {
      %0 = fir.convert %i_iv : (index) -> i32
      fir.store %0 to %i : !fir.ref<i32>

      %1 = fir.convert %j_iv : (index) -> i32
      fir.store %1 to %j : !fir.ref<i32>
    }

    [7 lines not shown]
DeltaFile
+163-0flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+116-0flang/include/flang/Optimizer/HLFIR/HLFIROps.td
+95-0flang/test/HLFIR/invalid.fir
+92-0flang/test/HLFIR/do_concurrent.fir
+466-04 files

LLVM/project dd56911flang/include/flang/Optimizer/HLFIR HLFIROps.td, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

[flang][hlfir] Add MLIR op for `do concurrent`

Adds new MLIR ops to model `do concurrent`. In order to make `do
concurrent` representation self-contained, a loop is modeled using 2
ops, one wrapper and one that contains the actual body of the loop. For
example, a 2D `do concurrent` loop is modeled as follows:

```mlir
  hlfir.do_concurrent {
    %i = fir.alloca i32
    %j = fir.alloca i32
    hlfir.do_concurrent.loop
      (%i_iv, %j_iv) = (%i_lb, %j_lb) to (%i_ub, %j_ub) step (%i_st, %j_st) {
      %0 = fir.convert %i_iv : (index) -> i32
      fir.store %0 to %i : !fir.ref<i32>

      %1 = fir.convert %j_iv : (index) -> i32
      fir.store %1 to %j : !fir.ref<i32>
    }

    [7 lines not shown]
DeltaFile
+163-0flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+116-0flang/include/flang/Optimizer/HLFIR/HLFIROps.td
+95-0flang/test/HLFIR/invalid.fir
+92-0flang/test/HLFIR/do_concurrent.fir
+466-04 files

LLVM/project dc66ca4llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,348-1,952llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+17,078-9,8592,714 files not shown
+131,118-67,3922,720 files

LLVM/project d4e79afllvm/test/CodeGen/AMDGPU global_atomics_scan_fsub.ll global_atomics_scan_fadd.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o03-cancel-directive-name
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+10,668-4,9201,301 files not shown
+51,893-31,2131,307 files

LLVM/project 7dc7264llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/ylzsx/r-tls-noie
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+203,722-016,100 files not shown
+2,040,184-604,85516,106 files

LLVM/project 33f623dllvm/test/CodeGen/AMDGPU vni8-across-blocks.ll shufflevector-physreg-copy.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o02-metadirective-flush
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+603-1,206llvm/test/CodeGen/X86/matrix-multiply.ll
+706-540llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+812-407llvm/test/CodeGen/Thumb2/mve-vld3.ll
+795-0llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
+8,664-2,153747 files not shown
+23,408-10,802753 files

LLVM/project 2ff290bllvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll qci-interrupt-attr.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-store-i8-stride-7.ll

Rebase

Created using spr 1.3.5
DeltaFile
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,532-1,534llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+16,837-3,2681,830 files not shown
+73,594-27,5911,836 files

LLVM/project 40e245aflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder TemporaryStorage.cpp

[flang] add support for procedure pointer assignment inside FORALL (#130114)

Very similar to object pointer assignment, the difference is the SSA
types of the LHS (!fir.ref<!fir.boxproc<()->()>> and RHS
(!fir.boxproc<()->()).

The RHS must be saved as simple address, not descriptors (it is not
possible to make CFI descriptor out of procedure entity).
DeltaFile
+222-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-codegen.fir
+126-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling-character.f90
+123-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling.f90
+21-13flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+24-9flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+18-9flang/lib/Lower/Bridge.cpp
+534-316 files not shown
+567-4912 files

LLVM/project f08aedcflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder TemporaryStorage.cpp

[flang] add support for procedure pointer assignment inside FORALL

Very similar to object pointer assignment, the difference is the SSA types of
the LHS (!fir.ref<!fir.boxproc<()->()>> and RHS (!fir.boxproc<()->()).

The RHS must be saved as simple address, not descriptors (it is not possible to
make CFI descriptor out of procedure entity).
DeltaFile
+222-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-codegen.f90
+126-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling-character.f90
+123-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling.f90
+21-13flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+24-9flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+18-9flang/lib/Lower/Bridge.cpp
+534-316 files not shown
+567-4912 files

LLVM/project 8cb72bdllvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm60.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

reb

Created using spr 1.3.4
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+88,808-6,1733,815 files not shown
+253,453-75,5073,821 files

LLVM/project 7302e1bflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder HLFIRTools.cpp

[flang] implement simple pointer assignments inside FORALL (#129522)

The semantic of pointer assignments inside FORALL requires evaluating
the targets (RHS) and pointer variables (LHS) of all iterations before
evaluating the assignments.

In practice, if the compiler can prove that the RHS and LHS evaluations
are not impacted by the assignments, the evaluation of the FORALL
assignment statement can be done in a single loop. However, if the
compiler cannot prove this, it needs to "save" the addresses of the
targets and/or the pointer descriptors of each iterations before doing
the assignments.

This patch implements the most common cases where there is no lower bound
spec, no bounds remapping, the LHS is not polymorphic, and the RHS is
not NULL.

The HLFIR operation used to represent assignments inside FORALL can be
used for pointer assignments to (the only difference being that the LHS

    [9 lines not shown]
DeltaFile
+200-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-codegen.fir
+111-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
+77-18flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
+62-3flang/lib/Lower/Bridge.cpp
+47-0flang/test/HLFIR/order_assignments/vector-subscripts-codegen.fir
+33-5flang/lib/Optimizer/Builder/HLFIRTools.cpp
+530-268 files not shown
+605-3214 files

LLVM/project 66effd4flang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder HLFIRTools.cpp TemporaryStorage.cpp

[flang] implement simple pointer assignments inside FORALL

The semantic of pointer assignments inside FORALL requires evaluating
the targets (RHS) and pointer variables (LHS) of all iterations before
evaluating the assignments.

In practice, if the compiler can prove that the RHS and LHS evaluations
are not impacted by the assignments, the evaluation of the FORALL
assignment statement can be done in a single loop.
However, if the compiler cannot prove this, it needs to "save" the addresses
of the targets and/or the pointer descriptors of each iterations before doing
the assignments.

This patch implement the most common cases where there is no lower bound spec,
no bounds remapping, the LHS is not polymorphic, and the RHS is not NULL.

The HLFIR operation used to represent assignments inside FORALL can be used
for pointer assignments to (the only difference being that the LHS is a
descriptor address).

    [16 lines not shown]
DeltaFile
+200-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-codegen.fir
+111-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
+80-24flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
+62-3flang/lib/Lower/Bridge.cpp
+33-5flang/lib/Optimizer/Builder/HLFIRTools.cpp
+24-0flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+510-327 files not shown
+561-3813 files

LLVM/project 559f55dflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder HLFIRTools.cpp TemporaryStorage.cpp

[flang] implement simple pointer assignments inside FORALL

The semantic of pointer assignments inside FORALL requires evaluating
the targets (RHS) and pointer variables (LHS) of all iterations before
evaluating the assignments.

In practice, if the compiler can prove that the RHS and LHS evaluations
are not impacted by the assignments, the evaluation of the FORALL
assignment statement can be done in a single loop.
However, if the compiler cannot prove this, it needs to "save" the addresses
of the targets and/or the pointer descriptors of each iterations before doing
the assignments.

This patch implement the most common cases where there is no lower bound spec,
no bounds remapping, the LHS is not polymorphic, and the RHS is not NULL.

The HLFIR operation used to represent assignments inside FORALL can be used
for pointer assignments to (the only difference being that the LHS is a
descriptor address).

    [16 lines not shown]
DeltaFile
+200-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-codegen.fir
+112-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
+80-24flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
+62-3flang/lib/Lower/Bridge.cpp
+33-5flang/lib/Optimizer/Builder/HLFIRTools.cpp
+24-0flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+511-327 files not shown
+562-3813 files

LLVM/project e45a72allvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

refactor

Created using spr 1.3.4
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-015,561 files not shown
+1,914,489-576,76815,567 files

LLVM/project d9751a3llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Merge branch 'main' into users/chapuni/yaml/newgen

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-logical-mixed.cpp
        llvm/test/tools/llvm-cov/Inputs/branch-macros.cpp
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956-030,003 files not shown
+3,294,806-1,187,82230,009 files

LLVM/project 03645efllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Merge branch 'main' into users/ylzsx/r-call36
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-010,990 files not shown
+1,581,431-416,52410,996 files

LLVM/project b9ae94eclang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/AArch64 neon-dotreduce.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+20,021-0llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
+13,743-0llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
+3,087-8,187llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,676-1,531llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+57,554-9,7205,762 files not shown
+304,241-135,9965,768 files

LLVM/project 5211ad2clang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/AArch64 neon-dotreduce.ll

use fixed size for dynamic inst count

Created using spr 1.3.6-beta.1
DeltaFile
+20,021-0llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
+13,743-0llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
+3,087-8,187llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,676-1,531llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+57,554-9,7205,764 files not shown
+304,247-136,0005,770 files

LLVM/project a63f09ellvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

rebase

Created using spr 1.3.4
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+164,956-014,444 files not shown
+1,781,638-474,01214,450 files

LLVM/project 2c4bdb2clang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/AArch64 neon-dotreduce.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+20,021-0llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
+13,743-0llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
+3,087-8,187llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+10,982-0llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,045-2clang/test/AST/ast-dump-templates.cpp
+3,676-1,531llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+57,554-9,7205,761 files not shown
+304,233-135,9885,767 files