LLVM/project 552f6c9llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

rebase

Created using spr 1.3.4
DeltaFile
+3,128-3,170llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487-2,510llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
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+1,716-1,780llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343-11,6084,566 files not shown
+159,258-104,3134,572 files

LLVM/project 85e290bllvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm70.ll

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350-4,196llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
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+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+90,478-10,3696,999 files not shown
+425,286-177,3787,005 files

LLVM/project 2ece26fllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Update OB name from `type` to `callee_type`.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+164,956-024,133 files not shown
+2,356,601-721,36324,139 files

LLVM/project 9c94049llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
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+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project 05307cfllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

Update LTO compilation CodeGen flag for call-graph-section.

Created using spr 1.3.6-beta.1
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
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+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,129 files not shown
+2,356,435-721,19824,135 files

LLVM/project de23806llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+30,641-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+164,956-024,128 files not shown
+2,356,423-721,19324,134 files

LLVM/project 2c57c89llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle
DeltaFile
+2,099-2,096llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053-2,052llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434-1,828llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434-1,418llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940-1,896llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875-9,2902,274 files not shown
+97,298-62,3572,280 files

LLVM/project dc66ca4llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,348-1,952llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+17,078-9,8592,714 files not shown
+131,118-67,3922,720 files

LLVM/project d4e79afllvm/test/CodeGen/AMDGPU global_atomics_scan_fsub.ll global_atomics_scan_fadd.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o03-cancel-directive-name
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,246-1,246llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,214-1,214llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+10,668-4,9201,301 files not shown
+51,893-31,2131,307 files

LLVM/project 7dc7264llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/ylzsx/r-tls-noie
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,655-0llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,139-0llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933-0llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+203,722-016,100 files not shown
+2,040,184-604,85516,106 files

LLVM/project 33f623dllvm/test/CodeGen/AMDGPU vni8-across-blocks.ll shufflevector-physreg-copy.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

Merge branch 'main' into users/kparzysz/spr/o02-metadirective-flush
DeltaFile
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+603-1,206llvm/test/CodeGen/X86/matrix-multiply.ll
+706-540llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+812-407llvm/test/CodeGen/Thumb2/mve-vld3.ll
+795-0llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
+8,664-2,153747 files not shown
+23,408-10,802753 files

LLVM/project 2ff290bllvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll qci-interrupt-attr.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-store-i8-stride-7.ll

Rebase

Created using spr 1.3.5
DeltaFile
+3,951-0llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746-1,734llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,532-1,534llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,927-0llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821-0llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+16,837-3,2681,830 files not shown
+73,594-27,5911,836 files

LLVM/project 40e245aflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder TemporaryStorage.cpp

[flang] add support for procedure pointer assignment inside FORALL (#130114)

Very similar to object pointer assignment, the difference is the SSA
types of the LHS (!fir.ref<!fir.boxproc<()->()>> and RHS
(!fir.boxproc<()->()).

The RHS must be saved as simple address, not descriptors (it is not
possible to make CFI descriptor out of procedure entity).
DeltaFile
+222-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-codegen.fir
+126-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling-character.f90
+123-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling.f90
+21-13flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+24-9flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+18-9flang/lib/Lower/Bridge.cpp
+534-316 files not shown
+567-4912 files

LLVM/project f08aedcflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder TemporaryStorage.cpp

[flang] add support for procedure pointer assignment inside FORALL

Very similar to object pointer assignment, the difference is the SSA types of
the LHS (!fir.ref<!fir.boxproc<()->()>> and RHS (!fir.boxproc<()->()).

The RHS must be saved as simple address, not descriptors (it is not possible to
make CFI descriptor out of procedure entity).
DeltaFile
+222-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-codegen.f90
+126-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling-character.f90
+123-0flang/test/HLFIR/order_assignments/forall-proc-pointer-assignment-scheduling.f90
+21-13flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+24-9flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+18-9flang/lib/Lower/Bridge.cpp
+534-316 files not shown
+567-4912 files

LLVM/project 8cb72bdllvm/test/CodeGen/NVPTX cmpxchg-sm90.ll cmpxchg-sm60.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

reb

Created using spr 1.3.4
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
+5,680-0llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+88,808-6,1733,815 files not shown
+253,453-75,5073,821 files

LLVM/project 7302e1bflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder HLFIRTools.cpp

[flang] implement simple pointer assignments inside FORALL (#129522)

The semantic of pointer assignments inside FORALL requires evaluating
the targets (RHS) and pointer variables (LHS) of all iterations before
evaluating the assignments.

In practice, if the compiler can prove that the RHS and LHS evaluations
are not impacted by the assignments, the evaluation of the FORALL
assignment statement can be done in a single loop. However, if the
compiler cannot prove this, it needs to "save" the addresses of the
targets and/or the pointer descriptors of each iterations before doing
the assignments.

This patch implements the most common cases where there is no lower bound
spec, no bounds remapping, the LHS is not polymorphic, and the RHS is
not NULL.

The HLFIR operation used to represent assignments inside FORALL can be
used for pointer assignments to (the only difference being that the LHS

    [9 lines not shown]
DeltaFile
+200-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-codegen.fir
+111-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
+77-18flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
+62-3flang/lib/Lower/Bridge.cpp
+47-0flang/test/HLFIR/order_assignments/vector-subscripts-codegen.fir
+33-5flang/lib/Optimizer/Builder/HLFIRTools.cpp
+530-268 files not shown
+605-3214 files

LLVM/project b2e1758llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-vmul.ll neon_vmul.ll

Rebase, address comments

Created using spr 1.3.5
DeltaFile
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+1,348-1,952llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+0-1,933llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
+1,933-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1.ll
+1,917-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1_lane.ll
+11,371-10,0581,125 files not shown
+41,367-24,0581,131 files

LLVM/project 5ea9c7eclang/lib/Headers avx10_2convertintrin.h, llvm/test/Instrumentation/MemorySanitizer/AArch64 neon_vmul.ll arm64-vmul.ll

Reabse, address comments

Created using spr 1.3.5
DeltaFile
+0-6,173llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+6,173-0llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+2,854-51clang/lib/Headers/avx10_2convertintrin.h
+0-1,933llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
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+0-1,917llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
+10,960-10,0741,598 files not shown
+58,088-25,8271,604 files

LLVM/project a704e65flang/include/flang/Optimizer/Builder HLFIRTools.h, flang/lib/Optimizer/Builder HLFIRTools.cpp

[flang] Added alternative inlining code for hlfir.cshift. (#129176)

Flang generates slower code for `CSHIFT(CSHIFT(PTR(:,:,I),sh1,1),sh2,2)`
pattern in facerec than other compilers. The first CSHIFT can be done
as two memcpy's wrapped in a loop for the second dimension.
This does require creating a temporary array, but it seems to be faster,
than the current hlfir.elemental inlining.

I started with modifying the new index computation in
hlfir.elemental inlining: the new arith.select approach does enable
some vectorization in LLVM, but on x86 it is using gathers/scatters
and does not give much speed-up.

I also experimented with LoopBoundSplitPass
and InductiveRangeCheckElimination for a simple (not chained) CSHIFT
case, but I could not adjust them to split the loop with a condition
on the value of the IV into two loops with disjoint iteration spaces.
I thought if I could do it, I would be able to keep the hlfir.elemental
inlining mostly untouched, and then adjust the hlfir.elemental inlining

    [10 lines not shown]
DeltaFile
+268-200flang/test/HLFIR/simplify-hlfir-intrinsics-cshift.fir
+327-26flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+49-0flang/lib/Optimizer/Builder/HLFIRTools.cpp
+13-0flang/include/flang/Optimizer/Builder/HLFIRTools.h
+657-2264 files

LLVM/project 66effd4flang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder HLFIRTools.cpp TemporaryStorage.cpp

[flang] implement simple pointer assignments inside FORALL

The semantic of pointer assignments inside FORALL requires evaluating
the targets (RHS) and pointer variables (LHS) of all iterations before
evaluating the assignments.

In practice, if the compiler can prove that the RHS and LHS evaluations
are not impacted by the assignments, the evaluation of the FORALL
assignment statement can be done in a single loop.
However, if the compiler cannot prove this, it needs to "save" the addresses
of the targets and/or the pointer descriptors of each iterations before doing
the assignments.

This patch implement the most common cases where there is no lower bound spec,
no bounds remapping, the LHS is not polymorphic, and the RHS is not NULL.

The HLFIR operation used to represent assignments inside FORALL can be used
for pointer assignments to (the only difference being that the LHS is a
descriptor address).

    [16 lines not shown]
DeltaFile
+200-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-codegen.fir
+111-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
+80-24flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
+62-3flang/lib/Lower/Bridge.cpp
+33-5flang/lib/Optimizer/Builder/HLFIRTools.cpp
+24-0flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+510-327 files not shown
+561-3813 files

LLVM/project 559f55dflang/lib/Lower Bridge.cpp, flang/lib/Optimizer/Builder HLFIRTools.cpp TemporaryStorage.cpp

[flang] implement simple pointer assignments inside FORALL

The semantic of pointer assignments inside FORALL requires evaluating
the targets (RHS) and pointer variables (LHS) of all iterations before
evaluating the assignments.

In practice, if the compiler can prove that the RHS and LHS evaluations
are not impacted by the assignments, the evaluation of the FORALL
assignment statement can be done in a single loop.
However, if the compiler cannot prove this, it needs to "save" the addresses
of the targets and/or the pointer descriptors of each iterations before doing
the assignments.

This patch implement the most common cases where there is no lower bound spec,
no bounds remapping, the LHS is not polymorphic, and the RHS is not NULL.

The HLFIR operation used to represent assignments inside FORALL can be used
for pointer assignments to (the only difference being that the LHS is a
descriptor address).

    [16 lines not shown]
DeltaFile
+200-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-codegen.fir
+112-0flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
+80-24flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
+62-3flang/lib/Lower/Bridge.cpp
+33-5flang/lib/Optimizer/Builder/HLFIRTools.cpp
+24-0flang/lib/Optimizer/Builder/TemporaryStorage.cpp
+511-327 files not shown
+562-3813 files

LLVM/project 519ae24llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/trunk
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+102,453-36,85810,567 files not shown
+953,290-609,13410,573 files

LLVM/project 03c851allvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/nest-base

Conflicts:
        clang/test/CoverageMapping/mcdc-single-cond.cpp
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,782-7,782llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+7,427-7,427llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+7,255-7,255llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+6,967-6,967llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+102,453-36,85810,567 files not shown
+953,290-609,13410,573 files

LLVM/project d6cb61allvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/bitmapaddr
DeltaFile
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LLVM/project 457cf4bllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/mcdcstate
DeltaFile
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LLVM/project aac9c6dllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/lnot
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
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LLVM/project e57bdccllvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/tests' into users/chapuni/mcdc/nest/expect
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
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LLVM/project 9a175d0llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/chapuni/mcdc/nest/tests
DeltaFile
+65,595-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
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+953,289-609,03210,571 files

LLVM/project e45a72allvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll

refactor

Created using spr 1.3.4
DeltaFile
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LLVM/project d9751a3llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2f16.v8f16.ll

Merge branch 'main' into users/chapuni/yaml/newgen

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-logical-mixed.cpp
        llvm/test/tools/llvm-cov/Inputs/branch-macros.cpp
DeltaFile
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