LLVM / project - FreshBSD

LLVM/project 552f6c9 — llvm/test/CodeGen/X86 vector-interleaved-store-i8-stride-7.ll vector-interleaved-store-i16-stride-6.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-ld1.ll

users/fmayer/spr/mte-generalize-overalignment-size-of-mte-globals

rebase

Created using spr 1.3.4

Delta		File
+3,128	-3,170	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,487	-2,510	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,716	-1,780	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+15,343	-11,608	4,566 files not shown
+159,258	-104,313	4,572 files

LLVM/project 85e290b — llvm/test/CodeGen/AMDGPU bf16.ll, llvm/test/CodeGen/NVPTX cmpxchg-sm70.ll cmpxchg-sm90.ll

3 days ago by Michael Kruse on ⎇

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' into users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+7,350	-4,196	llvm/test/CodeGen/AMDGPU/bf16.ll
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
+5,680	-0	llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+90,478	-10,369	6,999 files not shown
+425,286	-177,378	7,005 files

LLVM/project 2c57c89 — llvm/test/Analysis/CostModel/AArch64 arith-widening.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll

4 days ago by Helena Kotas on ⎇

users/hekota/pr-130338-remove-old-res-middle

Merge branch 'main' of https://github.com/llvm/llvm-project into remove-old-res-middle

Delta		File
+2,099	-2,096	llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+2,053	-2,052	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
+1,434	-1,828	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+2,915	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+1,434	-1,418	llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+940	-1,896	llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+10,875	-9,290	2,274 files not shown
+97,298	-62,357	2,280 files

LLVM/project dc66ca4 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll, llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll

6 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvfiximprove-max-safe-distance-analysis

Rebase, address comments

Created using spr 1.3.5

Delta		File
+6,173	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
+0	-6,173	llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
+3,951	-0	llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746	-1,734	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,348	-1,952	llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+17,078	-9,859	2,714 files not shown
+131,118	-67,392	2,720 files

LLVM/project d4e79af — llvm/test/CodeGen/AMDGPU global_atomics_scan_fadd.ll global_atomics_scan_fsub.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

6 days ago by Krzysztof Parzyszek via GitHub on ⎇

users/kparzysz/spr/o03-cancel-directive-name

Merge branch 'main' into users/kparzysz/spr/o03-cancel-directive-name

Delta		File
+2,927	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+1,246	-1,246	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,214	-1,214	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+10,668	-4,920	1,301 files not shown
+51,893	-31,213	1,307 files

LLVM/project 7dc7264 — llvm/test/CodeGen/AMDGPU shufflevector.v2i64.v8i64.ll shufflevector.v2bf16.v8bf16.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

7 days ago by yangzhaoxin on ⎇

users/ylzsx/r-tls-noie

Merge branch 'main' into users/ylzsx/r-tls-noie

Delta		File
+65,595	-0	llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+29,745	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
+27,655	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
+27,139	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
+25,933	-0	llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+203,722	-0	16,100 files not shown
+2,040,184	-604,855	16,106 files

LLVM/project 33f623d — llvm/test/CodeGen/AMDGPU vni8-across-blocks.ll shufflevector-physreg-copy.ll, llvm/test/CodeGen/RISCV qci-interrupt-attr.ll qci-interrupt-attr-fpr.ll

9 days ago by Krzysztof Parzyszek via GitHub on ⎇

users/kparzysz/spr/o02-metadirective-flush

Merge branch 'main' into users/kparzysz/spr/o02-metadirective-flush

Delta		File
+2,927	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+603	-1,206	llvm/test/CodeGen/X86/matrix-multiply.ll
+706	-540	llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+812	-407	llvm/test/CodeGen/Thumb2/mve-vld3.ll
+795	-0	llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
+8,664	-2,153	747 files not shown
+23,408	-10,802	753 files

LLVM/project 2ff290b — llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll qci-interrupt-attr.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-store-i8-stride-7.ll

9 days ago by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible-1

Rebase

Created using spr 1.3.5

Delta		File
+3,951	-0	llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+3,860	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-ld1.ll
+1,746	-1,734	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,532	-1,534	llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+2,927	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+2,821	-0	llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+16,837	-3,268	1,830 files not shown
+73,594	-27,591	1,836 files

LLVM/project 2c8b2dc — compiler-rt/include/orc_rt c_api.h, compiler-rt/lib/orc wrapper_function_utils.h macho_platform.cpp

9 days ago by Lang Hames on ⎇

main

[ORC-RT] Rename 'orc_rt_*CWrapper*' types and functions to 'orc_rt_*Wrapper*'.

The orc_rt_ prefix implies C API anyway (the C++ API should use the orc_rc::
namespace), so the 'C' is redundant here.

Delta		File
+55	-53	compiler-rt/lib/orc/tests/unit/c_api_test.cpp
+36	-36	compiler-rt/include/orc_rt/c_api.h
+22	-22	compiler-rt/lib/orc/wrapper_function_utils.h
+12	-12	compiler-rt/lib/orc/tests/unit/wrapper_function_utils_test.cpp
+10	-10	compiler-rt/lib/orc/macho_platform.cpp
+9	-9	compiler-rt/lib/orc/elfnix_platform.cpp
+144	-142	4 files not shown
+156	-154	10 files

LLVM/project 16e61cf — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Jan 7 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-riscv_atomich-and-zawrs-builtins

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	45,766 files not shown
+4,106,333	-2,097,168	45,772 files

LLVM/project d7d008b — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Dec 11, 2024 by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/libclocale-update-grouping-tests

Merge branch 'main' into users/vitalybuka/spr/libclocale-update-grouping-tests

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	43,237 files not shown
+4,159,794	-2,020,023	43,243 files

LLVM/project e51ce07 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprasmprintercallgraphsection-emit-call-graph-section-4

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 17ee91d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.asmprintercallgraphsection-emit-call-graph-section-4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 4f31680 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

Rebase on top of upstream main. Remove opt has_value, value use.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project a993e6d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 26a149b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 2cb9de4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project a3ca3e2 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 08dc8a4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 23ac5ef — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallgraphsection-add-call-graph-section-options-and-documentation

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project c0b6218 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by LLVM GN Syncbot via prabhukr on ⎇

users/Prabhuk/sprmain.callgraphsection-add-call-graph-section-options-and-documentation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files

LLVM/project 7be0b9e — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,726	-528,067	20,522 files

LLVM/project 6642107 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit '03a98412270d51e6703118329a0d0d0ce1b0cf29' into users/meinersbur/irbuilder-extract

Delta		File
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,314	-3,494	llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+2,461	-2,481	llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+33,259	-12,669	4,211 files not shown
+227,743	-108,376	4,217 files

LLVM/project b1cb13e — clang/test/OpenMP nvptx_SPMD_codegen.cpp target_teams_distribute_reduction_codegen.cpp, llvm/test/CodeGen/AMDGPU offset-split-flat.ll carryout-selection.ll

Nov 3, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract

Merge commit '4add729e3e77e641ae2c8c44214263bdd1ae6406' into users/meinersbur/irbuilder-extract

Delta		File
+26,460	-181	clang/test/OpenMP/nvptx_SPMD_codegen.cpp
+8,503	-32	clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp
+2,577	-1,095	llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
+3,484	-44	clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp
+2,199	-697	clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp
+2,683	-175	llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+45,906	-2,224	1,157 files not shown
+98,888	-18,597	1,163 files

LLVM/project ad220d9 — clang/test/OpenMP target_teams_distribute_parallel_for_simd_schedule_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp, llvm/test/CodeGen/X86 large-gep-chain.ll

Nov 2, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit 'e2d1e2183a9615c669392eefcfe632cc0b59a649' into users/meinersbur/irbuilder-extract

Delta		File
+0	-116,484	llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+0	-115,677	llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+0	-98,954	llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+25,277	-25,277	llvm/test/CodeGen/X86/large-gep-chain.ll
+9,540	-24,668	clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+9,364	-24,292	clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+44,181	-405,352	42,672 files not shown
+3,761,432	-2,721,703	42,678 files

LLVM/project 03a9841 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Nov 2, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit '14120227a34365e829d05c1413033d235d7d272c' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,314	-3,494	llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+2,461	-2,481	llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+33,259	-12,669	4,211 files not shown
+227,743	-108,376	4,217 files

LLVM/project 4add729 — clang/test/OpenMP nvptx_SPMD_codegen.cpp target_teams_distribute_reduction_codegen.cpp, llvm/test/CodeGen/AMDGPU offset-split-flat.ll carryout-selection.ll

Nov 1, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit '5da674492a5acf8e08a58f611e39ff4cd6a16dfe^' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+26,460	-181	clang/test/OpenMP/nvptx_SPMD_codegen.cpp
+8,503	-32	clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp
+2,577	-1,095	llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
+3,484	-44	clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp
+2,199	-697	clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp
+2,683	-175	llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+45,906	-2,224	1,157 files not shown
+98,888	-18,597	1,163 files

LLVM/project 254d2eb — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 1, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvenable-max-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,088 files not shown
+2,335,277	-1,222,511	26,094 files