LLVM / project - FreshBSD

LLVM/project f0f728f — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/elfwasm-update-datalayout-strings-to-latest-version

rebase and fix commit message

Created using spr 1.3.6-beta.1

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,589	-7,092	15,395 files not shown
+1,090,107	-393,768	15,401 files

LLVM/project e62ef5f — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/runtimes-allow-building-against-an-installed-llvm-tree

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,621 files not shown
+1,489,827	-860,953	17,627 files

LLVM/project 58f7320 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 24, 2024 by Florian Hahn via Alex Richardson on ⎇

users/arichardson/spr/main.runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	17,620 files not shown
+1,489,825	-860,949	17,626 files

LLVM/project 922f38c — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 24, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-add-profile-density-computation

show-density=true, threshold=50

Created using spr 1.3.4

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,552 files not shown
+569,777	-266,956	9,558 files

LLVM/project b4be4af — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 24, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-add-profile-density-computation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,551 files not shown
+569,775	-266,954	9,557 files

LLVM/project 942a6e9 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/sanitizer_allocatorcpp-ensure-at-least-sizeofvoid-alignment

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	46,218 files not shown
+4,313,171	-1,926,653	46,224 files

LLVM/project 9028b4e — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 15, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-add-options-for-annotate-tablejump

reimplement

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	15,921 files not shown
+1,245,447	-839,596	15,927 files

LLVM/project 941da60 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 14, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-support-perf2bolt-n-in-the-driver

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,240 files not shown
+560,523	-263,795	9,246 files

LLVM/project 7b06db7 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-initial-support-of-memcmp-expansion

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	9,418 files not shown
+599,216	-259,096	9,424 files

LLVM/project 60baf2a — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-add-initial-support-of-memcmp-expansion

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	9,418 files not shown
+596,040	-255,920	9,424 files

LLVM/project 8ca0b2a — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-tests-for-memcmp-expansion

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	9,418 files not shown
+596,040	-255,920	9,424 files

LLVM/project fb87349 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 8, 2024 by Florian Mayer on ⎇

users/fmayer/spr/mte-do-not-allow-local-aliases-to-mte-globals

reb

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	10,988 files not shown
+937,390	-704,057	10,994 files

LLVM/project d38562a — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 3, 2024 by Paul Kirth on ⎇

users/ilovepi/spr/mlirtest-test-conversion-of-tosa-to-emitc-via-linalg

Update script and test corpus

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,693 files not shown
+2,060,103	-1,198,997	26,699 files

LLVM/project 87bb491 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 1, 2024 by Matheus Izvekov on ⎇

users/mizvekov/clang-p0522-complete-implementation

Merge remote-tracking branch 'origin/main' into users/mizvekov/clang-p0522-complete-implementation

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	7,412 files not shown
+520,006	-213,331	7,418 files

LLVM/project 6f9b985 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 1, 2024 by Nathan Lanza on ⎇

users/lanza/sprcir-build-out-ast-consumer-patterns-to-reach-the-entry-point-into-cirgen

rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	10,819 files not shown
+930,831	-708,375	10,825 files

LLVM/project ab65708 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Sep 30, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvinitial-support-for-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase, address comments

Created using spr 1.3.5

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+62,888	-7,547	8,444 files not shown
+565,751	-221,162	8,450 files

LLVM/project c67340a — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 25, 2024 by Corbin Robeck via GitHub on ⎇

users/crobeck/remove-renamedInGFX9-bit

Merge branch 'main' into users/crobeck/remove-renamedInGFX9-bit

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	33,290 files not shown
+2,709,253	-1,363,414	33,296 files

LLVM/project 9bc6c9e — llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 25, 2024 by Fangrui Song on ⎇

users/MaskRay/spr/riscv-restore-dw_eh_pe_uleb128-call-site-encoding-for-gcc_except_table

rebase

Created using spr 1.3.5-bogner

Delta		File
+22,225	-17,874	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+19,816	-19,812	llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+105,211	-106,884	50,557 files not shown
+5,033,721	-2,425,704	50,563 files

LLVM/project 09ebdca — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Sep 20, 2024 by Florian Mayer on ⎇

users/fmayer/spr/hwasan-optimize-attrinfer-fix-for-selective-hwasan

rebase

Created using spr 1.3.4

Delta		File
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+1,929	-2,007	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+30,971	-10,176	3,341 files not shown
+176,161	-76,106	3,347 files

LLVM/project 0b48b3b — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Sep 20, 2024 by Victor Campos via GitHub on ⎇

users/vhscampos/smallset-simplify

Merge branch 'main' into users/vhscampos/smallset-simplify

Delta		File
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,314	-3,494	llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+41,060	-10,188	3,244 files not shown
+179,435	-81,881	3,250 files

LLVM/project 130f1cf — clang/unittests/Rename RenameClassTest.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp.ll vfma-vp.ll

Sep 19, 2024 by Fangrui Song on ⎇

users/MaskRay/spr/parallel-ensure-getthreadindex0-for-sequential-tasks

.

Created using spr 1.3.5-bogner

Delta		File
+581	-1,883	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+2,087	-362	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+1,718	-195	llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+1,154	-8	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+0	-820	clang/unittests/Rename/RenameClassTest.cpp
+664	-17	llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+6,204	-3,285	533 files not shown
+29,515	-11,437	539 files

LLVM/project 7f1bd09 — clang/unittests/Rename RenameClassTest.cpp, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll setcc-fp-vp.ll

Sep 18, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/sanitizer-fix-intersecting-stacks-workaround

rebase

Created using spr 1.3.4

Delta		File
+2,087	-362	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+1,718	-195	llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+1,154	-8	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+37	-906	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+0	-820	clang/unittests/Rename/RenameClassTest.cpp
+664	-17	llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+5,660	-2,308	534 files not shown
+28,884	-10,622	540 files

LLVM/project 4e08384 — clang/unittests/Rename RenameClassTest.cpp, llvm/test/CodeGen/AArch64 vecreduce-bitext.ll

Sep 18, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/sanitizer-switch-from-lazy-threaddescriptorsize

rebase

Created using spr 1.3.4

Delta		File
+2,087	-362	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+1,718	-195	llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+1,202	-0	llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
+1,154	-8	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+37	-906	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+0	-820	clang/unittests/Rename/RenameClassTest.cpp
+6,198	-2,291	796 files not shown
+39,515	-13,155	802 files

LLVM/project 3e35f76 — clang/unittests/Rename RenameClassTest.cpp, llvm/test/CodeGen/AArch64 vecreduce-bitext.ll

Sep 18, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/main.sanitizer-switch-from-lazy-threaddescriptorsize

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,087	-362	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+1,718	-195	llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+1,202	-0	llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
+1,154	-8	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+37	-906	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+0	-820	clang/unittests/Rename/RenameClassTest.cpp
+6,198	-2,291	796 files not shown
+39,515	-13,155	802 files

LLVM/project 99c48d8 — clang/unittests/Rename RenameClassTest.cpp, llvm/test/CodeGen/AArch64 vecreduce-bitext.ll

Sep 18, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/nfcsanitizer-move-inittlssize

rebase

Created using spr 1.3.4

Delta		File
+2,087	-362	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+1,718	-195	llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+1,202	-0	llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
+1,154	-8	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+37	-906	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+0	-820	clang/unittests/Rename/RenameClassTest.cpp
+6,198	-2,291	796 files not shown
+39,509	-13,155	802 files

LLVM/project ce32abb — clang/unittests/Rename RenameClassTest.cpp, llvm/test/CodeGen/AArch64 vecreduce-bitext.ll

Sep 18, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/main.nfcsanitizer-move-inittlssize

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,087	-362	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+1,718	-195	llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+1,202	-0	llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
+1,154	-8	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+37	-906	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+0	-820	clang/unittests/Rename/RenameClassTest.cpp
+6,198	-2,291	796 files not shown
+39,509	-13,155	802 files

LLVM/project 6356597 — clang/unittests/Rename RenameClassTest.cpp, llvm/test/CodeGen/AArch64 vecreduce-bitext.ll

Sep 18, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/main.nfcsanitizer-move-inittlssize-into-initializeplatformearly

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,087	-362	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+1,718	-195	llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+1,202	-0	llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
+1,154	-8	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+37	-906	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+0	-820	clang/unittests/Rename/RenameClassTest.cpp
+6,198	-2,291	796 files not shown
+39,509	-13,155	802 files

LLVM/project c0ad0fa — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Aiden Grossman on ⎇

users/boomanaiden154/x86-cpuid-compilerrt-test-infra

Merge branch 'main' into users/boomanaiden154/x86-cpuid-compilerrt-test-infra

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	16,027 files not shown
+1,282,243	-905,121	16,033 files

LLVM/project 8a42b19 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Chao Chen via GitHub on ⎇

users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter

Merge branch 'main' into users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,984 files not shown
+1,067,270	-799,696	13,990 files

LLVM/project 4eee0cf — mlir/test/python execution_engine.py

Sep 18, 2024 by Tulio Magno Quites Machado Filho via GitHub on ⎇

main

[MLIR] Reuse the path to runner_utils libraries (#108579)

Prefer to get the path to libmlir_runner_utils and
libmlir_c_runner_utils via %mlir_runner_utils and %mlir_c_runner_utils.
Fallback to the previous paths only if they aren't defined.

This ensures the test will pass regardless of the build configuration
used downstream.

Delta		File
+11	-5	mlir/test/python/execution_engine.py
+11	-5	1 files