LLVM / project - FreshBSD

LLVM/project 87bb491 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 1, 2024 by Matheus Izvekov on ⎇

users/mizvekov/clang-p0522-complete-implementation

Merge remote-tracking branch 'origin/main' into users/mizvekov/clang-p0522-complete-implementation

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	7,412 files not shown
+520,006	-213,331	7,418 files

LLVM/project 6f9b985 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 1, 2024 by Nathan Lanza on ⎇

users/lanza/sprcir-build-out-ast-consumer-patterns-to-reach-the-entry-point-into-cirgen

rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	10,819 files not shown
+930,831	-708,375	10,825 files

LLVM/project ab65708 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll

Sep 30, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvinitial-support-for-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase, address comments

Created using spr 1.3.5

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+62,888	-7,547	8,444 files not shown
+565,751	-221,162	8,450 files

LLVM/project c67340a — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 25, 2024 by Corbin Robeck via GitHub on ⎇

users/crobeck/remove-renamedInGFX9-bit

Merge branch 'main' into users/crobeck/remove-renamedInGFX9-bit

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	33,290 files not shown
+2,709,253	-1,363,414	33,296 files

LLVM/project 9bc6c9e — llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 25, 2024 by Fangrui Song on ⎇

users/MaskRay/spr/riscv-restore-dw_eh_pe_uleb128-call-site-encoding-for-gcc_except_table

rebase

Created using spr 1.3.5-bogner

Delta		File
+22,225	-17,874	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+19,816	-19,812	llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+105,211	-106,884	50,557 files not shown
+5,033,721	-2,425,704	50,563 files

LLVM/project 09ebdca — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Sep 20, 2024 by Florian Mayer on ⎇

users/fmayer/spr/hwasan-optimize-attrinfer-fix-for-selective-hwasan

rebase

Created using spr 1.3.4

Delta		File
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+1,929	-2,007	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+30,971	-10,176	3,341 files not shown
+176,161	-76,106	3,347 files

LLVM/project 0b48b3b — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Sep 20, 2024 by Victor Campos via GitHub on ⎇

users/vhscampos/smallset-simplify

Merge branch 'main' into users/vhscampos/smallset-simplify

Delta		File
+10,102	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,314	-3,494	llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+41,060	-10,188	3,244 files not shown
+179,435	-81,881	3,250 files

LLVM/project c0ad0fa — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Aiden Grossman on ⎇

users/boomanaiden154/x86-cpuid-compilerrt-test-infra

Merge branch 'main' into users/boomanaiden154/x86-cpuid-compilerrt-test-infra

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	16,027 files not shown
+1,282,243	-905,121	16,033 files

LLVM/project 8a42b19 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Chao Chen via GitHub on ⎇

users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter

Merge branch 'main' into users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,984 files not shown
+1,067,270	-799,696	13,990 files

LLVM/project 7172da5 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 18, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-add-profile-density-computation

rebase, profile-density-threshold=0

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,413 files not shown
+1,076,696	-789,199	13,419 files

LLVM/project 60d9539 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-add-profile-density-computation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	13,412 files not shown
+1,076,695	-789,198	13,418 files

LLVM/project 4ad90e1 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-set-rawbranchcount-in-dataaggregator

rebase

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	14,739 files not shown
+1,174,924	-859,037	14,745 files

LLVM/project 3f21bd8 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 18, 2024 by harishch4 via Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-set-rawbranchcount-in-dataaggregator

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	14,739 files not shown
+1,174,924	-859,037	14,745 files

LLVM/project 835b141 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 17, 2024 by Fangrui Song on ⎇

users/MaskRay/spr/x86-dont-fold-offsets-that-are-too-closer-to-int32_min-in-non-large-code-models

be much more conservative

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	19,063 files not shown
+1,530,803	-1,015,737	19,069 files

LLVM/project 0a15015 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Sep 16, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpadd-subvector-vectorization-for-non-load-nodes

Rebase

Created using spr 1.3.5

Delta		File
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+8,355	-1,124	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+1,929	-2,007	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+29,224	-10,154	2,946 files not shown
+151,221	-65,222	2,952 files

LLVM/project 05e21e8 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Sep 16, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpvectorize-of-gathered-loads

Rebase, address comments

Created using spr 1.3.5

Delta		File
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+8,355	-1,124	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+1,929	-2,007	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+29,224	-10,154	2,947 files not shown
+152,315	-65,123	2,953 files

LLVM/project affdc53 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AArch64 fptosi-sat-vector.ll fptoui-sat-vector.ll

Sep 16, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpinitial-support-for-non-power-of-2-but-still-whole-register-number-of-elements-in-operands-1

Rebase, address comments

Created using spr 1.3.5

Delta		File
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+8,355	-1,124	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+4,636	-2,363	llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+3,650	-1,844	llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+1,929	-2,007	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,558	-1,475	llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+29,224	-10,154	2,760 files not shown
+158,638	-67,941	2,766 files

LLVM/project 149a150 — clang/test/Misc target-invalid-cpu-note.c, clang/test/Preprocessor predefined-arch-macros.c

Sep 16, 2024 by Ganesh Gopalasubramanian via Tobias Hieta on ⎇

release/19.x

[X86] AMD Zen 5 Initial enablement

Delta		File
+142	-0	clang/test/Preprocessor/predefined-arch-macros.c
+20	-0	compiler-rt/lib/builtins/cpu_model/x86.c
+19	-0	llvm/lib/TargetParser/Host.cpp
+15	-0	llvm/lib/Target/X86/X86.td
+4	-4	clang/test/Misc/target-invalid-cpu-note.c
+5	-0	llvm/lib/TargetParser/X86TargetParser.cpp
+205	-4	24 files not shown
+238	-4	30 files

LLVM/project bfeba7f — clang/test/CodeGen/aarch64-sme2-intrinsics acle_sme2_min.c acle_sme2_max.c, clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c acle_sve_reinterpret-bfloat.c

Sep 14, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/sanitizer-fix-intersecting-stacks-workaround

rebase

Created using spr 1.3.4

Delta		File
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+1,056	-1,200	clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c
+1,056	-1,200	clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c
+1,776	-270	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c
+552	-984	clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_store.c
+704	-800	clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c
+14,240	-5,795	557 files not shown
+40,509	-24,976	563 files

LLVM/project 30e0706 — clang/test/CodeGen/aarch64-sme2-intrinsics acle_sme2_min.c acle_sme2_max.c, clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c acle_sve_reinterpret-bfloat.c

Sep 14, 2024 by Arteen Abrishami via Vitaly Buka on ⎇

users/vitalybuka/spr/main.sanitizer-fix-intersecting-stacks-workaround

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+1,056	-1,200	clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c
+1,056	-1,200	clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c
+1,776	-270	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c
+552	-984	clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_store.c
+704	-800	clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c
+14,240	-5,795	557 files not shown
+40,509	-24,976	563 files

LLVM/project 02e4186 — clang/lib/Basic/Targets X86.cpp, clang/test/Preprocessor predefined-arch-macros.c

Sep 13, 2024 by Ganesh via GitHub on ⎇

main

[X86] AMD Zen 5 Initial enablement (#107964)

This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.

Delta		File
+142	-0	clang/test/Preprocessor/predefined-arch-macros.c
+20	-0	compiler-rt/lib/builtins/cpu_model/x86.c
+19	-0	llvm/lib/TargetParser/Host.cpp
+15	-0	llvm/lib/Target/X86/X86.td
+5	-0	llvm/lib/TargetParser/X86TargetParser.cpp
+4	-0	clang/lib/Basic/Targets/X86.cpp
+205	-0	24 files not shown
+238	-0	30 files

LLVM/project 1c8b150 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 11, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Less naive pseudo probe function matching: for each non-matching YamlBF, determine best matching binary inline subtrees, find corresponding binary functions, attach the profile to binary function without a profile and most probes

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,020 files not shown
+1,054,256	-818,251	13,026 files

LLVM/project 836f08b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 11, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,020 files not shown
+1,054,117	-818,226	13,026 files

LLVM/project 0f455d0 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 4, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

rebase

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,304 files not shown
+1,065,629	-822,709	13,310 files

LLVM/project bfa0afc — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 4, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	13,305 files not shown
+1,065,625	-823,010	13,311 files

LLVM/project d275d17 — llvm/test/CodeGen/AMDGPU atomic_optimizations_local_pointer.ll global_atomics_scan_fadd.ll, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-vshift.ll

Aug 27, 2024 by Nathan Lanza on ⎇

users/lanza/sprcir-build-out-ast-consumer-patterns-to-reach-the-entry-point-into-cirgen

fix lit tes

Created using spr 1.3.5

Delta		File
+16,170	-3,365	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+8,242	-3,692	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+7,904	-3,210	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+9,778	-303	llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+9,827	-0	llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+9,694	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+61,615	-10,570	16,467 files not shown
+926,718	-451,777	16,473 files

LLVM/project 5e4d38d — llvm/test/CodeGen/AMDGPU global-atomicrmw-fadd.ll memory-legalizer-global-agent.ll

Aug 26, 2024 by Alex Richardson on ⎇

users/arichardson/spr/runtimes-allow-building-against-an-installed-llvm-tree

rebased on latest HEAD

Created using spr 1.3.6-beta.1

Delta		File
+23,315	-0	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+13,562	-6,388	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
+16,240	-3,435	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+13,029	-6,571	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
+12,862	-6,132	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
+12,041	-6,669	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
+91,049	-29,195	33,105 files not shown
+2,476,872	-986,650	33,111 files

LLVM/project e288141 — llvm/test/CodeGen/AMDGPU global-atomicrmw-fadd.ll memory-legalizer-global-agent.ll

Aug 26, 2024 by vporpo via Alex Richardson on ⎇

users/arichardson/spr/main.runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+23,315	-0	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+13,562	-6,388	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
+16,240	-3,435	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+13,029	-6,571	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
+12,862	-6,132	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
+12,041	-6,669	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
+91,049	-29,195	33,105 files not shown
+2,476,872	-986,650	33,111 files

LLVM/project 94132fc — clang/include/clang/Sema Sema.h, clang/test/OpenMP nesting_of_regions.cpp

Aug 19, 2024 by Fangrui Song on ⎇

users/MaskRay/spr/driver-default-msmall-data-limit-to-0-and-clean-up-code

rebase. remove warn_drv_unsupported_sdata

Created using spr 1.3.5-bogner

Delta		File
+23,315	-0	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+11,571	-11,038	clang/include/clang/Sema/Sema.h
+14,822	-5,432	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
+14,223	-5,559	llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
+16,260	-3,461	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+0	-19,580	clang/test/OpenMP/nesting_of_regions.cpp
+80,191	-45,070	38,395 files not shown
+3,008,922	-1,208,090	38,401 files

LLVM/project 029a8d3 — clang/test/OpenMP task_codegen.cpp, libc/newhdrgen/yaml math.yaml

Aug 14, 2024 by Justin Bogner on ⎇

users/bogner/sprdxilanalysis-implement-enough-of-dxilresourceanalysis-for-buffers

Update test to match comment

Created using spr 1.3.5-bogner

Delta		File
+9,694	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+2,593	-2,593	clang/test/OpenMP/task_codegen.cpp
+5,032	-0	llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll
+1,940	-1,646	libc/newhdrgen/yaml/math.yaml
+3,300	-0	llvm/test/MC/Disassembler/X86/avx10_2ni-32.txt
+3,300	-0	llvm/test/MC/Disassembler/X86/avx10_2ni-64.txt
+25,859	-4,239	3,744 files not shown
+208,244	-93,524	3,750 files