LLVM / project - FreshBSD

LLVM/project c55290e — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Simon Pilgrim via Alex Richardson on ⎇

users/arichardson/spr/main.datalayoutlangref-split-non-integral-and-unstable-pointer-properties

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,113	-881,962	18,271 files

LLVM/project 35afb97 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayoutlangref-split-non-integral-and-unstable-pointer-properties

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,112	-881,961	18,271 files

LLVM/project 82c7f36 — libcxx/include/__cxx03 regex string, llvm/test/CodeGen/AArch64 neon-dotreduce.ll

Oct 25, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-add-profile-density-computation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+6,804	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+5,836	-0	libcxx/include/__cxx03/regex
+4,352	-0	libcxx/include/__cxx03/string
+2,870	-1,287	llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+3,643	-417	llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
+32,701	-1,704	5,320 files not shown
+397,120	-90,981	5,326 files

LLVM/project 4bd5209 — clang/lib/Headers movrs_avx10_2intrin.h, clang/test/CodeGen/X86 movrs-avx10.2-builtins.c

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayout-refactor-storage-of-non-integral-address-spaces

address feedback

Created using spr 1.3.6-beta.1

Delta		File
+333	-0	llvm/test/CodeGen/AArch64/GlobalISel/legalize-atan2.mir
+329	-0	llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll
+174	-0	clang/lib/Headers/movrs_avx10_2intrin.h
+171	-0	clang/test/CodeGen/X86/movrs-avx10.2-builtins.c
+163	-0	llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll
+98	-0	llvm/test/MC/Disassembler/X86/movrs-avx10-64.txt
+1,268	-0	91 files not shown
+2,469	-72	97 files

LLVM/project 1bda0dd — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayout-refactor-storage-of-non-integral-address-spaces

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,901 files not shown
+1,517,614	-867,434	17,907 files

LLVM/project f0f728f — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/elfwasm-update-datalayout-strings-to-latest-version

rebase and fix commit message

Created using spr 1.3.6-beta.1

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,589	-7,092	15,395 files not shown
+1,090,107	-393,768	15,401 files

LLVM/project c4248fa — clang/lib/Headers movrs_avx10_2intrin.h, clang/test/CodeGen/X86 movrs-avx10.2-builtins.c movrs-avx10.2-builtins-error-32.c

Oct 25, 2024 by Freddy Ye via GitHub on ⎇

main

[X86] Support MOVRS and AVX10.2 instructions. (#113274)

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

Delta		File
+329	-0	llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll
+174	-0	clang/lib/Headers/movrs_avx10_2intrin.h
+171	-0	clang/test/CodeGen/X86/movrs-avx10.2-builtins.c
+163	-0	llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll
+98	-0	llvm/test/MC/Disassembler/X86/movrs-avx10-64.txt
+98	-0	clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c
+1,033	-0	24 files not shown
+1,593	-0	30 files

LLVM/project e62ef5f — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/runtimes-allow-building-against-an-installed-llvm-tree

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,621 files not shown
+1,489,827	-860,953	17,627 files

LLVM/project 58f7320 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 24, 2024 by Florian Hahn via Alex Richardson on ⎇

users/arichardson/spr/main.runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	17,620 files not shown
+1,489,825	-860,949	17,626 files

LLVM/project 922f38c — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 24, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-add-profile-density-computation

show-density=true, threshold=50

Created using spr 1.3.4

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,552 files not shown
+569,777	-266,956	9,558 files

LLVM/project b4be4af — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 24, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-add-profile-density-computation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,551 files not shown
+569,775	-266,954	9,557 files

LLVM/project 942a6e9 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/sanitizer_allocatorcpp-ensure-at-least-sizeofvoid-alignment

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	46,218 files not shown
+4,313,171	-1,926,653	46,224 files

LLVM/project 9e3d465 — compiler-rt/lib/builtins/cpu_model x86.c, llvm/lib/TargetParser Host.cpp

Oct 23, 2024 by Freddy Ye via GitHub on ⎇

main

[X86] Update Model value for Arrow Lake. (#113273)

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

Delta		File
+2	-0	compiler-rt/lib/builtins/cpu_model/x86.c
+2	-0	llvm/lib/TargetParser/Host.cpp
+4	-0	2 files

LLVM/project eb75607 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU flat_atomics_i64_system_noprivate.ll flat_atomics_i64_noprivate.ll

Oct 19, 2024 by Matt Arsenault via GitHub on ⎇

users/arsenm/amdgpu-si-fold-operands-frame-index-add

Merge branch 'main' into users/arsenm/amdgpu-si-fold-operands-frame-index-add

Delta		File
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+6,804	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+932	-5,548	llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
+2,814	-2,432	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+754	-4,432	llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
+23,790	-15,702	5,384 files not shown
+248,483	-137,544	5,390 files

LLVM/project 9028b4e — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 15, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-add-options-for-annotate-tablejump

reimplement

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	15,921 files not shown
+1,245,447	-839,596	15,927 files

LLVM/project 09b149c — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU memcpy-param-combinations.ll memmove-param-combinations.ll

Oct 14, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvinitial-support-for-safe-distance-in-predicated-datawithevl-vectorization-mode

Address comments, rebase

Created using spr 1.3.5

Delta		File
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,630	-3,624	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+932	-5,548	llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
+754	-4,432	llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
+26,210	-20,825	4,983 files not shown
+205,158	-113,501	4,989 files

LLVM/project 941da60 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 14, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-support-perf2bolt-n-in-the-driver

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,240 files not shown
+560,523	-263,795	9,246 files

LLVM/project efa1900 — llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir legalize-load-private.mir, llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll

Oct 12, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.boltnfc-speedup-batwritemaps

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.4

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+6,905	-7	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+4,660	-1,793	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+55,768	-8,578	5,327 files not shown
+302,437	-141,679	5,333 files

LLVM/project 734092a — llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir legalize-load-private.mir, llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll

Oct 12, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/boltnfc-speedup-batwritemaps

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+6,905	-7	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+4,660	-1,793	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+55,768	-8,578	5,327 files not shown
+302,453	-141,696	5,333 files

LLVM/project ca8d388 — clang/docs LibASTMatchersReference.html, clang/include/clang/ASTMatchers ASTMatchers.h

Oct 10, 2024 by Florian Mayer on ⎇

users/fmayer/spr/mte-do-not-allow-local-aliases-to-mte-globals

rev

Created using spr 1.3.4

Delta		File
+10,807	-1,742	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+2,266	-5,673	clang/docs/LibASTMatchersReference.html
+6,938	-29	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+1,688	-4,141	clang/include/clang/ASTMatchers/ASTMatchers.h
+2,525	-2,525	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+27,514	-17,400	4,087 files not shown
+185,816	-103,343	4,093 files

LLVM/project 8189111 — llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir legalize-load-private.mir, llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll

Oct 9, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-allow-builtin_unreachable-to-be-at-maxsize-address

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+6,905	-7	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+4,660	-1,793	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+55,768	-8,578	5,321 files not shown
+302,370	-141,658	5,327 files

LLVM/project 779c5e9 — llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir legalize-load-private.mir, llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll

Oct 9, 2024 by Maksim Panchenko via Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-allow-builtin_unreachable-to-be-at-maxsize-address

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.4

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+6,905	-7	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+4,660	-1,793	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+55,768	-8,578	5,320 files not shown
+302,334	-141,656	5,326 files

LLVM/project 7b06db7 — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-initial-support-of-memcmp-expansion

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	9,418 files not shown
+599,216	-259,096	9,424 files

LLVM/project 60baf2a — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-add-initial-support-of-memcmp-expansion

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	9,418 files not shown
+596,040	-255,920	9,424 files

LLVM/project 8ca0b2a — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-flat.mir

Oct 9, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-tests-for-memcmp-expansion

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+66,351	-9,265	9,418 files not shown
+596,040	-255,920	9,424 files

LLVM/project fb87349 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 8, 2024 by Florian Mayer on ⎇

users/fmayer/spr/mte-do-not-allow-local-aliases-to-mte-globals

reb

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	10,988 files not shown
+937,390	-704,057	10,994 files

LLVM/project 7705dae — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, libcxx/include module.modulemap

Oct 8, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-support-option-directive

update tests, address @SixWeining's comments.

Created using spr 1.3.5-bogner

Delta		File
+10,775	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+6,905	-7	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+2,525	-2,525	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+1,064	-3,333	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+2,156	-2,041	libcxx/include/module.modulemap
+26,715	-12,914	3,564 files not shown
+152,315	-81,879	3,570 files

LLVM/project 415690f — clang/lib/Sema SemaFunctionEffects.cpp, flang/lib/Lower/OpenMP OpenMP.cpp

Oct 7, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpimprove-masked-loads-vectorization-attempting-gathered-loads

Address comments, Rebase

Created using spr 1.3.5

Delta		File
+0	-3,279	llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
+1,657	-1,604	llvm/test/DebugInfo/NVPTX/debug-info.ll
+957	-1,449	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+1,577	-0	clang/lib/Sema/SemaFunctionEffects.cpp
+571	-571	flang/test/Fir/target-rewrite-complex.fir
+529	-504	flang/lib/Lower/OpenMP/OpenMP.cpp
+5,291	-7,407	1,722 files not shown
+41,311	-30,534	1,728 files

LLVM/project c5f7a32 — compiler-rt/lib/builtins/cpu_model x86.c, llvm/lib/TargetParser Host.cpp

Oct 7, 2024 by RipleyTom via GitHub on ⎇

main

[X86] Add AMD Llano family detection (#111312)

Very simple one liner, adds the missing detection for the Llano family
which is essentially a refreshed K10:
Documentation of the family id:
https://en.wikichip.org/wiki/amd/cpuid#Family_18_.2812h.29
Documentation that it fits into amdfam10:
https://en.wikipedia.org/wiki/AMD_10h#12h

Delta		File
+1	-0	llvm/lib/TargetParser/Host.cpp
+1	-0	compiler-rt/lib/builtins/cpu_model/x86.c
+2	-0	2 files

LLVM/project d38562a — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 3, 2024 by Paul Kirth on ⎇

users/ilovepi/spr/mlirtest-test-conversion-of-tosa-to-emitc-via-linalg

Update script and test corpus

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,693 files not shown
+2,060,103	-1,198,997	26,699 files