LLVM / project - FreshBSD

LLVM/project c7f248d — lldb/docs lldb-gdb-remote.txt, lldb/docs/resources lldbgdbremote.md

Apr 29, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpimprove-reordering-for-consts-splats-and-ops-from-same-nodes-improved-analysis-1

Rebase, address comments

Created using spr 1.3.5

Delta		File
+3,617	-0	llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
+3,478	-0	offload/plugins-nextgen/amdgpu/src/rtl.cpp
+0	-3,478	openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
+2,473	-0	lldb/docs/resources/lldbgdbremote.md
+0	-2,286	lldb/docs/lldb-gdb-remote.txt
+0	-2,225	openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
+9,568	-7,989	3,785 files not shown
+176,968	-104,814	3,791 files

LLVM/project 0b7ebea — flang/test/Lower/OpenMP/FIR target.f90 if-clause.f90, libcxx/include/__format escaped_output_table.h

Apr 28, 2024 by Krzysztof Parzyszek via GitHub on ⎇

users/kparzysz/leaforself-unit

Merge branch 'main' into users/kparzysz/leaforself-unit

Delta		File
+733	-1,092	libcxx/include/__format/escaped_output_table.h
+513	-513	llvm/test/MC/RISCV/rvv/zvlsseg.s
+916	-0	llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
+857	-0	llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+0	-554	flang/test/Lower/OpenMP/FIR/target.f90
+0	-498	flang/test/Lower/OpenMP/FIR/if-clause.f90
+3,019	-2,657	490 files not shown
+11,800	-15,630	496 files

LLVM/project 0736f3a — llvm/test/CodeGen/RISCV half-round-conv-sat.ll, llvm/test/CodeGen/X86 combine-or-shuffle.ll combine-or.ll

Apr 28, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-generate-profiles-from-riscvprofilestd

Rebase and sync RISCVProfile definition

Created using spr 1.3.6-beta.1

Delta		File
+513	-513	llvm/test/MC/RISCV/rvv/zvlsseg.s
+916	-0	llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
+862	-0	llvm/test/CodeGen/X86/combine-or-shuffle.ll
+857	-0	llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+312	-336	llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+138	-468	llvm/test/CodeGen/X86/combine-or.ll
+3,598	-1,317	471 files not shown
+14,754	-7,408	477 files

LLVM/project f863584 — llvm/test/CodeGen/RISCV half-round-conv-sat.ll, llvm/test/CodeGen/X86 combine-or-shuffle.ll combine-or.ll

Apr 28, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-generate-profiles-from-riscvprofilestd

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+513	-513	llvm/test/MC/RISCV/rvv/zvlsseg.s
+916	-0	llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
+862	-0	llvm/test/CodeGen/X86/combine-or-shuffle.ll
+857	-0	llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+312	-336	llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+138	-468	llvm/test/CodeGen/X86/combine-or.ll
+3,598	-1,317	471 files not shown
+14,753	-7,407	477 files

LLVM/project 5b10a8d — libcxx/include/__format escaped_output_table.h, llvm/test/CodeGen/RISCV half-round-conv-sat.ll

Apr 27, 2024 by Nathan Lanza on ⎇

users/lanza/sprcir-add-options-to-emit-clangir-and-enable-the-clangir-pipeline

cc1

Created using spr 1.3.5

Delta		File
+3,617	-0	llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
+1,082	-901	libcxx/include/__format/escaped_output_table.h
+513	-513	llvm/test/MC/RISCV/rvv/zvlsseg.s
+862	-0	llvm/test/CodeGen/X86/combine-or-shuffle.ll
+312	-336	llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+138	-468	llvm/test/CodeGen/X86/combine-or.ll
+6,524	-2,218	832 files not shown
+25,886	-12,228	838 files

LLVM/project 6c4b180 — libcxx/include/__format escaped_output_table.h, llvm/test/CodeGen/RISCV half-round-conv-sat.ll

Apr 27, 2024 by Congcong Cai via Nathan Lanza on ⎇

users/lanza/sprmain.cir-add-options-to-emit-clangir-and-enable-the-clangir-pipeline

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5

[skip ci]

Delta		File
+3,617	-0	llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
+1,082	-901	libcxx/include/__format/escaped_output_table.h
+513	-513	llvm/test/MC/RISCV/rvv/zvlsseg.s
+862	-0	llvm/test/CodeGen/X86/combine-or-shuffle.ll
+312	-336	llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+138	-468	llvm/test/CodeGen/X86/combine-or.ll
+6,524	-2,218	832 files not shown
+25,885	-12,227	838 files

LLVM/project cf27e51 — llvm/test/CodeGen/X86 gfni-funnel-shifts.ll, llvm/test/Instrumentation/MemorySanitizer/X86 mmx-intrinsics.ll

Apr 26, 2024 by Florian Mayer on ⎇

users/fmayer/spr/wip-mte-stack-record

dwarf

Created using spr 1.3.4

Delta		File
+2,815	-2,410	llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+3,717	-0	llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
+3,617	-0	llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
+3,478	-0	offload/plugins-nextgen/amdgpu/src/rtl.cpp
+0	-3,478	openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
+2,686	-4	llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
+16,313	-5,892	3,803 files not shown
+195,461	-99,380	3,809 files

LLVM/project c69f388 — llvm/test/CodeGen/X86 gfni-funnel-shifts.ll, llvm/test/Instrumentation/MemorySanitizer/X86 mmx-intrinsics.ll

Apr 26, 2024 by Florian Mayer on ⎇

users/fmayer/spr/main.wip-mte-stack-record

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,815	-2,410	llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+3,717	-0	llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
+3,617	-0	llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
+3,478	-0	offload/plugins-nextgen/amdgpu/src/rtl.cpp
+0	-3,478	openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
+2,686	-4	llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
+16,313	-5,892	3,802 files not shown
+195,458	-99,379	3,808 files

LLVM/project b27f86b — llvm/test/MC/RISCV/rvv zvlsseg.s compare.s

Apr 26, 2024 by Craig Topper via GitHub on ⎇

main

[RISCV] Add an instruction PrettyPrinter to llvm-objdump (#90093)

This prints the opcode bytes in the same order as GNU objdump without a
space between them.

Delta		File
+513	-513	llvm/test/MC/RISCV/rvv/zvlsseg.s
+83	-83	llvm/test/MC/RISCV/rvv/compare.s
+64	-64	llvm/test/MC/RISCV/rvv/load.s
+59	-59	llvm/test/MC/RISCV/rvv/add.s
+50	-50	llvm/test/MC/RISCV/rvv/sub.s
+48	-48	llvm/test/MC/RISCV/rvv/fmacc.s
+817	-817	59 files not shown
+1,629	-1,575	65 files

LLVM/project 00dfd4f — llvm/lib/Target/RISCV/MCTargetDesc RISCVInstPrinter.cpp, llvm/test/CodeGen/RISCV patchable-function-entry.ll

May 29, 2021 by Jessica Clarke on ⎇

release/13.x

Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"

The replacement doesn't work for llc, but it is needed by
patchable-function-entry.ll.

This reverts commit aa9a30b83a06e3e5e68e32ea645ec2d9edc27efc.

Delta		File
+7	-2	llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+4	-4	llvm/test/MC/RISCV/option-pic.s
+4	-4	llvm/test/MC/RISCV/rv32c-only-valid.s
+4	-4	llvm/test/CodeGen/RISCV/patchable-function-entry.ll
+4	-4	llvm/test/MC/RISCV/rv32fc-valid.s
+4	-4	llvm/test/MC/RISCV/option-nopic.s
+27	-22	73 files not shown
+136	-131	79 files

LLVM/project aa9a30b — llvm/lib/Target/RISCV/MCTargetDesc RISCVInstPrinter.cpp, llvm/test/CodeGen/RISCV patchable-function-entry.ll

May 29, 2021 by Jessica Clarke on ⎇

release/13.x

[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases

Whilst here, also remove a couple of unnecessary -o - instances.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D103201

Delta		File
+2	-7	llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+4	-4	llvm/test/MC/RISCV/option-nopic.s
+4	-4	llvm/test/MC/RISCV/rv32c-only-valid.s
+4	-4	llvm/test/MC/RISCV/option-pic.s
+4	-4	llvm/test/CodeGen/RISCV/patchable-function-entry.ll
+4	-4	llvm/test/MC/RISCV/rv32fc-valid.s
+22	-27	73 files not shown
+131	-136	79 files

LLVM/project e4fc8c3 — llvm/test/MC/RISCV compress-rv32i.s compress-rv32b.s

May 26, 2021 by Jessica Clarke on ⎇

release/13.x

[RISCV][NFC] Fix some whitespace nits in MC test RUN lines

Delta		File
+12	-12	llvm/test/MC/RISCV/compress-rv32i.s
+12	-12	llvm/test/MC/RISCV/compress-rv32b.s
+12	-12	llvm/test/MC/RISCV/option-rvc.s
+12	-12	llvm/test/MC/RISCV/compress-rv32d.s
+6	-6	llvm/test/MC/RISCV/compress-rv64i.s
+6	-6	llvm/test/MC/RISCV/compress-rv64b.s
+60	-60	7 files not shown
+79	-79	13 files

LLVM/project ad923ed — llvm/test/MC/RISCV rvi-aliases-valid.s rv32-relaxation.s

Dec 4, 2020 by Craig Topper on ⎇

release/12.x

[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump

This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on D76591

It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name?

Differential Revision: https://reviews.llvm.org/D92147

Delta		File
+48	-24	llvm/test/MC/RISCV/rvi-aliases-valid.s
+24	-24	llvm/test/MC/RISCV/rv32-relaxation.s
+26	-14	llvm/test/MC/RISCV/compress-rv32i.s
+18	-18	llvm/test/MC/RISCV/rv64-relaxation.s
+24	-12	llvm/test/MC/RISCV/rv32i-valid.s
+14	-8	llvm/test/MC/RISCV/rv32e-valid.s
+154	-100	18 files not shown
+252	-169	24 files

LLVM/project e51183e — libc/AOR_v20.02/math/test/traces sincosf.txt exp.txt, lldb/source/Target RegisterContextUnwind.cpp

Mar 18, 2020 by Dominik Montada on

[DPWBS-1403] Merge branch community master into htc/master

The following files needed to be touched due to changes in the
upstream community:

ELFObjectFile.h:                536ba6373f05fb1e9bc7199e301fbf4bc514006f
TriCoreFrameLowering.cpp:       d000655a8cd58c8449a86a1761038c8c1dd78d87
TriCore.td:                     a26bd4ec1652da20872e55d0bf468f52149a2ec9
TriCoreInstrInfo.td:            a26bd4ec1652da20872e55d0bf468f52149a2ec9
TriCoreInstrFormats.td:         a26bd4ec1652da20872e55d0bf468f52149a2ec9

The following tests needed to be updated as well:

elf-header.s:                   536ba6373f05fb1e9bc7199e301fbf4bc514006f
legalize-ctlz.mir:              c0241f150dcb0a5c6abd2955310d6cc8ef7b9f94
legalize-cttz.mir:              c0241f150dcb0a5c6abd2955310d6cc8ef7b9f94
legalize-load-store.mir:        c0241f150dcb0a5c6abd2955310d6cc8ef7b9f94
legalize-merge-values.mir:      c0241f150dcb0a5c6abd2955310d6cc8ef7b9f94


    [10 lines not shown]

Delta		File
+31,999	-0	libc/AOR_v20.02/math/test/traces/sincosf.txt
+16,000	-0	libc/AOR_v20.02/math/test/traces/exp.txt
+3,281	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+3,011	-0	llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
+2,233	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+2,215	-0	lldb/source/Target/RegisterContextUnwind.cpp
+58,739	-0	4,917 files not shown
+209,458	-69,487	4,923 files

LLVM/project ecd6d72 — llvm/test/CodeGen/ARM trap.ll, llvm/test/CodeGen/Mips/tailcall tailcall-wrong-isa.ll

Mar 16, 2020 by Fangrui Song on ⎇

release/11.x

[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options

As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html

Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option
A subsequent change will reject -long-option.

Delta		File
+143	-143	llvm/test/Object/macho-invalid.test
+27	-27	llvm/test/MC/X86/x86_long_nop.s
+12	-12	llvm/test/MC/RISCV/csr-aliases.s
+10	-10	llvm/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll
+6	-6	llvm/test/MC/Mips/expansion-jal-sym-pic.s
+6	-6	llvm/test/CodeGen/ARM/trap.ll
+204	-204	817 files not shown
+1,130	-1,130	823 files

LLVM/project d901dfc — llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-constant.mir legalize-load-local.mir, llvm/test/CodeGen/RISCV atomic-rmw.ll

Oct 10, 2019 by Konstantin Schwarz on

[DPWBS-1041] Merge community 'master' into HighTec htc/master

llvm-objcopy has been refactored, making part of [DPWBS-997] obsolete (ArchMap addition).

Delta		File
+13,431	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+12,706	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+12,589	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+11,606	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+11,271	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+5,358	-5,238	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+66,961	-5,238	9,064 files not shown
+391,462	-150,493	9,070 files

LLVM/project d57de49 — llvm/lib/Target/RISCV/MCTargetDesc RISCVInstPrinter.cpp, llvm/test/MC/RISCV align.s rvi-aliases-valid.s

Sep 10, 2019 by Sam Elliott on ⎇

release/10.x

[RISCV] Support llvm-objdump -M no-aliases and -M numeric

Summary:
Now that llvm-objdump allows target-specific options, we match the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump.

This is done by overriding the variables used for the command-line options, so
that the command-line options are still supported.

This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use
`llvm-objdump -M no-aliases`.

Reviewers: luismarques, asb

Reviewed By: luismarques, asb

Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

    [4 lines not shown]

Delta		File
+18	-0	llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+4	-4	llvm/test/MC/RISCV/align.s
+2	-2	llvm/test/MC/RISCV/rvi-aliases-valid.s
+2	-2	llvm/test/MC/RISCV/rvf-aliases-valid.s
+2	-2	llvm/test/MC/RISCV/rvdc-aliases-valid.s
+2	-2	llvm/test/MC/RISCV/rvd-aliases-valid.s
+30	-12	52 files not shown
+100	-80	58 files

LLVM/project c1b0e66 — llvm/lib/Target/RISCV RISCVInstrInfoC.td, llvm/test/CodeGen/RISCV alu32.ll

Apr 6, 2018 by Sameer AbuAsal on ⎇

release/7.x

    [RISCV] Tablegen-driven Instruction Compression.

Summary:

    This patch implements a tablegen-driven Instruction Compression
    mechanism for generating RISCV compressed instructions
    (C Extension) from the expanded instruction form.

    This tablegen backend processes CompressPat declarations in a
    td file and generates all the compile-time and runtime checks
    required to validate the declarations, validate the input
    operands and generate correct instructions.

    The checks include validating register operands, immediate
    operands, fixed register operands and fixed immediate operands.

    Example:
      class CompressPat<dag input, dag output> {
        dag Input  = input;

    [55 lines not shown]

Delta		File
+806	-0	llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+262	-1	llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+207	-0	llvm/test/MC/RISCV/compress-rv32i.s
+60	-0	llvm/test/MC/RISCV/compress-rv64i.s
+44	-0	llvm/test/MC/RISCV/compress-rv32d.s
+42	-0	llvm/test/CodeGen/RISCV/alu32.ll
+1,421	-1	23 files not shown
+1,672	-44	29 files