LLVM / project - FreshBSD

LLVM/project 9511215 — clang/test/CodeGen/SystemZ zvector.c, flang/include/flang/Parser parse-tree-visitor.h

Nov 14, 2024 by Paul Kirth on ⎇

users/ilovepi/spr/main.fuchsiacmake-allow-using-fatlto-when-building-runtimes-1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+2,604	-2,501	clang/test/CodeGen/SystemZ/zvector.c
+0	-3,374	llvm/test/CodeGen/RISCV/branch-relaxation.ll
+2,253	-0	llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll
+0	-2,154	llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-x86.ll
+891	-854	flang/include/flang/Parser/parse-tree-visitor.h
+1,520	-0	llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
+7,268	-8,883	1,198 files not shown
+45,059	-23,278	1,204 files

LLVM/project 6203a67 — clang/test/CodeGen/SystemZ zvector.c, flang/include/flang/Parser parse-tree-visitor.h

Nov 14, 2024 by Paul Kirth on ⎇

users/ilovepi/spr/libcxxabi-always-link-against-libzircon-for-fuchsia-targets

Use --as-needed when adding libzircon

Created using spr 1.3.4

Delta		File
+2,604	-2,501	clang/test/CodeGen/SystemZ/zvector.c
+0	-3,374	llvm/test/CodeGen/RISCV/branch-relaxation.ll
+2,253	-0	llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll
+0	-2,154	llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-x86.ll
+891	-854	flang/include/flang/Parser/parse-tree-visitor.h
+1,520	-0	llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
+7,268	-8,883	1,197 files not shown
+45,055	-23,278	1,203 files

LLVM/project be18736 — llvm/lib/Target/AMDGPU GCNSubtarget.cpp AMDGPUSplitModule.cpp

Nov 14, 2024 by Kazu Hirata via GitHub on ⎇

main

[AMDGPU] Remove unused includes (NFC) (#116154)

Identified with misc-include-cleaner.

Delta		File
+0	-4	llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+0	-4	llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+0	-3	llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+0	-3	llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+0	-3	llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
+0	-2	llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
+0	-19	46 files not shown
+0	-69	52 files

LLVM/project c9b691e — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 12, 2024 by Florian Mayer on ⎇

users/fmayer/spr/apply-alignment-size-in-linker-rather-than-ir

upd

Created using spr 1.3.4

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	14,682 files not shown
+1,228,750	-629,516	14,688 files

LLVM/project 49ce824 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 12, 2024 by Paul Kirth on ⎇

users/ilovepi/spr/libcxxcmake-allow-using-fatlto-in-libc-builds

rebase and enable FatLTO for Fuchsia targets

Created using spr 1.3.4

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	14,261 files not shown
+1,198,063	-619,427	14,267 files

LLVM/project 2ad6038 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 12, 2024 by Paul Kirth on ⎇

users/ilovepi/spr/main.fuchsiacmake-allow-using-fatlto-when-building-runtimes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	14,260 files not shown
+1,198,054	-619,426	14,266 files

LLVM/project 71e373c — llvm/test/CodeGen/AMDGPU atomic_optimizations_local_pointer.ll, llvm/test/CodeGen/RISCV memcmp.ll memcmp-optsize.ll

Nov 12, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit '644a9a4327af4fb4f7b09832cafe3c82843231b5^' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+6,378	-0	llvm/test/CodeGen/RISCV/memcmp.ll
+2,599	-2,718	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+3,463	-1,761	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+3,475	-1,723	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+5,018	-0	llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+3,295	-0	llvm/test/TableGen/x86-instr-mapping.inc
+24,228	-6,202	3,794 files not shown
+124,032	-56,968	3,800 files

LLVM/project 822ff0d — llvm/test/CodeGen/AMDGPU flat_atomics_i64_system.ll atomic_optimizations_local_pointer.ll, llvm/test/CodeGen/RISCV memcmp.ll

Nov 11, 2024 by Alexander Richardson via Alex Richardson on ⎇

users/arichardson/spr/reapply-runtimes-allow-building-against-an-installed-llvm-tree

rebase

Created using spr 1.3.6-beta.1

Delta		File
+9,804	-3,343	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+5,177	-5,299	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+4,559	-4,571	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+3,436	-3,249	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+3,340	-3,153	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+6,378	-0	llvm/test/CodeGen/RISCV/memcmp.ll
+32,694	-19,615	3,965 files not shown
+235,716	-183,374	3,971 files

LLVM/project 9c55766 — llvm/test/CodeGen/AMDGPU flat_atomics_i64_system.ll atomic_optimizations_local_pointer.ll, llvm/test/CodeGen/RISCV memcmp.ll

Nov 11, 2024 by Alex Richardson on ⎇

users/arichardson/spr/main.reapply-runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+9,804	-3,343	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+5,177	-5,299	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+4,559	-4,571	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+3,436	-3,249	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+3,340	-3,153	llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+6,378	-0	llvm/test/CodeGen/RISCV/memcmp.ll
+32,694	-19,615	3,964 files not shown
+235,713	-183,381	3,970 files

LLVM/project bf07578 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/RISCV/rvv expandload.ll

Nov 9, 2024 by LLVM GN Syncbot via Amir Ayupov on ⎇

users/aaupov/spr/main.mc-use-stringrefs-from-pseudo_probe_desc-section-if-its-mapped

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,675	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+8,731	-1,154	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+77,825	-2,829	10,870 files not shown
+737,289	-200,227	10,876 files

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files

LLVM/project 7be0b9e — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,726	-528,067	20,522 files

LLVM/project e7bce6d — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

address comments

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,744 files not shown
+1,374,895	-489,660	18,750 files

LLVM/project c84de42 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,743 files not shown
+1,374,820	-489,573	18,749 files

LLVM/project 7f60f13 — llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp AMDGPUMCResourceInfo.cpp, llvm/test/CodeGen/AMDGPU unnamed-function-resource-info.ll

Nov 7, 2024 by Janek van Oirschot via GitHub on ⎇

main

[AMDGPU] Fix resource usage information for unnamed functions (#115320)

Resource usage information would try to overwrite unnamed functions if
there are multiple within the same compilation unit. This aims to either
use the `MCSymbol` assigned to the unnamed function (i.e.,
`CurrentFnSym`), or, rematerialize the `MCSymbol` for the unnamed
function.

Delta		File
+29	-22	llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+48	-0	llvm/test/CodeGen/AMDGPU/unnamed-function-resource-info.ll
+25	-11	llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
+102	-33	3 files

LLVM/project 94991b2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 7, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolttest-add-callcont-fallthrutest

Drop call check

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+77,630	-4,605	13,289 files not shown
+985,511	-356,667	13,295 files

LLVM/project 91fd9e8 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit 'a5345114e5ac1c767aa4cd6be2aa333bea9c5009' into users/meinersbur/irbuilder-extract

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+54,322	-12,281	6,813 files not shown
+381,470	-187,676	6,819 files

LLVM/project a534511 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 2, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit 'fa789dffb1e12c2aece0187aeacc48dfb1768340' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+3,585	-4,386	llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
+7,294	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+54,322	-12,281	6,813 files not shown
+381,470	-187,676	6,819 files

LLVM/project 254d2eb — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 1, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvenable-max-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,088 files not shown
+2,335,277	-1,222,511	26,094 files

LLVM/project c55290e — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Simon Pilgrim via Alex Richardson on ⎇

users/arichardson/spr/main.datalayoutlangref-split-non-integral-and-unstable-pointer-properties

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,113	-881,962	18,271 files

LLVM/project 35afb97 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayoutlangref-split-non-integral-and-unstable-pointer-properties

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,112	-881,961	18,271 files

LLVM/project 1bda0dd — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayout-refactor-storage-of-non-integral-address-spaces

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,901 files not shown
+1,517,614	-867,434	17,907 files

LLVM/project f0f728f — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/elfwasm-update-datalayout-strings-to-latest-version

rebase and fix commit message

Created using spr 1.3.6-beta.1

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,589	-7,092	15,395 files not shown
+1,090,107	-393,768	15,401 files

LLVM/project e62ef5f — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/runtimes-allow-building-against-an-installed-llvm-tree

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,621 files not shown
+1,489,827	-860,953	17,627 files

LLVM/project 58f7320 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 24, 2024 by Florian Hahn via Alex Richardson on ⎇

users/arichardson/spr/main.runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	17,620 files not shown
+1,489,825	-860,949	17,626 files

LLVM/project 922f38c — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 24, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-add-profile-density-computation

show-density=true, threshold=50

Created using spr 1.3.4

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,552 files not shown
+569,777	-266,956	9,558 files

LLVM/project b4be4af — clang/test/CodeGen/aarch64-sve-intrinsics acle_sve_reinterpret.c, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Oct 24, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-add-profile-density-computation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,549	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,084	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+9,096	-1,341	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+10,262	-0	llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+69,595	-7,092	9,551 files not shown
+569,775	-266,954	9,557 files

LLVM/project 942a6e9 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/sanitizer_allocatorcpp-ensure-at-least-sizeofvoid-alignment

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	46,218 files not shown
+4,313,171	-1,926,653	46,224 files

LLVM/project 9028b4e — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 15, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-add-options-for-annotate-tablejump

reimplement

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	15,921 files not shown
+1,245,447	-839,596	15,927 files