LLVM / project - FreshBSD

LLVM/project 23ac5ef — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallgraphsection-add-call-graph-section-options-and-documentation

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project c0b6218 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by LLVM GN Syncbot via prabhukr on ⎇

users/Prabhuk/sprmain.callgraphsection-add-call-graph-section-options-and-documentation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 6675226 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU flat_atomics_i64_system_noprivate.ll flat_atomics_i64_noprivate.ll

Nov 20, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/merge

Merge branch 'users/chapuni/cov/single/test' into users/chapuni/cov/single/merge

Delta		File
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+3,630	-3,624	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,804	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+40,524	-10,845	8,255 files not shown
+418,694	-225,256	8,261 files

LLVM/project 2d5f7f4 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 19, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slp-match-poison-as-instruction-with-the-same-opcode

Address comments

Created using spr 1.3.5

Delta		File
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+13,103	-0	clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
+0	-13,103	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+4,704	-4,272	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,085	-2,727	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+38,310	-37,520	5,483 files not shown
+418,240	-352,825	5,489 files

LLVM/project cfc6dbe — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,041 files not shown
+1,309,194	-678,314	16,047 files

LLVM/project 7caea4d — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_move-files

Merge branch 'users/meinersbur/flang_runtime_split-headers2' into users/meinersbur/flang_runtime_move-files

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,200	-678,317	16,048 files

LLVM/project bf24912 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers2

Merge branch 'users/meinersbur/flang_runtime_split-headers' into users/meinersbur/flang_runtime_split-headers2

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,196	-678,318	16,048 files

LLVM/project 2a97e4a — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers

Merge branch 'main' into users/meinersbur/flang_runtime_split-headers

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,196	-678,318	16,048 files

LLVM/project 7420027 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpadd-cost-estimation-for-gather-node-reshuffling

Address comments

Created using spr 1.3.5

Delta		File
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+9,804	-3,343	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+0	-13,103	clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c
+13,103	-0	clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
+4,559	-4,571	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+44,884	-38,435	5,875 files not shown
+562,412	-488,585	5,881 files

LLVM/project 9122c52 — llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll atomic-rmw.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll expandload.ll

Nov 15, 2024 by Pengcheng Wang via GitHub on ⎇

main

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

Delta		File
+4,704	-4,272	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,085	-2,727	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+2,234	-2,381	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+2,023	-2,023	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,032	-1,876	llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
+1,949	-1,437	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+16,027	-14,716	482 files not shown
+57,250	-55,122	488 files

LLVM/project a56f42c — llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll atomic-rmw.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll expandload.ll

Nov 12, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-set-disablelatencyheuristic-to-true

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+4,704	-4,272	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,085	-2,727	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+2,234	-2,381	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+2,023	-2,023	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,032	-1,876	llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
+1,949	-1,437	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+16,027	-14,716	484 files not shown
+57,829	-55,785	490 files

LLVM/project 3b2d22d — llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll atomic-rmw.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll expandload.ll

Nov 12, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-enable-shouldtracklanemasks-when-having-vector-instructions

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1

Delta		File
+4,704	-4,272	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,085	-2,727	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+2,234	-2,381	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+2,023	-2,023	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,032	-1,876	llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
+1,949	-1,437	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+16,027	-14,716	484 files not shown
+57,829	-55,785	490 files

LLVM/project cd92184 — llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll atomic-rmw.ll, llvm/test/CodeGen/RISCV/rvv vfma-vp.ll expandload.ll

Nov 12, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-enable-shouldtracklanemasks-when-having-vector-instructions

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+4,704	-4,272	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,085	-2,727	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+2,234	-2,381	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+2,023	-2,023	llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,032	-1,876	llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
+1,949	-1,437	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+16,027	-14,716	482 files not shown
+57,592	-55,476	488 files

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files

LLVM/project 7be0b9e — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,726	-528,067	20,522 files

LLVM/project e7bce6d — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

address comments

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,744 files not shown
+1,374,895	-489,660	18,750 files

LLVM/project c84de42 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,743 files not shown
+1,374,820	-489,573	18,749 files

LLVM/project 94991b2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-flat.mir

Nov 7, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolttest-add-callcont-fallthrutest

Drop call check

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+77,630	-4,605	13,289 files not shown
+985,511	-356,667	13,295 files

LLVM/project aed2ade — llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll nontemporal.ll, llvm/test/CodeGen/X86 vector-shift-lut.ll

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit 'b067189699f16c8b1671d11058615a9c25001313' into users/meinersbur/irbuilder-extract

Delta		File
+1,885	-1,884	llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
+1,846	-1,845	llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
+1,774	-1,768	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,241	-0	llvm/test/CodeGen/X86/vector-shift-lut.ll
+1,510	-1,510	llvm/test/CodeGen/RISCV/nontemporal.ll
+776	-775	llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+11,032	-7,782	776 files not shown
+31,909	-20,217	782 files

LLVM/project 57e0f7f — libcxx/include regex, libcxx/src locale.cpp

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit '4619a32ad6bde20ee1f2d8297c431c0679c2c8bf' into users/meinersbur/irbuilder-extract

Delta		File
+27,218	-219	llvm/test/CodeGen/AMDGPU/bf16.ll
+11,620	-11,712	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,442	-5,290	libcxx/src/locale.cpp
+3,731	-4,881	libcxx/include/regex
+2,972	-4,148	llvm/test/CodeGen/AArch64/vecreduce-add.ll
+3,242	-3,243	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+53,225	-29,493	7,802 files not shown
+546,928	-278,424	7,808 files

LLVM/project 72fd292 — llvm/test/CodeGen/AMDGPU gfx-callable-argument-types.ll, llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vsuxseg-rv64.ll

Nov 2, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit '2118b9d39b91e93c0146611235072cd6ca0f27b1^' into HEAD

Delta		File
+8,414	-8,431	llvm/test/CodeGen/SystemZ/Large/branch-01.ll
+6,033	-3,884	llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+3,318	-3,318	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+3,318	-3,318	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+3,318	-3,318	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+3,318	-3,318	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+27,719	-25,587	7,153 files not shown
+259,838	-233,505	7,159 files

LLVM/project b067189 — llvm/test/CodeGen/RISCV wide-scalar-shift-by-byte-multiple-legalization.ll nontemporal.ll, llvm/test/CodeGen/X86 vector-shift-lut.ll

Nov 2, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit '76007138f4ffd4e0f510d12b5e8cad529c21f24d' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+1,885	-1,884	llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
+1,846	-1,845	llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
+1,774	-1,768	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+3,241	-0	llvm/test/CodeGen/X86/vector-shift-lut.ll
+1,510	-1,510	llvm/test/CodeGen/RISCV/nontemporal.ll
+776	-775	llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+11,032	-7,782	776 files not shown
+31,909	-20,217	782 files

LLVM/project 4619a32 — libcxx/include regex, libcxx/src locale.cpp

Nov 2, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit 'd041af3019984f505530bac3acb94ca2f13f33cd^' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+27,218	-219	llvm/test/CodeGen/AMDGPU/bf16.ll
+11,620	-11,712	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,442	-5,290	libcxx/src/locale.cpp
+3,731	-4,881	libcxx/include/regex
+2,972	-4,148	llvm/test/CodeGen/AArch64/vecreduce-add.ll
+3,242	-3,243	llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+53,225	-29,493	7,802 files not shown
+546,928	-278,424	7,808 files

LLVM/project 254d2eb — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 1, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvenable-max-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,088 files not shown
+2,335,277	-1,222,511	26,094 files

LLVM/project e1acf65 — llvm/test/CodeGen/AArch64/Atomics aarch64-atomicrmw-rcpc3.ll aarch64-atomicrmw-rcpc.ll, llvm/test/CodeGen/AMDGPU gfx-callable-argument-types.ll

Nov 1, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit 'f9599bbc7a3f831e1793a549d8a7a19265f3e504^' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+8,414	-8,431	llvm/test/CodeGen/SystemZ/Large/branch-01.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
+5,620	-3,841	llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+52,750	-12,272	21,723 files not shown
+2,716,037	-1,117,083	21,729 files

LLVM/project 39816b2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64_system_noprivate.ll, llvm/test/CodeGen/RISCV memcmp.ll

Oct 31, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-initial-support-of-memcmp-expansion

Reduce CHECKs

Created using spr 1.3.6-beta.1

Delta		File
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+7,870	-1,851	llvm/test/CodeGen/RISCV/memcmp.ll
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+9,076	-0	llvm/test/MC/AMDGPU/gfx12_asm_vopc-fake16.s
+63,625	-1,851	8,926 files not shown
+660,033	-194,290	8,932 files

LLVM/project b9a0425 — clang/docs/tools clang-formatted-files.txt, llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64_system_noprivate.ll

Oct 31, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-add-initial-support-of-memcmp-expansion

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+9,076	-0	llvm/test/MC/AMDGPU/gfx12_asm_vopc-fake16.s
+0	-8,827	clang/docs/tools/clang-formatted-files.txt
+55,755	-8,827	8,926 files not shown
+649,322	-199,873	8,932 files

LLVM/project 0d2677d — clang/docs/tools clang-formatted-files.txt, llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64_system_noprivate.ll

Oct 31, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-tests-for-memcmp-expansion

Reduce CHECKs

Created using spr 1.3.6-beta.1

Delta		File
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+10,948	-0	llvm/test/MC/AMDGPU/gfx11_asm_vopc-fake16.s
+10,486	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+9,076	-0	llvm/test/MC/AMDGPU/gfx12_asm_vopc-fake16.s
+0	-8,827	clang/docs/tools/clang-formatted-files.txt
+55,755	-8,827	8,926 files not shown
+649,322	-199,873	8,932 files

LLVM/project 2c29f5d — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU flat_atomics_i64_system_noprivate.ll flat_atomics_i64_noprivate.ll

Oct 27, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/nextcount

Merge branch 'users/chapuni/cov/single/nextcount-base' into HEAD

Delta		File
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+6,804	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+932	-5,548	llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
+2,814	-2,432	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+754	-4,432	llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
+23,790	-15,702	5,959 files not shown
+265,327	-147,852	5,965 files