LLVM / project - FreshBSD

LLVM/project 7629cef — llvm/test/CodeGen/X86 vector-interleaved-store-i64-stride-7.ll vector-interleaved-load-i64-stride-8.ll

Nov 2, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit '1833de3ee364a996d03bb23b19fe472e3e2ddf3b^' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+22,204	-17,874	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+22,733	-6,530	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
+21,621	-6,188	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
+21,152	-6,073	llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+14,429	-12,423	llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
+14,732	-9,307	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+116,871	-58,395	6,515 files not shown
+938,511	-711,420	6,521 files

LLVM/project 254d2eb — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 1, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvenable-max-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,088 files not shown
+2,335,277	-1,222,511	26,094 files

LLVM/project e1acf65 — llvm/test/CodeGen/AArch64/Atomics aarch64-atomicrmw-rcpc3.ll aarch64-atomicrmw-rcpc.ll, llvm/test/CodeGen/AMDGPU gfx-callable-argument-types.ll

Nov 1, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit 'f9599bbc7a3f831e1793a549d8a7a19265f3e504^' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+8,414	-8,431	llvm/test/CodeGen/SystemZ/Large/branch-01.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+9,679	-0	llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
+5,620	-3,841	llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+52,750	-12,272	21,723 files not shown
+2,716,037	-1,117,083	21,729 files

LLVM/project c55290e — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Simon Pilgrim via Alex Richardson on ⎇

users/arichardson/spr/main.datalayoutlangref-split-non-integral-and-unstable-pointer-properties

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,113	-881,962	18,271 files

LLVM/project 35afb97 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayoutlangref-split-non-integral-and-unstable-pointer-properties

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,112	-881,961	18,271 files

LLVM/project 1bda0dd — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayout-refactor-storage-of-non-integral-address-spaces

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,901 files not shown
+1,517,614	-867,434	17,907 files

LLVM/project e62ef5f — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/runtimes-allow-building-against-an-installed-llvm-tree

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,621 files not shown
+1,489,827	-860,953	17,627 files

LLVM/project 58f7320 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 24, 2024 by Florian Hahn via Alex Richardson on ⎇

users/arichardson/spr/main.runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	17,620 files not shown
+1,489,825	-860,949	17,626 files

LLVM/project 942a6e9 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/sanitizer_allocatorcpp-ensure-at-least-sizeofvoid-alignment

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	46,218 files not shown
+4,313,171	-1,926,653	46,224 files

LLVM/project 9028b4e — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 15, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-add-options-for-annotate-tablejump

reimplement

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	15,921 files not shown
+1,245,447	-839,596	15,927 files

LLVM/project fb87349 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 8, 2024 by Florian Mayer on ⎇

users/fmayer/spr/mte-do-not-allow-local-aliases-to-mte-globals

reb

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	10,988 files not shown
+937,390	-704,057	10,994 files

LLVM/project d38562a — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 3, 2024 by Paul Kirth on ⎇

users/ilovepi/spr/mlirtest-test-conversion-of-tosa-to-emitc-via-linalg

Update script and test corpus

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,693 files not shown
+2,060,103	-1,198,997	26,699 files

LLVM/project c67340a — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 25, 2024 by Corbin Robeck via GitHub on ⎇

users/crobeck/remove-renamedInGFX9-bit

Merge branch 'main' into users/crobeck/remove-renamedInGFX9-bit

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	33,290 files not shown
+2,709,253	-1,363,414	33,296 files

LLVM/project 9bc6c9e — llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 25, 2024 by Fangrui Song on ⎇

users/MaskRay/spr/riscv-restore-dw_eh_pe_uleb128-call-site-encoding-for-gcc_except_table

rebase

Created using spr 1.3.5-bogner

Delta		File
+22,225	-17,874	llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+19,816	-19,812	llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+105,211	-106,884	50,557 files not shown
+5,033,721	-2,425,704	50,563 files

LLVM/project c0ad0fa — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Aiden Grossman on ⎇

users/boomanaiden154/x86-cpuid-compilerrt-test-infra

Merge branch 'main' into users/boomanaiden154/x86-cpuid-compilerrt-test-infra

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	16,027 files not shown
+1,282,243	-905,121	16,033 files

LLVM/project 8a42b19 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Chao Chen via GitHub on ⎇

users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter

Merge branch 'main' into users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,984 files not shown
+1,067,270	-799,696	13,990 files

LLVM/project 7172da5 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-add-profile-density-computation

rebase, profile-density-threshold=0

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	13,413 files not shown
+1,076,696	-789,199	13,419 files

LLVM/project 60d9539 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-add-profile-density-computation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,412 files not shown
+1,076,695	-789,198	13,418 files

LLVM/project 4ad90e1 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolt-set-rawbranchcount-in-dataaggregator

rebase

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	14,739 files not shown
+1,174,924	-859,037	14,745 files

LLVM/project 3f21bd8 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 18, 2024 by harishch4 via Amir Ayupov on ⎇

users/aaupov/spr/main.bolt-set-rawbranchcount-in-dataaggregator

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	14,739 files not shown
+1,174,924	-859,037	14,745 files

LLVM/project 835b141 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 17, 2024 by Fangrui Song on ⎇

users/MaskRay/spr/x86-dont-fold-offsets-that-are-too-closer-to-int32_min-in-non-large-code-models

be much more conservative

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	19,063 files not shown
+1,530,803	-1,015,737	19,069 files

LLVM/project 1c8b150 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 11, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Less naive pseudo probe function matching: for each non-matching YamlBF, determine best matching binary inline subtrees, find corresponding binary functions, attach the profile to binary function without a profile and most probes

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,020 files not shown
+1,054,256	-818,251	13,026 files

LLVM/project 836f08b — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 11, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	13,020 files not shown
+1,054,117	-818,226	13,026 files

LLVM/project b1c9a23 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 9, 2024 by Justin Bogner on ⎇

users/bogner/sprdirectx-lower-llvmdxtypedbufferstore-to-dxil-ops

Clean up tests, add docs

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	8,446 files not shown
+688,006	-612,420	8,452 files

LLVM/project ae6e0b8 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Sep 9, 2024 by Justin Bogner on ⎇

users/bogner/sprmain.directx-lower-llvmdxtypedbufferstore-to-dxil-ops

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	8,445 files not shown
+687,943	-612,405	8,451 files

LLVM/project 63e2f09 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 7, 2024 by Justin Bogner on ⎇

users/bogner/sprdirectx-lower-llvmdxtypedbufferload-to-dxil-ops

Rework to match llvm/wg-hlsl#59

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	8,525 files not shown
+692,028	-613,469	8,531 files

LLVM/project 3e7a95c — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 7, 2024 by Mircea Trofin via Justin Bogner on ⎇

users/bogner/sprmain.directx-lower-llvmdxtypedbufferload-to-dxil-ops

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	8,524 files not shown
+691,802	-613,298	8,530 files

LLVM/project 0f455d0 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 4, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

rebase

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,304 files not shown
+1,065,629	-822,709	13,310 files

LLVM/project bfa0afc — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Sep 4, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	13,305 files not shown
+1,065,625	-823,010	13,311 files

LLVM/project c3db84a — llvm/lib/Target/AMDGPU AMDGPUSplitModule.cpp, llvm/test/CodeGen/AArch64 sve-bitcast.ll

Aug 29, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpbetter-cost-estimation-for-masked-gather-or-clustered-loads

Rebase

Created using spr 1.3.5

Delta		File
+3,646	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1-fake16.s
+3,508	-0	llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1-fake16.s
+2,731	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16-fake16.s
+1,306	-563	llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+249	-807	llvm/test/CodeGen/AArch64/sve-bitcast.ll
+590	-381	llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
+12,030	-1,751	1,425 files not shown
+44,405	-16,813	1,431 files