LLVM / project - FreshBSD

LLVM/project 76aaed5 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 9, 2024 by Caroline Tice on ⎇

users/cmtice/DIL-collaboration-work

Merge remote-tracking branch 'origin/main' into DIL-work-new

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	36,026 files not shown
+3,104,398	-1,498,303	36,032 files

LLVM/project 3bd1ec2 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by shawbyoung via Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-functions-with-pseudo-probes

Pseudo probe function matchign

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,774	-528,137	20,522 files

LLVM/project 7be0b9e — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-functions-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	20,516 files not shown
+1,508,726	-528,067	20,522 files

LLVM/project e7bce6d — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes

address comments

Created using spr 1.3.4

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,744 files not shown
+1,374,895	-489,660	18,750 files

LLVM/project c84de42 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir

Nov 8, 2024 by Amir Ayupov on ⎇

users/shawbyoung/spr/main.bolt-match-blocks-with-pseudo-probes

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+22,543	-674	llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+11,425	-1,782	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+9,526	-2,235	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+10,208	-1,146	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+89,937	-5,837	18,743 files not shown
+1,374,820	-489,573	18,749 files

LLVM/project 9b3db9b — llvm/test/CodeGen/AMDGPU flat_atomics_i64.ll flat_atomics_i64_system.ll, llvm/test/CodeGen/NVPTX load-store.ll

Nov 7, 2024 by Amir Ayupov on ⎇

users/aaupov/spr/bolttest-add-callcont-fallthrutest

Drop = from comment

Created using spr 1.3.4

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+11,425	-1,675	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+8,731	-1,154	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+6,378	-0	llvm/test/CodeGen/RISCV/memcmp.ll
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+2,599	-2,718	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+54,094	-6,969	5,935 files not shown
+217,583	-82,601	5,941 files

LLVM/project fbe8a2f — llvm/test/CodeGen/AMDGPU atomic_optimizations_local_pointer.ll, llvm/test/CodeGen/NVPTX load-store.ll

Nov 7, 2024 by wanglei on ⎇

users/wangleiat/spr/runtimedyld-add-loongarch-support

Address @DavidSpickett's comments

Created using spr 1.3.5-bogner

Delta		File
+6,378	-0	llvm/test/CodeGen/RISCV/memcmp.ll
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+2,599	-2,718	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+3,463	-1,761	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+3,475	-1,723	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+5,018	-0	llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+25,708	-7,624	3,377 files not shown
+110,665	-53,576	3,383 files

LLVM/project 03ac1b2 — llvm/test/CodeGen/AMDGPU atomic_optimizations_local_pointer.ll, llvm/test/CodeGen/NVPTX load-store.ll

Nov 6, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvenable-max-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase

Created using spr 1.3.5

Delta		File
+6,378	-0	llvm/test/CodeGen/RISCV/memcmp.ll
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+2,599	-2,718	llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+3,463	-1,761	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+3,475	-1,723	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+5,018	-0	llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+25,708	-7,624	3,356 files not shown
+106,036	-49,654	3,362 files

LLVM/project 5dfa889 — llvm/test/CodeGen/AMDGPU flat_atomics_i64.ll flat_atomics_i64_system.ll, llvm/test/CodeGen/NVPTX load-store.ll

Nov 6, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-support-non-power-of-2-types-when-expanding-memcmp

Vector load size should be at least 2*XLen or the codegen isn't optimal

Created using spr 1.3.6-beta.1

Delta		File
+2,022	-19,128	llvm/test/CodeGen/RISCV/memcmp.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+11,425	-1,675	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+1,877	-10,237	llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+8,731	-1,154	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+49,016	-33,616	2,664 files not shown
+152,324	-72,382	2,670 files

LLVM/project 080b9fd — llvm/test/CodeGen/AMDGPU flat_atomics_i64.ll flat_atomics_i64_system.ll, llvm/test/CodeGen/NVPTX load-store.ll

Nov 6, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-support-non-power-of-2-types-when-expanding-memcmp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+1,986	-21,543	llvm/test/CodeGen/RISCV/memcmp.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+11,425	-1,675	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+1,805	-10,092	llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+8,731	-1,154	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+48,908	-35,886	2,664 files not shown
+152,216	-74,652	2,670 files

LLVM/project d876b41 — llvm/test/CodeGen/AMDGPU flat_atomics_i64.ll flat_atomics_i64_system.ll, llvm/test/CodeGen/NVPTX load-store.ll

Nov 6, 2024 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-support-memcmp-expansion-for-vectors

Fix comments

Created using spr 1.3.6-beta.1

Delta		File
+1,986	-21,543	llvm/test/CodeGen/RISCV/memcmp.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+11,425	-1,675	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+1,805	-10,092	llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+8,731	-1,154	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+48,908	-35,886	2,664 files not shown
+152,216	-74,652	2,670 files

LLVM/project a31d951 — llvm/test/CodeGen/AMDGPU flat_atomics_i64.ll flat_atomics_i64_system.ll, llvm/test/CodeGen/NVPTX load-store.ll

Nov 6, 2024 by Pengcheng Wang via Wang Pengcheng on ⎇

users/wangpc-pp/spr/main.riscv-support-memcmp-expansion-for-vectors

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+2,005	-19,324	llvm/test/CodeGen/RISCV/memcmp.ll
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+11,425	-1,675	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+1,775	-10,366	llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+8,731	-1,154	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+48,897	-33,941	2,664 files not shown
+152,202	-72,704	2,670 files

LLVM/project 66939f5 — llvm/test/CodeGen/AMDGPU flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel inst-select-load-global-old-legalization.mir ssubsat.ll

Nov 5, 2024 by Alexander Richardson via Alex Richardson on ⎇

users/arichardson/spr/reapply-runtimes-allow-building-against-an-installed-llvm-tree

rebase

Created using spr 1.3.6-beta.1

Delta		File
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+3,323	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
+1,526	-878	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,555	-0	llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
+536	-530	llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+928	-91	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+12,643	-2,921	1,796 files not shown
+58,965	-21,158	1,802 files

LLVM/project dc90919 — llvm/test/CodeGen/AMDGPU flat_atomics_i64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel inst-select-load-global-old-legalization.mir ssubsat.ll

Nov 5, 2024 by Alex Richardson on ⎇

users/arichardson/spr/main.reapply-runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+4,775	-1,422	llvm/test/CodeGen/NVPTX/load-store.ll
+3,323	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
+1,526	-878	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,555	-0	llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
+536	-530	llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+928	-91	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+12,643	-2,921	1,796 files not shown
+58,965	-21,158	1,802 files

LLVM/project 433ea28 — llvm/test/CodeGen/AArch64 neon-scalar-by-elem-fma.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-setcc-fp-vp.ll fixed-vectors-shuffle-changes-length.ll

Nov 5, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/nfctsan-eliminate-a-few-macros

rebase

Created using spr 1.3.4

Delta		File
+1,526	-878	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+0	-997	mlir/test/Dialect/Arith/int-narrowing.mlir
+0	-790	mlir/lib/Dialect/Arith/Transforms/IntNarrowing.cpp
+390	-105	llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
+39	-270	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
+300	-2	mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
+2,255	-3,042	349 files not shown
+8,752	-6,049	355 files

LLVM/project f27002c — llvm/test/CodeGen/AArch64 neon-scalar-by-elem-fma.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-setcc-fp-vp.ll fixed-vectors-shuffle-changes-length.ll

Nov 5, 2024 by Vitaly Buka on ⎇

users/vitalybuka/spr/main.nfctsan-eliminate-a-few-macros

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Delta		File
+1,526	-878	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+0	-997	mlir/test/Dialect/Arith/int-narrowing.mlir
+0	-790	mlir/lib/Dialect/Arith/Transforms/IntNarrowing.cpp
+390	-105	llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
+39	-270	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
+300	-2	mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
+2,255	-3,042	349 files not shown
+8,752	-6,049	355 files

LLVM/project b2d2494 — libcxx/test/benchmarks unordered_set_operations.bench.cpp hash.bench.cpp, libcxx/test/benchmarks/format write_string_comparison.bench.cpp

Nov 5, 2024 by Louis Dionne via GitHub on ⎇

main

[libc++] Make benchmarks forward-compatible with the test suite (#114502)

This patch fixes warnings and errors that come up when running the
benchmarks as part of the test suite. It also adds the necessary Lit
annotations to make it pass in various configurations and increases the
portability of the benchmarks.

Delta		File
+15	-79	libcxx/test/benchmarks/unordered_set_operations.bench.cpp
+0	-38	libcxx/test/benchmarks/hash.bench.cpp
+18	-10	libcxx/test/benchmarks/string.bench.cpp
+6	-13	libcxx/test/benchmarks/format/write_string_comparison.bench.cpp
+10	-1	libcxx/test/benchmarks/allocation.bench.cpp
+5	-5	libcxx/test/benchmarks/ContainerBenchmarks.h
+54	-146	67 files not shown
+240	-161	73 files

LLVM/project 4573095 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit '31ad71477b68d9cafc033011e6a556a542199d82' into users/meinersbur/irbuilder-extract

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	4,106 files not shown
+431,905	-511,379	4,112 files

LLVM/project ed40726 — llvm/test/CodeGen/AMDGPU global-atomicrmw-fmax.ll global-atomicrmw-fmin.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll

Nov 4, 2024 by U-BERGUFFLEN\meinersbur on ⎇

users/meinersbur/irbuilder-extract

Merge commit '69882261b6f50bef5dbd8bf83aeabc08d9931c7a' into users/meinersbur/irbuilder-extract

Delta		File
+7,997	-7,524	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+7,997	-7,524	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+9,394	-2,007	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+9,546	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+3,578	-3,584	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+5,975	-1,080	llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+44,487	-21,719	6,808 files not shown
+406,120	-189,297	6,814 files

LLVM/project 31ad714 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 2, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

erge commit 'e17a39bc314f97231e440c9e68d9f46a9c07af6d' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	4,106 files not shown
+431,905	-511,379	4,112 files

LLVM/project 6988226 — llvm/test/CodeGen/AMDGPU global-atomicrmw-fmin.ll global-atomicrmw-fmax.ll, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll

Nov 2, 2024 by Michael Kruse on ⎇

users/meinersbur/irbuilder-extract-refactor

Merge commit 'b143b2483fc5d7e73763ff9292dec6479552de9e' into users/meinersbur/irbuilder-extract-refactor

Delta		File
+7,997	-7,524	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+7,997	-7,524	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+9,394	-2,007	llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+9,546	-0	llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+3,578	-3,584	llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+5,975	-1,080	llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+44,487	-21,719	6,808 files not shown
+406,120	-189,297	6,814 files

LLVM/project 254d2eb — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 1, 2024 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvenable-max-safe-distance-in-predicated-datawithevl-vectorization-mode

Rebase

Created using spr 1.3.5

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	26,088 files not shown
+2,335,277	-1,222,511	26,094 files

LLVM/project c55290e — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 25, 2024 by Simon Pilgrim via Alex Richardson on ⎇

users/arichardson/spr/main.datalayoutlangref-split-non-integral-and-unstable-pointer-properties

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,113	-881,962	18,271 files

LLVM/project 35afb97 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayoutlangref-split-non-integral-and-unstable-pointer-properties

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	18,265 files not shown
+1,539,112	-881,961	18,271 files

LLVM/project 1bda0dd — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 25, 2024 by Alex Richardson on ⎇

users/arichardson/spr/datalayout-refactor-storage-of-non-integral-address-spaces

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,901 files not shown
+1,517,614	-867,434	17,907 files

LLVM/project e62ef5f — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/runtimes-allow-building-against-an-installed-llvm-tree

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	17,621 files not shown
+1,489,827	-860,953	17,627 files

LLVM/project 58f7320 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Oct 24, 2024 by Florian Hahn via Alex Richardson on ⎇

users/arichardson/spr/main.runtimes-allow-building-against-an-installed-llvm-tree

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	17,620 files not shown
+1,489,825	-860,949	17,626 files

LLVM/project 942a6e9 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 24, 2024 by Alex Richardson on ⎇

users/arichardson/spr/sanitizer_allocatorcpp-ensure-at-least-sizeofvoid-alignment

rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	46,218 files not shown
+4,313,171	-1,926,653	46,224 files

LLVM/project 9028b4e — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 15, 2024 by wanglei on ⎇

users/wangleiat/spr/loongarch-add-options-for-annotate-tablejump

reimplement

Created using spr 1.3.5-bogner

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	15,921 files not shown
+1,245,447	-839,596	15,927 files

LLVM/project fb87349 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Oct 8, 2024 by Florian Mayer on ⎇

users/fmayer/spr/mte-do-not-allow-local-aliases-to-mte-globals

reb

Created using spr 1.3.4

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	10,988 files not shown
+937,390	-704,057	10,994 files