LLVM / project - FreshBSD

LLVM/project f2abcde — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

users/meinersbur/flang_runtime_remove-FLANG_INCLUDE_RUNTIME

Merge branch 'main' into users/meinersbur/flang_runtime_FortranDecimal

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+233	-6,579	llvm/test/DebugInfo/NVPTX/debug-info.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+19,871	-21,121	4,699 files not shown
+229,007	-108,850	4,705 files

LLVM/project df1b617 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/AMDGPU dagcombine-fmul-sel.ll

Jan 20 by ZhaoQi via GitHub on ⎇

users/zhaoqi5/pre-commit-tlsle-mergebaseoffset-tests

Merge branch 'main' into users/zhaoqi5/pre-commit-tlsle-mergebaseoffset-tests

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+3,130	-1,856	llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+25,717	-13,992	5,312 files not shown
+294,216	-135,084	5,318 files

LLVM/project eab9b11 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 17 by Alexey Bataev on ⎇

users/alexey-bataev/spr/lvfix-max-safe-elements-calculations

Rebase, address comments

Created using spr 1.3.5

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,263	-2,208	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+21,901	-16,750	3,291 files not shown
+182,635	-84,891	3,297 files

LLVM/project f1a1be0 — llvm/test/CodeGen/RISCV/rvv vfma-vp.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i8-stride-8.ll

Jan 17 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpimproved-reduction-costcodegen

Rebase

Created using spr 1.3.5

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,429	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,263	-2,208	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+21,901	-16,750	4,167 files not shown
+210,098	-98,516	4,173 files

LLVM/project 31f9136 — clang/include/clang/Basic BuiltinsX86.td, llvm/test/CodeGen/AMDGPU dagcombine-fmul-sel.ll

Jan 17 by ZhaoQi via GitHub on ⎇

users/zhaoqi5/avoid-scheduling-and-attach-relax

Merge branch 'main' into users/zhaoqi5/avoid-scheduling-and-attach-relax

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,056	-4,201	llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+5,378	-4	clang/include/clang/Basic/BuiltinsX86.td
+2,667	-2,586	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+3,130	-1,856	llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+25,717	-13,992	4,774 files not shown
+272,955	-129,723	4,780 files

LLVM/project a8d8e9b — clang/test/CodeGen/AArch64/fp8-intrinsics acle_sve2_fp8_reinterpret.c, llvm/test/CodeGen/RISCV memcpy.ll

Jan 14 by Paul Kirth on ⎇

users/ilovepi/spr/reapply-fuchsiacmake-allow-using-fatlto-when-building-runtimes-119252

Rebase on main

Created using spr 1.3.6-beta.1

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,182	-0	clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
+2,164	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+760	-760	llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+1,375	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+676	-359	llvm/test/CodeGen/RISCV/memcpy.ll
+12,996	-6,464	1,397 files not shown
+57,771	-26,846	1,403 files

LLVM/project dfe7d7b — clang/test/CodeGen/AArch64/fp8-intrinsics acle_sve2_fp8_reinterpret.c, llvm/test/CodeGen/RISCV memcpy.ll

Jan 14 by Paul Kirth on ⎇

users/ilovepi/spr/main.reapply-fuchsiacmake-allow-using-fatlto-when-building-runtimes-119252

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,182	-0	clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
+2,164	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+760	-760	llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+1,375	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+676	-359	llvm/test/CodeGen/RISCV/memcpy.ll
+12,996	-6,464	1,397 files not shown
+57,771	-26,846	1,403 files

LLVM/project 31067ba — clang/test/CodeGen/AArch64/fp8-intrinsics acle_sve2_fp8_reinterpret.c, llvm/test/CodeGen/RISCV memcpy.ll

Jan 14 by Paul Kirth on ⎇

users/ilovepi/spr/libunwindcmake-compile-_unwind-routines-with-fexceptions

Rebase on main

Created using spr 1.3.6-beta.1

Delta		File
+4,839	-5,345	llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+3,182	-0	clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
+2,164	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+760	-760	llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+1,375	-0	llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+676	-359	llvm/test/CodeGen/RISCV/memcpy.ll
+12,996	-6,464	1,397 files not shown
+57,771	-26,846	1,403 files

LLVM/project 7aeb1c9 — llvm/test/MC/AMDGPU gfx12_asm_vop3c_dpp16-fake16.s gfx12_asm_vop3cx-fake16.s, llvm/test/MC/Disassembler/AMDGPU gfx11_dasm_vopc.txt gfx11_dasm_vop3_from_vopc.txt

Jan 13 by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpinitial-non-power-of-2-but-still-whole-register-for-remaining-nodes

Rebase, address comments

Created using spr 1.3.5

Delta		File
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,583	-2,582	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,413	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,205	-2,204	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+2,065	-2,062	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+3,414	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3cx-fake16.s
+19,327	-9,258	1,584 files not shown
+100,551	-44,646	1,590 files

LLVM/project b39c5cb — mlir/include/mlir/Transforms InliningUtils.h, mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

Jan 13 by William Moses via GitHub on ⎇

main

[MLIR][LLVM] Fix inlining of a single block ending with unreachable (#122646)

alternate option to https://github.com/llvm/llvm-project/pull/122615

Delta		File
+16	-0	mlir/test/Dialect/LLVMIR/inlining.mlir
+15	-1	mlir/lib/Transforms/Utils/InliningUtils.cpp
+10	-0	mlir/include/mlir/Transforms/InliningUtils.h
+8	-0	mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+49	-1	4 files

LLVM/project d4c9588 — llvm/test/MC/AMDGPU gfx12_asm_vop3c_dpp16-fake16.s gfx12_asm_vop3cx-fake16.s, llvm/test/MC/Disassembler/AMDGPU gfx11_dasm_vopc.txt gfx11_dasm_vop3_from_vopc.txt

Jan 13 by wanglei on ⎇

users/wangleiat/spr/lldbloongarch-add-lsx-and-lasx-register-definitions-and-operations

Merge into a singal test, and fix issue of failing to restore regs after `expr`

Created using spr 1.3.5-bogner

Delta		File
+6,647	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16-fake16.s
+2,583	-2,582	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+2,413	-2,410	llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,205	-2,204	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+2,065	-2,062	llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+3,414	-0	llvm/test/MC/AMDGPU/gfx12_asm_vop3cx-fake16.s
+19,327	-9,258	1,113 files not shown
+74,707	-35,545	1,119 files

LLVM/project b306eff — mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp, mlir/test/Dialect/LLVMIR inlining.mlir

Jan 11 by William Moses via GitHub on ⎇

main

[MLIR] Enable inlining for private symbols (#122572)

The inlining code for llvm funcs seems to have needlessly forbidden
inlining of private (e.g. non-cloning) symbols.

Delta		File
+13	-0	mlir/test/Dialect/LLVMIR/inlining.mlir
+0	-2	mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+13	-2	2 files

LLVM/project 16e61cf — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Jan 7 by Wang Pengcheng on ⎇

users/wangpc-pp/spr/riscv-add-riscv_atomich-and-zawrs-builtins

Rebase

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	45,766 files not shown
+4,106,333	-2,097,168	45,772 files

LLVM/project 631bc35 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Dec 21, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/replace

Merge branch 'main' into users/chapuni/cov/single/replace

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,081	-2,450	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,046	-22,710	26,925 files not shown
+2,067,496	-1,063,533	26,931 files

LLVM/project ce7c17d — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Dec 21, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/pair

Merge branch 'main' into users/chapuni/cov/single/pair

Delta		File
+16,880	-2,842	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+19,618	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,081	-2,450	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,046	-22,710	26,925 files not shown
+2,067,496	-1,063,533	26,931 files

LLVM/project d7d008b — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Dec 11, 2024 by Vitaly Buka via GitHub on ⎇

users/vitalybuka/spr/libclocale-update-grouping-tests

Merge branch 'main' into users/vitalybuka/spr/libclocale-update-grouping-tests

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	43,237 files not shown
+4,159,794	-2,020,023	43,243 files

LLVM/project e51ce07 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprasmprintercallgraphsection-emit-call-graph-section-4

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 17ee91d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.asmprintercallgraphsection-emit-call-graph-section-4

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project 4f31680 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

Rebase on top of upstream main. Remove opt has_value, value use.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,612	-1,404,794	25,904 files

LLVM/project a993e6d — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extract-and-propagate-indirect-call-type-ids

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 26a149b — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 2cb9de4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.callsiteinfocallgraphsection-extend-callsiteinfo-with-typeid

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project a3ca3e2 — llvm/test/CodeGen/RISCV/rvv vloxseg-rv64.ll vluxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,610	-1,404,792	25,904 files

LLVM/project 08dc8a4 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprmain.clangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 23ac5ef — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by Necip Fazil Yildiran via prabhukr on ⎇

users/Prabhuk/sprcallgraphsection-add-call-graph-section-options-and-documentation

Rebase on top of upstream main.

Created using spr 1.3.6-beta.1

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project c0b6218 — llvm/test/CodeGen/RISCV/rvv vluxseg-rv64.ll vloxseg-rv64.ll

Nov 20, 2024 by LLVM GN Syncbot via prabhukr on ⎇

users/Prabhuk/sprmain.callgraphsection-add-call-graph-section-options-and-documentation

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Delta		File
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+17,258	-17,152	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+14,327	-17,447	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
+12,923	-11,789	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
+89,016	-92,776	25,898 files not shown
+2,366,606	-1,404,789	25,904 files

LLVM/project 6675226 — clang/test/Sema/aarch64-sve2-intrinsics acle_sve2.cpp, llvm/test/CodeGen/AMDGPU flat_atomics_i64_system_noprivate.ll flat_atomics_i64_noprivate.ll

Nov 20, 2024 by NAKAMURA Takumi on ⎇

users/chapuni/cov/single/merge

Merge branch 'users/chapuni/cov/single/test' into users/chapuni/cov/single/merge

Delta		File
+9,493	-2,213	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+8,111	-1,718	llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+9,196	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+3,630	-3,624	llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+6,804	-0	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+3,290	-3,290	clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2.cpp
+40,524	-10,845	8,255 files not shown
+418,694	-225,256	8,261 files

LLVM/project cfc6dbe — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime

Merge branch 'users/meinersbur/flang_runtime_move-files' into users/meinersbur/flang_runtime

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,041 files not shown
+1,309,194	-678,314	16,047 files

LLVM/project 7caea4d — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_move-files

Merge branch 'users/meinersbur/flang_runtime_split-headers2' into users/meinersbur/flang_runtime_move-files

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,200	-678,317	16,048 files

LLVM/project bf24912 — clang/test/CodeGen aarch64-neon-intrinsics.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Nov 15, 2024 by Michael Kruse on ⎇

users/meinersbur/flang_runtime_split-headers2

Merge branch 'users/meinersbur/flang_runtime_split-headers' into users/meinersbur/flang_runtime_split-headers2

Delta		File
+20,186	-0	llvm/test/CodeGen/RISCV/rvv/expandload.ll
+16,877	-2,839	llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+17,418	-0	clang/test/CodeGen/AArch64/neon-intrinsics.c
+0	-17,418	clang/test/CodeGen/aarch64-neon-intrinsics.c
+16,049	-0	llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+12,078	-2,340	llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+82,608	-22,597	16,042 files not shown
+1,309,196	-678,318	16,048 files