SysV SHM: make kern_shmat static
This is the opposite of most kern_ cases, but SysV IP is designed to be
loaded as a module and freebsd32 support lives inside the main
implementation file. Arguably it should be in a seperate module with a
dependency, but that's a refactor for another day.
Effort: CHERI upstreaming
Sponsored by: Innovate UK
Pull Request: https://github.com/freebsd/freebsd-src/pull/2284
zfs: merge openzfs/zfs at 013c77e66
Notable upstream pull request merges:
#17567 816804dfd Add support for anyraid vdevsG
#18826 -multiple FDT: don't extend dedup across RAIDZ expansion
#18861 1ff8fc14a Fix out-of-bound access when resizing in receive_spill
#19026 518021947 Add alloc factor logic
#19091 e056f4df3 don't send spill or oversized blocks as WRITE_EMBEDDED
#19125 6d5d3f635 Wait for the txg-time database write before setting
spa_final_txg
#19170 b060bcb1d zio: drop a queued scan read only when its block is freed
#19171 3db7dde41 dsl_scan: resume a scan which suspends at the origin
snapshot
#19178 497f28f07 vdev_raidz: keep unverified dRAID rebuild repairs
speculative
#19188 5f1957a15 spa: number new txgs above every uberblock on disk
#19190 495d09b51 Export zpool_valid_proplist from libzfs
#19191 ed07ad74e zdb: Lower eviction timeouts on prefetched data
#19192 86b3fb1f4 Build the pool stats config without the namespace lock
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modstat: don't copyout while holding a lock
If a user arranges for a page fault to never be filled (e.g., via a
FUSE file system), this can hold the shared lock forever.
To make this all work, refactor kern_modstat and freebsd32_modstat to
malloc a temporary buffer and fill it before copying it out rather
than doing a bunch of copies.
Add COMPAT_* ifdefs around compat code. The module_stat_v1 code is
really for a.out binaries in practice and thus a bit questionable.
Reviewed by: markj
Reported by: llm-postcr
Sponsored by: Innovate UK
Fixes: 7f8c2056db1e ("modstat: avoid copying from freed memory")
Differential Revision: https://reviews.freebsd.org/D61432
allwinner: h6: Put the PM pins in bank M
The PM0 to PM4 entries of the pad table of the R_PIO controller had port
0 and pin 0, copied from the PL ones, so no pin could be found for a
<&r_pio 1 N> specifier. On the Pine H64 model B the reset GPIO of the
SDIO WiFi power sequence is PM3, and the kernel panicked in
mmc_pwrseq_attach() with "invalid pin" as the pin number was never set.
Use port 1 and the real pin numbers, like the PL entries do with port 0.
Tested on: H6
aw_ccu: h6: Use the 1x PLL_PERIPH as parents of the MMC clocks
The MMC clocks of the H6 have the doubled outputs of the PLL_PERIPH0
and PLL_PERIPH1 as inputs of their mux, followed by a fixed post divider
of 2 that the driver does not know about. The rate it computed was
twice the real one: on a Pine H64 the SD card requested at 50MHz and the
eMMC at 52MHz ran at half of that, and transfers at about half the speed
they should reach. U-Boot does the same compensation, as it pretends
the parent is the 1x PLL.
Name the 1x PLLs as parents, like the H3 driver does. The position in
the mux is the same.
Tested on: H6
aw_gpio: Fail when a pin cannot be mapped
aw_gpio_map_gpios() returned success without setting the pin when no
entry of the pad table matched the bank and pin of the specifier, so
the caller went on with whatever was in its variable. Return EINVAL.
Tested on: H6
aw_ccu: h6: Document why the UART gates are not enabled
Enabling the gates makes uart_snps get the clock rate from the CCU, it
then detects a 256 bytes FIFO and the input of the console is delayed:
a character is only seen when the next one is typed. Explain it in the
comment instead of the old "weird behavior".
Tested on: H6
aw_ccu: h6: Add the HDMI CEC clock
Add the HDMI CEC clock, a mux and a gate. Its second parent is
PLL_PERIPH0(2X) divided by a fixed 36621, which gives about 32.768kHz,
so add this division as a fixed clock.
Tested on: H6
aw_ccu: h6: Add the PCIe clocks
Add the 100MHz reference clock, which is PLL_PERIPH0(4X) divided by 24,
its two gates, the MAXI and AUX clocks, and the bus gate and the two
resets of PCIe.
Tested on: H6
aw_ccu: h6: Fix the id of PLL_DE and the names of the R_APB2 gates
CLK_PLL_DE had the same id as CLK_PLL_VE, 14, so two clocks of the CCU
shared an id. Use 15 as the Linux driver does.
The gates of the R_APB2 UART and I2C were named r_apb1-uart and
r_apb1-i2c, but their parent is r_apb2. Name them after it.
Tested on: H6
aw_ccu: h6: Add the CSI clocks
Add the CCI gate, the TOP and MCLK clocks, and the bus gate and reset of
the CSI. The mux of the TOP clock has no parent for the value 1.
Tested on: H6
aw_ccu: h6: Add the DE, DI, GPU, CE, VE, EMCE and VP9 clocks
Add the module clocks, bus gates and resets of the display engine, the
deinterlacer, the GPU, the crypto engine, the video engine, the EMCE
and the VP9 decoder.
Tested on: H6
aw_ccu: h6: Add the HDMI, TCON and HDCP clocks
Add the module clocks, bus gates and resets of HDMI, TCON LCD0, TCON
TV0 and HDCP, and the HDMI slow clock. The TCON LCD clock has no
divider.
The HDMI CEC clock is not added, its second parent is PLL_PERI0(2X)
divided by 36621, which needs a fixed pre-divider.
Tested on: H6
aw_ccu: h6: Add the IR, W1, RSB and RTC clocks of the R CCU
Add the IR and 1-wire module clocks, which are a gate, a mux, a power
of two N and a M, the RSB and RTC bus gates and the RSB reset.
The manual does not document the registers of the R CCU, the offsets
and the fields are the ones used by Linux.
Tested on: H6
aw_ccu: h6: Add the MBUS clock
Add the MBUS clock, which selects between OSC24M, PLL_PERIPH0(2X),
PLL_DDR0 and PLL_PERIPH0(4X) and has a divider from 1 to 8, with its
reset, and the gates of the MBUS clock of the DMA, VE, CE, TS, NAND, CSI
and DE interlace masters.
Tested on: H6
