Add <sys/cdefs.h> inclusion to a number of headers.
These are the last non-contrib headers that were using macros from
<sys/cdefs.h> but were not including it.
nvmm(4): Improve guest TSC handling
Don't skip updating TSC if the emulator set a zero value, which can
happen if the emulator resets the VM. In this case, we really want this
to be applied.
Meanwhile, rename 'gtsc_match' to 'gtsc_last'.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Make use of kernel_fpu_begin() and kernel_fpu_end()
The kernel_fpu_*() API was added to help drm/amdgpu in commit
1be00ff1850ebb705db236c08160ee8fea99b32a, shortly after I ported NVMM.
Use this API to reduce difference with the NVMM upstream.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Fix CPUID bits
- FMA/F16C/VAES/VPCLMULQDQ are part of AVX and should not be exposed.
- PSE36 is not supported and should not be exposed.
- EferLmsleUnsupp should be unconditionally exposed on AMD.
- SHA is part of XMM, which is supported, so it can be exposed.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Add TPR support for SVM
If DecodeAssist is supported, intercept writes to CR8, and deliver
TPR_CHANGED VMEXITs to the emulator. This should improve the accuracy of
interrupt delivery on guests like Windows that make heavy use of CR8.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Remove NVMM_IOC_VCPU_INJECT and associated artifacts
Events are injected in vcpu_run, so this ioctl is not used anymore.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Fix the XSAVE area size
- Fix nvmm_x86_xsave_size(): x87/SSE are in the legacy region, and the
size of that region is constant regardless of whether SSE is enabled.
- When XSAVEC is supported, CPUID leaf 0x0000000D:ECX=1[EBX] is supposed
to return the current XSAVE area size, but NVMM mistakenly returns
zero. Given that NVMM supports only x87/SSE, XSAVEC is useless, so
rather than fixing the EBX return value, just don't advertise XSAVEC.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Advertise new CPUID and ARCH_CAP bits
Advertise SsbdNotRequired and BTC_NO bits in CPUID and mitigation bits
in ARCH_CAP, for the guest to know not to turn on costly mitigations if
the CPU doesn't require them.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Sync a few minor changes from m00nbsd
* Add new CPUID bits, and rename a few existing ones.
* Define NPF constants locally; don't rely on OS-provided PGEX_* values.
* Use os_vmspace_t instead of 'struct vmspace', which is the proper
OS-independent structure.
No functional changes.
Credit: Maxime Villard (m00nbsd)
nvmm(4): Explicitly specify sub-leaf 0 for CPUID 0x00000007
The 0x00000007 (Structured Extended Feature Flags) leaf has sub-leaves,
so use x86_get_cpuid2() to explicitly specify the sub-leaf for
correctness and portability.
See also the commit 0087a1d163488a57787a9a6431dd94070b1988d4 that fixes
do_cpuid() to explicitly set ECX=0.
nvmm(4): Improve ARCH_CAP feature bit exposure on VMX
The CPUID_0_07_EDX is reserved and is zero on AMD SVM, so simplify the
logic to expose the ARCH_CAP feature bit on VMX.
This improves my previous commit 01caa5e3ae83149daac28ad634f8236d39dbaedd.
Credit: Maxime Villard (m00nbsd)
doc: Document the steps to import and upgrade GCC
This is partially based on a README created by Scott Parlane (sparlane).
Credit: Scott Parlane (sparlane)
