pf: fix min-ttl and set-tos for nat64
If we have both af-to and min-ttl or set-tos on a single rule we didn't
apply the new ttl or tos.
That's because the scrub code still applied the change, but we
subsequently create a new header for the new address family. That's done
based on the ttl/tos saved in the struct pf_pdesc, which are the values
from the incoming packet, before the scrub modification(s).
Also update the struct pf_pdesc values when we update packets.
Reported by: Marek Zarychta
Sponsored by: Rubicon Communications, LLC ("Netgate")
[clang-tidy] New option to remove arguments from the command line (#164344)
When using clang-tidy from a compilation database, some options might
not be
recognized by clang if the compilation database was generated for
another compiler.
This forces the user to add conditional code in their CMakeLists.txt to
remove
those arguments when using clang-tidy.
A new option was added to the .clang-tidy config to remove
those unknown flags without the need to generate a second
compilation_commands.json
Fixes #108455
Please see #111453 and #162201 for previous discussions regarding this
option.
This implementation was slightly changed from the initial PR based on
the following comment
[6 lines not shown]
[AMDGPU] tensor_{load_to/store_from}_lds => ..._d2 simplification (#171540)
This commit adds the rewrite
```
llvm.amdgcn.tensor.{load.to/store.from}.lds(
<4 x i32> %d0, <8 x i32> %d1, <4 x i32> zeroinitializer,
<4 x i32> zeroinitializer, i32 [cachepolicy])
=>
llvm.amdgcn.tensor.{load.to/store.from}.lds.d2(
<4 x i32> %$d0, <8 x i32> %d1, i32 [cachepolicy])
```
This is justifed because, when the short encoding that uses the NULL
SGPR for registers 2 and 3 is used, the hardware acts as if those
registers were 0, including in the gather mode.
It is always safe not to run this transformation.
(Note: tests were LLM'd and then tweaked.)
[X86] combineStore - attempt to store i256/i512 types as v4i64/v8i64 vectors (#172288)
If the larger than legal scalar integer is freely foldable to a vector
type, or is likely to be custom lowered to an operation using vectors,
attempt to convert to a vector store.
This doesn't appear to be worth it for i128 types which can more easily
convert between types with extra insert_subvector steps etc.
InstCombine: Stop using m_c_BinOp for non-commutative ops
The previous flow tried both m_BinOp and m_c_BinOp for noncommutative
ops. Seems to have worked out OK though, since there are no test changes.
netmap: Fix error handling in nm_os_extmem_create()
We bump the object reference count prior to mapping it into the kernel
map, at which point the vm_map_entry owns the reference. Then, if
vm_map_wire() fails, vm_map_remove() will release the reference, so we
should avoid decrementing it in the error path.
Reported by: Ilja van Sprundel <ivansprundel at ioactive.com>
Reviewed by: vmaffione
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D53066
(cherry picked from commit dfc1041c08ba32f24b8050b4d635a0bbbfd9b767)
netmap: Fix error handling in nm_os_extmem_create()
We bump the object reference count prior to mapping it into the kernel
map, at which point the vm_map_entry owns the reference. Then, if
vm_map_wire() fails, vm_map_remove() will release the reference, so we
should avoid decrementing it in the error path.
Reported by: Ilja van Sprundel <ivansprundel at ioactive.com>
Reviewed by: vmaffione
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D53066
(cherry picked from commit dfc1041c08ba32f24b8050b4d635a0bbbfd9b767)
[SPIRV][HLSL] Add FixedVector GEP legalization (#171682)
fixes #170241
PR #169090 updated vector swizzle elements individually for HLSL This is
because rawbuffer writes via rawBufferStore can cause datarace in
concurrent writing the way vectors are written all at once. This means
we needed individual writes per element. So that means we need to be
able to GEP into an element of a vector.
The SPIRV backend did not support this pattern. SPIRV assumes Composite
types (ie Vectors, Structs, and Arrays) only for Ptr legalization in
it's store transformations via transformStore.
Fixing things at the point of ptr legalziation for the store would be
too late because we would have lost critical ptr type information still
available in LLVM IR. Instead what we needed to do is teach the
walkLogicalAccessChain used by buildLogicalAccessChainFromGEP to
converts a byte-offset GEP on an i8-pointer into a logical SPIR-V
[14 lines not shown]
Fix another int-conversion issue in python code and bump REVISION
In file included from /usr/local/include/python3.13/Python.h:73,
from py-rcsparse.c:18:
py-rcsparse.c: At top level:
/usr/local/include/python3.13/object.h:138:9: error: initialization
of 'long int' from 'PyTypeObject *' {aka 'struct _typeobject *'}
makes integer from pointer without a cast [-Wint-conversion]
138 | (type) \
| ^
py-rcsparse.c:773:9: note: in expansion of macro 'PyObject_HEAD_INIT'
773 | PyObject_HEAD_INIT(&PyType_Type)
| ^~~~~~~~~~~~~~~~~~
OK sthen@
amd64/vmm.c: Fix an incorrect memory segment check in vm_iommu_{un}map
This change fixes two checks that conflated memory mapping and memory
segment idenitifers. In both cases the code iterates over all memory
mappings but passes the index to `vm_memseg_sysmem`, which is wrong.
Fix this by passing the memory mapping's segment identifier instead.
Differential Revision: https://reviews.freebsd.org/D54210
Reviewed by: markj
Fixes: c76c2a19ae37
PR: 290920
(cherry picked from commit f1809eab82a796845f126b703c01d4a31ccf2193)
AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES
Move G_UNMERGE_VALUES handling to AMDGPURegBankLegalizeRules.cpp.
Fix sgpr S16 unmerge by lowering using shift and using S32.
Previously sgpr S16 unmerge was selected using _lo16 and _hi16 subreg
indexes which are exclusive to vgpr register classes.
For remaing cases we do trivial mapping, assigns same reg bank
to all operands, vgpr or sgpr.
amd64/vmm.c: Fix an incorrect memory segment check in vm_iommu_{un}map
This change fixes two checks that conflated memory mapping and memory
segment idenitifers. In both cases the code iterates over all memory
mappings but passes the index to `vm_memseg_sysmem`, which is wrong.
Fix this by passing the memory mapping's segment identifier instead.
Differential Revision: https://reviews.freebsd.org/D54210
Reviewed by: markj
Fixes: c76c2a19ae37
PR: 290920
Set webshell homedir properly
This commit retrieves the configured homedir for users authenticating
via webshell. If NSS responds that user does not exist, then raise
an exception.
NAS-138906 / 26.04 / Refactor `ReplicationService._validate` (#17814)
This method is a bit long. Split it up into four smaller private methods
for better maintainability. This results in no behavior change.
We're mixing quote types in this file, so standardize double quotes as
well (easier to grep for expressions containing string literals).
http://jenkins.eng.ixsystems.net:8080/job/tests/job/api_tests/6921/
Fix build when the build directory isn't just immediately nested in the source dir
The include path here tried to recover the root source directory by assuming
a build directory immediately nested there.
aw_rtc: bump settime() delays
There are delay loops, checking the BUSY status bit, before writing to
the date or time registers. Each iteration contains a 1usec delay, for a
maximum of 70 iterations.
This is frequently not enough on the D1 platform, where the message is
emitted:
rtc0: could not set date, RTC busy
Bump the loop delay to 10usecs each, and the maximum number of
iterations to 150, for a maximum delay of 1.5msecs between each write of
the register.
In my testing this seems to be adequate.
The loop variable is renamed for clarity/simplicity.
[4 lines not shown]
