LLVM/project e054384.github/workflows prune-unused-branches.py prune-branches.yml

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+89-0.github/workflows/prune-unused-branches.py
+30-0.github/workflows/prune-branches.yml
+119-02 files

LLVM/project 13cd700offload/plugins-nextgen/level_zero/src L0Memory.cpp

[NFC][Offload] Rename a function (#175673)

Renamed a function as suggested in #175664.
DeltaFile
+6-6offload/plugins-nextgen/level_zero/src/L0Memory.cpp
+6-61 files

FreeNAS/freenas f8d6a97src/middlewared/middlewared/plugins auth.py

Fix
DeltaFile
+5-4src/middlewared/middlewared/plugins/auth.py
+5-41 files

FreeNAS/freenas 1355993tests/directory_services test_directory_services_basic.py

Remove import from plugins.   Define local to the test module.
DeltaFile
+3-1tests/directory_services/test_directory_services_basic.py
+3-11 files

FreeNAS/freenas 0f00c34tests/directory_services test_directory_services_basic.py

Fix import.
DeltaFile
+1-2tests/directory_services/test_directory_services_basic.py
+1-21 files

LLVM/project 99d6141llvm/include/llvm/Transforms/Utils LowerMemIntrinsics.h, llvm/lib/Transforms/Utils LowerMemIntrinsics.cpp

Memset
DeltaFile
+112-37llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
+31-18llvm/test/Transforms/PreISelIntrinsicLowering/X86/memcpy-inline-non-constant-len.ll
+20-8llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll
+4-2llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h
+0-3llvm/utils/profcheck-xfail.txt
+167-685 files

FreeNAS/freenas b4cac52src/middlewared/middlewared/plugins auth.py

Fix
DeltaFile
+1-1src/middlewared/middlewared/plugins/auth.py
+1-11 files

FreeBSD/ports 85819a4math/Imath Makefile

math/Imath: default-enable PYTHON

Required for upcoming new port,
Reported by:    Martin Filla
DeltaFile
+2-1math/Imath/Makefile
+2-11 files

LLVM/project adf7824llvm/lib/Transforms/Vectorize VPlan.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize tripcount.ll

capture weights
DeltaFile
+23-6llvm/lib/Transforms/Vectorize/VPlan.cpp
+9-6llvm/test/Transforms/LoopVectorize/tripcount.ll
+2-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+34-123 files

LLVM/project 5d45dfdllvm/lib/CodeGen CodeGenPrepare.cpp

[WIP][profcheck] Codegen Prepare
DeltaFile
+15-2llvm/lib/CodeGen/CodeGenPrepare.cpp
+15-21 files

LLVM/project a204658llvm/test/Transforms/LoopVectorize tripcount.ll

[NFC] use UTC for LoopVectorize/tripcount.ll
DeltaFile
+213-29llvm/test/Transforms/LoopVectorize/tripcount.ll
+213-291 files

LLVM/project a01b7c2. .gitignore

[LLVM] Ignore two Cursor specific files. (#175683)

DeltaFile
+2-0.gitignore
+2-01 files

LLVM/project ed9f5c9llvm/lib/Target/RISCV RISCVInstrInfoVPseudos.td, llvm/test/tools/llvm-mca/RISCV/SiFiveX390 vector-fp.s

[RISCV] Add the missing SEW search table field to vector FMA instructions (#175646)

We split vector floating point FMA (pseudo) instructions' opcodes by SEW
since c6b7944be4dfbb1fb35301c670812726845acaa7 , but forgot to populate
their `SEW` field, which is used by various search tables. This results
in incorrect pseudo instruction opcodes lookup -- and to a larger
extent, incorrect scheduling class lookups -- in llvm-mca. This patch
fixes such issue.
DeltaFile
+129-129llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
+48-48llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test
+32-32llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+210-2104 files

LLVM/project 438f887llvm CMakeLists.txt

[cmake] Make CMAKE_BUILD_TYPE=Release the default (#174520)

Currently, we report a fatal error if the user leaves CMAKE_BUILD_TYPE
blank. This was implemented in https://reviews.llvm.org/D124153 /
350bdf9227ceb , based on this RFC:

https://discourse.llvm.org/t/rfc-select-a-better-linker-by-default-or-warn-about-using-bfd/61899/1

Tom Stellard mentioned that he'd like to revisit this on Discord, and
Aiden, myself, and apparently most people on the original RFC agree, so
I'm proposing we do it. However, on the review, several folks objected
and insisted that Debug was a better default. I want to reopen the
question.

I think we've made the wrong tradeoff. I wish Debug builds worked out of
the box on most systems, but they don't, and LLVM has only gotten bigger
over the last four years, making the build scalability problems of Debug
builds worse. I think we should optimize our build configuration for new
developers, not experienced longtime contributors who are invested

    [9 lines not shown]
DeltaFile
+3-8llvm/CMakeLists.txt
+3-81 files

FreeNAS/freenas bea94edsrc/middlewared/middlewared/plugins/directoryservices_ connection.py, src/middlewared/middlewared/plugins/network_ common.py global_config.py

Avoid import of aiohttp, move DEFAULT_DOMAIN_NAME from utils/network.py to plugins/network_/common.py
DeltaFile
+3-0src/middlewared/middlewared/plugins/network_/common.py
+0-3src/middlewared/middlewared/utils/network.py
+1-1src/middlewared/middlewared/plugins/directoryservices_/connection.py
+1-1src/middlewared/middlewared/plugins/network_/global_config.py
+5-54 files

LLVM/project 2329d04llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

Remove cleanup of incorrect output in test dir (#171256)

This follows #171255 , removing the cleanup line.
DeltaFile
+0-1llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+0-11 files

LLVM/project a7ad427llvm/lib/Transforms/Vectorize VPlan.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize tripcount.ll

capture weights
DeltaFile
+23-6llvm/lib/Transforms/Vectorize/VPlan.cpp
+9-6llvm/test/Transforms/LoopVectorize/tripcount.ll
+2-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+34-123 files

LLVM/project 0dcd112llvm/test/Transforms/LoopVectorize tripcount.ll

[NFC] use UTC for LoopVectorize/tripcount.ll
DeltaFile
+213-29llvm/test/Transforms/LoopVectorize/tripcount.ll
+213-291 files

LLVM/project f9c561bllvm/lib/Transforms/Utils LoopUtils.cpp, llvm/test/Transforms/LoopVectorize branch-weights.ll

[profcheck] Fix encoding of 0 loopEstimatedTrip count (#174896)

We currently encode an estimated trip count of 0 as the latch having branch probabilities 0-0. That's an invalid pair of weights. The probability of a branch is computed as a fraction of its corresponding weight and the sum of the weights. In fact, `BranchProbabilityInfo::calcMetadataWeights` will convert this to a 1-1, meaning 50% - 50%, which isn't quite what we want. To indicate the loop is never taken, we just need to initialize the exit probability to non-zero (hence, 1)

Related: https://reviews.llvm.org/D67905

Issue #147390
DeltaFile
+5-5llvm/test/Transforms/LoopVectorize/AArch64/check-prof-info.ll
+4-1llvm/lib/Transforms/Utils/LoopUtils.cpp
+2-2llvm/test/Transforms/LoopVectorize/branch-weights.ll
+1-1llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
+12-94 files

LLVM/project 26624d5clang/include/clang/Basic BuiltinsAMDGPU.def, clang/test/CodeGenOpenCL amdgpu-features.cl amdgpu-cluster-dims.cl

[AMDGPU]Add specific instruction feature for multicast load (#175503)

DeltaFile
+7-7clang/include/clang/Basic/BuiltinsAMDGPU.def
+11-1llvm/lib/Target/AMDGPU/AMDGPU.td
+2-2clang/test/CodeGenOpenCL/amdgpu-features.cl
+2-2clang/test/CodeGenOpenCL/amdgpu-cluster-dims.cl
+2-2llvm/lib/Target/AMDGPU/FLATInstructions.td
+3-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+27-141 files not shown
+28-147 files

LLVM/project a9037dcorc-rt Maintainers.md

[orc-rt] Add Maintainers.md. (#175691)

DeltaFile
+10-0orc-rt/Maintainers.md
+10-01 files

LLVM/project 587bac6llvm/lib/Target/RISCV RISCVMakeCompressible.cpp, llvm/test/CodeGen/RISCV make-compressible-xqci.mir

[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#175572)

We only need two uses in Xqcilo load/store instructions for the base
adjustment to be profitable as compared to three uses in the base
load/store instructions.
DeltaFile
+48-5llvm/test/CodeGen/RISCV/make-compressible-xqci.mir
+38-7llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+86-122 files

LLVM/project c6fc6adclang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 avx512vlvp2intersect-builtins.c avx512vp2intersect-builtins.c

[CIR][X86] Add support for `intersect` builtins (#172554)

adds support for the
`__builtin_ia32_vp2intersect_d`/`__builtin_ia32_vp2intersect_q` x86
builtins.

Part of #167765

---------

Signed-off-by: vishruth-thimmaiah <vishruththimmaiah at gmail.com>
DeltaFile
+161-0clang/test/CIR/CodeGenBuiltins/X86/avx512vlvp2intersect-builtins.c
+77-0clang/test/CIR/CodeGenBuiltins/X86/avx512vp2intersect-builtins.c
+64-10clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+302-103 files

LLVM/project e4b2201clang/test/CodeGen/AMDGPU nullptr-in-different-address-spaces.cpp

[FIX] Add target requirement in `clang/test/CodeGen/AMDGPU/nullptr-in-different-address-spaces.cpp`
DeltaFile
+1-0clang/test/CodeGen/AMDGPU/nullptr-in-different-address-spaces.cpp
+1-01 files

LLVM/project 1b69dfeflang CMakeLists.txt, flang/include/flang/Semantics expression.h

[flang] Turn -Werror back off for Flang build (#175689)

Different build environments are picking up warnings that my testing
didn't expose; turn -Werror back off.
(And also delete an unused data member that was triggering some MSVC
warnings.)
DeltaFile
+1-1flang/CMakeLists.txt
+0-1flang/include/flang/Semantics/expression.h
+1-22 files

NetBSD/pkgsrc VblQX4ldoc CHANGES-pkgsrc-2025Q4

   doc: update for tickets 7042, 7043
VersionDeltaFile
1.1.2.6+7-1doc/CHANGES-pkgsrc-2025Q4
+7-11 files

NetBSD/pkgsrc Vhg5rH2games/tyrquake Makefile distinfo, games/tyrquake/patches patch-include_common.h

   Pullup ticket #7043 - requested by nia
   games/tyrquate: Build fix correction

   Revisions pulled up:
   - games/tyrquake/Makefile                                       1.13
   - games/tyrquake/distinfo                                       1.10
   - games/tyrquake/patches/patch-include_common.h                 1.2

   ---
      Module Name:      pkgsrc
      Committed By:     nia
      Date:             Fri Jan  9 23:02:01 UTC 2026

      Modified Files:
        pkgsrc/games/tyrquake: Makefile distinfo
        pkgsrc/games/tyrquake/patches: patch-include_common.h

      Log Message:
      tyrquake: Fix NetBSD bswap workaround.

    [3 lines not shown]
VersionDeltaFile
1.1.14.1+3-4games/tyrquake/patches/patch-include_common.h
1.12.14.1+4-1games/tyrquake/Makefile
1.9.14.1+2-2games/tyrquake/distinfo
+9-73 files

FreeBSD/ports fa5c456net-mgmt/librenms distinfo Makefile

net-mgmt/librenms: Update to 26.1.1

re: https://github.com/librenms/librenms/releases/tag/26.1.1
DeltaFile
+5-5net-mgmt/librenms/distinfo
+2-2net-mgmt/librenms/Makefile
+7-72 files

NetBSD/pkgsrc 7bY4CaHsecurity/libgcrypt distinfo, security/libgcrypt/patches patch-cipher_aria.c

   Pullup ticket #7042 - requested by nia
   security/libgcrypt: Build fix correction

   Revisions pulled up:
   - security/libgcrypt/distinfo                                   1.103
   - security/libgcrypt/patches/patch-cipher_aria.c                1.2

   ---
      Module Name:      pkgsrc
      Committed By:     nia
      Date:             Fri Jan  9 19:26:57 UTC 2026

      Modified Files:
        pkgsrc/security/libgcrypt: distinfo
        pkgsrc/security/libgcrypt/patches: patch-cipher_aria.c

      Log Message:
      libgcrypt: Fix bswap patch.
VersionDeltaFile
1.1.12.1+5-3security/libgcrypt/patches/patch-cipher_aria.c
1.102.4.1+2-2security/libgcrypt/distinfo
+7-52 files

LLVM/project 9596c92llvm/lib/Target/RISCV RISCVInstrInfo.cpp, llvm/test/CodeGen/RISCV zilsd-spill.ll zdinx-spill.ll

[RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled (#153595)

We are currently only using `PseudoRV32ZdinxSD/LD` for spills and
reloads when the register class is `GPRPairRegClass` . However, we can
use `LD_RV32/SD_RV32` when the `Zilsd` extension is enabled and certain
alignment requirements are met.
DeltaFile
+220-0llvm/test/CodeGen/RISCV/zilsd-spill.ll
+147-36llvm/test/CodeGen/RISCV/zdinx-spill.ll
+18-6llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+385-423 files