LLVM/project a7f489bllvm/lib/Target/AMDGPU SIRegisterInfo.td GCNSubtarget.h, llvm/test/CodeGen/AMDGPU regalloc-vgpr_lo128-gfx1250.mir regalloc-vgpr_lo128-gfx1250-t16.mir

[AMDGPU] Limit allocation of lo128 registers for occupancy

Parent change allows allocation of lo128 VGPRs from all 4 banks.
That may result in the undesired allocation leaving a hole of
maximum 128 registers in case if for example v0-v127 are allocated,
and v128-v255 are free.

Limit the available allocation order to the occupancy. Both hard
occupancy limits and occupancy achieved during scheduling are
considered. That is better to spill a register than to drop occupancy
in this case.
DeltaFile
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250-t16.mir
+53-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250-t16.mir
+30-4llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+29-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
+8-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+314-61 files not shown
+321-67 files

LLVM/project 663647fcross-project-tests/dtlto multimodule.test, llvm/include/llvm/LTO LTO.h

[DTLTO] Fix handling of multi-module bitcode inputs (#174624)

This change fixes two issues when processing multi-module bitcode files
in DTLTO:

1. The DTLTO archive handling code incorrectly uses
getSingleBitcodeModule(), which asserts when the bitcode file contains
more than one module.
2. The temporary file containing the contents of an input archive member
was not emitted for multi-module bitcode files. This was due to
incorrect logic for recording whether a bitcode input contains any
ThinLTO modules. In a typical multi-module bitcode file, the first
module is a ThinLTO module while a subsequent auxiliary module is
non-ThinLTO. When modules are processed in order, the auxiliary module
causes the entire bitcode file to be classified as non-ThinLTO, and the
archive-member emission logic then incorrectly skips it.

In addition, this patch adds a test that verifies that multi-module
bitcode files can be successfully linked with DTLTO. The test reproduces

    [2 lines not shown]
DeltaFile
+42-0cross-project-tests/dtlto/multimodule.test
+3-1llvm/lib/LTO/LTO.cpp
+2-0llvm/include/llvm/LTO/LTO.h
+1-1llvm/lib/DTLTO/DTLTO.cpp
+48-24 files

LLVM/project d7b6df7clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 avx512vldq-builtins.c avx10_2bf16-builtins.c

[CIR][X86] Add CIR codegen support for fpclass x86 builtins (#172813)

This implements the handling for x86-specific fpclass builtin functions.
DeltaFile
+173-0clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
+72-0clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
+72-0clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
+60-4clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+37-0clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
+36-0clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
+450-41 files not shown
+451-47 files

FreeNAS/freenas 72cf61dsrc/middlewared/middlewared/plugins network.py

whoops, forgot commit
DeltaFile
+5-3src/middlewared/middlewared/plugins/network.py
+5-31 files

LLVM/project a11feefclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp, clang/test/CIR/IR vector.cir throw.cir

[CIR] Make cir.alloca alignment mandatory (#172663)

Fixed a crash in `CIRToLLVMAllocaOpLowering` where `cir.alloca`
operations without an explicit alignment attribute caused failures.

Modified the ODS definition of `cir.alloca` to use
`ConfinedAttr<I64Attr, [IntMinValue<0>]>`. This ensures the attribute is
always present.

Added a regression test in `clang/test/CIR/Lowering/alloca.cir`.

---------

Co-authored-by: Sirui Mu <msrlancern at gmail.com>
DeltaFile
+17-17clang/test/CIR/IR/vector.cir
+13-0clang/test/CIR/Lowering/alloca.cir
+3-3clang/test/CIR/IR/throw.cir
+3-3clang/test/CIR/IR/invalid-complex.cir
+2-2clang/test/CIR/Transforms/vector-extract-fold.cir
+2-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+40-2710 files not shown
+53-4016 files

LLVM/project 779c05aclang/lib/CodeGen CodeGenPGO.cpp CodeGenPGO.h, clang/test/Profile c-mcdc-logicalop-ternary.c

[MC/DC] Create dedicated MCDCCondBitmapAddr for each Decision (#125411)

MCDCCondBitmapAddr is moved from `CodeGenFunction` into `MCDCState` and
created for each Decision.

In `maybeCreateMCDCCondBitmap`, Allocate bitmaps for all valid Decisions
and emit them order by ID, to prevent nondeterminism.
DeltaFile
+44-10clang/lib/CodeGen/CodeGenPGO.cpp
+10-8clang/test/Profile/c-mcdc-logicalop-ternary.c
+3-5clang/lib/CodeGen/CodeGenPGO.h
+0-3clang/lib/CodeGen/CodeGenFunction.h
+2-0clang/lib/CodeGen/MCDCState.h
+59-265 files

LLVM/project 01f7057utils/bazel MODULE.bazel.lock, utils/bazel/llvm-project-overlay/clang BUILD.bazel

Revert "Fix bazel build for d5442b8 (#176034)"

This reverts commit 43f1edf0cfcbcce7c928e0e27221a5de1fb797ba.

Fixed already by 44b691a1e9e1201034120d71de8bc5b9b3c044e6.
DeltaFile
+1-18utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+2-3utils/bazel/MODULE.bazel.lock
+3-212 files

LLVM/project a809862llvm/lib/Analysis ValueTracking.cpp, llvm/lib/IR Instruction.cpp Operator.cpp

[IR] Teach `drop/hasPoisonGeneratingAnnotations()` about `abs`, `ctlz` and `cttz` (#175941)

DeltaFile
+9-9llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll
+13-0llvm/lib/IR/Instruction.cpp
+11-0llvm/lib/IR/Operator.cpp
+2-3llvm/lib/Analysis/ValueTracking.cpp
+0-5llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+35-175 files

LLVM/project 43f1edfutils/bazel MODULE.bazel.lock, utils/bazel/llvm-project-overlay/clang BUILD.bazel

Fix bazel build for d5442b8 (#176034)

Bazel equivalent of cmakelists changes.
DeltaFile
+18-1utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+3-2utils/bazel/MODULE.bazel.lock
+21-32 files

LLVM/project 882560eclang/lib/Sema OpenCLBuiltins.td, clang/test/SemaOpenCL fdeclare-opencl-builtins.cl

[OpenCL] Add missing mipmap read_write image builtins to OpenCLBuiltins.td (#175748)

This issue was discovered while writing tests for #175120.
DeltaFile
+57-0clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl
+2-2clang/lib/Sema/OpenCLBuiltins.td
+59-22 files

FreeBSD/ports ff6db80devel/freebsd-git-devtools distinfo Makefile

devel/freebsd-git-devtools: Update to 2026-01-05 snapshot

Base commits since last update:
1c8dafe61887 - git-arc: Try to improve documentation
684c762485d3 - git-arc: Try to make patching more useful

Sponsored by:   The FreeBSD Foundation
DeltaFile
+7-7devel/freebsd-git-devtools/distinfo
+2-2devel/freebsd-git-devtools/Makefile
+9-92 files

FreeBSD/ports f9c4099dns/dnsmasq Makefile distinfo, dns/dnsmasq/files patch-src_util.c update.py

dns/dnsmasq: update to v2.92 + inotify patch

Changelog:      https://lists.thekelleys.org.uk/pipermail/dnsmasq-discuss/2026q1/018380.html

We keep the local patch to enable inotify on FreeBSD 15,
which was only merged after the release but had been in this port
already.

Make it so the pkg-message is printed on new installs and upgrades.
DeltaFile
+0-73dns/dnsmasq/files/patch-src_util.c
+52-0dns/dnsmasq/files/update.py
+5-5dns/dnsmasq/Makefile
+3-3dns/dnsmasq/distinfo
+1-1dns/dnsmasq/files/pkg-message.in
+0-0dns/dnsmasq/files/simon-kelley-keyring.asc
+61-826 files

LLVM/project eaa7516llvm/lib/Target/X86 X86ISelLowering.cpp X86InstrSSE.td, llvm/test/CodeGen/X86 clmul.ll clmul-x86.ll

[X86] Lower scalar llvm.clmul intrinsics to PCLMULQDQ (#175189) (#175216)

Add support for lowering scalar llvm.clmul intrinsics (i8/i16/i32/i64)
to the PCLMULQDQ hardware instruction on X86 targets with the PCLMUL
feature, instead of using the default software expansion.

The lowering:

- Extends smaller types to the target's native width (i64 on x86-64, i32
on i686)
- Uses SCALAR_TO_VECTOR to create vectors (v2i64 on x86-64, v4i32 with
bitcast to v2i64 on i686)
- Performs X86ISD::PCLMULQDQ with immediate 0x00
- Extracts the result and truncates back to the original type

i8/i16/i32 CLMUL is enabled on both 32-bit and 64-bit targets. i64
CLMUL/CLMULH is only enabled on 64-bit targets.

Also adds ISD::CLMULH i64 support by extracting the upper element from

    [2 lines not shown]
DeltaFile
+215-0llvm/test/CodeGen/X86/clmul.ll
+58-0llvm/lib/Target/X86/X86ISelLowering.cpp
+11-13llvm/lib/Target/X86/X86InstrSSE.td
+18-0llvm/test/CodeGen/X86/clmul-x86.ll
+4-4llvm/lib/Target/X86/X86InstrAVX512.td
+3-0llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+309-172 files not shown
+315-178 files

FreeNAS/freenas 1c5735csrc/middlewared/middlewared/plugins/account_ constants.py privilege.py, src/middlewared/middlewared/utils privilege_constants.py

NAS-139304 / 26.04 / Convert ALLOWED_BUILTIN_GIDS to frozenset (#18023)

Correcting issues with #17894
The LocalAdminGroups included non-admin groups. Split those groups into
a separate enum class.
Renamed the class to more clearly indicate they are 'builtin' groups.
Changed the ALLOWED_BUILTIN_GIDS set to a frozenset and populate it with
the values of the new enum classes.

This passes all CI tests related to 'privilege' and manual targeted
testing.
DeltaFile
+10-10src/middlewared/middlewared/plugins/account_/constants.py
+9-5src/middlewared/middlewared/utils/privilege_constants.py
+3-3src/middlewared/middlewared/plugins/account_/privilege.py
+22-183 files

FreeNAS/freenas b472932src/middlewared/middlewared/plugins dlm.py

In local_reset start any stopped lockspace on a BlockingIOError
DeltaFile
+9-1src/middlewared/middlewared/plugins/dlm.py
+9-11 files

FreeNAS/freenas ad7ac8bsrc/middlewared/middlewared/plugins/iscsi_ alua.py scst.py

Add additional lun health checks to standby_after_start

- Ensure that all expected IQNs and LUNs are present
- Ensure that SCST deems the LUN healthy to add to copy manager
DeltaFile
+43-1src/middlewared/middlewared/plugins/iscsi_/alua.py
+14-0src/middlewared/middlewared/plugins/iscsi_/scst.py
+57-12 files

FreeNAS/freenas 488ae19src/middlewared/middlewared/plugins/iscsi_ fs_attachment_delegate.py extents.py

Improve ALUA handling with locked or disabled extents

Previously iscsi.target.active_targets did not return any targets
where any LUNs were either disabled or locked.  This prevented the
STANDBY node from offering these targets when ALUA was enabled.

Once this was rectified then improvements wrt LUN status change
were required for both disable/enable and lock/unlock.

To optimize handling of LUNs locking added an optional
do_reload parameter to iscsi.alua.removed_target_extent
DeltaFile
+117-1src/middlewared/middlewared/plugins/iscsi_/fs_attachment_delegate.py
+78-3src/middlewared/middlewared/plugins/iscsi_/extents.py
+53-19src/middlewared/middlewared/plugins/iscsi_/targets.py
+10-14src/middlewared/middlewared/plugins/iscsi_/target_to_extent.py
+5-2src/middlewared/middlewared/plugins/iscsi_/alua.py
+263-395 files

FreeNAS/freenas 8ba60dcsrc/middlewared/middlewared/plugins/iscsi_ alua.py, src/middlewared/middlewared/plugins/service_/services iscsitarget.py

Ensure standby_fix_cluster_mode does not run too soon

Ensure that we have reached a certain point in standby_after_start
before allowing standby_fix_cluster_mode to run.
DeltaFile
+11-1src/middlewared/middlewared/plugins/iscsi_/alua.py
+3-0src/middlewared/middlewared/plugins/service_/services/iscsitarget.py
+14-12 files

FreeNAS/freenas 824a893src/middlewared/middlewared/plugins/iscsi_ iscsi_global.py

Eliminate redundant reload of iscsitarget on STANDBY node

This code pre-dated the introduction of standby_after_start, etc
DeltaFile
+0-6src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+0-61 files

FreeNAS/freenas cd632easrc/middlewared/middlewared/etc_files systemd.py

For HA systems do not use systemd to start scst

Instead it will be started by vrrp_master and if ALUA is enabled
vrrp_backup.  This allows finer control.
DeltaFile
+3-0src/middlewared/middlewared/etc_files/systemd.py
+3-01 files

FreeNAS/freenas 2a61254src/middlewared/middlewared/plugins/iscsi_ alua.py utils.py

Chunk the IO in set_all_cluster_mode
DeltaFile
+2-6src/middlewared/middlewared/plugins/iscsi_/alua.py
+7-0src/middlewared/middlewared/plugins/iscsi_/utils.py
+3-2src/middlewared/middlewared/plugins/iscsi_/scst.py
+12-83 files

FreeNAS/freenas 60eaac6src/middlewared/middlewared/plugins dlm.py, src/middlewared/middlewared/plugins/iscsi_ alua.py

Improve iscsi.alua.reset_active

Also call reset_active from standby_after_start
DeltaFile
+18-29src/middlewared/middlewared/plugins/iscsi_/alua.py
+7-0src/middlewared/middlewared/plugins/dlm.py
+25-292 files

LLVM/project fb0881fmlir/lib/Dialect/SCF/Transforms TileUsingInterface.cpp, mlir/lib/Dialect/Tensor/Transforms SwapExtractSliceWithProducerPatterns.cpp

[mlir][Tensor] Add rank-reducing slice in generatedSlices (#174248)

When `replaceExtractSliceWithTiledProducer `creates a rank-reducing
slice to handle type mismatches, it should be tracked in
`generatedSlices `so downstream cleanup patterns (like IREE's
FoldExtractSliceOfBroadcast) can process it.
 
This PR also fixes an infinite loop in getUntiledProducerFromSliceSource
where adding the slice to generatedSlices caused the fusion worklist to
repeatedly try to re-fuse producers already inside the innermost loop;
the fix skips producers that are already inside the innermost loop via
an isProperAncestor check.

Added a lit test (@fuse_through_rank_reducing_slice) demonstrating
correct fusion through rank-reducing slices. Note that demonstrating the
generatedSlices tracking benefit requires a cleanup pattern
(SwapExtractSliceWithFillPatterns) to consume the slice; IREE's full CI
suite (iree-org/iree#23012) validates this works correctly in practice
with patterns like FoldExtractSliceOfBroadcast.

    [3 lines not shown]
DeltaFile
+60-0mlir/test/Interfaces/TilingInterface/tile-and-fuse-using-interface.mlir
+12-1mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
+4-1mlir/test/Interfaces/TilingInterface/tile-and-fuse-with-reduction-tiling.mlir
+1-0mlir/lib/Dialect/Tensor/Transforms/SwapExtractSliceWithProducerPatterns.cpp
+77-24 files

LLVM/project a0b71b0lldb/source/Plugins/Language/CPlusPlus MsvcStlVariant.cpp, lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant TestDataFormatterStdVariant.py main.cpp

Revert "[LLDB] Fix MS STL `variant` with non-trivial types" (#176059)

Reverts llvm/llvm-project#171489 because it causes
`TestDataFormatterStdVariant.py` to fail on Darwin.

Affected bots:

- https://ci.swift.org/view/all/job/llvm.org/view/LLDB/job/as-lldb-cmake/
- https://ci.swift.org/view/all/job/llvm.org/view/LLDB/job/lldb-cmake/
DeltaFile
+0-21lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/TestDataFormatterStdVariant.py
+5-11lldb/source/Plugins/Language/CPlusPlus/MsvcStlVariant.cpp
+0-5lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/main.cpp
+5-373 files

LLVM/project 21b3642lldb/source/Plugins/SymbolFile/NativePDB PdbAstBuilderClang.cpp PdbAstBuilder.cpp, lldb/source/Plugins/TypeSystem/Clang TypeSystemClang.h

[LLDB][NativePDB] Introduce PdbAstBuilderClang (#175840)

This changes `PdbAstBuilder` to a language-neutral abstract interface
and moves all of its functionality to the `PdbAstBuilderClang` derived
class.

All Clang-specific methods with external callers are now public methods
on `PdbAstBuilderClang`. `TypeSystemClang` and `UdtRecordCompleter` use
`PdbAstBuilderClang` directly.

Did my best to clean up includes and unused methods.

RFC for context:

https://discourse.llvm.org/t/rfc-lldb-make-pdbastbuilder-language-agnostic/89117
DeltaFile
+1,547-0lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.cpp
+0-1,544lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
+182-0lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.h
+23-148lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.h
+7-1lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
+3-4lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.h
+1,762-1,6975 files not shown
+1,770-1,70711 files

FreeNAS/freenas ed2436btests/api2 test_300_nfs.py

Skip the NFS bindip test if no static IP is available.
DeltaFile
+10-0tests/api2/test_300_nfs.py
+10-01 files

LLVM/project 0f85aa1lldb/source/Plugins/Language/CPlusPlus MsvcStlVariant.cpp, lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant TestDataFormatterStdVariant.py main.cpp

Revert "[LLDB] Fix MS STL `variant` with non-trivial types (#171489)"

This reverts commit 9a632fd684e1729b93f9f5272ad6b5798f38ba77.
DeltaFile
+0-21lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/TestDataFormatterStdVariant.py
+5-11lldb/source/Plugins/Language/CPlusPlus/MsvcStlVariant.cpp
+0-5lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/main.cpp
+5-373 files

LLVM/project 1463fballvm/test/CodeGen/AMDGPU local-stack-alloc-add-references.gfx8.mir coalesce-copy-to-agpr-to-av-registers.mir, llvm/test/MC/Disassembler/AMDGPU gfx12_dasm_vop1_dpp8.txt

[AMDGPU] Allow allocation of lo128 registers from all banks

We can encode 16-bit operands in a short form for VGPRs [0..127].
When we have 1K registers available we can in fact allocate 4
times more from all 4 banks. That, however, requires an allocatable
class for these operands. When for most of the instructions it will
result in the VOP3 longer form, for V_FMAAMK/FMADAK_F16 it will
simply prohibit the encoding because these do not have VOP3 forms.

A straight forward solution would be to create a register class
with all registers having bit 8 of the encoding zero, i.e. to
create a register class with holes punched in it: [0-127, 256-383,
512-639, 768-895]. LLVM, however, does not like register classes
with punched holes when they also have subregisters. The cross-
product of all classes explodes and some combinations of a 'class
having a common subreg with another' becomeing impossible. Just
doing so explodes our register info to 4+Gb, uncompilable too.

The solution proposed is to define _lo128 RC with contigous 896

    [17 lines not shown]
DeltaFile
+180-180llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+118-118llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+90-90llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+177-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250-t16.mir
+49-46llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
+94-0llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250-t16.mir
+708-43440 files not shown
+1,340-73446 files

FreeNAS/freenas 42340cedebian/debian ix-reboot.service

NAS-139317 / 25.10.2 / Call ha_panic for ix-reboot.service as we do for ix-shutdown (by bmeagherix) (#18029)

Recently in PR #17833 the `ha_panic` script was added and called on
`ExecStop` in `ix-shutdown.service`.

This PR makes a similar change to `ix-reboot.service` for the same
rationale.

Original PR: https://github.com/truenas/middleware/pull/18028

Co-authored-by: Brian M <brian.meagher at ixsystems.com>
DeltaFile
+1-0debian/debian/ix-reboot.service
+1-01 files

FreeNAS/freenas 19e197adebian/debian ix-reboot.service

NAS-139317 / 26.04 / Call ha_panic for ix-reboot.service as we do for ix-shutdown (#18028)

DeltaFile
+1-0debian/debian/ix-reboot.service
+1-01 files