LLVM/project d15ff59libcxx/include/__algorithm copy_backward.h for_each_segment.h

[libc++] Merge the segmented iterator code for {copy,move}_backward (#165160)

This removes a bit of code duplication and might simplify future
segmented iterator optimitations.
DeltaFile
+5-21libcxx/include/__algorithm/copy_backward.h
+26-0libcxx/include/__algorithm/for_each_segment.h
+5-21libcxx/include/__algorithm/move_backward.h
+36-423 files

LLVM/project 57cf1fflibcxx/include __tree map

[libc++] Remove initializer_list specific optimization in __tree (#169413)

We've seen in quite a few cases while optimizing `__tree`'s copy
construction that `_DetachedTreeCache` is actually quite slow and not
necessarily an optimization at all. This patch removes the code, since
it's now only used by `operator=(initializer_list)`, which should be
quite cold code. We might look into actually optimizing it again in the
future, but I doubt an optimization will be small enough compared to the
likely speedup in real-world code this would give.
DeltaFile
+0-158libcxx/include/__tree
+4-2libcxx/include/map
+4-2libcxx/include/set
+8-1623 files

LLVM/project df6c27elibcxx/docs/ReleaseNotes 22.rst, libcxx/include/__memory allocator.h

[libc++] Make std::allocator always trivially default constructible (#169914)

This is technically ABI breaking, since `is_trivial` and
`is_trivially_default_constructible` now return different results.
However, I don't think that's a significant issue, since `allocator` is
almost always used in classes which own memory, making them non-trivial
anyways.
DeltaFile
+10-23libcxx/include/__memory/allocator.h
+27-0libcxx/test/libcxx/memory/allocator_triviality.deprecated_abi.compile.pass.cpp
+0-26libcxx/test/libcxx/memory/allocator_void.trivial.compile.pass.cpp
+24-0libcxx/test/libcxx/memory/allocator_triviality.compile.pass.cpp
+4-0libcxx/docs/ReleaseNotes/22.rst
+0-3libcxx/test/std/utilities/optional/optional.specalg/make_optional_explicit.pass.cpp
+65-521 files not shown
+65-557 files

FreeBSD/src a717a40sys/netpfil/pf pf.c, tests/sys/netpfil/pf sctp.py

pf: relax sctp v_tag verification

pf was too strict when validating SCTP tags. When a server receives a
retransmitted INIT it will reply with a random initiate tag every time.
However, pf saves the first initiate tag and expects every subsequent INIT_ACK
retransmission to have the same tag. This is not the case, leading to endless
INIT/INIT_ACK cycles.

Allow the tag to be updated as long as we've not gone past COOKIE_WAIT.

Add a test case to verify this.

MFC after:      2 weeks
See also:       https://redmine.pfsense.org/issues/16516
Sponsored by:   Rubicon Communications, LLC ("Netgate")

(cherry picked from commit bc3b72ff48953551e0e8bd6e5a2c718ecd973285)
DeltaFile
+67-0tests/sys/netpfil/pf/sctp.py
+6-2sys/netpfil/pf/pf.c
+73-22 files

FreeBSD/src f629ee0lib/libpfctl libpfctl.c

libpfctl: improve error handling

If we fail to open /dev/pf don't try to close it again. That would result in
errno getting overwritten by close(), hiding potentially useful information.

MFC after:      2 weeks
Sponsored by:   Rubicon Communications, LLC ("Netgate")

(cherry picked from commit 238ad591da9eede122a708be925b6b6a20e9046b)
DeltaFile
+2-2lib/libpfctl/libpfctl.c
+2-21 files

FreeBSD/src cc638b2sys/netpfil/pf pf.c, tests/sys/netpfil/pf sctp.py

pf: relax sctp v_tag verification

pf was too strict when validating SCTP tags. When a server receives a
retransmitted INIT it will reply with a random initiate tag every time.
However, pf saves the first initiate tag and expects every subsequent INIT_ACK
retransmission to have the same tag. This is not the case, leading to endless
INIT/INIT_ACK cycles.

Allow the tag to be updated as long as we've not gone past COOKIE_WAIT.

Add a test case to verify this.

MFC after:      2 weeks
See also:       https://redmine.pfsense.org/issues/16516
Sponsored by:   Rubicon Communications, LLC ("Netgate")

(cherry picked from commit bc3b72ff48953551e0e8bd6e5a2c718ecd973285)
DeltaFile
+67-0tests/sys/netpfil/pf/sctp.py
+5-1sys/netpfil/pf/pf.c
+72-12 files

FreeBSD/src 7b4482fsys/netpfil/pf pf.c, tests/sys/netpfil/pf sctp.py

pf: relax sctp v_tag verification

pf was too strict when validating SCTP tags. When a server receives a
retransmitted INIT it will reply with a random initiate tag every time.
However, pf saves the first initiate tag and expects every subsequent INIT_ACK
retransmission to have the same tag. This is not the case, leading to endless
INIT/INIT_ACK cycles.

Allow the tag to be updated as long as we've not gone past COOKIE_WAIT.

Add a test case to verify this.

MFC after:      2 weeks
See also:       https://redmine.pfsense.org/issues/16516
Sponsored by:   Rubicon Communications, LLC ("Netgate")

(cherry picked from commit bc3b72ff48953551e0e8bd6e5a2c718ecd973285)
DeltaFile
+67-0tests/sys/netpfil/pf/sctp.py
+6-2sys/netpfil/pf/pf.c
+73-22 files

LLVM/project 45126abllvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp

[AArch64][GlobalISel] Refactored Legaliser Changes

Early returns implemented where possible, in order to reduce
indentation.
DeltaFile
+68-69llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+68-691 files

LLVM/project 4d335cbllvm/test/tools/llvm-mca/AArch64/Neoverse V3AE-rcpc-immo-instructions.s N2-rcpc-immo-instructions.s

[AArch64] Fix scheduling info for Armv8.4-a LDAPUR* instructions (#171637)

They were using the wrong scheduler resource. They're also missing from
the optimisation guides, but WriteLD should be closer at least.
DeltaFile
+19-19llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s
+19-19llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s
+19-19llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s
+19-19llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s
+19-19llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s
+19-19llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s
+114-1141 files not shown
+115-1157 files

LLVM/project c9c432fmlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

review comments, Tom
DeltaFile
+1-4mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+1-41 files

LLVM/project 5fbb19emlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp, mlir/test/Target/LLVMIR openmp-private-allloca-hoisting.mlir

[OpenMP][MLIR] Hoist static `alloca`s emitted by private `init` regions to the allocation IP of the construct

Having more than 1 descritpr (allocatable or array) on the same `private` clause triggers a runtime crash on GPUs at the moment.

For SPMD kernels, the issue happens because the initialization logic includes:
* Allocating a number of temporary structs (these are emitted by flang when `fir` is lowered to `mlir.llvm`).
* There is a conditional branch that determines whether we will allocate storage for the descriptor and initialize array bounds from the original descriptor or whether we will initialize the private descriptor to null.

Because of these 2 things, temp allocations needed for descriptors beyond the 1st one are preceded by branching which causes the observed the runtime crash.

This PR solves this issue by hoisting these static `alloca`s instructions to the suitable allca IP of the parent construct.
DeltaFile
+79-0mlir/test/Target/LLVMIR/openmp-private-allloca-hoisting.mlir
+67-8mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+146-82 files

OPNSense/core c6ffd18src/www firewall_rules_edit.php

firewall: fix typo in previous

(cherry picked from commit 559701cbc0df0c39abaf85102eca098164fe575d)
DeltaFile
+1-1src/www/firewall_rules_edit.php
+1-11 files

OPNSense/core 559701csrc/www firewall_rules_edit.php

firewall: fix typo in previous
DeltaFile
+1-1src/www/firewall_rules_edit.php
+1-11 files

LLVM/project 6573f62llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 atomic-fp.ll

[X86] LowerATOMIC_STORE - on 32-bit targets see if i64 values were originally legal f64 values that we can store directly. (#171602)

Based off feedback from #171478
DeltaFile
+207-467llvm/test/CodeGen/X86/atomic-fp.ll
+8-1llvm/lib/Target/X86/X86ISelLowering.cpp
+215-4682 files

FreeBSD/src a35545esys/vm vm_glue.c

vm: Fix kstack alignment assertion

The expectation that the allocation will be aligned to the kstack size
only applies when allocating from a kstack arena, not when allocating a
non-standard size from the kernel arena.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Sponsored by:   NetApp, Inc.
Fixes:          7a79d0669761 ("vm: improve kstack_object pindex calculation to avoid pindex holes")
Reviewed by:    bnovkov, siderop1_netapp.com
Differential Revision:  https://reviews.freebsd.org/D54171
DeltaFile
+6-4sys/vm/vm_glue.c
+6-41 files

OPNSense/core 6423241src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms dialogDNatRule.xml

nat/dnat: Source and destination cannot be multi select (#9513)

DeltaFile
+2-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogDNatRule.xml
+2-21 files

FreeBSD/ports 3166f9bjava/javamail Makefile distinfo, java/javamail/files patch-build.properties

java/javamail: remove java from run dependencies

As javamail is a library and not an application itself it should not
have a run-dependency on Java. It doesn't run on its own.
It will always use the java version of the application that uses javamail.

Use source and target arguments compatible with jdk21.

If not using openjdk8 bring back the Java Activation Framework. In
openjdk8 these classes were included in the core packages. In later
JDK versions it was removed again.

PR:     291388
DeltaFile
+15-3java/javamail/Makefile
+2-2java/javamail/files/patch-build.properties
+3-1java/javamail/distinfo
+20-63 files

OPNSense/core d3ada54src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms dialogDNatRule.xml

nat/dnat: Source and destination cannot be multi select
DeltaFile
+2-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogDNatRule.xml
+2-21 files

LLVM/project 59b13d6libcxx/include/__algorithm find_end.h

[libc++] Add `__find_end` optimizations back (#171374)

This essentially reverts #100685 and fixes the bidirectional and random
access specializations to be actually used.

```
Benchmark                                                                old             new    Difference    % Difference
------------------------------------------------------------  --------------  --------------  ------------  --------------
rng::find_end(deque<int>)_(match_near_end)/1000                       366.91           47.63       -319.28         -87.02%
rng::find_end(deque<int>)_(match_near_end)/1024                      3273.31           35.42      -3237.89         -98.92%
rng::find_end(deque<int>)_(match_near_end)/8192                    171608.41          285.04    -171323.38         -99.83%
rng::find_end(deque<int>)_(near_matches)/1000                       31808.40        19214.35     -12594.05         -39.59%
rng::find_end(deque<int>)_(near_matches)/1024                       37428.72        20773.87     -16654.85         -44.50%
rng::find_end(deque<int>)_(near_matches)/8192                     1719468.34      1213967.45    -505500.89         -29.40%
rng::find_end(deque<int>)_(process_all)/1000                          275.81          336.29         60.49          21.93%
rng::find_end(deque<int>)_(process_all)/1024                          258.88          320.36         61.47          23.74%
rng::find_end(deque<int>)_(process_all)/1048576                    277117.41       327640.37      50522.96          18.23%
rng::find_end(deque<int>)_(process_all)/8192                         2166.36         2533.52        367.16          16.95%
rng::find_end(deque<int>)_(same_length)/1000                         1280.06          362.53       -917.53         -71.68%

    [246 lines not shown]
DeltaFile
+105-0libcxx/include/__algorithm/find_end.h
+105-01 files

OPNSense/ports ca2d0e0opnsense/hostwatch Makefile distinfo, opnsense/hostwatch/files hostwatch.in

opnsense/hostwatch: update to 1.0.3 and style
DeltaFile
+3-6opnsense/hostwatch/Makefile
+3-3opnsense/hostwatch/distinfo
+0-0opnsense/hostwatch/files/hostwatch.in
+6-93 files

LLVM/project 4a92060llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

Fix build
DeltaFile
+24-12llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+24-121 files

LLVM/project b67f8f0llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU lds-dma-waits.ll

(reland) [AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)

Fixed a crash in Blender due to some weird control flow.
The issue was with the "merge" function which was only looking at the
keys of the "Other" VMem/SGPR maps. It needs to look at the keys of both
maps and merge them.

Original commit message below
----

The pass was already "reinventing" the concept just to deal with 16 bit
registers. Clean up the entire tracking logic to only use register
units.

There are no test changes because functionality didn't change, except:
- We can now track more LDS DMA IDs if we need it (up to `1 << 16`)
- The debug prints also changed a bit because we now talk in terms of
register units.


    [9 lines not shown]
DeltaFile
+311-282llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+4-4llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
+315-2862 files

LLVM/project db06ebbllvm/lib/Target/AArch64 AArch64PerfectShuffle.h AArch64ISelLowering.cpp

[AArch64][NFC] Add isTRNMask improvements to isZIPMask (#171532)

Some [ideas for
improvement](https://github.com/llvm/llvm-project/pull/169858#pullrequestreview-3525357470)
came up during review of recent changes to `isTRNMask`.
This PR applies them also to `isZIPMask`, which is implemented almost
identically.
DeltaFile
+18-17llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
+12-12llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+30-292 files

LLVM/project 2c1decblibcxx/include __split_buffer deque, libcxx/include/__vector vector.h

[libc++] Don't instantiate __split_buffer with an allocator reference (#171651)

Allocators should be extremely cheap, if not free, to copy. Furthermore,
we have requirements on allocator types that copies must compare equal,
and that move and copy must be the same.

Hence, taking an allocator by reference should not provide benefits
beyond making a copy of it. However, taking the allocator by reference
leads to complexity in __split_buffer, which can be removed if we stop
using that pattern.
DeltaFile
+20-25libcxx/include/__split_buffer
+17-17libcxx/include/__vector/vector.h
+8-8libcxx/include/deque
+45-503 files

NetBSD/src Ysy9WNKsys/dev/fdt arasan_sdhc_fdt.c

   fix RK3399 emmc and set SDHC_FLAG_NO_PWR0.

   tested on rockpro64 and pinebookpro.
VersionDeltaFile
1.14+3-2sys/dev/fdt/arasan_sdhc_fdt.c
+3-21 files

FreeNAS/freenas 6940d13src/middlewared/middlewared/plugins/truenas_connect hostname.py

Do not spam middleware logs

This commit fixes an issue where if networking is not working and we fail to sync interface ips for tnc, it can result in middleware logs getting spammed non-stop if there are continuous network events being generated.

(cherry picked from commit 7ffe8a41aa21385af84ca0d2bdd1fc5402e5b701)
DeltaFile
+4-1src/middlewared/middlewared/plugins/truenas_connect/hostname.py
+4-11 files

FreeNAS/freenas aa04f8bsrc/middlewared/middlewared/plugins/truenas_connect hostname.py

NAS-138887 / 26.04 / Do not spam middleware logs (#17803)

This commit fixes an issue where if networking is not working and we
fail to sync interface ips for tnc, it can result in middleware logs
getting spammed non-stop if there are continuous network events being
generated.
DeltaFile
+4-1src/middlewared/middlewared/plugins/truenas_connect/hostname.py
+4-11 files

DragonFlyBSD/src 2a7c11esys/dev/misc/syscons sckmsrndr.c

syscons - Fixup typo in fill_rect16() from 7550650651ca31fcb7d2edd0d60

Noticed-By: Aaron LI
DeltaFile
+1-1sys/dev/misc/syscons/sckmsrndr.c
+1-11 files

OpenBSD/ports IUXnKnLx11/gnome/localsearch distinfo Makefile

   Update to localsearch-3.10.2.
VersionDeltaFile
1.7+2-2x11/gnome/localsearch/distinfo
1.12+1-1x11/gnome/localsearch/Makefile
+3-32 files

LLVM/project 15df9e7llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU insert_vector_dynelt.ll extract_vector_dynelt.ll

[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323)

Before this patch, `insertelement/extractelement` with dynamic indices
would
fail to select with `-O0` for vector 32-bit element types with sizes 3,
5, 6 and 7,
which did not map to a `SI_INDIRECT_SRC/DST` pattern.

Other "weird" sizes bigger than 8 (like 13) are properly handled
already.

To solve this issue we add the missing patterns for the problematic
sizes.

Solves SWDEV-568862
DeltaFile
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+3,310-0llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+16-0llvm/lib/Target/AMDGPU/SIInstructions.td
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+9,297-04 files