[Support] Optimize DebugCounter (#170305)
Currently, DebugCounters work by creating a unique counter ID during
registration, and then using that ID to look up the counter information
in the global registry.
However, this means that anything working with counters has to always go
through the global instance. This includes the fast path that checks
whether any counters are enabled.
Instead, we can drop the counter IDs, and make the counter variables use
CounterInfo themselves. We can then directly check whether the specific
counter is active without going through the global registry. This is
both faster for the fast-path where all counters are disabled, and also
faster for the case where only one counter is active (as the fast-path
can now still be used for all the disabled counters).
After this change, disabled counters become essentially free at runtime,
and we should be able to enable them in non-assert builds as well.
ARM GICv3: Add support for non-coherent and/or bus address range limited DMA.
Due to an implementation bug, the GICv3 and ITS master ports may be connected
to a non-coherent bus. The new DT resolves this issue by marking these ports
with the "dma-nocoherent" attribute. The older DT does not have this attribute,
so we must match the affected SoC.
Additionally, the RK356x family has GIC master ports on a 32-bit bus.
Therefore, we must limit the address range for all tables and command buffers
allocated for it. In this case, the DT does not have an attribute for this
case, so the quirk should only be applied by SoC matching.
MFC after: 4 weeks
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D47488
ofw: Add ofw_bus_is_machine_compat().
We need a quick way to identify a given machine (SoC), mainly when
implementing quirks for a given SoC.
MFC after: 2 weeks
Reviwed by: imp
Differential Revision: https://reviews.freebsd.org/D53992
ofw: Add ofw_bus_is_machine_compat().
We need a quick way to identify a given machine (SoC), mainly when
implementing quirks for a given SoC.
MFC after: 2 weeks
Reviwed by: imp
Differential Revision: https://reviews.freebsd.org/D53992
ARM GICv3: Add support for non-coherent and/or bus address range limited DMA.
Due to an implementation bug, the GICv3 and ITS master ports may be connected
to a non-coherent bus. The new DT resolves this issue by marking these ports
with the "dma-nocoherent" attribute. The older DT does not have this attribute,
so we must match the affected SoC.
Additionally, the RK356x family has GIC master ports on a 32-bit bus.
Therefore, we must limit the address range for all tables and command buffers
allocated for it. In this case, the DT does not have an attribute for this
case, so the quirk should only be applied by SoC matching.
MFC after: 4 weeks
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D47488
