LLVM/project debb251llvm/include/llvm/MC MCAssembler.h, llvm/lib/MC MCAssembler.cpp

[MC] Fuse relaxation and layout into a single forward pass (#184544)

Replace the two-pass inner loop in relaxOnce (relaxFragment +
layoutSection) with a single forward pass that sets each fragment's
offset before processing it.

- Extract relaxAlign from layoutSection's FT_Align handling and call
  it from relaxFragment. FT_Align padding is computed inline with the
  tracked Offset, so alignment fragments always see fresh upstream
  offsets. This structurally eliminates the O(N) convergence pitfall
  where stale offsets caused each iteration to fix only one more
  alignment fragment.

- The new MCAssembler::Stretch field tracks the cumulative upstream size
  delta. In evaluateFixup, for PCRel fixups during relaxation, Stretch
  is added to forward-reference target values (LayoutOrder comparison).
  This makes displacement = target_old - source_old, identical to the
  old two-pass approach, preventing premature relaxation for
  span-dependent instructions.

    [17 lines not shown]
DeltaFile
+60-42llvm/lib/MC/MCAssembler.cpp
+37-0llvm/test/MC/X86/align-branch-convergence.s
+6-8llvm/test/MC/ELF/relax-branch-align.s
+6-1llvm/include/llvm/MC/MCAssembler.h
+109-514 files

LLVM/project cd01e65lld/ELF Relocations.cpp Relocations.h, lld/ELF/Arch LoongArch.cpp

[ELF] Add target-specific relocation scanning for LoongArch (#182236)

Implement LoongArch::scanSectionImpl, following the pattern established
for x86, PPC64, SystemZ, AArch64. This merges the getRelExpr and TLS
handling for SHF_ALLOC sections into the target-specific scanner,
enabling devirtualization and eliminating abstraction overhead.

- Inline relocation classification into scanSectionImpl with a switch
  on relocation type, replacing the generic rs.scan() path.
- Use processR_PC/processR_PLT_PC for common PC-relative and PLT
  relocations.
- Inline TLS handling: IE->LE optimization for _PC_ variants only (not
  _PCADD_ or absolute), TLSDESC->IE/LE for non-extreme code model,
  GD/LD flag setting without going through generic handleTlsRelocation.
- Remove adjustTlsExpr by inlining its logic into scanSectionImpl.
- Remove LoongArch-specific code from Relocations.cpp:
  handleTlsRelocation, execOptimizeInLoongArch, and the sort condition.
- Simplify getRelExpr to only handle relocations needed by
  relocateNonAlloc, scanEhSection, and the extreme code model fallback
  in relocateAlloc.
DeltaFile
+331-224lld/ELF/Arch/LoongArch.cpp
+6-43lld/ELF/Relocations.cpp
+0-2lld/ELF/Relocations.h
+0-2lld/ELF/InputSection.cpp
+337-2714 files

LLVM/project 027447cllvm/test/MC/ELF relax-branch-align.s

[MC][test] Add relax-branch-align.s demonstrating unnecessary branch relaxation (#184551)

The two-pass relaxation approach (relaxFragment, then layoutSection)
can unnecessarily relax a backward branch from short (2B) to near (5B).

When a forward branch relaxes (2B->6B), it shifts the backward target
by +4B. A .p2align between target and source absorbs this growth. The
true displacement is -125 (fits short), but the two-pass approach
evaluates the backward branch with stale target offsets, seeing -129
(beyond [-128,127]) and relaxing it unnecessarily.
DeltaFile
+49-0llvm/test/MC/ELF/relax-branch-align.s
+49-01 files

LLVM/project b3d2953llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Rewrite formula in the Weak Zero SIV tests
DeltaFile
+67-72llvm/lib/Analysis/DependenceAnalysis.cpp
+8-8llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll
+4-8llvm/include/llvm/Analysis/DependenceAnalysis.h
+2-6llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-overflow.ll
+2-2llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll
+83-965 files

LLVM/project 906843cllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak_zero_siv_parametric_coeff.ll WeakZeroDstSIV.ll

[DA] Fix the WeakZeroSIV tests when the coeff may be non-zero
DeltaFile
+4-10llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_coeff.ll
+4-2llvm/lib/Analysis/DependenceAnalysis.cpp
+1-1llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
+1-1llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
+10-144 files

LLVM/project 3e9db74llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Remove isPeelFirst and isPeelLast
DeltaFile
+1-24llvm/include/llvm/Analysis/DependenceAnalysis.h
+0-20llvm/lib/Analysis/DependenceAnalysis.cpp
+3-3llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
+3-3llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
+7-504 files

LLVM/project dd8d5ffllvm/test/CodeGen/RISCV/rvv nontemporal-vp-scalable.ll vl-opt.mir

[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)

The last feature that RISCVVectorPeephole::tryToReduceVL has that
RISCVVLOptimizer doesn't is that if the vl to reduce to doesn't dominate
a vector pseudo, it can sink the pseudo below the vl definition if it's
safe to do so.

This PR shares the logic to check for physical register clobbering in
RISCVInstrInfo, but there may be a better place for it.

The DemandedVLs DenseMap needs to be switched to a MapVector to get
deterministic ordering, since the order in which we sink instructions
can affect the resulting codegen.

This helps removes a few vsetvli toggles in llvm-test-suite.
DeltaFile
+730-700llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
+176-1llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+66-90llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+61-81llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
+46-39llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
+41-39llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+1,120-95030 files not shown
+1,435-1,23136 files

LLVM/project 348f4fbllvm/test/Analysis/DependenceAnalysis weak_zero_siv_parametric_coeff.ll weak_zero_siv_parametric_const.ll

[DA] Add tests that represent edge cases for the Weak Zero SIV tests (NFC) (#183735)

This patch adds test cases that capture edge cases for the Weak‑Zero SIV
tests. These cases involve loop‑invariant, non‑constant variables, and
special care is required when those variables may be zero.
DeltaFile
+106-0llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_coeff.ll
+101-0llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_const.ll
+207-02 files

LLVM/project f5f0930llvm/lib/Transforms/Utils VNCoercion.cpp, llvm/test/Transforms/GVN svcount-access.ll

[GVN] Fix crash when svcount is used with globals-aa (#184347)

When -globals-aa is used, `analyzeLoadAvailiability` calls
`analyzeLoadClobberringStore` which in turn calls
`isFirstClassAggregateOrScalableType` which is using
`isa<ScalableVectorType>`. Ideally it should use type's isScalableType()
method.

The crash does not occur when default (BasicAA) is used because
`analyzeLoadAvailiability` function does not take the load clobbering
path as BasicAA returns `Def`.

Fixes #159368
DeltaFile
+16-0llvm/test/Transforms/GVN/svcount-access.ll
+1-1llvm/lib/Transforms/Utils/VNCoercion.cpp
+17-12 files

LLVM/project 5f29cdcllvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVInstrInfoP.td, llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.h

[RISCV] Remove OperandType OPERAND_SIMM10_UNSIGNED. Rename OPERAND_SIMM8_UNSIGNED->OPERAND_SIMM8 (#184540)

The UNSIGNED only refers to what we allow in assembly parsing. The
MachineInstr/MCInst should always be canonicalized to signed.
DeltaFile
+1-3llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1-1llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+4-63 files

LLVM/project 288060dllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'main' into users/kasuga-fj/da-add-test-for-weak-zero-siv
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+13,685-22,906llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+19,112-16,445llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+188,395-181,3632,312 files not shown
+362,144-296,9262,318 files

LLVM/project 4b85c13clang-tools-extra/clang-tidy/readability RedundantPreprocessorCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix false positive in readability-redundant-preprocessor for builtin checks (#181734)

Different `__has_builtin()` checks were incorrectly flagged as redundant
because ConditionRange collapsed after macro expansion. It now reads
condition text directly from source to fix this.

Assisted-by: Claude
Fixes #64825
DeltaFile
+153-0clang-tools-extra/test/clang-tidy/checkers/readability/redundant-preprocessor.cpp
+37-2clang-tools-extra/clang-tidy/readability/RedundantPreprocessorCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+195-23 files

LLVM/project a6bbe46clang/lib/FrontendTool ExecuteCompilerInvocation.cpp

[clang][CIR] Pass VFS to command-line parsing (#184226)

This explicitly passes Clang's VFS to MLIR command-line parsing that
runs when ClangIR is enabled. This matches the rest of Clang and fixes a
sandbox violation.
DeltaFile
+3-1clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
+3-11 files

LLVM/project 32c141allvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'fix-blockfreq-unroll-unconditional-latches--fast' into fix-blockfreq-unroll-unconditional-latches--uniform
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,112-16,445llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+11,541-22,066llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+186,251-180,5232,952 files not shown
+427,667-315,0292,958 files

LLVM/project e808a7fllvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp

[RISCV][GISel] Replace buildInstr with BuildMI (#183714)

As @arsenm mentioned in some of my PRs, such as:
https://github.com/llvm/llvm-project/pull/171092, we should use
`BuildMI` instead of `MachineInstrBuilder::buildInstr` in Selector.
This PR is tring to replace all `MachineInstrBuilder::buildInstr` with
`BuildMI`.
DeltaFile
+213-142llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+213-1421 files

LLVM/project e6b9d81clang/lib/Headers hvx_hexagon_protos.h .clang-format-ignore

[Hexagon] Ignore formatting of generated proto files (#184427)

hexagon_protos.h, hexagon_circ_brev_intrinsics.h, and
hvx_hexagon_protos.h are generated C header files that consist of
macro definitions and help fields in comments. These files are large.
Automatic formatting of these files breaks their regular structure
and increases maintenance effort.
DeltaFile
+102-80clang/lib/Headers/hvx_hexagon_protos.h
+4-0clang/lib/Headers/.clang-format-ignore
+106-802 files

LLVM/project dcbc5delldb/include/lldb/Host LZMA.h

[lldb][NFC] Add missing include to LZMA.h (#184536)

This header assumed you already included this otherwise it has errors
DeltaFile
+1-0lldb/include/lldb/Host/LZMA.h
+1-01 files

LLVM/project 6e1ab3aclang/lib/Sema SemaType.cpp, clang/test/Modules var-inst-def.cppm pr149404-02.cppm

[Serialization] Stop demote var definition as declaration (#172430) (#177117) (#184287)

Close https://github.com/llvm/llvm-project/issues/172241 Close
https://github.com/llvm/llvm-project/issues/64034 Close
https://github.com/llvm/llvm-project/issues/149404 Close
https://github.com/llvm/llvm-project/issues/174858

After this patch, we (the clang dev) no longer assumes there are at most
one definition in a redeclaration chain.

See


https://discourse.llvm.org/t/rfc-clang-not-assuming-there-is-at-most-one-definition-in-a-redeclaration-chain/89360
for details.

---

Update since last commit:

    [13 lines not shown]
DeltaFile
+110-0clang/test/Modules/var-inst-def.cppm
+104-0clang/test/Modules/pr149404-02.cppm
+94-0clang/test/Modules/demote-var-def.cpp
+60-24clang/lib/Sema/SemaType.cpp
+83-0clang/test/Modules/module-init-forcelly-loaded-module.cpp
+47-0clang/test/Modules/pr172241.cppm
+498-241 files not shown
+508-267 files

LLVM/project 7fb92cdthird-party/benchmark/include/benchmark benchmark.h

[Benchmark] Fix warnings around usage of __COUNTER__ (#184524)

Premerge CI is currently failing with the following after the update to
clang v22:

```
/home/gha/llvm-project/clang-tools-extra/clangd/benchmarks/IndexBenchmark.cpp:92:1: error: '__COUNTER__' is a C2y extension [-Werror,-Wc2y-extensions]
   92 | BENCHMARK(dexQueries);
      | ^
```

Some original work was done around this in
df1d786c460e0e47c9074f3533f098190ebfbc1b, which was then done in
upstream Google benchmark in

https://github.com/google/benchmark/commit/d8db2f90b643eb28a12976beb4d57bcfb639911d.
The original work done in the patch implementing this feature doesn't
seem to account for as many cases as the upstream patch does. This patch
reverts the diff in df1d786c460e0e47c9074f3533f098190ebfbc1b and applies
the applicable hunks from the upstream patch.
DeltaFile
+17-11third-party/benchmark/include/benchmark/benchmark.h
+17-111 files

LLVM/project 98c4626llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/PowerPC clmul-vector.ll

[TargetLowering][PowerPC] Don't unroll vector CLMUL when MUL is not supported. (#184238)

We can use the bittest lowering instead.
DeltaFile
+2,338-2,209llvm/test/CodeGen/PowerPC/clmul-vector.ll
+0-4llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+2,338-2,2132 files

LLVM/project 1c43492utils/bazel .bazelrc

[bazel] Remove old zlib config variable (#184527)

Use was removed in a268127736e4d703cef8c9f4841f9a8e8ac21ba7
DeltaFile
+0-8utils/bazel/.bazelrc
+0-81 files

LLVM/project 3a85d99utils/bazel/llvm-project-overlay/third-party BUILD.bazel, utils/bazel/third_party_build zlib-ng.BUILD

[bazel] Fix building lldb with zlib disabled (#184525)

In cmake this value is set in llvm-config.h, we're not really handling
that the same way in bazel so we can just allow all targets to inherit
this disabled, otherwise it fails since lldb assumes it is always
something
DeltaFile
+3-1utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
+3-1utils/bazel/third_party_build/zlib-ng.BUILD
+6-22 files

LLVM/project 928505clld/test/wasm archive.ll archive.s, lld/test/wasm/Inputs archive2.ll archive2.s

[lld][WebAssembly] Convert more tests to assembly. NFC (#184418)

The only expectations change here is that `__stack_pointer` is
no longer exports in the `archive-export.test` test. This is because
we don't enable the mutable-globals feature (since the assembly files
don't contains all the now-default features of the generic CPU).
DeltaFile
+0-54lld/test/wasm/archive.ll
+53-0lld/test/wasm/archive.s
+0-14lld/test/wasm/Inputs/archive2.ll
+12-0lld/test/wasm/Inputs/archive2.s
+0-11lld/test/wasm/Inputs/archive3.ll
+4-7lld/test/wasm/archive-export.test
+69-863 files not shown
+86-959 files

LLVM/project 3b4d5ffmlir/lib/Dialect/XeGPU/IR XeGPUOps.cpp, mlir/lib/Dialect/XeGPU/Transforms XeGPUUnroll.cpp XeGPUBlocking.cpp

[MLIR][XeGPU] Add blocking and subgroup to lane distribution support for ConvertLayout operation (#183837)

This PR refactors blocking support for ConvertLayout op to allow it
unrollable, not just removing it for specialize case.
It also removes the foldable attribute for ConvertLayout op, as we
expect the OP to be explicitly handled by XeGPU lowering.
It adds subgroup to lane distribution support for ConvertLayout op.
DeltaFile
+56-7mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
+45-11mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
+22-27mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
+22-1mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+0-23mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+16-0mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
+161-691 files not shown
+161-717 files

LLVM/project 7a7716ellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'fix-blockfreq-unroll-unconditional-latches' into fix-blockfreq-unroll-unconditional-latches--fast
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,112-16,445llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+11,541-22,066llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+186,251-180,5232,952 files not shown
+427,667-315,0292,958 files

LLVM/project 45dbce3lldb/include/lldb/Utility LLDBLog.h, lldb/source/Initialization SystemInitializerCommon.cpp

[lldb] Wrap LLDBLog Initialize/Terminate in a class (NFC) (#184469)

This matches what we do for all the other log channels (GDB Remote,
POSIX, Windows, KDP, etc).
DeltaFile
+5-2lldb/include/lldb/Utility/LLDBLog.h
+2-4lldb/source/Initialization/SystemInitializerCommon.cpp
+2-4lldb/source/Utility/LLDBLog.cpp
+9-103 files

LLVM/project 53fbbaalldb/source/Initialization SystemInitializerCommon.cpp, lldb/source/Plugins/Process/MacOSX-Kernel ProcessKDPLog.h ProcessKDP.cpp

[lldb] Fix Initialization/Termination for all log channels (#184467)

Similar to #184261, but for all the other log channels.
DeltaFile
+2-14lldb/source/Plugins/Process/Windows/Common/ProcessWindowsLog.cpp
+3-4lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemoteLog.cpp
+3-4lldb/source/Plugins/Process/POSIX/ProcessPOSIXLog.cpp
+6-0lldb/source/Initialization/SystemInitializerCommon.cpp
+1-0lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDPLog.h
+1-0lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
+16-223 files not shown
+19-229 files

LLVM/project 75a4a31llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h, llvm/test/Transforms/LoopVectorize/VPlan vplan-print-after-all.ll

[NFC][VPlan] Split `makeMemOpWideningDecisions` into subpasses

The idea is to have handling of strided memory operations (either from
https://github.com/llvm/llvm-project/pull/147297 or for VPlan-based
multiversioning for unit-strided accesses) done after some mandatory
processing has been performed (e.g., some types **must** be scalarized)
but before legacy CM's decision to widen (gather/scatter) or scalarize
has been committed.

And in longer term, we can uplift all other memory widening decision to
be done here directly at VPlan level. I expect this structure would also
be beneficial for that.
DeltaFile
+63-25llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+10-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+0-10llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+76-354 files

LLVM/project 7f3d5f1llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPRecipeBuilder.h

Fold one `Legal` use into `tryToWidenHistogram` renamed to `widenIfHistogram`
DeltaFile
+10-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+6-6llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+3-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+19-133 files

LLVM/project bd9847dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorize.cpp

Move another `Legal` use to `VPRecipeBuilder::replaceWithFinalIfReductionStore`
DeltaFile
+10-21llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+21-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+8-0llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+1-3llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+40-254 files