LLVM/project 78d53f1llvm/lib/Target/AMDGPU SIInsertHardClauses.cpp, llvm/test/CodeGen/AMDGPU hard-clauses-gfx1250.mir

[AMDGPU] Prevent clauses with incompatible scopes on gfx1250-strict
DeltaFile
+168-8llvm/test/CodeGen/AMDGPU/hard-clauses-gfx1250.mir
+20-1llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
+188-92 files

LLVM/project a80c564libcxxabi/src/demangle ItaniumDemangle.h, libcxxabi/test DemangleTestCases.inc

[ItaniumDemangle] Fix conversion operators failing to demangle types with substitutions
DeltaFile
+9-0llvm/unittests/Demangle/DemangleTest.cpp
+5-0libcxxabi/test/DemangleTestCases.inc
+4-0llvm/include/llvm/Demangle/ItaniumDemangle.h
+4-0libcxxabi/src/demangle/ItaniumDemangle.h
+22-04 files

LLVM/project 7f83ee4flang/lib/Lower Bridge.cpp PFTBuilder.cpp, flang/test/Lower assigned-goto-target-in-loop.f90

[flang][PFT] Mark ASSIGN'd labels as assigned GO TO targets

An assigned GO TO with an explicit label list only marked the listed
labels as branch targets.  Lowering is more permissive: genFIR for
AssignedGotoStmt in flang/lib/Lower/Bridge.cpp builds the switch from the
labels ASSIGN'd to the variable and ignores the list.

A construct holding an ASSIGN'd label that the list omits therefore
looked wrappable, was placed in an scf.execute_region, and the branch
then crossed a region boundary:

  error: 'fir.select' op branching to block of a different region

Mark both sets so the wrappability analysis sees every escape.
DeltaFile
+17-21flang/lib/Lower/PFTBuilder.cpp
+27-0flang/test/Lower/assigned-goto-target-in-loop.f90
+2-0flang/lib/Lower/Bridge.cpp
+46-213 files

LLVM/project ac1f755mlir/test/Conversion/VectorToLLVM vector-to-llvm-32b.mlir

test fix
DeltaFile
+4-3mlir/test/Conversion/VectorToLLVM/vector-to-llvm-32b.mlir
+4-31 files

LLVM/project 211bed0mlir/lib/Conversion/VectorToLLVM ConvertVectorToLLVM.cpp, mlir/test/Conversion/VectorToLLVM vector-to-llvm-32b.mlir

[mlir][VectorToLLVM] Use the converted index type in vector.type_cast

`VectorTypeCastOpConversion` hardcoded `i64` for the offset, size and stride
constants it inserts into the target memref descriptor, while the descriptor's
fields have the converted index type. With a type converter configured for a
32-bit index the pattern therefore emitted invalid IR:

  'llvm.insertvalue' op Type mismatch: cannot insert 'i64' into
  '!llvm.struct<(ptr, ptr, i32)>'

Build the constants from the converted index type instead.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+11-13mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
+16-0mlir/test/Conversion/VectorToLLVM/vector-to-llvm-32b.mlir
+27-132 files

LLVM/project 519a53emlir/include/mlir/Conversion/LLVMCommon Pattern.h, mlir/lib/Conversion/LLVMCommon Pattern.cpp MemRefBuilder.cpp

[mlir][NFC] Share createIndexAttrConstant as a free function (#218736)

The `LLVM::ConstantOp` with an index-typed attribute idiom existed in
three byte-identical copies: the protected `ConvertToLLVMPattern`
member, a file-static helper in `MemRefBuilder.cpp`, and open-coded in
the free function `mlir::LLVM::getStridedElementPtr`, which cannot reach
the protected member.

Promote a single free `mlir::LLVM::createIndexAttrConstant` and route
all three through it, so that a change to how these constants are built
has one place to happen.

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+10-17mlir/lib/Conversion/LLVMCommon/MemRefBuilder.cpp
+11-7mlir/lib/Conversion/LLVMCommon/Pattern.cpp
+5-0mlir/include/mlir/Conversion/LLVMCommon/Pattern.h
+26-243 files

LLVM/project 6efa392clang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGenCUDA hip-cuid-incremental.hip

[clang][CodeGen] Skip __hip_cuid_ global in incremental(clang-repl) mode (#217228)

With this patch, when run in incremental mode (clang-repl), Clang skips
emitting the `__hip_cuid_` global. This is handled in
`clang/lib/CodeGen/CodeGenModule.cpp` on
`LangOpts.IncrementalExtensions`.

I have also added a test at
`clang/test/CodeGenCUDA/hip-cuid-incremental.hip` which checks that the
`__hip_cuid_` global is emitted normally but not in the presence of
`-fincremental-extensions`.

Assisted by Claude Opus 4.8
DeltaFile
+22-0clang/test/CodeGenCUDA/hip-cuid-incremental.hip
+5-1clang/lib/CodeGen/CodeGenModule.cpp
+27-12 files

LLVM/project 82d338dmlir/test/Conversion/VectorToLLVM vector-to-llvm-32b.mlir

test fix
DeltaFile
+4-3mlir/test/Conversion/VectorToLLVM/vector-to-llvm-32b.mlir
+4-31 files

LLVM/project bc69ba1mlir/lib/Conversion/MPIToLLVM MPIToLLVM.cpp, mlir/test/Conversion/MPIToLLVM mpitollvm.mlir

[mlir][MPIToLLVM] Take the descriptor index type from the descriptor

`getRawPtrAndSize` extracted the memref descriptor's offset as `i64` and
unconditionally truncated the extents to `i32`. Both assume a 64-bit index: with
a 32-bit one the extract disagrees with the descriptor's field type and the
truncation becomes an invalid `llvm.trunc` from `i32` to `i32`.

Read the index type off the descriptor and only adjust the extent width when it
actually differs. While here, drop the rank-0 branch that rebuilt the already
available element count as an `arith.constant` in the middle of an LLVM
lowering.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+71-1mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir
+18-10mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
+89-112 files

LLVM/project d598281.github/workflows pr-code-lint.yml pr-code-format.yml

[Github] Bump containers in pr-code-{format,lint} workflows (#218835)

This will pick up the LLVM 23 upgrade.
DeltaFile
+1-1.github/workflows/pr-code-lint.yml
+1-1.github/workflows/pr-code-format.yml
+2-22 files

LLVM/project 9c571c3clang/include/clang/AST Expr.h

[clang][AST] Improve StringLiteral documentation (#218705)

Add some docs and improve existing ones.
DeltaFile
+23-8clang/include/clang/AST/Expr.h
+23-81 files

LLVM/project aa46cfellvm/include/llvm/Transforms/Utils BuildLibCalls.h, llvm/lib/Transforms/Utils BuildLibCalls.cpp SimplifyLibCalls.cpp

[MemProf] Support cold-only and min hint when optimizing existing hot/cold new (#218803)

Change -optimize-existing-hot-cold-new to an enum option supporting:
- none (default): Do not optimize existing hot/cold new calls
- cold: Only optimize existing hot/cold new calls if determined to be
cold
- always: Always optimize existing hot/cold new calls

Add a new option -min-existing-hot-cold-new-hint (off by default) that,
when optimizing an existing hot/cold operator new call, takes the
minimum
of the compiler hint and the existing hint.
DeltaFile
+98-45llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+59-5llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
+12-14llvm/lib/Transforms/Utils/BuildLibCalls.cpp
+6-7llvm/include/llvm/Transforms/Utils/BuildLibCalls.h
+175-714 files

LLVM/project 9c46718llvm/lib/ProfileData SampleProfWriter.cpp, llvm/test/tools/llvm-profdata eytzinger-split-nametable-partition.test

[SampleProfile] Apply minor readability cleanups (#217878)
DeltaFile
+2-2llvm/lib/ProfileData/SampleProfWriter.cpp
+1-1llvm/test/tools/llvm-profdata/eytzinger-split-nametable-partition.test
+3-32 files

LLVM/project f50a689mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp, mlir/test/Dialect/LLVMIR inlining-alias-scopes.mlir

[mlir][LLVM] Use a disjoint scope domain when inlining noalias

This matches recent changes to the LLVM inliner.

AI disclosure: Claude wrote the code, I wrote the commit message and
have done initial review.
DeltaFile
+28-25mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+10-18mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+38-432 files

LLVM/project 8194eb2mlir/include/mlir/Dialect/LLVMIR LLVMAttrDefs.td, mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

[mlir][LLVM] Add disjointScopes to AliasScopeDomainAttr

This also updates the MLIR-side inliner to clone disjoint domains
while cloning alias scopes, matching changes to LLVM.

AI disclosure: Claude wrote the code, I wrote the commit message and
looked at the code.
DeltaFile
+25-0mlir/test/Target/LLVMIR/Import/metadata-alias-scopes.ll
+23-0mlir/test/Target/LLVMIR/attribute-alias-scopes.mlir
+17-2mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+4-2mlir/lib/Target/LLVMIR/ModuleImport.cpp
+4-1mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+2-2mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+75-76 files

LLVM/project 35b0ce7llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/test/CodeGen/AMDGPU lower-lds-struct-aa-memcpy.ll remove-no-kernel-id-attribute.ll

[AMDGPU] Use a disjoint scope domain for merged LDS structs

When lowering LDS values, all the values are mutually disjoint, so we
can use the newly-added disjoint scopes feature to simplify the IR.

AI disclosure: Claude wrote this and I reviewed it and wrote the
 commit message
DeltaFile
+15-52llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+35-10llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
+15-18llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
+11-13llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
+8-12llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
+9-10llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
+93-1156 files not shown
+139-16112 files

LLVM/project e621ec6llvm/lib/Target/AMDGPU AMDGPULowerKernelArguments.cpp, llvm/test/CodeGen/AMDGPU lower-kernargs.ll si-split-load-store-alias-info.ll

[AMDGPU] Use a disjoint scope domain for noalias kernel arguments

All noalias arguments of a kernel are disjoint with each other, so we
can use a disjoint scope to save on metadata construction.

AI disclosure: Claude wrote this, I looked at it and wrote this
message.
DeltaFile
+53-64llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
+20-13llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
+11-11llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
+8-8llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
+4-4llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
+96-1005 files

LLVM/project 4ca9b8dclang/test/CodeGen arm_neon_intrinsics.c arm-v8.2a-neon-intrinsics-generic.c, llvm/lib/Bitcode/Reader MetadataLoader.cpp

[IR] Add alias scope domains with disjoint scopes

See RFC at
https://discourse.llvm.org/t/rfc-disjoint-scope-alias-scope-noalias-domains/91537

This commit adds support for declaring an alias scope domain disjoint.
Disjoint domains are ones where each scope is implicitly `!noalias`
with each other scope in the domain. This is represented by adding an
`i1` into the scope's domain as the second argument, with `i1 true`
representing disjoint scopes and `i1 false` representing the old
non-disjoint behavior. AutoUpgrade mechanisms have been added to add
in the missing `i1 false` to existing metadata.

This commit updates alias analysis to know about disjoint scopes and
updates the function cloner to also clone the alias domain if it's
disjoint (since, as a herd of LLMs discovered, you don't want the old
IR to be noalias with a clone of itself).

Commits to migrate passes to use disjoint scopes where that's an

    [4 lines not shown]
DeltaFile
+72-72clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
+54-54clang/test/CodeGen/arm_neon_intrinsics.c
+97-0llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+95-0llvm/test/Transforms/InstCombine/noalias-scope-decl-disjoint-domain.ll
+42-42llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll
+39-35llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
+399-203189 files not shown
+1,342-718195 files

LLVM/project 0e0ca42clang/test/CodeGen arm-v8.2a-neon-intrinsics-generic.c arm_neon_intrinsics.c, llvm/lib/Transforms/Utils InlineFunction.cpp

[Inliner] Use a disjoint scope domain for noalias arguments

InlineFunction creates alias.scope/noalias metadata to represent the
set of `noalias` arguments to a function. We don't need the `!noalias`
now that we have the ability to use disjoint scopes, saving us IR size
and metadata bloat.

TODO move these to a previous commit.
Also changes InstCombine to not drop the experimental.noalias.scope.decl
for disjoint scopes even if they're not mentioned in a `!noalias`, but
do still delete them if they're not used.
DeltaFile
+324-324clang/test/CodeGen/arm_neon_intrinsics.c
+72-72clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
+35-30llvm/lib/Transforms/Utils/InlineFunction.cpp
+13-14llvm/test/Transforms/Inline/noalias-calls2.ll
+12-12llvm/test/Transforms/Inline/noalias2.ll
+11-11llvm/test/Transforms/PhaseOrdering/pr39282.ll
+467-4639 files not shown
+487-48315 files

LLVM/project 2bb0571llvm/test/tools/UpdateTestChecks/update_test_checks dot_value_in_metadata_string.test, llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs dot_value_in_metadata_string.ll dot_value_in_metadata_string.ll.expected

[utils] Don't rename %. inside quoted strings in test checkseg

Replacing `%.foo` with `%dotfoo` everywhere also caught any `%.foo`
inside metadata, which would then cause incorrect CHECK lines to be
generated (since the value in the metedata isn't going to be
modified).

This commit fixes the issue by matching quoted strings in a regex
before looking for %. to replace.

AI disclosure: Claude found and fixed this, I wrote the commit message
DeltaFile
+22-0llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/dot_value_in_metadata_string.ll.expected
+10-1llvm/utils/UpdateTestChecks/common.py
+11-0llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/dot_value_in_metadata_string.ll
+7-0llvm/test/tools/UpdateTestChecks/update_test_checks/dot_value_in_metadata_string.test
+50-14 files

LLVM/project 24ac21ellvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp

Address comments

Created using spr 1.3.6-beta.1
DeltaFile
+12-11llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+12-111 files

LLVM/project fb4b133llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/InstCombine/RISCV riscv-vsetvlimax-ispow2.ll

[ValueTracking] Treat RISC-V vsetvlimax as a power of two (#218831)

VLMAX = VLEN * LMUL / SEW is always a non-zero power of two for any valid
vtype, so llvm.riscv.vsetvlimax is a power of two regardless of SEW/LMUL or
whether a vscale_range is present. Report this in isKnownToBeAPowerOfTwo
so that consumers such as ctpop and the x & (x - 1) idiom can fold.

Assisted-by: TRAE CLI (Opus 4.8)
DeltaFile
+63-0llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvlimax-ispow2.ll
+4-0llvm/lib/Analysis/ValueTracking.cpp
+67-02 files

LLVM/project f79da0allvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Transforms/Scalar ExpandMemCmp.cpp

[ExpandMemCmp] Apply NumLoadsPerBlock to ordering compares (#215186)

Make NumLoadsPerBlock control both equality and ordering memcmp
expansions. For ordering comparisons, pack consecutive legal loads
in memory order into a value no wider than the target preferred
load width, then compare the packed values. This preserves
lexicographic semantics while reducing conditional branches.

BPF uses groups of eight byte-load pairs, so an align-1 32-byte
comparison forms four i64 compare blocks instead of 32 byte compare
blocks.

Other targets retain their existing default ordering behavior unless
grouping is explicitly requested.

Assisted-by: TRAE CLI (GPT-5)
DeltaFile
+898-0llvm/test/Transforms/ExpandMemCmp/BPF/memcmp.ll
+190-107llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
+168-75llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
+56-75llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
+14-14llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
+5-3llvm/include/llvm/Analysis/TargetTransformInfo.h
+1,331-2748 files not shown
+1,342-28014 files

LLVM/project 2c972ab.github/workflows/containers/github-action-ci-tooling Dockerfile

[Github] Bump formatting/tools container to 23.1.0 (#218815)

Now that 23.1.0 has been released, we should update the container to
ensure we're using the latest released version of the tooling.
DeltaFile
+2-2.github/workflows/containers/github-action-ci-tooling/Dockerfile
+2-21 files

LLVM/project 16852a1.github/workflows pr-code-format.yml

[Github] Hash pin ci-format container (#218816)

This follows our own CI best practices and ensures zizmor/CodeQL will
not complain about this when people inevitably touch it in the future.
DeltaFile
+1-1.github/workflows/pr-code-format.yml
+1-11 files

LLVM/project cfe9defllvm/lib/IR Verifier.cpp, llvm/test/Verifier/RISCV vsetvli.ll

[RISCV][Verifier] Check operands and result type of RISC-V vsetvli/vsetvlimax (#218594)

The result of `llvm.riscv.vsetvli/vsetvlimax` models VLMAX (or a VL bounded
by it) and is only defined for XLen, so the result type must be i32 or i64.
Narrower types cannot represent the architectural VLMAX range of [1, 65536]
that value analyses rely on.

Also check that the VSEW and VLMUL immediate operands encode a valid
SEW/LMUL pair (VSEW <= 3, VLMUL != reserved), so that consumers can
assume a well-formed vtype.

Assisted-by: TRAE CLI (Opus 4.8)
DeltaFile
+25-0llvm/test/Verifier/RISCV/vsetvli.ll
+22-0llvm/lib/IR/Verifier.cpp
+47-02 files

LLVM/project 106601aclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen arm-neon-vld.c

[CIR][AArch64] Upstream load (vld1_*/vld1q_*) NEON builtins (#218319)

Related to https://github.com/llvm/llvm-project/issues/185382

CIR lowering for load intrinsics (`vld1_*`/`vld1q_*`)

(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#stride)

Port tests:
- `clang/test/CodeGen/AArch64/neon-intrinsics.c`
- `clang/test/CodeGen/AArch64/neon-ldst-one.c`
- `clang/test/CodeGen/AArch64/poly64.c`
- `clang/test/CodeGen/arm-neon-vld.c`

to `clang/test/CodeGen/AArch64/neon/load.c`
DeltaFile
+2,240-0clang/test/CodeGen/AArch64/neon/load.c
+365-576clang/test/CodeGen/arm-neon-vld.c
+1-743clang/test/CodeGen/AArch64/neon-ldst-one.c
+0-698clang/test/CodeGen/AArch64/neon-intrinsics.c
+66-14clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+0-20clang/test/CodeGen/AArch64/poly64.c
+2,672-2,0511 files not shown
+2,678-2,0577 files

LLVM/project 63e0da0clang/include/clang/Lex Preprocessor.h, clang/lib/Frontend InitPreprocessor.cpp

[C++][Modules] Don't insert `#include` before GMF when `-include` used (#212533)

Clang currently emits command-line implicit inputs such as `-imacros`,
`-include-pch`/`-include-pth`, and `-include` as part of the predefines
buffer. This causes them to be processed before the main source file.

For a C++20 module unit with a global module fragment:

```cpp
module;
export module M;
```

a force-included header containing declarations was effectively
processed as:

```cpp
#include "Header.h"
module;

    [23 lines not shown]
DeltaFile
+157-0clang/test/Modules/cxx20-force-include.cpp
+56-18clang/lib/Lex/DependencyDirectivesScanner.cpp
+51-0clang/unittests/Lex/DependencyDirectivesScannerTest.cpp
+49-0clang/lib/Lex/Preprocessor.cpp
+23-12clang/lib/Frontend/InitPreprocessor.cpp
+31-1clang/include/clang/Lex/Preprocessor.h
+367-314 files not shown
+412-4410 files

LLVM/project e1ff57eclang/test/CodeGenCXX module-initializer-elision.cpp

[NFC] Skip a test on target={{.*}}-apple-darwin for TLS using (#218824)

Close https://github.com/llvm/llvm-project/pull/218346
DeltaFile
+2-0clang/test/CodeGenCXX/module-initializer-elision.cpp
+2-01 files

LLVM/project f872635llvm/lib/Target/X86 X86InstrFragments.td X86InstrCompiler.td, llvm/test/CodeGen/X86 pr218583.ll

[X86] Limit the result of XOR8rr_NOREX unused (#218640)

In case it may be zero/sign-extended into an REX/REX2 register.

Fixes: #218583

Assisted-by: Claude Opus 4.8
DeltaFile
+77-0llvm/test/CodeGen/X86/pr218583.ll
+10-3llvm/lib/Target/X86/X86InstrCompiler.td
+5-0llvm/lib/Target/X86/X86InstrFragments.td
+92-33 files