[LV,LLE] Add tests for checks with versioned strides (NFC) (#233276)
Add tests for trip counts rewritten using versioned strides and for the
stride check on a possibly poison stride.
[ARM] Fix miscompile in MAC for 64b values (#231702)
AddCombineTo64BitSMLAL16 is invoked from PerformADDECombine where the
combined node N is AddeNode, but it returned SDValue(AddcNode, 0).
Because RV.getNode() != N, DAGCombiner::Run did not stop replacing and
called DAG.ReplaceAllUsesWith(AddeNode, AddcNode), replacing uses of
the high-word carry/overflow flag (AddeNode, 1) with the low-word
addition flag (AddcNode, 1).
Assisted-by: Gemini
Fixes: e9113618cba6 ("[ARM] Custom Lowering for SADDO_CARRY and
SSUBO_CARRY (#154419)")
(cherry picked from commit 28999cd08f23dd7baeb63b7ca4addef4214999e3)
[clang-tidy] Fix assignment-in-if-condition false positive in statement expressions (#231704)
The check traversed into GNU statement expressions and diagnosed
assignments in separate statements inside them, e.g. `({ ...; r = ...;
r; })`.
Now the check only looks at the last statement of a GNU statement
expression, skipping any labels or attributes on it. An assignment that
is itself the value is still diagnosed.
Fixes #210638
[Clang][OpenMP] Fix crash on `atomic` with an erroneous statement (#228914)
Fixes #107979
A statement under `#pragma omp atomic` that already has an error, such
as `0--;` or an assignment to a `const` variable, reaches
`OpenMPAtomicUpdateChecker` as a `RecoveryExpr`. Since #71480 the
checker reports it with a `NotAValidExpression` code, but that code is
also used as the `%select` index of `note_omp_atomic_update`, which only
had eight options. So for `atomic`, `atomic update` and the `v = expr`
form of `atomic capture` the note was emitted with index 8 and we hit
the assertion in `HandleSelectModifier`.
The note now has an option for `NotAValidExpression`, so every error
code of the checker has a matching message. The checker also no longer
builds the helper update expression when an operand contains errors,
which used to add a second error, `invalid operands to binary expression
('int' and '<dependent type>')`, for statements such as `x += 0--;`.
Assisted-by : AI tools
[ADT] Clean up DenseMap.h after removing CRTP (NFC) (#228981)
This patch makes several minor cleanups in DenseMap.h following the
removal of CRTP. While most changes are obvious, notable ones include:
- Drop the redundant "= 4" default argument on SmallDenseMapStorage's
InlineBuckets template parameter, as SmallDenseMap already provides
it.
- Inline DenseMapBase::hasher into its sole caller
DenseMapBase::grow.
Assisted-by: Antigravity
[SLP]Count only reduction root candidates for store-based reductions
Exclude stores of loads, non-instructions, and already vectorized
stores, as they cannot start a reduction, but they blocked the reduction
attempt.
Fixes #91780
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/233271
[KnownFPClass] Correct denormal mode handling for `KnownFPClass::minMaxLike` (#220148)
Part of https://github.com/llvm/llvm-project/issues/219295
Corrects denormal mode and NaN sign bit handling for
`KnownFPClass::minMaxLike`.
I have rewritten `KnownFPClass::minMaxLike` so the sign bit is never
inferred incorrectly in the first place. The sign bit from the arguments
is no longer propagated to the result. Denormal modes are now applied to
the operands up front and to the result at the end, instead of being
fixed up afterwards.
This also fixes a bug where qNaN was incorrectly ruled out when the
inputs may be sNaN but not qNaN, since a sNaN may be quieted.
There are other NaN handling issues with minnum/maxnum (they may return
a NaN for an sNaN input), but fixing those touches a lot of
InstSimplify, InstCombine, and AMDGPU tests, so I've left them for a
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[flang][OpenMP] Ignore DECLARE_SIMD and warn about missing implementa… (#232712)
…tion
Currently DECLARE_SIMD emits a "not yet implemented" error in the MLIR
to LLVM IR translation.
DECLARE_SIMD is a hint to the compiler and ignoring it is technically
speaking a conforming implementation (although obviously not desirable).
Do not abort compilation when DECLARE_SIMD is encountered, but emit a
warning that it's currently ignored.
[SLP]Compare main lanes of same-opcode and copyable states
For a same-opcode state both main lanes were skipped, so the original
main lane (potenitally with copyables) was never compared.
Fixes #230578
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/233266
[RISCV][P-ext] Use concat_vectors with 0 in widenPackedVectorWithZeros. (#232940)
This will be legalized and combined to a vector_shuffle. That shuffle
can then be matched to a pack with x0 after #232892.
This changes the zext.w to a pack, but that's not obviously worse. If we
need to canonicalize we can add a DAG combine later.
[RISCV][P-ext] Remove custom lowering of insert_subvector for v2i16/v4i8 on RV64. (#232899)
This was for handling inserting into a zero vector. After #232892 we let
the insert_subvector legalize to a shuffle_vector which we can then
lower as pack.
This changes the codegen from zext.w to pack, but that's not necessarily
worse. If it turns out to be a problem we can canonicalize pack with
zero with a DAGCombine or isel patterns in the future.
[flang][OpenMP] Switch clause verification to descriptor-based
Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
[X86] combineConcatVectorOps - ensure at least one of the VSELECT/BLENDV selection operands fully concatenates (#233245)
Don't rely on IsConcatFree - we might still end up with temporary
CONCAT_VECTORS nodes that might not get folded away before another
combine recognises a vector that can be freely split.
Fixes #233185
[InstCombine] Added log2-ceil check for non-power-of-two integer widths (#232418)
The log2-ceil fold is only valid for power-of-two integer bit widths.
Adding check for verifying bit width is power of two.
Fixes #227862
[AMDGPU] Price memory operations by the number of memory instructions
Price a load or store as the number of memory instructions it is split
into.
Constant and buffer "fat" pointers are left alone (for now).
[AMDGPU] Price under-aligned memory operations
Without unaligned access for the address space, an access aligned below
4 bytes is split into pieces of its alignment. LDS accesses aligned to 4
use 8-byte pieces, and take a 12-byte piece only when aligned to 16 or
when unaligned DS access is enabled.
[X86] Allow bf16 masked load/store with AVX512BW (#230953)
bf16 masked loads/stores don't use any avx512bf16 instructions, but
isLegalMaskedLoadStore only accepted bfloat with hasBF16(). Without it
they got scalarized, which is pretty bad (one branch plus an
extend/truncate libcall per element). With BWI they can use vmovdqu16
the same way f16 does, and the existing mask_move_lowering_f16_bf16
patterns only need BWI.
This relaxes the TTI check to BWI like half, and makes
v8bf16/v16bf16/v32bf16 legal with BWI. They were only legal with
BF16/AVXNECONVERT before, so on plain BWI the masked ops were split
before isel ever saw them (avx512bf16 implies BWI anyway). To go with
that:
- v8bf16/v16bf16 masked loads/stores use the same non-VLX widening as
f16.
- A few broadcast/insert/extract/subvector zeroing patterns that don't
need any bf16 instructions are now enabled with BWI (or folded into the
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RegisterPressure: Detect dead physreg defs from LiveIntervals with lane masks (#233215)
Extend the fix from #225079 to the lane mask tracking path used by
targets with subregister liveness. adjustLaneLiveness also needs to
force the physreg unit ranges to be computed to identify dead defs,
rather than taking the conservative default when they are not cached.
Without this, an overlapping physreg def missing a dead flag is
counted as a live def. Conservatively assuming it is live doesn't work
because PressureDiff disagrees with the tracker and fails the
EXPENSIVE_CHECKS consistency assert.
This avoids an ll asm test failing when LiveVariables removed; #233202
fixes the missing dead flag for that case. I had additional patches
which nearly eliminate all missing dead flags. Unless the verifier
enforces accurate dead flags, we still need to handle this edge case.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[LV] Thread an explicit CM param through VPlan-building/costing helpers (#224836)
Parameterize `cost()`, `tryToBuildVPlan1()`, `tryToBuildVPlan()`,
`buildVPlans()` and `addReductionResultComputation` with an explicit
`LoopVectorizationCostModel &PlanCM` argument instead of always reaching
for the planner's own CM member.
This is preparation for tail-folded vector epilogue support, which will
plan against a separate CM from the one used for the main vector loop.
Passing the CM in explicitly lets these functions to be called with
whichever CM applies to what's currently being planned.
All existing call sites still pass *CM, so this is NFC.
[clang][docs] fix grammar and spelling errors in cir docs (#220877)
Fix some obvious typos and grammar mistakes in the CIR docs.
Signed-off-by: Hardik Kumar <hardikxk at gmail.com>
[flang][OpenMP] Switch clause verification to descriptor-based
Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
