LLVM/project 3015979 — clang/test/CodeGen/RISCV riscv-inline-asm.c, llvm/lib/Target/RISCV RISCVISelLowering.cpp

by joshua-arch1 via GitHub on ⎇
[RISCV] Support 'f' Inline Assembly Constraint for bfloat16 (#184566)

This patch is to add 'f' and 'cf' Inline Assembly Constraint for the `bfloat16` type, so they are passed in the floating point registers.
DeltaFile
+45-0llvm/test/CodeGen/RISCV/inline-asm-bf-constraint-f.ll
+4-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+4-0clang/test/CodeGen/RISCV/riscv-inline-asm.c
+53-03 files

LLVM/project 4ea72c1 — lld/ELF Relocations.cpp InputSection.cpp, lld/ELF/Arch RISCV.cpp

by Fangrui Song via GitHub on ⎇
[ELF] Add target-specific relocation scanning for RISC-V (#181332)

Implement RISCV::scanSectionImpl, following the pattern established
for x86 (#178846) and AArch64 (#181099). This merges the getRelExpr
and TLS handling for SHF_ALLOC sections into the target-specific
scanner, enabling devirtualization and eliminating abstraction
overhead.

- Inline relocation classification into scanSectionImpl with a switch
  on relocation type, replacing the generic rs.scan() path.
- Use processR_PC/processR_PLT_PC for common PC-relative and PLT
  relocations.
- Handle TLS IE and GD directly (RISC-V does not optimize GD/LD/IE).
- Replace TLS-optimization-specific expressions for TLSDESC, following
  the x86 pattern: R_RELAX_TLS_GD_TO_IE -> R_GOT_PC,
  R_RELAX_TLS_GD_TO_LE -> R_TPREL. Update relocateAlloc and relax()
  to dispatch on relocation type instead of RelExpr for TLSDESC.
- Simplify getRelExpr to only handle relocations needed by
  relocateNonAlloc and preprocessRelocs.

    [4 lines not shown]
DeltaFile
+185-94lld/ELF/Arch/RISCV.cpp
+36-6lld/test/ELF/riscv-vendor-relocations.s
+32-0lld/test/ELF/riscv-vendor-relocations2.test
+6-21lld/ELF/Relocations.cpp
+2-2lld/test/ELF/riscv-reloc-leb128.s
+1-1lld/ELF/InputSection.cpp
+262-1246 files

LLVM/project f7ca74f — llvm/lib/Target/RISCV RISCVInstrInfoV.td, llvm/test/MC/RISCV/rvv zvlsseg-invalid.s

by joshua-arch1 via GitHub on ⎇
[RISCV] Add register overlap checks to the assembler for vector indexed segment load (#184569)

The destination vector register group cannot overlap the source vector
register group for vector indexed segment load. This patch is to add
register overlap checks to the assembler.
DeltaFile
+66-0llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s
+4-0llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+70-02 files

LLVM/project 76ffbc7 — llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU vgpr-spill.mir

by Aaditya on ⎇
Review comments
DeltaFile
+8-7llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+4-4llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
+12-112 files

LLVM/project f712c97 — clang/include/clang/DependencyScanning ModuleDepCollector.h, clang/lib/DependencyScanning ModuleDepCollector.cpp

by Jan Svoboda via GitHub on ⎇
[clang][deps] Store `IgnoreCWD` on `ModuleDeps` (#184921)

This aligns us with downstream, where we need to be able to query
whether a module depends on CWD or not.
DeltaFile
+6-5clang/lib/DependencyScanning/ModuleDepCollector.cpp
+4-1clang/include/clang/DependencyScanning/ModuleDepCollector.h
+10-62 files

LLVM/project eaae8e2 — llvm/lib/Target/RISCV RISCVISelLowering.cpp

by Jim Lin via GitHub on ⎇
[RISCV] Remove outdated TODO in isExtractSubvectorCheap (#184938)

Index 0 is already handled by an early return, so the TODO comment about
extracting index 0 from a mask vector is no longer needed.
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+0-11 files

LLVM/project 0538d0a — clang/lib/Basic/Targets NVPTX.h, clang/test/Misc nvptx.unsupported_core.cl nvptx.languageOptsOpenCL.cl

by Wenju He via GitHub on ⎇
[NVPTX] Enable OpenCL 3d_image_writes support (#143331)

NV supports opencl_3d_image_writes according
https://developer.nvidia.com/blog/nvidia-is-now-opencl-3-0-conformant/

This PR allows removing explicit enabling of image extensions via
-cl-ext command line option, e.g. at
https://github.com/intel/llvm/blob/43b3d42e2b2060e9e9e3a96469a1982dc4c10ddd/libclc/CMakeLists.txt#L503
DeltaFile
+0-7clang/test/Misc/nvptx.unsupported_core.cl
+2-3clang/test/Misc/nvptx.languageOptsOpenCL.cl
+4-0clang/lib/Basic/Targets/NVPTX.h
+6-103 files

LLVM/project bcb85e3 — llvm/test/CodeGen/AArch64 clmul-fixed.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll clmul-sdnode.ll

by Connector Switch via GitHub on ⎇
Merge branch 'main' into users/c8ef/fold_left_first
DeltaFile
+53,024-7,001llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+15,172-1,553llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+6,520-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+3,717-56llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,441-0llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
+3,257-0llvm/test/CodeGen/X86/bit-manip-i256.ll
+85,131-8,6101,222 files not shown
+123,904-21,9951,228 files

LLVM/project 8acbd0c — libcxx/test/libcxx/strings/basic.string/string.cons constexpr_initialization_stress.pass.cpp

by Vitaly Buka on ⎇
5000

Created using spr 1.3.7
DeltaFile
+1-1libcxx/test/libcxx/strings/basic.string/string.cons/constexpr_initialization_stress.pass.cpp
+1-11 files

LLVM/project 61ead49 — clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/AST/HLSL Texture2D-vector-AST.hlsl Texture2D-scalar-AST.hlsl

by Vitaly Buka via GitHub on ⎇
Merge branch 'main' into users/vitalybuka/spr/libcxxstring-replace-asan-volatile-wrapper-with-memory-barrier
DeltaFile
+754-88clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+726-0clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
+722-0clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
+560-0clang/test/SemaSYCL/sycl-kernel-launch.cpp
+364-111llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+0-439clang/test/AST/HLSL/Texture2D-AST.hlsl
+3,126-638256 files not shown
+9,480-2,995262 files

LLVM/project dd79c92 — lld/ELF RelocScan.h, lld/ELF/Arch ARM.cpp

by Fangrui Song via GitHub on ⎇
[ELF] handleTlsGd: support disabling GD-to-IE/LE optimization. NFC (#184934)

Use this in ARM::scanSectionImpl for R_ARM_TLS_GD32 and the upcoming
RISC-V change.
DeltaFile
+15-14lld/ELF/RelocScan.h
+1-2lld/ELF/Arch/ARM.cpp
+16-162 files

LLVM/project 1f84b73 — llvm/lib/Target/RISCV RISCVInstrInfoXSpacemiT.td RISCVInstrFormatsSpacemitV.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

by LiqinWeng via GitHub on ⎇
[RISCV] Add contraints for SpacemiT X60 AI VDot Insts (#174364)

Spec: https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1
DeltaFile
+77-79llvm/test/MC/RISCV/xsmtvdot-valid.s
+32-124llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
+103-0llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td
+30-45llvm/test/MC/RISCV/xsmtvdot-invalid.s
+28-8llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+270-2565 files

LLVM/project f409804 — utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy BUILD.bazel

by Aiden Grossman on ⎇
[Bazel] Fix build for #184030

hicpp needed a new dependency.
DeltaFile
+1-0utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
+1-01 files

LLVM/project b0ecd04 — llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

by Jeffrey Byrnes on ⎇
Change old code

Change-Id: I26cff6c0c5743684778f022b264c9930eeff24ce
DeltaFile
+4-2llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+4-21 files

LLVM/project 8287e00 — llvm/test/Instrumentation/AddressSanitizer dynamic-shadow-windows.ll

by Zack Johnson on ⎇
Add instrumentation test for Windows dynamic shadow memory address on x64 and arm64
DeltaFile
+20-0llvm/test/Instrumentation/AddressSanitizer/dynamic-shadow-windows.ll
+20-01 files

LLVM/project 850a54f — clang/lib/Sema TreeTransform.h

by Tom Honermann via GitHub on ⎇
[NFC] Add template disambiguation for dependent call to getAttr. (#184928)

This fixes buildbot failures for darwin targets triggered by #152403. 
- https://lab.llvm.org/buildbot/#/builders/190/builds/37864
- https://lab.llvm.org/buildbot/#/builders/23/builds/18339
DeltaFile
+1-1clang/lib/Sema/TreeTransform.h
+1-11 files

LLVM/project e9606df — llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll coexec-sched-effective-stall.mir

by Jeffrey Byrnes on ⎇
[AMDGPU] Add HWUI pressure heuristics to coexec strategy

Change-Id: I322cc670c8d923a6df23588d8a14cdaec1f49da9
DeltaFile
+601-0llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+413-22llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+284-2llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+4-4llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+1,302-284 files

LLVM/project a500d65 — mlir/lib/Dialect/OpenACC/IR OpenACCCG.cpp

by Aiden Grossman on ⎇
[MLIR][ACC] Fix -Wunused-variable in dfe7738

There was a variable only used in an assertion which causes warnings in
non-assertions builds. Fix the issue by inlining the variable into the
assertion given it is only used in one place.
DeltaFile
+1-2mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
+1-21 files

LLVM/project 026b90f — libcxx/include string

by Vitaly Buka on ⎇
no dups

Created using spr 1.3.7
DeltaFile
+0-2libcxx/include/string
+0-21 files

LLVM/project 125519e — clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/AST/HLSL Texture2D-vector-AST.hlsl Texture2D-scalar-AST.hlsl

by Vitaly Buka on ⎇
no explicit limits

Created using spr 1.3.7
DeltaFile
+754-88clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+726-0clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
+722-0clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
+560-0clang/test/SemaSYCL/sycl-kernel-launch.cpp
+364-111llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+0-439clang/test/AST/HLSL/Texture2D-AST.hlsl
+3,126-638224 files not shown
+8,782-2,526230 files

LLVM/project 283116e — clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/AST/HLSL Texture2D-vector-AST.hlsl Texture2D-scalar-AST.hlsl

by Vitaly Buka on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+754-88clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+726-0clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
+722-0clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
+560-0clang/test/SemaSYCL/sycl-kernel-launch.cpp
+364-111llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+400-39clang/test/CodeGen/AArch64/neon/intrinsics.c
+3,526-238224 files not shown
+8,782-2,526230 files

LLVM/project 2d67bf9 — clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/AST/HLSL Texture2D-vector-AST.hlsl Texture2D-scalar-AST.hlsl

by Vitaly Buka on ⎇
no explicit limits

Created using spr 1.3.7
DeltaFile
+754-88clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+726-0clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
+722-0clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
+560-0clang/test/SemaSYCL/sycl-kernel-launch.cpp
+364-111llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+0-439clang/test/AST/HLSL/Texture2D-AST.hlsl
+3,126-638224 files not shown
+8,782-2,526230 files

LLVM/project b57d62c — clang/include/clang/AST ASTStructuralEquivalence.h

by Shafik Yaghmour via GitHub on ⎇
[Clang][NFC] Apply Rule of Three to AttrScopedAttrEquivalenceContext (#184905)

Static analysis flagged AttrScopedAttrEquivalenceContext as having a
user defined destructor but not having copy ctor or copy assignment. I
set them as deleted since they are not needed.
DeltaFile
+4-0clang/include/clang/AST/ASTStructuralEquivalence.h
+4-01 files

LLVM/project 08f6fed — clang/test/OpenMP loop_collapse_codegen.cpp, llvm/test/CodeGen/AArch64 clmul-fixed.ll

by Vitaly Buka on ⎇
rebase

Created using spr 1.3.7
DeltaFile
+6,520-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+3,707-46llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,441-0llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
+3,257-0llvm/test/CodeGen/X86/bit-manip-i256.ll
+857-0clang/test/OpenMP/loop_collapse_codegen.cpp
+706-0llvm/test/Transforms/LoopVectorize/float-induction.ll
+18,488-46437 files not shown
+31,961-4,273443 files

LLVM/project cc2c0f9 — clang/test/OpenMP loop_collapse_codegen.cpp, llvm/test/CodeGen/AArch64 clmul-fixed.ll

by Vitaly Buka on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+6,520-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+3,707-46llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,441-0llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
+3,257-0llvm/test/CodeGen/X86/bit-manip-i256.ll
+857-0clang/test/OpenMP/loop_collapse_codegen.cpp
+706-0llvm/test/Transforms/LoopVectorize/float-induction.ll
+18,488-46436 files not shown
+31,959-4,273442 files

LLVM/project 68708c6 — clang/lib/Lex HeaderSearch.cpp ModuleMap.cpp, clang/test/Modules deprecated-upwards-relative-path.m

by Vitaly Buka on ⎇
rebase

Created using spr 1.3.7
DeltaFile
+22-82lldb/test/API/python_api/run_locker/TestRunLocker.py
+91-0clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixFloatPrecisionWarnings.hlsl
+81-0clang/test/Modules/deprecated-upwards-relative-path.m
+46-27clang/lib/Lex/HeaderSearch.cpp
+36-12clang/lib/Lex/ModuleMap.cpp
+0-44libcxx/test/std/strings/basic.string/string.cons/constexpr_initialization_stress.pass.cpp
+276-16520 files not shown
+450-24426 files

LLVM/project cf8004b — llvm/include/llvm/ExecutionEngine/Orc WaitingOnGraph.h

by Lang Hames on ⎇
[ORC] Remove accidental #include left in 7f6ada93f72. NFC.

left in the final commit.
DeltaFile
+0-2llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
+0-21 files

LLVM/project a69df50 — llvm/test/CodeGen/AMDGPU call-argument-types.ll amdgcn.bitcast.768bit.ll

by Dhruva Chakrabarti on ⎇
[AMDGPU] Regenerated tests after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.
DeltaFile
+284-572llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+227-225llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+180-196llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+171-143llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+131-80llvm/test/CodeGen/AMDGPU/bf16.ll
+88-94llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+1,081-1,3109 files not shown
+1,477-1,70115 files

LLVM/project 63db92d — clang-tools-extra/clang-tidy/hicpp NoAssemblerCheck.cpp NoAssemblerCheck.h, clang-tools-extra/clang-tidy/portability NoAssemblerCheck.cpp NoAssemblerCheck.h

by Arjun Parmar via GitHub on ⎇
[clang-tidy] Rename hicpp-no-assembler to portability-no-assembler, keep hicpp as alias (#184030)

Part of #183462.

closes #183466.
DeltaFile
+37-0clang-tools-extra/clang-tidy/portability/NoAssemblerCheck.cpp
+0-37clang-tools-extra/clang-tidy/hicpp/NoAssemblerCheck.cpp
+30-0clang-tools-extra/clang-tidy/portability/NoAssemblerCheck.h
+0-30clang-tools-extra/clang-tidy/hicpp/NoAssemblerCheck.h
+12-0clang-tools-extra/test/clang-tidy/checkers/portability/no-assembler.cpp
+0-12clang-tools-extra/test/clang-tidy/checkers/hicpp/no-assembler.cpp
+79-798 files not shown
+110-8814 files

LLVM/project 7f6ada9 — llvm/include/llvm/ExecutionEngine/Orc WaitingOnGraph.h

by Lang Hames on ⎇
[ORC] Move WaitingOnGraph::hoistDeps into SuperNode. NFCI.

This simplifies the extraction of ModifiedPendingSNs at the start of the emit
function.
DeltaFile
+73-73llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraph.h
+73-731 files