LLVM/project 2680ba1clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp, clang/test/CIR/CodeGen new-delete-deactivation.cpp new-delete.cpp

[CIR] Match OGCG noalias and memory effects on operator new

Sane replaceable operator new calls now get return noalias and
memory(inaccessiblemem: readwrite, errnomem: write), matching classic
codegen. -fno-assume-sane-operator-new drops both.
DeltaFile
+44-44clang/test/CIR/CodeGen/new.cpp
+19-19clang/test/CIR/CodeGenCXX/new-array-init.cpp
+24-0clang/test/CIR/CodeGen/operator-new-noalias.cpp
+22-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+8-8clang/test/CIR/CodeGen/new-delete.cpp
+6-6clang/test/CIR/CodeGen/new-delete-deactivation.cpp
+123-776 files not shown
+151-8912 files

LLVM/project 14aebabclang/lib/StaticAnalyzer/Core ExprEngineCXX.cpp, clang/test/Analysis dtor-array.cpp

[analyzer] Fix crash destructing element of a sugared array type

ExprEngine::makeElementRegion falls short trying to determine the
element type of an array that involves a type aliasing a static array
type.

This leads to a crash in ExprEngine::ProcessMemberDtor where it assumes
that element type is a CXXRecordDecl, while it is still a type alias to
a static array type.

getBaseElementType is the canonical way to desugar and peel off the
array dimensions.

Assisted by Claude Opus 5

--
CPP-8838
DeltaFile
+2-6clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
+7-0clang/test/Analysis/dtor-array.cpp
+9-62 files

LLVM/project 4a41d7fclang/lib/CIR/CodeGen CIRGenCall.cpp, clang/test/CIR/CodeGen restrict-noalias.c

[CIR] Add noalias on malloc-like function returns

Mirror classic RestrictAttr handling so __attribute__((malloc)) and
__declspec(restrict) stamp llvm.noalias on the return, matching OGCG.
DeltaFile
+59-3clang/test/CIR/CodeGen/restrict-noalias.c
+9-3clang/lib/CIR/CodeGen/CIRGenCall.cpp
+68-62 files

LLVM/project d42b6eelibc/test/src/__support tlsf_table_test.cpp

fix test
DeltaFile
+4-5libc/test/src/__support/tlsf_table_test.cpp
+4-51 files

LLVM/project a4dd355llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp, mlir/test/Target/LLVMIR openmp-reduction-debug-loc.mlir

[OMPIRBuilder] Restore the debug location after the reduction alloca (#221253)

`createReductions` emits the array of type-erased pointers to the
private reduction values in the alloca block, which means leaving the
current insertion point and coming back. The insertion point is
re-established but the debug location is not. Everything emitted
afterwards like the `__kmpc_reduce` and the matching __kmpc_end_reduce
inherits whatever the terminator happened to carry, which is usually
nothing. This could result in a verifier error if program is linked with
openmp runtime that has debug information.

Fix it by restoring the debug location along with the InsertPoint.
DeltaFile
+56-0mlir/test/Target/LLVMIR/openmp-reduction-debug-loc.mlir
+3-0llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+59-02 files

LLVM/project 0d98376libc/src/__support tlsf_table.h

[libc] default NUM_TABLE_ENTRIES to a fixed value of 3

6 (192 entries) is too large for 32-bit devices and can cause shift overflow.
DeltaFile
+1-1libc/src/__support/tlsf_table.h
+1-11 files

LLVM/project f9a8decllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV and-negpow2-cmp.ll

[RISCV] Fix infinite DAGCombine loop with SETCC and SIGN_EXTEND_INREG (#221593)

We generalized (X & -(1 << C1) & 0xffffffff) == C2 << C1 using `sraiw`.
The combine generates a `SIGN_EXTEND_INREG` when simplifying.

However, when C1 is 0 and the sign bit (bit 31) of X is already known to
be zero, `DAGCombiner` sees that `SIGN_EXTEND_INREG` is semantically
equivalent to `AND X, 0xFFFFFFFF` (zext). Because `DAGCombiner`
considers `AND` to be more canonical than `SIGN_EXTEND_INREG` in this
context, it immediately reverts the node back to `AND`.

This caused an infinite DAGCombine loop. This patch disables the folding
when the C1 is zero. That case is covered by a later combine that already
checks if bit 31 is known to be zero.

Fixes: https://github.com/llvm/llvm-project/issues/221521
DeltaFile
+34-0llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+35-12 files

LLVM/project c70b9c0llvm/lib/Target/AMDGPU SIISelLowering.h AMDGPUISelLowering.h, llvm/test/CodeGen/AMDGPU frexp-inf-nan-combine.ll

[AMDGPU] Fold redundant inf/nan checks into frexp instructions (#214936)

Fixes #204204

The AMDGPU "v_frexp_exp" and "v_frexp_mant" instructions return 0 for
inf/nan inputs. This patch adds a DAG combine
("performFrexpSelectCombine") to fold redundant inf/nan checks with
frexp results, eliminating unnecessary compare and select instructions..

### Patterns folded:
  - `select (fcmp uno x, 0), 0, (frexp_exp x)` → `frexp_exp x`
  - `select (fcmp oeq |x|, inf), 0, (frexp_exp x)` → `frexp_exp x`
  - `select (fcmp ueq |x|, inf), 0, (frexp_exp x)` → `frexp_exp x`
  - `select (fcmp ord x, 0), (frexp_exp x), 0` → `frexp_exp x`
  - `select (fcmp one |x|, inf), (frexp_exp x), 0` → `frexp_exp x`
  - `select (is_fpclass x, finite), (frexp_exp x), 0` → `frexp_exp x`
  - Same patterns with `frexp_mant`

The optimization is disabled on SI (Southern Islands) which has

    [21 lines not shown]
DeltaFile
+148-253llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
+123-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-10llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+9-0llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+1-0llvm/lib/Target/AMDGPU/SIISelLowering.h
+281-2635 files

LLVM/project 7297a1ellvm/lib/Target/XCore/Disassembler CMakeLists.txt

Fix unresolved symbol XCoreMCRegisterClassStorage (#211420)

Fix for #211419

Add missing dependency to XCoreDisAssembler's CMakeLists.txt file
DeltaFile
+1-0llvm/lib/Target/XCore/Disassembler/CMakeLists.txt
+1-01 files

LLVM/project 2bd2609clang/test/CodeGen/AArch64/sve dup.c, clang/test/OpenMP parallel_for_codegen.cpp

Rebase

Created using spr 1.3.7
DeltaFile
+1,049-1,049clang/test/OpenMP/parallel_for_codegen.cpp
+892-872llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
+815-635llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+546-687llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+488-475llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
+824-0clang/test/CodeGen/AArch64/sve/dup.c
+4,614-3,718480 files not shown
+18,845-10,862486 files

LLVM/project d7b6632compiler-rt/lib/builtins comparedf2.cpp

if defined -> ifdef
DeltaFile
+4-3compiler-rt/lib/builtins/comparedf2.cpp
+4-31 files

LLVM/project 2060d76compiler-rt/lib/builtins comparedf2.cpp, libc/shared/builtins gedf2.h ledf2.h

[compiler-rt][builtins] libc-backed double-float comparison builtins
DeltaFile
+54-0compiler-rt/lib/builtins/comparedf2.cpp
+30-0libc/src/__support/builtins/gedf2.h
+30-0libc/src/__support/builtins/ledf2.h
+30-0libc/src/__support/builtins/unorddf2.h
+29-0libc/shared/builtins/gedf2.h
+29-0libc/shared/builtins/ledf2.h
+202-06 files not shown
+266-412 files

LLVM/project 41359e7clang/test/CodeGen/AArch64/sve dup.c, clang/test/OpenMP parallel_for_codegen.cpp

Rebase

Created using spr 1.3.7
DeltaFile
+1,049-1,049clang/test/OpenMP/parallel_for_codegen.cpp
+892-872llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
+839-654llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+546-687llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+488-475llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
+824-0clang/test/CodeGen/AArch64/sve/dup.c
+4,638-3,737478 files not shown
+18,852-10,873484 files

LLVM/project 0c553f5llvm/lib/Transforms/InstCombine InstCombineCasts.cpp, llvm/test/Transforms/InstCombine trunc.ll

[InstCombine] Use common flags for shl in shl/trunc fold. (#221769)

As pointed out post-commit in
https://github.com/llvm/llvm-project/pull/219443, whether the flags from
the trunc can be transferred directly to the shl depends on the involved
types: https://alive2.llvm.org/ce/z/zN_TFq

For now, just use the common flags.

PR: https://github.com/llvm/llvm-project/pull/221769
DeltaFile
+14-3llvm/test/Transforms/InstCombine/trunc.ll
+3-5llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+17-82 files

LLVM/project bceb55alibc/src/__support/builtins CMakeLists.txt

fix
DeltaFile
+18-10libc/src/__support/builtins/CMakeLists.txt
+18-101 files

LLVM/project 6a6f476libc/src/__support/builtins CMakeLists.txt

fix conflict
DeltaFile
+2-0libc/src/__support/builtins/CMakeLists.txt
+2-01 files

LLVM/project 42ff8cfcompiler-rt/lib/builtins comparesf2.cpp, libc/shared/builtins lesf2.h unordsf2.h

[compiler-rt][builtins] libc-backed single-float comparison builtins
DeltaFile
+54-0compiler-rt/lib/builtins/comparesf2.cpp
+30-0libc/src/__support/builtins/unordsf2.h
+30-0libc/src/__support/builtins/lesf2.h
+30-0libc/src/__support/builtins/gesf2.h
+29-0libc/shared/builtins/lesf2.h
+29-0libc/shared/builtins/unordsf2.h
+202-06 files not shown
+270-012 files

LLVM/project 783dd9doffload/liboffload/API Memory.td, offload/liboffload/src OffloadImpl.cpp

[offload][omp] Manage memory allocation through liboffload

Migrate DeviceTy::allocData/deleteData off GenericPluginTy::data_alloc/
data_delete onto liboffload's olMemAlloc*/olMemFree, migrate
targetLockExplicit/targetUnlockExplicit off data_lock/data_unlock onto
olMemRegister/olMemUnregister (fixing a latent bug where these passed
the OpenMP-visible device number instead of the plugin device id), and
migrate DeviceTy::isAccessiblePtr onto a new olMemIsAccessible API
(added with a unit test) since liboffload had no equivalent for
querying accessibility of arbitrary, not-necessarily-liboffload-
allocated pointers. Removes the now-dead GenericPluginTy::data_alloc/
data_delete/data_lock/data_unlock/is_accessible_ptr wrappers and their
exports entries.
DeltaFile
+44-0offload/unittests/OffloadAPI/memory/olMemIsAccessible.cpp
+0-16offload/plugins-nextgen/common/src/PluginInterface.cpp
+15-0offload/liboffload/API/Memory.td
+14-0offload/liboffload/src/OffloadImpl.cpp
+6-1offload/libompaccsupport/device.cpp
+2-1offload/unittests/OffloadAPI/CMakeLists.txt
+81-182 files not shown
+81-228 files

LLVM/project 809c089clang/test/OpenMP parallel_for_codegen.cpp, libc/utils cmake_format.py

Rebase

Created using spr 1.3.7
DeltaFile
+1,004-1,744llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
+1,049-1,049clang/test/OpenMP/parallel_for_codegen.cpp
+892-872llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
+957-735llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1,534-0libc/utils/cmake_format.py
+642-878llvm/test/CodeGen/X86/clmul-vector.ll
+6,078-5,2781,069 files not shown
+44,955-29,7721,075 files

LLVM/project 77208d8clang/test/OpenMP parallel_for_codegen.cpp, libc/utils cmake_format.py

Rebase

Created using spr 1.3.7
DeltaFile
+1,004-1,744llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
+1,049-1,049clang/test/OpenMP/parallel_for_codegen.cpp
+892-872llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
+889-668llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1,534-0libc/utils/cmake_format.py
+642-878llvm/test/CodeGen/X86/clmul-vector.ll
+6,010-5,2111,218 files not shown
+51,212-30,5001,224 files

LLVM/project cc4c418clang/test/OpenMP interchange_codegen.cpp, llvm/lib/Target/Hexagon HexagonDepMask.h

Rebase

Created using spr 1.3.7
DeltaFile
+17,282-3,458llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-sve-instructions.s
+7,983-1,591llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-neon-instructions.s
+1,750-2,445clang/test/OpenMP/interchange_codegen.cpp
+3,312-825llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+2,226-1,164llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+0-2,819llvm/lib/Target/Hexagon/HexagonDepMask.h
+32,553-12,3023,830 files not shown
+203,703-95,7613,836 files

LLVM/project 3e149a5llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-merge-readanylane.mir regbankcombiner-smed3.mir

comments
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
+5-53 files

LLVM/project 54b2840llvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-smed3.mir regbankcombiner-clamp-fmed3-const.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankCombiner" to NPM
DeltaFile
+81-32llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+13-2llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+101-381 files not shown
+102-387 files

LLVM/project f98f858llvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui.mir regbankselect-load.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM
DeltaFile
+50-17llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+21-3llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+3-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+1-1llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+78-231 files not shown
+79-237 files

LLVM/project 809dee0llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPU.h

comments
DeltaFile
+18-25llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+3-3llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+23-303 files

LLVM/project 69abec4clang/test/OpenMP interchange_codegen.cpp, llvm/lib/Target/Hexagon HexagonDepMask.h

Rebase

Created using spr 1.3.7
DeltaFile
+17,282-3,458llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-sve-instructions.s
+7,983-1,591llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-neon-instructions.s
+1,750-2,445clang/test/OpenMP/interchange_codegen.cpp
+3,312-825llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+2,226-1,164llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+0-2,819llvm/lib/Target/Hexagon/HexagonDepMask.h
+32,553-12,3023,573 files not shown
+193,950-93,7293,579 files

LLVM/project 271af38llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPUPassRegistry.def, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui-regbankselect.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankSelect" to NPM (#217321)

Assisted-by: Opus-4.8
DeltaFile
+43-15llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+18-3llvm/lib/Target/AMDGPU/AMDGPU.h
+3-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
+67-225 files

LLVM/project b1a72e3utils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Fixes e92c19a (#221761)

This fixes e92c19abae25beb03234bfbf6cfa1a431c6d380a (#221236).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=e92c19abae25beb03234bfbf6cfa1a431c6d380a

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+5-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+5-01 files

LLVM/project c5fc983llvm/test/CodeGen/X86 pr1505b.ll

[X86] pr1505b.ll - regenerate test checks (#221774)
DeltaFile
+39-17llvm/test/CodeGen/X86/pr1505b.ll
+39-171 files

LLVM/project ead188allvm/lib/Target/AArch64 AArch64.td AArch64ValidateRetiredNames.td, llvm/test/TableGen aarch64-retired-names.td

[AArch64] Prevent reuse of retired architecture names

Add explicit lists of retired AArch64 feature and system register names,
with TableGen validation preventing future definitions from reusing them.

This preserves names previously exposed by LLVM after their architectural
features or registers have been withdrawn or removed. Add coverage for
target features, architecture extension names and aliases, architectural
FEAT_* names, and system registers.
DeltaFile
+43-0llvm/test/TableGen/aarch64-retired-names.td
+37-0llvm/lib/Target/AArch64/AArch64ValidateRetiredNames.td
+12-0llvm/lib/Target/AArch64/AArch64.td
+92-03 files