LLVM/project 44c4c02llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-sext.ll

[X86] Move PSHUF(SHIFT(X,C0),C1) -> SHIFT(PSHUF(X,C1),C0) to canonicalizeShuffleWithOp (#225313)

No need for this to be in combineTargetShuffle, and we can generalize it
to work with more shuffles in a future patch.
DeltaFile
+42-38llvm/lib/Target/X86/X86ISelLowering.cpp
+2-2llvm/test/CodeGen/X86/vector-sext.ll
+44-402 files

LLVM/project 2ccc678llvm/lib/Target/AArch64 AArch64A53Fix835769.cpp, llvm/test/CodeGen/AArch64 aarch64-fix-cortex-a53-835769-debug.ll

[AArch64] Fix position of nop inserted for +fix-cortex-a53-835769 under debug. (#224830)

Make sure that the position of the nop added for +fix-cortex-a53-835769
is not dependant on debug instructions at the start of the block.

Fixes #224661
DeltaFile
+56-0llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769-debug.ll
+1-1llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
+57-12 files

LLVM/project 1833848clang/lib/Interpreter Interpreter.cpp Wasm.cpp

[clang-repl] Support wasm64 execution (#225311)

Emscripten-forge is adding wasm64 builds on its emscripten 6-x branch
which exposed two wasm32 hardcoded assumptions in clang-repl's
WebAssembly execution path.

`IncrementalCompilerBuilder::CreateCpp()` currently hardcodes
`wasm32-unknown-emscripten`, even when clang-repl itself is built for
wasm64.

Once Clang emits a wasm64 object, the in-process linker must also select
the correct emulation. `wasm-ld` defaults to wasm32 and otherwise fails
in `InputFile::checkArch()` with:

```text
must specify -mwasm64 to process wasm64 object files
```

The pipeline is this 

    [12 lines not shown]
DeltaFile
+3-2clang/lib/Interpreter/Interpreter.cpp
+5-0clang/lib/Interpreter/Wasm.cpp
+8-22 files

LLVM/project 999b8c4orc-rt/test/regression lit.cfg.py, orc-rt/test/regression/darwin check-rt-process-info.test

[orc-rt] Make check-rt-process-info.test test more generic. (#225314)

Add %host-arch and %host-os substitutions to orc-rt-lit's config, and
use them to make the regression test platform agnostic.
DeltaFile
+7-0orc-rt/test/regression/lit.cfg.py
+0-6orc-rt/test/regression/darwin/check-rt-process-info.test
+7-62 files

LLVM/project 3a4d8a9clang/lib/CodeGen CGBuilder.h CGExpr.cpp, clang/test/CodeGenCXX strict-vtable-pointers.cpp

[Clang] Stop using strip.invariant.group (#225072)

Clang currently emits calls to llvm.strip.invariant.group under
`-fstrict-vtable-pointers` whenever a pointer to a dynamic object is
used in a comparison or might be used in a comparison through operations
we cannot track.

The purpose of the llvm.strip.invariant.group intrinsic is to make sure
that if we have a dominating condition like `a ==
launder.invariant.group(a)`, we don't end up replacing the latter with
the former, as that would allow the optimizer to assume that the memory
stays invariant, despite going through a launder operation (e.g. on
placement new).

However, since this was introduced, we've come to the understanding that
replacing pointers based on equality comparison is generally only legal
if they have the same provenance, and stopped doing such replacements.
The specific strip.invariant.group/launder.invariant.group case was
still buggy due to an implementation bug, but this was fixed in

    [4 lines not shown]
DeltaFile
+13-33clang/test/CodeGenCXX/strict-vtable-pointers.cpp
+2-37clang/lib/CodeGen/CGExprScalar.cpp
+0-12clang/lib/CodeGen/CGExpr.cpp
+0-6clang/lib/CodeGen/CGBuilder.h
+15-884 files

LLVM/project 167761dllvm/lib/Transforms/Utils LowerVectorIntrinsics.cpp, llvm/utils profcheck-xfail.txt

[CodeGen][ProfCheck] Mark scalable intrinsic expansion loop with unknown weights (#225050)
DeltaFile
+0-4llvm/utils/profcheck-xfail.txt
+3-1llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
+3-52 files

LLVM/project 7bc7f2bllvm/include/llvm/ABI TargetInfo.h, llvm/lib/ABI DefaultTargetInfo.cpp TargetInfo.cpp

[llvm][ABI] Make the _BitInt register threshold target-driven
DeltaFile
+121-4llvm/unittests/ABI/TargetInfoTest.cpp
+4-39llvm/lib/ABI/TargetInfo.cpp
+9-8llvm/include/llvm/ABI/TargetInfo.h
+6-4llvm/lib/ABI/DefaultTargetInfo.cpp
+140-554 files

LLVM/project e8c46bbllvm/lib/Target/PISA PISAPostLegalizerCombiner.cpp PISACombine.td

Replace /// with //
DeltaFile
+11-11llvm/lib/Target/PISA/PISAPreLegalizerCombiner.cpp
+1-1llvm/lib/Target/PISA/PISAPostLegalizerCombiner.cpp
+1-1llvm/lib/Target/PISA/PISACombine.td
+13-133 files

LLVM/project e10ed7bflang/lib/Semantics resolve-names.cpp, flang/test/Semantics/CUDA cuda-pinned-implicit-modfile.cuf

[flang][cuda] Record implicit pinned attribution in module files

Under -gpu=mem:pinned an unattributed ALLOCATABLE is attributed as pinned by
the compiler, the same way -gpu=mem:managed attributes one as managed, but
only the latter recorded that it had done so. The module file therefore spelled
an implicitly applied PINNED the same as one the user wrote, and a reader
treated it as a user requirement: adding -gpu=mem:pinned to a module's build
rejected its OpenACC-only consumers over an attribute the user never wrote.

Record the attribution for pinned as well, so it is written as
PINNED(IMPLICIT) and consumers can tell the two apart.
DeltaFile
+42-0flang/test/Semantics/CUDA/cuda-pinned-implicit-modfile.cuf
+3-1flang/lib/Semantics/resolve-names.cpp
+45-12 files

LLVM/project 2dacc78flang/docs ModFiles.md, flang/include/flang/Support Fortran-features.h

[flang][cuda] Restrict the MANAGED(IMPLICIT) spelling to module files
DeltaFile
+22-1flang/docs/ModFiles.md
+14-0flang/test/Semantics/CUDA/cuda-managed-implicit-modfile.cuf
+4-3flang/include/flang/Support/Fortran-features.h
+3-2flang/lib/Parser/Fortran-parsers.cpp
+4-0flang/lib/Semantics/mod-file.cpp
+3-0flang/lib/Support/Fortran-features.cpp
+50-66 files

LLVM/project 6c50c03flang/include/flang/Parser parse-tree.h, flang/lib/Parser unparse.cpp Fortran-parsers.cpp

[flang][cuda] Record implicit managed attribution in module files

An attribute the compiler applied under -gpu=mem:managed is written into the
module file the same way a user-written one is, so a reader cannot tell them
apart. It then treats the attribute as a user requirement: allocating such a
component in a DEVICE object is rejected, and the memory space the user did
ask for on the object no longer wins.

Spell the distinction in the module file as MANAGED(IMPLICIT), modelled on
INTENT(IN): CUDA-data-attr gains an optional parenthesized qualifier, carried
by a new CUDADataAttrSpec parse-tree node in AttrSpec and ComponentAttrSpec.
ATTRIBUTES(...) keeps the bare attribute, so the qualifier cannot be written
there.

The attribute itself is still written out, so a component keeps the same
memory space no matter which options a consumer is compiled with.

Also stop an implicitly applied attribute from making a module a definer of
CUDA symbols. Without this, adding -gpu=mem:managed to a module's build
rejects its OpenACC-only consumers over an attribute the user never wrote.
DeltaFile
+76-0flang/test/Semantics/CUDA/cuda-managed-implicit-modfile.cuf
+29-9flang/lib/Semantics/resolve-names.cpp
+19-3flang/lib/Semantics/mod-file.cpp
+13-2flang/include/flang/Parser/parse-tree.h
+10-2flang/lib/Parser/Fortran-parsers.cpp
+6-0flang/lib/Parser/unparse.cpp
+153-162 files not shown
+159-188 files

LLVM/project 9f58887llvm/lib/Target/PISA PISALegalizerInfo.cpp

Replace llvm_unreachable with reportFatalUsageError
DeltaFile
+2-1llvm/lib/Target/PISA/PISALegalizerInfo.cpp
+2-11 files

LLVM/project bb5dcd5llvm/include/llvm/ABI DefaultTargetInfo.h, llvm/lib/ABI CMakeLists.txt DefaultTargetInfo.cpp

Create DefaultTargetInfo class
DeltaFile
+60-0llvm/lib/ABI/DefaultTargetInfo.cpp
+38-0llvm/include/llvm/ABI/DefaultTargetInfo.h
+10-12llvm/unittests/ABI/TargetInfoTest.cpp
+1-0llvm/lib/ABI/CMakeLists.txt
+109-124 files

LLVM/project 9517d71llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/AArch64 sve-low-trip-count-ic-3.ll low-trip-count-body-size-limit.ll

[LoopVectorize] Improve Vectorization of Low Trip Count Loops (#195823)

Currently, Small Loops with Trip Counts less than 16, and in situations
where the Trip Count (TC) is less than the Tail Folding Threshold are
harder to vectorize, its only possible where no epilogue will be
emitted. However, for loops with large bodies and small trip counts this
can be counterproductive to performance, often failing to vectorize
entirely. This is more prevalent with targets where
`getMinTripCountTailFoldingThreshold()` returns a value greater than 0.

To address this, the Small Loops where the TC == VF + 1 can now
vectorize, leading to a vectorized iteration (or loop if interleaving is
required) and a single scalar iteration. Later passes can then remove
the loop's entirely.

Testing an with OpenSource Fortran HPC Benchmark which includes multiple
loops with small trip counts, but large loop bodies, has shown
significant improvement to runtime after these changes.

Assisted-by: Claude Sonnet 4.6/Codex
DeltaFile
+562-30llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
+125-0llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-body-size-limit.ll
+123-0llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count-body-size-limit.ll
+111-0llvm/test/Transforms/LoopVectorize/RISCV/small-trip-count-vf-plus-one.ll
+47-0llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count-ic-3.ll
+46-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1,014-306 files

LLVM/project 24088afllvm/lib/ABI TargetInfo.cpp, llvm/unittests/ABI TargetInfoTest.cpp

update
DeltaFile
+0-105llvm/unittests/ABI/TargetInfoTest.cpp
+3-3llvm/lib/ABI/TargetInfo.cpp
+3-1082 files

LLVM/project 85ae9c1llvm/include/llvm/ABI TargetInfo.h, llvm/lib/ABI TargetInfo.cpp

[ABI] Add default argument/return classifiers to TargetInfo
DeltaFile
+129-0llvm/unittests/ABI/TargetInfoTest.cpp
+39-0llvm/lib/ABI/TargetInfo.cpp
+8-0llvm/include/llvm/ABI/TargetInfo.h
+176-03 files

LLVM/project b65e290llvm/lib/Target/ARM ARMISelLowering.cpp, llvm/test/CodeGen/Thumb2 mve-vctp.ll

[ARM] Fix swapped condition in PerformVSetCCToVCTPCombine. (#225112)

This was swapping the wrong condition to a SETUGT. Came up in #224857.

Also remove vctp64 as we cannot fold 64bit integers to vctp.
DeltaFile
+69-25llvm/test/CodeGen/Thumb2/mve-vctp.ll
+1-4llvm/lib/Target/ARM/ARMISelLowering.cpp
+70-292 files

LLVM/project e9ad356llvm/lib/Target/PISA PISALegalizerInfo.cpp

Rename legalizeGLoad to legalizeGLoadStore (it handles both loads and stores)
DeltaFile
+3-3llvm/lib/Target/PISA/PISALegalizerInfo.cpp
+3-31 files

LLVM/project 0c53ebfllvm/include/llvm/ABI TargetInfo.h, llvm/lib/ABI TargetInfo.cpp DefaultTargetInfo.cpp

[llvm][ABI] Make the _BitInt register threshold target-driven
DeltaFile
+29-1llvm/unittests/ABI/TargetInfoTest.cpp
+6-4llvm/lib/ABI/DefaultTargetInfo.cpp
+9-0llvm/include/llvm/ABI/TargetInfo.h
+4-0llvm/lib/ABI/TargetInfo.cpp
+48-54 files

LLVM/project 38001a2llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.dot.ll

[AMDGPU][InstCombine] Canonicalize dot constant operands

Move constant dot product source operands to the right hand side
and add tests for signed and unsigned dot intrinsics.
DeltaFile
+12-12llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
+9-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+21-122 files

LLVM/project 6f511callvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.dot.ll

[AMDGPU][InstCombine] Fold zero dot operands to accumulator

Fold AMDGPU dot intrinsics when either operand is zero.

`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
DeltaFile
+15-30llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
+3-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+18-302 files

LLVM/project d1af1cbllvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.dot.ll

[AMDGPU][InstCombine] Fold constant add/sub into the dot accumulator

`amdgcn.{s,u}dot{2,4,8}(a, b, C) +/- K -> dot(a, b, C +/- K)` when both the
accumulator C and K are constants. The new constant is computed with
wrapping APInt arithmetic to match the non-clamping accumulate.

Only applies when clamp is false (the saturating accumulate does not
reassociate) and the dot has a single use. K - dot is left alone since it
would need the dot product negated.
DeltaFile
+33-66llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
+38-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+71-662 files

LLVM/project ff7cdcallvm/lib/Target/PISA PISACallLowering.cpp

Replace assert with reportFatalUsageError
DeltaFile
+3-2llvm/lib/Target/PISA/PISACallLowering.cpp
+3-21 files

LLVM/project 851a76fllvm/docs AMDGPUMemoryModel.md AMDGPUUsage.rst

[AMDGPU][docs] Describe cluster broadcast using async loads

Assisted-By: AI Coding Assistant
DeltaFile
+46-3llvm/docs/AMDGPUDMAOperations.md
+46-0llvm/docs/AMDGPUUsage.rst
+1-1llvm/docs/AMDGPUMemoryModel.md
+93-43 files

LLVM/project 67f4a07cmake/Modules LLVMVersion.cmake, libcxx/include __config

Bump version to 23.1.3
DeltaFile
+1-1llvm/utils/mlgo-utils/mlgo/__init__.py
+1-1llvm/utils/lit/lit/__init__.py
+1-1llvm/utils/gn/secondary/llvm/version.gni
+1-1libcxx/include/__config
+1-1cmake/Modules/LLVMVersion.cmake
+5-55 files

LLVM/project 1899433llvm/lib/Target/PISA PISACallLowering.cpp

Use LLT::scalarOrVector
DeltaFile
+1-1llvm/lib/Target/PISA/PISACallLowering.cpp
+1-11 files

LLVM/project d2d2885clang-tools-extra/clang-tidy/readability SimplifyBooleanExprCheck.cpp, clang-tools-extra/docs ReleaseNotes.md

[clang-tidy] Fix De Morgan for overloaded comparisons (#221432)

Before my patch:


(https://source.chromium.org/chromium/chromium/src/+/main:base/trace_event/memory_allocator_dump.cc;l=174)

```diff
-  if (!(name == rhs.name && units == rhs.units &&
-        entry_type == rhs.entry_type)) {
+  if (!name == rhs.name || !units == rhs.units ||
+        entry_type != rhs.entry_type) {
```

With the patch:

```diff
-  if (!(name == rhs.name && units == rhs.units &&
-        entry_type == rhs.entry_type)) {

    [4 lines not shown]
DeltaFile
+57-0clang-tools-extra/test/clang-tidy/checkers/readability/simplify-boolean-expr-demorgan.cpp
+23-0clang-tools-extra/clang-tidy/readability/SimplifyBooleanExprCheck.cpp
+5-1clang-tools-extra/docs/ReleaseNotes.md
+85-13 files

LLVM/project 20b4d70flang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics openmp-utils.cpp check-omp-variant.cpp

Share construct contexts for variant reachability

Use AppendDirectiveContextTraits when building reachable directive paths
so semantic checks and lowering apply the same construct-context rules.
This excludes informational directives such as ASSUME while retaining
executable loop transformations and the source order of combined constructs.

Make AppendConstructTraitsForDirective private again and add semantic
tests for TILE, UNROLL, ASSUME, and TEAMS DISTRIBUTE PARALLEL DO. These
complement the existing lowering tests. The ASSUME case detects the old
collector counting an extra position and skipping a required diagnostic.
DeltaFile
+71-0flang/test/Semantics/OpenMP/metadirective-construct-paths.f90
+2-23flang/lib/Semantics/check-omp-variant.cpp
+0-5flang/include/flang/Semantics/openmp-utils.h
+1-1flang/lib/Semantics/openmp-utils.cpp
+2-0flang/test/Driver/bbc-openmp-target-context.f90
+76-295 files

LLVM/project d2df6a0llvm/test/CodeGen/PISA/GlobalISel prelegalizer-zext-and.mir legalizer-mulh-i64.mir

Remove IR sections from MIR tests
DeltaFile
+0-13llvm/test/CodeGen/PISA/GlobalISel/postlegalizer-compare-select.mir
+1-11llvm/test/CodeGen/PISA/GlobalISel/build-vector-with-constants-trunc-double.mir
+0-11llvm/test/CodeGen/PISA/GlobalISel/legalizer-extract-vector-elt-illegal-size.mir
+0-9llvm/test/CodeGen/PISA/GlobalISel/prelegalizer-zext-and.mir
+0-9llvm/test/CodeGen/PISA/GlobalISel/legalizer-mulh-i64.mir
+0-9llvm/test/CodeGen/PISA/GlobalISel/combine-select-trunc-one-zero.mir
+1-627 files not shown
+1-10813 files

LLVM/project d357463llvm/lib/Target/RISCV RISCVAsmPrinter.cpp, llvm/test/CodeGen/RISCV module-asm-features.ll riscv-func-target-feature.ll

[RISC-V] Update streamer ArchString in emitTargetFeaturePush()

Previously, RISCVAsmPrinter::emitTargetFeaturePush() only emitted `.option push`
and `.option arch` without updating the streamer's active ArchString. When
emitting an ELF object file directly (`-filetype=obj`),
RISCVTargetELFStreamer::emitDirectiveOptionArch() is a no-op while
emitTargetFeaturePop() resets ArchString back to the pushed ArchString, so
module-level inline assembly and functions with custom `target-features` failed
to emit updated `$x<arch>` mapping symbols.

Call RTS.setArchString() with the parsed ISA string in emitTargetFeaturePush()
so `-filetype=obj` records the active `$x<arch>` mapping symbol alongside
`.option arch`.

This commit was created with the help of AI tools
DeltaFile
+2-5llvm/test/CodeGen/RISCV/module-asm-features.ll
+4-3llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
+2-0llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+8-83 files