[AMDGPU] Save entry EXEC in whole-wave prologue with no WWM spills (#207924)
PR #207781 replaced the prologue S_XOR_SAVEEXEC (which set EXEC to
~entryEXEC) with a plain S_MOV EXEC, -1, but dropped the save of the
entry EXEC that the return restores from, leaving an undefined register
read
se S_OR_SAVEEXEC to both save entry EXEC and set EXEC to -1
[AArch64] llvm-mca C1-Ultra tests: SVE instructions added by SME when not streaming [NFC] (#207948)
In the C1-Ultra llvm-mca test, moves some instructions that were
incorrectly in the test file for "Instructions available with no SME but
will be sent to CME when in streaming SVE mode" into a file specifically
for instruction that are "SVE instructions added by SME and available
when not in Streaming SVE mode".
This is in preparation for forthcoming C1-Nano SME support to the
scheduling model that currently has no information about these
instruction due to lack of information in the C1-Nano SWOG.
This change is currently NFC because the C1-Ultra is still running the
the same tests, just from different test files.
AMDGPU: Migrate unittests to subarch triples
Replace specifying a processor name with the triple
subarch.
The register-limit helpers in AMDGPUUnitTests.cpp that enumerate every
valid CPU via fillValidArchListAMDGCN still pass the CPU explicitly, as
does the MC Disassembler smoke test (its C disassembler API derives the
subtarget from the CPU, not the triple subarch).
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang: Start using new amdgpu subarch triples
Fixup invocations using --target=amdgcn + -mcpu to introduce
the subarch in the triple.
For offload toolchains, a single toolchain is constructed for the
top level amdgpu architecture, and the effective triple is used for
target specific tool invocations.
The specifics of the resource directory layout are tbd. This does
try to find resources in the subarch named directory. The paths
are searched at toolchain creation time, so that does not work
when there are multiple subarches.
Fixes #154925
clang/AMDGPU: Validate -target-cpu in cc1 is valid for the subarch
Restrict the reported list of valid target-cpus based on the triple's
subarch. This is more consistent with how other targets validate the
target CPU name. Currently we have split handling validating the target
name for the triple in both the driver and here. The driver based diagnostic
seems to be an amdgpu-ism in 2 different places (though there is one arm
validation emitting the same diagnostic). In the future we could probably
drop those.
clang/AMDGPU: Stop passing redundant -target-cpu to cc1
Now that the exact target is encoded in the triple's subarch field,
-target-cpu is redundant. This avoids polluting the resultant IR with
unwanted "target-cpu" attributes. The net result is the desired codegen
when compiling libraries for a major subarch and linking it into a
program compiled for a specific arch. e.g., compiling for "gfx9-generic"
would pollute the IR with "target-cpu"="gfx9-generic", so codegen
would ultimately be performed for the generic target even after
linking into the concrete gfx9 cpu. The specialization will now be
achieved by merging the triples without the linker or optimization
passes needing to fixup function attributes.
AMDGPU: Introduce amdgpu triple arch
Move towards using the triple for representing incompatible
ISA changes. Use the subarch field to represent the various
incompatible cases. Previously we pretended a single triple arch
was universally compatible, and only distinguished by function
level subtargets. Move towards using distinct triples to enable
more sophisticated toolchain handling in the future, like proper
runtime library linking.
Introduce a new subarch per unique ISA, but also introduce
"major subarches" which are compatible by a set of covered
minor ISA versions. These map to the existing generic targets.
There are a few placeholder subarch entries, which currently
have missing backing generic arches for codegen.
This should be the preferred triple arch name going forward,
but is treated as an alias of amdgcn. This does not yet change
clang to emit the new triples.
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[LLE][LoopDistribution][LoopVersioning] Form LCSSA at Caller Invoking LoopVersioning Utility (#202296)
LoopVersioning utility `versionLoop()` expects the input form to be
LCSSA. However, passes like Loop distribution, Loop-load-elimination,
may invoke versioning with a non-LCSSA IR. Versioning updates exit-block
PHIs to handle both the original loop and the cloned loop. However, a
raw non-LCSSA use in the exit block (such as `switch i1 %C`) still
points to the original loop’s `%C`. On the cloned-loop path, control
reaches the exit block without executing the original `%C`, resulting in
error: `Instruction does not dominate all uses!`.
The fix is to form LCSSA at the caller pass.
[NFC][SPIRV] Use `StringRef` by value (no `const`, no `&`) (#207940)
A `StringRef` is non-modifiable and it acts as a reference, so there is
no need to declare it as `const` nor `&`.
---------
Co-authored-by: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
[lldb][Linux] Show si_addr for SIGBUS signals (#207718)
The general rule is if si_addr is the same as the PC, we don't show it
because it doesn't add any new information.
SIGBUS signals are caused by an instruction trying to do something, but
si_addr is not the address of the instruction. It's some virtual
address, which is the important bit so add it to the description.
https://man7.org/linux/man-pages/man7/signal.7.html
> SIGBUS <...> Bus error (bad memory access)
Before:
```
* thread #1, name = 'test.o', stop reason = signal SIGBUS: illegal address
* frame #0: 0x0000aaaaaaaa0b80 test.o`main at test.c:42:13
```
After:
```
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[libc] Add auxiliary vector and note macros to elf.h (#207914)
Added missing macros to elf.h:
* sys-auxv-macros.h: Added AT_RSEQ_FEATURE_SIZE and AT_RSEQ_ALIGN.
* elf.yaml: Added PT_AARCH64_MEMTAG_MTE, PN_XNUM, ELFCLASSNUM, EV_NUM,
and AT_* macros (via sys-auxv-macros.h). Also added NN_* and NT_* note
macros (including NT_FPREGSET and NT_SIGINFO) to match system headers.
* CMakeLists.txt: Added sys_auxv_macros dependency to elf target.
Assisted-by: Automated tooling, human reviewed.
[RISCV] Fix interleaved + strided costs for e64 elements on rv32 (#207927)
This is the same fix as #176105 for interleaved + strided memory op
costs.
We currently compute the cost of interleaved + strided ops as N *
scalar element memory ops, but on rv32 the scalar memory access will
be on an illegal type for 64 bit elements, even with zve64x. Prevent
it from overcosting by just using TCC_Basic.
[NFC][SPIRV] Correct misuses of `StringRef`
A `StringRef` is non-modifiable and it acts as a reference, so there is
no need to declare it as `const` or `&`.
