LLVM/project 19b40f7 — llvm/docs SPIRVUsage.rst, llvm/lib/Target/SPIRV SPIRVCommandLine.cpp SPIRVUtils.cpp

by Dmitry Sidorov via GitHub on ⎇
[SPIR-V] Add SPV_AMD_weak_linkage extension (#193307)

Spec is available here:
https://github.com/KhronosGroup/SPIRV-Registry/pull/401
DeltaFile
+31-0llvm/test/CodeGen/SPIRV/linkage/weak-linkage.ll
+3-1llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+4-0llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+2-0llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+2-0llvm/docs/SPIRVUsage.rst
+2-0llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+44-16 files

LLVM/project 4b44e20 — compiler-rt/test/fuzzer lit.cfg.py lit.site.cfg.py.in

by Vitaly Buka via GitHub on ⎇
[fuzzer] Set target_cflags instead of target_flags in lit config (#191510)

This PR fixes warning "Compiler lib dir != compiler-rt lib dir"

There is a check in compiler-rt/test/lit.common.cfg.py which detects
runtime dir using target_cflags.

If we set target_flags only, the test will complain as below:

The persistent from #111498, but I don't see anything wrong.

```
cmake -GNinja -DCMAKE_BUILD_TYPE=Release -DCMAKE_DISABLE_PRECOMPILE_HEADERS=ON -DLLVM_CCACHE_BUILD=ON  -DLLVM_ENABLE_ASSERTIONS=OFF '-DLLVM_ENABLE_PROJECTS='\''clang;lld'\''' '-DLLVM_ENABLE_RUNTIMES='\''compiler-rt;libunwind;libcxx;libcxxabi'\''' -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ ../../llvm-project/llvm

ninja check-compiler-rt
```

```
-- Installing: runtimes/runtimes-bins/compiler-rt/lib/tsan/libcxx_tsan_x86_64/lib/libc++.modules.json

    [20 lines not shown]
DeltaFile
+1-1compiler-rt/test/fuzzer/lit.cfg.py
+1-1compiler-rt/test/fuzzer/lit.site.cfg.py.in
+2-22 files

LLVM/project 083cab6 — llvm/test/Transforms/SLPVectorizer/RISCV basic-strided-stores.ll

by Ryan Buchner via GitHub on ⎇
[SLP] Precommit tests for strided store reordering (#193565)

Currently these tests generate incorrect vectorization because we try to re-order strided store
nodes in `reorderBottomToTop`.
DeltaFile
+98-0llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-stores.ll
+98-01 files

LLVM/project c09089d — libc/config/linux/x86_64 entrypoints.txt, libc/include elf.yaml

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+62-0libcxx/cmake/caches/Generic-llvm-libc.cmake
+27-0libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
+27-0libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
+20-0libcxx/utils/ci/run-buildbot
+6-0libc/include/elf.yaml
+3-0libc/config/linux/x86_64/entrypoints.txt
+145-06 files

LLVM/project ac5db03 — libc/config/linux/x86_64 entrypoints.txt, libcxx/cmake/caches Generic-llvm-libc.cmake

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+62-0libcxx/cmake/caches/Generic-llvm-libc.cmake
+27-0libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
+27-0libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
+20-0libcxx/utils/ci/run-buildbot
+3-0libc/config/linux/x86_64/entrypoints.txt
+139-05 files

LLVM/project ced532d — llvm/test/CodeGen/AArch64 hadd-combine.ll, llvm/test/CodeGen/RISCV/rvv vandn-vp.ll vxor-vp.ll

by gulfemsavrun via GitHub on ⎇
Merge branch 'main' into revert-193229-reapply-comdat-fix
DeltaFile
+897-327llvm/test/CodeGen/AArch64/hadd-combine.ll
+365-365llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+292-292llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+224-224llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+223-223llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+212-220llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
+2,213-1,65128 files not shown
+3,198-2,66834 files

LLVM/project e4e8bcb — llvm/test/CodeGen/RISCV/rvv vandn-vp.ll vxor-vp.ll

by Luke Lau via GitHub on ⎇
[RISCV] Expand vp.and, vp.or, vp.xor (#193542)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This expands 3 intrinsics from #179622. The codegen support is left in
for now as other parts in DAGCombiner/SelectionDAGBuilder can generate
these.
DeltaFile
+365-365llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+292-292llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+224-224llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+223-223llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+212-220llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
+163-173llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
+1,479-1,4977 files not shown
+1,721-1,75813 files

LLVM/project c23796d — libc/config/linux/x86_64 entrypoints.txt, libcxx/cmake/caches Generic-llvm-libc.cmake

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+62-0libcxx/cmake/caches/Generic-llvm-libc.cmake
+27-0libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
+27-0libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
+20-0libcxx/utils/ci/run-buildbot
+3-0libc/config/linux/x86_64/entrypoints.txt
+139-05 files

LLVM/project a15e3eb — libcxx/cmake/caches Generic-llvm-libc.cmake, libcxx/test/configs llvm-libc++-llvm-libc.cfg.in

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+62-0libcxx/cmake/caches/Generic-llvm-libc.cmake
+27-0libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
+27-0libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
+20-0libcxx/utils/ci/run-buildbot
+136-04 files

LLVM/project b515f0c — flang/include/flang/Lower PFTBuilder.h, flang/lib/Lower/OpenMP OpenMP.cpp

by Krzysztof Parzyszek on ⎇
[flang][OpenMP] Remove OmpEndLoopDiretive from PFT

It's no longer necessary. An end-directive for a loop construct used
to be a separate construct, but now it only exists as a member in
OpenMPLoopConstruct.
DeltaFile
+0-3flang/lib/Lower/OpenMP/OpenMP.cpp
+1-1flang/include/flang/Lower/PFTBuilder.h
+0-1flang/test/Lower/pre-fir-tree03.f90
+1-53 files

LLVM/project 7431a4f — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 non-schedulable-before-main.ll

by Alexey Bataev via GitHub on ⎇
[SLP]Fix dominance for multi-use copyable scalars in scheduled bundle

scheduleBlock skips copyable bundle members with their own ScheduleData,
leaving them at their original position. If such a scalar comes after
MainOp and satisfies doesNotNeedToBeScheduled, the vectorized op is
inserted at LastScheduledInst while the scalar stays behind, so the
insertelement feeding the copyable lane fails to be dominated by it.

After placing bundle members, move copyable scalars with more than one
use (same block as MainOp, doesNotNeedToBeScheduled, schedulable from
the tree entry's view) to just before LastScheduledInst.

Fixes #193513.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/193599
DeltaFile
+42-0llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-before-main.ll
+13-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+55-02 files

LLVM/project 24be43f — llvm/lib/Transforms/Vectorize VPlan.cpp, llvm/test/Transforms/LoopVectorize vector-loop-backedge-elimination-predicated-early-exit.ll

by Florian Hahn via GitHub on ⎇
[VPlan] Pick correct insert point after creating canonical IV. (#193587)

Retrieve (or create) the canonical IV increment before setting up the
VPBuilder insertion point at Header->begin(). getOrCreate may insert the
increment recipe into the Header, which would invalidate an insertion
point captured before the increment exists.

Fixes https://github.com/llvm/llvm-project/issues/193164.
DeltaFile
+54-0llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
+1-1llvm/lib/Transforms/Vectorize/VPlan.cpp
+55-12 files

LLVM/project 1bec68a — llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVTargetTransformInfo.h, llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abs-vp.ll

by Luke Lau via GitHub on ⎇
[RISCV] Remove codegen for vp_abs (#193533)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off vp_abs from #179622.
DeltaFile
+174-224llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+129-179llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+6-21llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+0-1llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+309-4254 files

LLVM/project dec3b1f — lldb/source/Plugins/Process/scripted ScriptedThread.cpp

by Med Ismail Bennani via GitHub on ⎇
[lldb] Fix empty backtraces for scripted threads with no artificial frames (#193387)

Following 86aa43999bec, `ScriptedThread::LoadArtificialStackFrames`
unconditionally calls `SetAllFramesFetched` even when the scripted
thread provided zero artificial stack frames via `get_stackframes`.

This prevents the normal unwinder from creating frames from the register
context, leaving `m_frames` empty. When GetFrameAtIndex(0) is
subsequently called, it triggered the follow on assertion builds:

```
  assert(!m_thread.IsValid() && "A valid thread has no frames.")
```

This affects scripted threads that provide register context via
`get_register_context` but rely on the unwinder for frame creation
rather than overriding `get_stackframes`.

This patch fixes the issue by returning early in

    [6 lines not shown]
DeltaFile
+5-0lldb/source/Plugins/Process/scripted/ScriptedThread.cpp
+5-01 files

LLVM/project ed2f5f4 — llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU rsq.f64.ll fdiv.f64.ll

by Matt Arsenault via GitHub on ⎇
AMDGPU: Skip last corrections in afn f64 reciprocal (#183696)

Device libs has a fast reciprocal macro that is close
to the fast division expansion, but skips the last terms
compared to the full division.

The basic reciprocal handling has identical output to this
macro. The negative reciprocal case has different fneg placement
and smaller code size, but I believe should be the same.
DeltaFile
+32-116llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+37-7llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+17-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+16-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-2llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
+0-4llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+114-1311 files not shown
+114-1337 files

LLVM/project 5df1430 — compiler-rt/test/fuzzer lit.cfg.py

by Vitaly Buka on ⎇
""

Created using spr 1.3.7
DeltaFile
+1-1compiler-rt/test/fuzzer/lit.cfg.py
+1-11 files

LLVM/project 59596d7 — llvm/test/CodeGen/AArch64 hadd-combine.ll

by David Green via GitHub on ⎇
[AArch64][GlobalISel] Add hadd-combine globalisel test coverage. NFC (#193591)
DeltaFile
+897-327llvm/test/CodeGen/AArch64/hadd-combine.ll
+897-3271 files

LLVM/project eec9f38 — llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

by Vitaly Buka on ⎇
fix libfuzzer

Created using spr 1.3.7
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-05,691 files not shown
+1,201,357-154,5385,697 files

LLVM/project 33ad3b4 — clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowAnalysis.cpp

by Ziqing Luo on ⎇
fix clang-format
DeltaFile
+4-2clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowAnalysis.cpp
+4-21 files

LLVM/project b9b472c — clang/test/SemaTemplate concepts-out-of-line-def.cpp

by Erich Keane via GitHub on ⎇
[NFC] Add check lines to concepts-out-of-line-def.cpp to fix failure (#193579)

Revert in #193558 failed to correct a test that was fixed in the
meantime, and was dependent on this. This patch adds a check-line to
make CI go green again.
DeltaFile
+5-1clang/test/SemaTemplate/concepts-out-of-line-def.cpp
+5-11 files

LLVM/project 968b8b0 — clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowAnalysis.cpp

by Ziqing Luo on ⎇
change 'result()' to 'getResult()'
DeltaFile
+5-5clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowAnalysis.cpp
+5-51 files

LLVM/project 031f4bc — llvm/include/llvm/Analysis TargetTransformInfoImpl.h, llvm/include/llvm/CodeGen BasicTTIImpl.h

by Michael Berg on ⎇
[LV][RISCV] Add explicit LMUL controls via computeFeasibleMaxVF

Add components of maxVF and its support for scalable
vectorization. The default for unspecified RISCV is
LMUL=4 with this change, so some tests will have
the flag that controls max LMUL to extend to LMUL=8
when the request is made.
DeltaFile
+32-0llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+7-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-3llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-maxbandwidth.ll
+5-0llvm/lib/Analysis/TargetTransformInfo.cpp
+5-0llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+5-0llvm/include/llvm/CodeGen/BasicTTIImpl.h
+57-34 files not shown
+65-510 files

LLVM/project 698dce1 — flang/lib/Optimizer/Builder IntrinsicCall.cpp, flang/test/Lower/Intrinsics transfer-unsigned.f90

by Zhen Wang via GitHub on ⎇
[flang] Fix inline transfer for unsigned integer types (#193570)

Fix a crash when transfer is used with Fortran unsigned types. The
arith.bitcast op requires signless integer or float operands, but the
inline optimization was applying it to unsigned integer types (ui32),
causing a verification failure. Changed the guard from
mlir::isa<mlir::IntegerType> to isSignlessIntOrFloat() so unsigned
integer transfers fall through to the address-level fir.convert path
instead.

This is to fix a regression reported here:
https://github.com/llvm/llvm-project/pull/191589#issuecomment-4298846795
DeltaFile
+16-0flang/test/Lower/Intrinsics/transfer-unsigned.f90
+2-2flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+18-22 files

LLVM/project fed79d4 — llvm/lib/Target/RISCV RISCVTargetTransformInfo.h, llvm/test/CodeGen/RISCV/rvv vp-inttoptr-ptrtoint.ll fixed-vectors-inttoptr-ptrtoint.ll

by Luke Lau via GitHub on ⎇
[RISCV] Expand vp.inttoptr, vp.ptrtoint (#193530)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off 2 intrinsics from #179622. There are no corresponding
ISD nodes, they are converted into the appropriate integer casts in
SelectionDAGBuilder
DeltaFile
+15-15llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
+4-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
+0-2llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+19-213 files

LLVM/project 2cb6359 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

by Aiden Grossman on ⎇
update

Created using spr 1.3.7
DeltaFile
+158,756-173,230llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+50,477-50,088llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92,827-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+764,189-265,66642,201 files not shown
+6,544,899-3,297,05042,207 files

LLVM/project 32ba94a — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

by Jeff Bailey via Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+158,756-173,230llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+50,477-50,088llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92,827-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+764,189-265,66642,198 files not shown
+6,544,872-3,297,04042,204 files

LLVM/project 76c06c4 — llvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG/X86 switch-to-lookup-comdat.ll

by gulfemsavrun via GitHub on ⎇
Revert "Reapply "[SimplifyCFG] Reuse function comdat for switch lookup table"…"

This reverts commit 347dc1321ed50578bb09da6fa10ccec581d8a2b6.
DeltaFile
+0-58llvm/test/Transforms/SimplifyCFG/X86/switch-to-lookup-comdat.ll
+0-1llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+0-592 files

LLVM/project 97015ad — clang/include/clang/Basic IdentifierTable.h TokenKinds.def, clang/lib/Basic IdentifierTable.cpp

by Joshua Batista via GitHub on ⎇
[HLSL] Disallow `volatile` keyword (#193322)

This PR disallows the `volatile` keyword in HLSL.
The keyword is meaningless in this language, and it comes from the C++
foundation that HLSL stands on.
Fixes https://github.com/llvm/llvm-project/issues/192559
It is arguably in the category of this scenario:
https://github.com/llvm/wg-hlsl/issues/300
Assisted by: Github Copilot
DeltaFile
+10-0clang/test/SemaHLSL/Language/Volatile.hlsl
+4-3clang/include/clang/Basic/IdentifierTable.h
+2-1clang/include/clang/Basic/TokenKinds.def
+3-0clang/lib/Basic/IdentifierTable.cpp
+19-44 files

LLVM/project af626d8 — clang/docs ReleaseNotes.rst, clang/lib/AST StmtProfile.cpp

by Walter Lee via GitHub on ⎇
Revert "[clang] fix profiling of pack index expressions (#192810)"

This reverts commit b5048038ef7c8c344d49b0bfe5b5d32db45ed8f3.
DeltaFile
+0-10clang/test/SemaCXX/cxx2c-pack-indexing.cpp
+3-3clang/lib/AST/StmtProfile.cpp
+1-2clang/docs/ReleaseNotes.rst
+4-153 files

LLVM/project 835daba — llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

by Ziqing Luo on ⎇
Merge branch 'users/ziqingluo/PR-174874942-2' into users/ziqingluo/PR-174874942-3

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowAnalysis.h
        clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowAnalysis.cpp
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-03,180 files not shown
+976,533-61,1103,186 files