LLVM/project 214f9e4llvm/utils/git github-automation.py

[Workflows] Mark miscompilation:undef as uninteresting (#220300)

Address comment
https://github.com/llvm/llvm-project/issues/218908#issuecomment-5470741016.
DeltaFile
+9-0llvm/utils/git/github-automation.py
+9-01 files

LLVM/project f3028e2lld/test/ELF aarch64-reloc-pauth-undef-weak.s aarch64-reloc-pauth-undef-weak-pie.s

`.tlsdescauthcall` -> `.tlsauthdesccall` (per documentation)
DeltaFile
+1-1lld/test/ELF/aarch64-reloc-pauth-undef-weak.s
+1-1lld/test/ELF/aarch64-reloc-pauth-undef-weak-pie.s
+1-1lld/test/ELF/aarch64-reloc-pauth-undef-weak-dso.s
+3-33 files

LLVM/project bc9f5a2lld/ELF Relocations.cpp, lld/test/ELF aarch64-reloc-pauth-undef-weak.s aarch64-reloc-pauth-undef-weak-pie.s

Address review comments
DeltaFile
+50-20lld/test/ELF/aarch64-reloc-pauth-undef-weak-dso.s
+2-2lld/test/ELF/aarch64-reloc-pauth-undef-weak.s
+2-2lld/test/ELF/aarch64-reloc-pauth-undef-weak-pie.s
+1-2lld/ELF/Relocations.cpp
+55-264 files

LLVM/project 85c4a66lld/ELF SyntheticSections.h SyntheticSections.cpp, lld/test/ELF aarch64-reloc-pauth-undef-weak.s aarch64-reloc-pauth-undef-weak-pie.s

Address review comments
DeltaFile
+3-3lld/ELF/SyntheticSections.cpp
+3-3lld/ELF/Relocations.cpp
+2-2lld/test/ELF/aarch64-reloc-pauth-undef-weak.s
+2-2lld/test/ELF/aarch64-reloc-pauth-undef-weak-pie.s
+2-2lld/test/ELF/aarch64-reloc-pauth-undef-weak-dso.s
+1-1lld/ELF/SyntheticSections.h
+13-136 files

LLVM/project d902a56lld/ELF Relocations.cpp SyntheticSections.cpp, lld/ELF/Arch AArch64.cpp

[PAC][lld] Do not emit AUTH relocs against undef weak non-preemptible symbols

Undefined weak non-preemptible symbols should be statically resolved
and not signed.

See the corresponding relaxation described in docs:
https://github.com/ARM-software/abi-aa/blob/6e0d6611ac977628af7b2444ff841e76931a3557/design-documents/pauthabi-tls.rst

Previously, a dynamic relocation against such symbols was emitted,
which is not a correct behavior.

See also: https://github.com/ARM-software/abi-aa/pull/391

Depends on: #198327

Resolves #173296
DeltaFile
+79-9lld/ELF/Arch/AArch64.cpp
+48-0lld/test/ELF/aarch64-reloc-pauth-undef-weak.s
+48-0lld/test/ELF/aarch64-reloc-pauth-undef-weak-dso.s
+47-0lld/test/ELF/aarch64-reloc-pauth-undef-weak-pie.s
+15-5lld/ELF/SyntheticSections.cpp
+13-6lld/ELF/Relocations.cpp
+250-202 files not shown
+256-218 files

LLVM/project 5a01e5ellvm/lib/Target/RISCV RISCVInstrInfoZc.td RISCVInstrInfoXqci.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Merge decodeUImmOperand and decodeUImmOperandGE. NFC (#223925)

Add the LowerBound template argument to decodeUImmOperand with a default
value of 0.

Similar for decodeUImmPlus1Operand and decodeUImmPlus1OperandGE, but
default the LowerBound to 1.
DeltaFile
+6-24llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+9-273 files

LLVM/project b8f1eebllvm/lib/Target/RISCV RISCVRegisterInfo.td RISCVInstrInfoZicfiss.td, llvm/test/MC/RISCV rvzimop-valid.s

[RISCV] Add hasCompleteDecoder to sspopchk, sspush, and ssrdp operands. (#223847)

This allows them to disassemble as mop.r.28 or mop.rr.7 when the
operands are not valid for the Zicfiss mnemonic.

Assisted-by: Claude
DeltaFile
+8-11llvm/test/MC/RISCV/rvzimop-valid.s
+11-1llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+4-0llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+23-123 files

LLVM/project 98bee8bllvm/lib/Analysis VectorUtils.cpp, llvm/test/Transforms/LoopVectorize intrinsic.ll

[VectorUtils] Allow trivially vectorising llvm.[su]mulh. (#223998)
DeltaFile
+60-0llvm/test/Transforms/LoopVectorize/intrinsic.ll
+2-0llvm/lib/Analysis/VectorUtils.cpp
+62-02 files

LLVM/project 630b6b9clang/lib/CodeGen CodeGenAction.cpp BackendUtil.cpp, clang/test/CodeGen asan-unified-lto.ll PR44896.ll

clang: Do not overwrite a module's DataLayout in the backend (#224012)

emitAssembly() unconditionally reset the module's DataLayout from
TargetMachine::createDataLayout(). The TargetMachine's DataLayout is
unreliable given the existence of the "target-abi" module flag, so it
should not be used.

For -x ir input modules this would discard the correct datalayout in
favor of a possibly wrong one.

The post-codegen consistency check compared the module's DataLayout
against clang's frontend getDataLayoutString(), which likewise ignores the
target-abi flag. Recompute the expected layout from the module's own ABI via
Triple::computeDataLayout(getTargetABIName(M)) so the check stays
meaningful without assuming the DataLayout is a fixed property of the target
options. This still detects frontend/LLVM DataLayout drift for generated modules.

PR44896.ll and asan-unified-lto.ll declared x86_64 modules but ran without an 
explicit triple, relying on the old overwrite to convert them to the default target. 

    [2 lines not shown]
DeltaFile
+38-0clang/test/CodeGen/riscv-ir-datalayout-preserve.ll
+10-8clang/lib/CodeGen/BackendUtil.cpp
+12-0clang/test/CodeGen/Inputs/riscv-ilp32e-no-datalayout.ll
+3-5clang/lib/CodeGen/CodeGenAction.cpp
+4-4clang/test/CodeGen/asan-unified-lto.ll
+4-4clang/test/CodeGen/PR44896.ll
+71-214 files not shown
+78-3010 files

LLVM/project c1ee481llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp VOP3PInstructions.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h

AMDGPU: Separate getCoExecInfo opcode classification (#220329)

Extract WMMA opcode classification from getCoExecInfo into a dedicated
helper. Also track functional unit occupancy separately from the
co-execution window.
DeltaFile
+38-80llvm/lib/Target/AMDGPU/AMDGPUCoExecInfo.h
+27-8llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+13-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+79-894 files

LLVM/project 1efa5e7llvm/test/MC/AArch64 tls-auth-relocs.s

Address review comments
DeltaFile
+36-0llvm/test/MC/AArch64/tls-auth-relocs.s
+36-01 files

LLVM/project d049ef8llvm/test/MC/AArch64 tls-auth-relocs.s

Address review comments
DeltaFile
+2-2llvm/test/MC/AArch64/tls-auth-relocs.s
+2-21 files

LLVM/project c2ceaddllvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64AsmPrinter.cpp, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

`.tlsdescauthcall` -> `.tlsauthdesccall` (per documentation)
DeltaFile
+5-5llvm/test/CodeGen/AArch64/ptrauth-arm64-tls-dynamics.ll
+5-5llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+3-3llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+2-2llvm/test/MC/AArch64/tls-auth-relocs.s
+2-2llvm/test/MC/AArch64/directives-case_insensitive.s
+2-2llvm/lib/Target/AArch64/AArch64InstrInfo.td
+19-191 files not shown
+20-207 files

LLVM/project 99a890bllvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64AsmPrinter.cpp, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[PAC][ELF] Support R_AARCH64_AUTH_TLSDESC_CALL relocation

The R_AARCH64_AUTH_TLSDESC_CALL is introduced to allow linker relaxation of
AUTH TLSDESC call sequences for non-preemptible undefined weak symbols.

The lld patch introducing the relaxation: #194636

Corresponding ARM docs PR: https://github.com/ARM-software/abi-aa/pull/395
DeltaFile
+11-6llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+10-5llvm/test/CodeGen/AArch64/ptrauth-arm64-tls-dynamics.ll
+12-3llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+9-0llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+8-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+3-0llvm/test/MC/AArch64/directives-case_insensitive.s
+53-146 files

LLVM/project 2bef9bbutils/bazel/llvm-project-overlay/compiler-rt BUILD.bazel

[bazel][compiler-rt] Exclude sanitizer_offload sources from sanitizer_common (#224078)

Fixes build failure introduced by 988c5a95ffa7 ("[compiler-rt] Factor
HSA layer into common helpers (#223532)").
DeltaFile
+3-0utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel
+3-01 files

LLVM/project c14e0afclang/lib/Headers riscv_packed_simd.h, clang/test/CodeGen/RISCV rvp-intrinsics.c

[RISCV][P-ext] Support Packed Element Join (#223931)

See also
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-element-join.
DeltaFile
+182-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+63-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+26-0clang/lib/Headers/riscv_packed_simd.h
+271-03 files

LLVM/project 9df3e81clang/test/CodeGen/AArch64 abi-classify-return-types.cpp abi-classify-return-types.c, llvm/include/llvm/ABI TargetInfo.h

[LLVMAABI][AARCH64] Handle homogeneous aggregate return types (#218799)

This change implements the IsHomogenousAggregate() function, which is
shared across targets, and uses it to implement direct passthrough of
return values that meet the homogeneous aggregate criteria.

I'm also adding a new AArch64ABIOptions object that will be used to
track various conditions that are derived from target settings and must
be accounted for in the ABI handling. This change adds only two options,
IsILP32 and IsMicrosoftCXXABI. Other options are expected and will be
added as they are needed.

This change also revises the not-yet-implemented cases, having them
return Ignore rather than Direct so that they fail in more obvious ways.
This was necessary in order to be able to distinguish a return type that
was classified as Direct because it was a homogeneous aggregate from one
that was classified as Direct because it was an unhandled type.

Assisted-by: Cursor / various models
DeltaFile
+189-29llvm/unittests/ABI/AArch64TargetInfoTest.cpp
+118-0llvm/lib/ABI/TargetInfo.cpp
+81-14llvm/lib/ABI/Targets/AArch64.cpp
+79-0clang/test/CodeGen/AArch64/abi-classify-return-types.c
+78-0clang/test/CodeGen/AArch64/abi-classify-return-types.cpp
+48-3llvm/include/llvm/ABI/TargetInfo.h
+593-463 files not shown
+607-599 files

LLVM/project b8b586dllvm/lib/Target/AMDGPU VOP3PInstructions.td VOPInstructions.td, llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir

[AMDGPU] Cover missed gfx1250 VALU blocking-cycle opcodes

Annotate gfx12+ F64 add/mul and B64 shift pseudos, F64 class compares,
pseudo-scalar TRANS, integer dots, and DPP. Fix VOPC I64/U64 end-of-block
comments that said 32 instead of 2.
DeltaFile
+92-0llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+7-4llvm/lib/Target/AMDGPU/VOPCInstructions.td
+5-4llvm/lib/Target/AMDGPU/VOP2Instructions.td
+4-2llvm/lib/Target/AMDGPU/VOP3Instructions.td
+4-0llvm/lib/Target/AMDGPU/VOPInstructions.td
+1-1llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+113-116 files

LLVM/project b9dbeb2llvm/lib/Target/AMDGPU SIRegisterInfo.cpp

Merge branch 'users/mssefat/anti-hints-pr3-amdgpu-apply' into users/mssefat/anti-hints-pr4-amdgpu-pre-ra
DeltaFile
+31-26llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+31-261 files

LLVM/project 099e49allvm/lib/Target/AMDGPU SIRegisterInfo.cpp

Addressed reviews
DeltaFile
+31-26llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+31-261 files

LLVM/project fd2f003llvm/test/Transforms/SLPVectorizer/AArch64 splat-gather-subtree-inst-count.ll

[SLP][NFC]Add a test with missed vectorization because of instcount check, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/224074
DeltaFile
+42-0llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-inst-count.ll
+42-01 files

LLVM/project db96dfaflang/include/flang/Optimizer/Transforms FIRToMemRefTypeConverter.h, flang/unittests/Optimizer/OpenACC FIROpenACCPointerLikeTypeInterfaceTest.cpp

[flang][FIRToMemRef] Treat heap-pointer allocas as static, not as dynamic arrays (#223821)

Whole-array assignment of an allocatable inside !$acc kernels with
-Mstack_arrays aborted on !fir.ref<!fir.heap<!fir.array<?xf32>>>. A
fir.alloca !fir.heap<array> is a local heap pointer, but it was
unwrapped and handled as a dynamic array. The memref converter then
peeled only the outer ref and asserted because !fir.heap is not a memref
element.

Keep the pointer as a static allocation. Make convertibleMemrefType use
the same one-pointer peel as convertMemrefType so a nested pointer is
not treated as an f32 array.
DeltaFile
+51-59flang/include/flang/Optimizer/Transforms/FIRToMemRefTypeConverter.h
+44-0flang/unittests/Optimizer/OpenACC/FIROpenACCPointerLikeTypeInterfaceTest.cpp
+95-592 files

LLVM/project 9f6791blldb/test/API/tools/lldb-dap/stackTrace TestDAP_stackTrace.py

[lldb-dap][test] Only check compile units from stack frames for main.c (#223450)

The `test_stack_frame_compile_unit_id` test case added in #222512 checks
that compileUnitId in a stack frame points to the source file. However,
it does so by checking there is only one unique compileUnitId in the
whole stack trace. This may not be true if start.S is included as a
compile unit.

Relax the check by only looking for stack frames that point to main.c.
Also check the other way, i.e. ensure the same compile unit id isn't
referenced by a stack frame that doesn't point to main.c. This way the
test retains its stated goal of making sure the compile unit id resolves
to its source file while also allowing start.S from a different compile
unit to be present.
DeltaFile
+12-2lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
+12-21 files

LLVM/project 28cf187libcxx/test/benchmarks/containers/associative associative_container_benchmarks.h

[libc++] Fix query benchmarks for associative containers (#216065)

We were calling get_key and the random number generator in the hot loop.
Instead, create a pool of keys to draw from in the initial setup phase,
and then query these keys in a round-robin fashion.
DeltaFile
+18-4libcxx/test/benchmarks/containers/associative/associative_container_benchmarks.h
+18-41 files

LLVM/project 4005747libcxx/test/benchmarks/containers/associative unordered_set.bench.cpp unordered_multiset.bench.cpp

[libc++] Return a const reference from get_key in benchmarks (#216088)

It was unnecessary to create a temporary string, and in fact it would
have a negative impact on some benchmarks like `erase(key) (existent)`
which called get_key in the hot loop.
DeltaFile
+4-4libcxx/test/benchmarks/containers/associative/associative_container_benchmarks.h
+2-2libcxx/test/benchmarks/containers/associative/unordered_set.bench.cpp
+2-2libcxx/test/benchmarks/containers/associative/unordered_multiset.bench.cpp
+2-2libcxx/test/benchmarks/containers/associative/unordered_multimap.bench.cpp
+2-2libcxx/test/benchmarks/containers/associative/unordered_map.bench.cpp
+2-2libcxx/test/benchmarks/containers/associative/set.bench.cpp
+14-145 files not shown
+24-2411 files

LLVM/project f9de9e4clang/include/clang/CIR/Dialect/IR CIRTypes.td, clang/lib/CIR/CodeGen/Targets NVPTX.cpp

[CIR][CUDA] Add semantic surface reference type (#223013)
DeltaFile
+16-1clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+1-4clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
+5-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+1-1clang/test/CIR/CodeGenCUDA/surface.cu
+23-64 files

LLVM/project 9e39a5elibcxx/include/__configuration compiler.h

[libc++] Reword confusing warning message about AppleClang version (#222380)

AppleClang 26.4 is not a thing -- it's AppleClang 21.0 that shipped with
Xcode 26.4.
DeltaFile
+1-1libcxx/include/__configuration/compiler.h
+1-11 files

LLVM/project 1f1c824llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.h

[SandboxVec][LoadStoreVec] Vectorize load seed chains (#215944)

LoadStoreVec previously only vectorized store bundles. SeedCollection
already emits homogeneous store and load slices separately, so
runOnRegion() now dispatches on the seed kind and calls
vectorizeStores()
or vectorizeLoads() accordingly.

Add vectorizeLoads() to combine consecutive load chains into a single
vector load, unpack for remaining uses, and clean up dead scalar loads
and pointer operands.

Add load_store_vec_load_seeds.ll covering load-only seeds (no uses,
single use, general uses, vector-typed loads, and mixed-type cases), and
extend load_store_vec.ll with a trivial load-then-store case.
DeltaFile
+150-105llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+105-0llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_load_seeds.ll
+26-11llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
+15-4llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
+6-4llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+2-1llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+304-1256 files

LLVM/project 998c6e2libcxx CMakeLists.txt, libcxx/cmake/caches Apple.cmake

[libc++][pstl] Use libdispatch on Apple platforms by default (#223240)

Currently the default on Apple platforms is "std_thread", which is a
serial dummy.
To enable automatic benchmarking of PSTL, set the backend to
"libdispatch" by default, so it doesn't require specific overrides in
`libcxx/utils/ci/lnt/cmake`.

As a drive-by, fixes some of the minor issues with this backend that
surfaced once more pipelines started using it.
DeltaFile
+7-3libcxx/CMakeLists.txt
+2-0libcxx/test/libcxx/algorithms/pstl.libdispatch.chunk_partitions.pass.cpp
+0-1libcxx/cmake/caches/Apple.cmake
+1-0libcxx/include/__pstl/backends/libdispatch.h
+10-44 files

LLVM/project f175521llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.bitreplicate.ll

AMDGPU/GlobalISel: RegBankLegalize rules for s_bitreplicate (#189138)

Add uniform and divergent rules for s_bitreplicate intrinsic.

Assisted-By: Claude
DeltaFile
+44-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+48-22 files