[ORC] Export perf JIT loader wrapper symbols with LLVM_ALWAYS_EXPORT
PerfSupportPlugin resolves llvm_orc_registerJITLoaderPerf{Start,End,Impl} dynamically from process symbols, which fails when static executables are built with -fvisibility=hidden (e.g. CFI bootstrap builds).
Assisted-by: Gemini
[cfi] Ignore cfi-icall on LLVMContext::yield and JIT calls
LLVMContextSetYieldCallback casts a C callback with a mismatched pointer type, and ExecutionEngine / JIT tools invoke runtime-generated JIT code outside the link-time CFI jump table.
Assisted-by: Gemini
[VPlan] Use mayWriteToMemory to pick early-exit style (NFC). (#237101)
Replace the store pattern match in handleUncountableEarlyExits with a
check for any recipe that may write to memory, now that call
VPInstructions model call-site attributes. Pseudo-probes are skipped,
consistent with legality, which ignores them.
This removes the blanket store check and accounts for other recipes with
side-effects via an assert.
PR: https://github.com/llvm/llvm-project/pull/237101
[LoopUnrollAndJam] Jamming Outside Loop for stencil
Previously, we only tried to jam the loop if there was any
loop-invariant memory usage. This makes our UnrollAndJam quite
limited. GCC (gimple-loop-jam.cc) also handles stencils. What they do
is, for each MemRef pair, check the distance vector and allow jamming
if the vector is lexicographically positive.
Our safety checker (checkDependency) already allows these cases. To
match GCC's behavior, we try to calculate the actual step for each
memory usage using SCEV and find the maximum ReuseCount. Note that our
safety checker has already guaranteed that this is a forward edge, so
we don't need any additional safety checks here.
With this change running over llvm-test-suites. We observe a speedup
over my Ryzen 9 9955HX in some cases (Shootout-C++-ary3 (-34.6%),
oopack_v1p8 (-6.0%)).
Assisted by: Claude # Testcases
[SLP]Vectorize loads from the single predecessor block
Model loads from the single predecessor block as copyable elements of a
consecutive load node in the successor block. The wide load covers them
if their memory is not modified after them in the predecessor block or
anywhere in the successor block.
Fixes #43232
Assisted-by: Cursor
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/233297
[SCEV] Add test for loop guard rewrites using narrower zexts (NFC) (#237653)
Also use -scalar-evolution-classify-expressions=0 to cut down
unnecessary check lines; the tests only checks BTC
Use float literals for float option defaults. NFC (#237658)
MSVC warns about the field initializer `float ir2vec_arg_weight{0.2}`
from #236844 (C4305: truncation from 'double' to 'float'). Add the f
suffix.
[VPlan] Pass alignment explicitly to widen load/store recipes (NFC). (#237639)
Replace alignment lookup from underlying IR to explicitly storing it for
the recipe.
Preparation for fixing a miscompile with incorrect alignment when
narrowing interleave groups.
NFC except for the printed VPlans.
[VPlan] Store parent via ilist_parent, use iterator-only APIs (NFC) (#236659)
Store the parent VPBasicBlock of recipes in the ilist node via
ilist_parent<VPBasicBlock>, like Instruction/BasicBlock. This also gives
the list sentinel a parent, so any iterator into a recipe list,
including end(), knows its block.
Use this to simplify the APIs that took a block together with an
iterator, mirroring IRBuilder's removal of the separate insertion block.
PR: https://github.com/llvm/llvm-project/pull/236659
[X86] LowerRotate - directly use X86 non-uniform var-shift nodes for generic fallback (#237645)
Skip vector shift legalization and use the X86ISD::VSHLV/VSRLV nodes
directly to handle the RotAmt=0 case, so to correctly handle the out of
bounds shift by EltSizeInBits.
Fixes #236022
Attributor: Don't use callee return attributes for mismatched call types (#231629)
A call site returned position took the state and attributes of the
callee's returned position, even if the call uses a different return
type
than the callee, e.g. calling a void function as returning ptr. This
asserted in AANonNull::isImpliedByIR on the non-pointer callee return
type, and put the callee's nofpclass on calls returning another FP type.
Ignore the callee's returned position, and its returned arguments, if
the
types differ.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[SLP]Postpone small phi groups to build full register vectors
Small phi groups vectorized in the full-width stage took lanes from
wider vectors, producing 2-wide fma accumulators instead of 4-wide.
Postpone them, then try the candidates in prefix-first order at full
width, so phis from different groups with matching leading operands
get vectorized together.
Fixes #47830
Assisted-by: Cursor
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/234997
