LLVM/project 8470dfblldb/source/Expression DWARFExpression.cpp, lldb/unittests/Expression DWARFExpressionTest.cpp

[lldb] Guard DW_OP_convert against null DWARF unit and empty stack (#207008)

`Evaluate_DW_OP_convert` dereferenced `eval_ctx.dwarf_cu` (the
`DWARFExpression` Delegate) whenever the operand DIE offset was
non-zero,
and unconditionally read `eval_ctx.stack.back()`.  When a DWARF
expression is evaluated without a DWARF unit (as the
lldb-dwarf-expression-fuzzer does), two operand shapes crash:

- `DW_OP_convert` with a non-zero offset calls
  `dwarf_cu->GetDIEBitSizeAndSign(...)` on a null Delegate.
- `DW_OP_convert` with nothing on the stack reads the back of an empty
  vector.

The unit test feeds both with `dwarf_cu == nullptr` and crashes:

```
[ RUN      ] DWARFExpression.DW_OP_convert
 #2 SignalHandler(int, __siginfo*, void*)

    [15 lines not shown]
DeltaFile
+13-0lldb/unittests/Expression/DWARFExpressionTest.cpp
+3-0lldb/source/Expression/DWARFExpression.cpp
+16-02 files

LLVM/project 65bbeffmlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp, mlir/test/Conversion/SPIRVToLLVM gl-ops-to-llvm.mlir

[mlir][SPIR-V] Add SPIRVToLLVM conversion for GL.FClamp/SClamp/UClamp (#203831)

Lower the GLSL clamp ops as nested min/max following `min(max(x, y), z)`

---------

Co-authored-by: Igor Wodiany <dev at wodiany.com>
DeltaFile
+36-0mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
+26-0mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+62-02 files

LLVM/project 334eb77mlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp, mlir/test/Conversion/SPIRVToLLVM gl-ops-to-llvm.mlir cl-ops-to-llvm.mlir

[mlir][SPIR-V] Add SPIRVToLLVM conversions for GL.FMix and CL.mix (#206935)
DeltaFile
+51-1mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+26-0mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
+20-0mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
+97-13 files

LLVM/project 0efe9d7clang/lib/AST Type.cpp, clang/lib/CodeGen CodeGenModule.cpp

[clang][AMDGPU] Clean-up handling of named barrier type

- Do not allow the type in struct fields. This is more like a handle/resource than a real type. It does not follow the traditional C++ object model, and using it in a struct field can do some weird things if you instantiate too many of them.
- Use a `hip_barrier` LangAS for this type that currently maps to the local AS. This allows easy switching to the barrier AS in a future patch.

Alternative to #195612, see also #195613
DeltaFile
+23-14clang/test/CodeGenHIP/amdgpu-barrier-type.hip
+13-1clang/lib/AST/Type.cpp
+9-1clang/lib/Sema/SemaDecl.cpp
+6-0clang/lib/CodeGen/CodeGenModule.cpp
+5-0clang/test/SemaOpenCL/amdgpu-barrier.cl
+5-0clang/test/SemaHIP/amdgpu-barrier.hip
+61-1616 files not shown
+89-2022 files

LLVM/project 26e2b67llvm/include/llvm/Analysis ModuleSummaryAnalysis.h, llvm/lib/Analysis StackSafetyAnalysis.cpp ModuleSummaryAnalysis.cpp

[NPM] Port ImmutableModuleSummaryAnalysis to NPM
DeltaFile
+29-0llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
+5-2llvm/lib/Analysis/StackSafetyAnalysis.cpp
+2-0llvm/lib/Passes/PassRegistry.def
+1-0llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
+37-24 files

LLVM/project 818fe1fllvm/include/llvm/Analysis ModuleSummaryAnalysis.h

provide default nullptr to Index
DeltaFile
+1-1llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
+1-11 files

LLVM/project 04157a3llvm/include/llvm/CodeGen UnreachableBlockElim.h, llvm/lib/Target/AMDGPU AMDGPU.h GCNPreRALongBranchReg.h

[NPM] Make few more passes Required
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/include/llvm/CodeGen/UnreachableBlockElim.h
+1-1llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
+1-1llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
+1-1llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
+1-1llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
+10-1014 files not shown
+24-2420 files

LLVM/project 831ad2elibc/hdr/types struct_ipv6_mreq.h CMakeLists.txt, libc/include/llvm-libc-macros netinet-in-macros.h

[libc] Add struct ipv6_mreq and IPv6 socket options (#206448)

This patch adds struct ipv6_mreq and defines various IPv6 socket option
macros in <netinet/in.h>. I've also moved the existing option
definitions to the yaml file.

Assisted by Gemini.
DeltaFile
+44-0libc/include/netinet/in.yaml
+26-0libc/hdr/types/struct_ipv6_mreq.h
+24-0libc/include/llvm-libc-types/struct_ipv6_mreq.h
+9-0libc/hdr/types/CMakeLists.txt
+0-8libc/include/llvm-libc-macros/netinet-in-macros.h
+7-0libc/test/src/netinet/in_test.cpp
+110-83 files not shown
+113-89 files

LLVM/project b81a4c1llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU s-barrier.ll

[AMDGPU] Fix s.barrier.init/signal.var member count mask (#207660)

The count was shifted before masking, so bits above the low 6 could leak
past the member count field in M0
DeltaFile
+76-0llvm/test/CodeGen/AMDGPU/s-barrier.ll
+2-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+78-22 files

LLVM/project a0b14a1clang/unittests/Lex PPMemoryAllocationsTest.cpp, llvm/include/llvm/Support Allocator.h PerThreadBumpPtrAllocator.h

Revert "[Allocator] Drop RedZoneSize (non-sanitizer) and BytesAllocated membe…"

This reverts commit ca59c69132eef55cc42bf8854706590dfddf5584.
DeltaFile
+28-19llvm/include/llvm/Support/Allocator.h
+47-0llvm/unittests/ADT/ConcurrentHashtableTest.cpp
+12-0llvm/unittests/DebugInfo/MSF/MappedBlockStreamTest.cpp
+4-7clang/unittests/Lex/PPMemoryAllocationsTest.cpp
+10-0llvm/include/llvm/Support/PerThreadBumpPtrAllocator.h
+5-3llvm/unittests/Support/PerThreadBumpPtrAllocatorTest.cpp
+106-2911 files not shown
+130-3817 files

LLVM/project 46367bbllvm/test/CodeGen/X86 ucmp.ll vector-reduce-ctpop.ll

[X86] Attempt to narrow XMM->i64 (v)movq -> (v)movd if the upper 32-bits are known to be zero (#207615)

Add a custom 'X86upperzero' tablegen pattern to match vectors where the
upper half bits of every element is known zero.

Saves 1 byte by using (V)MOVD instead of (V)MOVQ - and avoids
differences in X86/X64 codegen that was bloating diffs in some upcoming
VECREDUCE_ADD work.

I've added an extra psadbw.ll test to ensure that the extractstore
pattern isn't being affected.

Cleanup for the upcoming VECREDUCE_ADD handling which will be using
PSADBW more aggressively (v2i64 result type but only 16 active bits for
element).
DeltaFile
+190-188llvm/test/CodeGen/X86/ucmp.ll
+21-21llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
+16-16llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
+30-2llvm/test/CodeGen/X86/psadbw.ll
+10-10llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
+8-8llvm/test/CodeGen/X86/divrem-by-select.ll
+275-24510 files not shown
+330-26916 files

LLVM/project 672342fllvm/test/Verifier/NVPTX tensormap-replace.ll

[NVPTX] Regenerate check lines (NFC) (#207684)

llvm-nvptx-nvidia-ubuntu buildbots were previously failing, appeared
after https://github.com/llvm/llvm-project/pull/207099.
DeltaFile
+4-4llvm/test/Verifier/NVPTX/tensormap-replace.ll
+4-41 files

LLVM/project 40d671fllvm/benchmarks ImmutableSetIteratorBM.cpp, llvm/include/llvm/ADT ImmutableSet.h

[ADT][NFC] Use isEqual for ImmutableSet/Map tree canonicalization (#207596)

`ImutAVLFactory::getCanonicalTree` deduplicates a newly built tree
against the trees already in its cache. On a digest collision it
confirmed structural equality with `compareTreeWithSection`, a plain
element-by-element in-order walk that is always linear in the tree size.

`ImutAVLTree` already provides `isEqual`, which performs the same
structural comparison but skips subtrees that are shared by pointer.
These persistent trees are heavily structurally shared -- a tree
produced by `add`/`remove` shares everything but the mutated spine with
its predecessor -- so switching `getCanonicalTree` to `isEqual` reduces
the confirmation from `O(tree size)` to `O(number of differing nodes)`
in the common case, and is never asymptotically worse. The comparison is
exact, so canonicalization behavior is unchanged.

This builds on the recent iterator rewrite in #205552 ("Rewrite
ImmutableSet/Map in-order iterator without per-node state"), which made
in-order traversal and `skipSubTree` ~2x faster. That change is a

    [58 lines not shown]
DeltaFile
+39-0llvm/benchmarks/ImmutableSetIteratorBM.cpp
+5-16llvm/include/llvm/ADT/ImmutableSet.h
+44-162 files

LLVM/project 11d3fbaclang/test/CIR/CodeGenHIP amdgcn-buffer-rsrc-type.hip builtins-amdgcn-buffer-rsrc-type.hip

[fix] rename test file name
DeltaFile
+80-0clang/test/CIR/CodeGenHIP/amdgcn-buffer-rsrc-type.hip
+0-80clang/test/CIR/CodeGenHIP/builtins-amdgcn-buffer-rsrc-type.hip
+80-802 files

LLVM/project bdb31e9clang/lib/CIR/CodeGen CIRGenTypes.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-buffer-rsrc-type.hip

[CIR][AMDGPU] Adds __amdgpu_buffer_rsrc_t in the buffer-resource address space
DeltaFile
+80-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-buffer-rsrc-type.hip
+3-1clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+83-12 files

LLVM/project 1e538dfllvm/include/llvm/Transforms/Utils LoopPeel.h UnrollLoop.h, llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopPeel] Peel last iteration to enable load widening

In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., i32) for
all other N-1 iterations.

Patterns such as:
```
  %a = load i8, ptr %p
  %b = load i8, ptr %p+1
  %c = load i8, ptr %p+2
  ...
  %p.next = getelementptr i8, ptr %p, 3
```

Can be transformed to:
```
  %wide = load i32, ptr %p  ; Read 4 bytes

    [9 lines not shown]
DeltaFile
+616-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+230-1llvm/lib/Transforms/Utils/LoopPeel.cpp
+104-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+19-13llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+12-7llvm/include/llvm/Transforms/Utils/LoopPeel.h
+2-1llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+983-226 files

LLVM/project 7830bbcllvm/lib/Transforms/Utils LoopPeel.cpp, llvm/test/Transforms/LoopUnroll peel-last-iteration-load-widening.ll peel-last-iteration-load-widening-be.ll

Address comments 1
DeltaFile
+1,694-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening.ll
+0-616llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+117-79llvm/lib/Transforms/Utils/LoopPeel.cpp
+0-104llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+67-0llvm/test/Transforms/LoopUnroll/PowerPC/peel-last-iteration-load-widening-be.ll
+56-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-disabled.ll
+1,934-7994 files not shown
+1,947-80910 files

LLVM/project 74eebbebolt/unittests/Profile PerfScripts.cpp

[BOLT] Fixed PerfScript unittest for X86 (#207408)

The test was not prepared to run on X86 target.
This change parameterized the test function to ensure proper
initialization for different targets.
DeltaFile
+32-15bolt/unittests/Profile/PerfScripts.cpp
+32-151 files

LLVM/project 753ceeclibc/src/sys/socket sockatmark.h CMakeLists.txt, libc/src/sys/socket/linux sockatmark.cpp CMakeLists.txt

[libc] Implement sockatmark (#205400)

This patch implements sockatmark as a simple wrapper around
ioctl(SIOCATMARK).

I don't test it with actual out of band data, as that requires a TCP
connection, which is more complicated to set up.

Assisted by Gemini.
DeltaFile
+54-0libc/test/src/sys/socket/linux/sockatmark_test.cpp
+36-0libc/src/sys/socket/linux/sockatmark.cpp
+25-0libc/src/sys/socket/sockatmark.h
+18-0libc/test/src/sys/socket/linux/CMakeLists.txt
+13-0libc/src/sys/socket/linux/CMakeLists.txt
+7-0libc/src/sys/socket/CMakeLists.txt
+153-04 files not shown
+162-010 files

LLVM/project b30c365clang/lib/Format UnwrappedLineParser.cpp UnwrappedLineParser.h

[clang-format][NFC] Refactor UnwrappedLineParser::parseLabel (#207674)

See
https://github.com/llvm/llvm-project/pull/196815#issuecomment-4470006692
DeltaFile
+17-19clang/lib/Format/UnwrappedLineParser.cpp
+1-2clang/lib/Format/UnwrappedLineParser.h
+18-212 files

LLVM/project 2866d23llvm/docs LangRef.rst, llvm/include/llvm/IR IntrinsicsAArch64.td

[AArch64][Bitcode] Use target memory for SME state (#205829)

Model AArch64 ZA and ZT0 intrinsic state using target_mem instead of
inaccessiblemem.

Bump the bitcode memory-attribute encoding and upgrade old AArch64
bitcode so prior inaccessiblemem effects are preserved on the new target
memory locations. Non-AArch64 bitcode keeps the old interpretation.
DeltaFile
+52-0llvm/test/Transforms/LICM/AArch64/sme-fp8-hoist.ll
+35-5llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+35-0llvm/test/Bitcode/target-memory-attribute.ll
+3-2llvm/docs/LangRef.rst
+2-2llvm/include/llvm/IR/IntrinsicsAArch64.td
+1-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+128-102 files not shown
+128-108 files

LLVM/project 604b4eellvm/include/llvm/CodeGen UnreachableBlockElim.h RenameIndependentSubregs.h, llvm/include/llvm/Transforms/Scalar StructurizeCFG.h

[NPM] Make few more passes Required
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/include/llvm/CodeGen/UnreachableBlockElim.h
+1-1llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
+1-1llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
+1-1llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
+1-1llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
+10-1014 files not shown
+24-2420 files

LLVM/project 276b1e9llvm/test/Transforms/OpenMP spmdization_guarding.ll spmdization_guarding_two_reaching_kernels.ll

fix nvptx tests
DeltaFile
+1-1llvm/test/Transforms/OpenMP/spmdization_guarding.ll
+1-1llvm/test/Transforms/OpenMP/spmdization_guarding_two_reaching_kernels.ll
+1-1llvm/test/Transforms/OpenMP/spmdization_no_guarding_two_reaching_kernels.ll
+3-33 files

LLVM/project bf74249clang/test/CodeGenCoroutines coro-elide.cpp coro-halo.cpp

[Clang] Require X86 backend for some coroutine tests (#207681)

The wrapper functions are generated without target features.
They can still be inlined based on target-specific logic, but this
requires the target to be available.

We should fix this by properly generating the target features,
but for now add a REQUIRES to unbreak the tests.
DeltaFile
+3-0clang/test/CodeGenCoroutines/coro-elide.cpp
+3-0clang/test/CodeGenCoroutines/coro-halo.cpp
+3-0clang/test/CodeGenCoroutines/pr65018.cpp
+9-03 files

LLVM/project 0c38875lldb/source/Target StopInfo.cpp Process.cpp, lldb/test/API/functionalities/fork/stop TestStopOnForkAndVFork.py main.c

[lldb] Revert stop-on-fork and stop-on-vfork (#207663)

This was causing failures on green dragon
DeltaFile
+0-72lldb/test/API/functionalities/fork/stop/TestStopOnForkAndVFork.py
+0-18lldb/test/API/functionalities/fork/stop/main.c
+6-8lldb/source/Target/StopInfo.cpp
+0-12lldb/source/Target/Process.cpp
+0-11lldb/test/Shell/Subprocess/stop-on-vfork.test
+0-11lldb/test/Shell/Subprocess/stop-on-fork.test
+6-1323 files not shown
+6-1459 files

LLVM/project 47acb0cllvm/include/llvm/Analysis ModuleSummaryAnalysis.h

provide default nullptr to Index
DeltaFile
+1-1llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
+1-11 files

LLVM/project d93dfabllvm/docs NVPTXUsage.rst, llvm/include/llvm/IR IntrinsicsNVVM.td

[NVPTX] Add missing Range attr to tensormap.replace intrinsics. (#207099)

Add missing `Range=[0, 5)` for `%ord imm` operand in
`nvvm.tensormap.replace` intrinsics.
DeltaFile
+26-0llvm/test/Verifier/NVPTX/tensormap-replace.ll
+4-4llvm/docs/NVPTXUsage.rst
+1-1llvm/include/llvm/IR/IntrinsicsNVVM.td
+31-53 files

LLVM/project 61679c3libc/include/llvm-libc-macros/linux sys-socket-macros.h

[libc] Add protocol family constants (#206911)

These aren't in POSIX, but are in 4.2BSD and they're still widely used.
DeltaFile
+7-0libc/include/llvm-libc-macros/linux/sys-socket-macros.h
+7-01 files

LLVM/project d180df7llvm/lib/Target/SPIRV SPIRVLegalizerInfo.cpp, llvm/test/CodeGen/SPIRV/llvm-intrinsics fixed-point-math-i64.ll

[SPIR-V] Support i64 smul.fix/umul.fix via SPV_ALTERA_arbitrary_precision_integers (#207405)
DeltaFile
+38-4llvm/test/CodeGen/SPIRV/llvm-intrinsics/fixed-point-math-i64.ll
+9-7llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+47-112 files

LLVM/project e9e3721llvm/test/CodeGen/AArch64/GlobalISel combine-max-min.ll

[AArch64] Remove duplicate combine-max-min.ll test. NFC (#207679)
DeltaFile
+0-87llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
+0-871 files