Revert "[AArch64][CostModel] Consider some nxv1 operations as legal" (#226531)
Reverts llvm/llvm-project#214471
This caused a failure in
https://lab.llvm.org/buildbot/#/builders/198/builds/15417 and I want to
spend a bit more time to test the ISel for vector_reverse and
vector_splice. It's also quite surprising that the test picked a VF of
`vscale x 1`
[clang-repl] Initialized HIP environment for clang-repl (#217582)
This PR initializes the HIP environment for clang-repl. Since an
IncrementalHipDeviceParser does not exist yet, a message is printed
after the environment setup indicating that the HIP environment was set
up but is not yet supported.
It also adds a test file that runs clang-repl with the -hip option and
checks that this message is printed. Once the parser is built, the
current test file will be removed and replaced with tests that verify
the complete flow.
This PR has a prerequisite, #217228, which skips emitting the
`__hip_cuid_` global under incremental extensions. Without it,
clang-repl's HIP mode would emit the same symbol in every incremental
module and fail at JIT link with a duplicate-symbol error.
Assisted by Claude Opus 4.8
[GVN] Don't coerce forwarded byte values through integers
When GVN forwards a store to a load of a different type, it goes through an
integer. It casts the stored value to `iN`, then shifts and truncates it. For
byte values that cast is wrong. It drops pointer provenance, and a single
poison bit makes the whole result poison.
Byte stores, and pointer stores that feed byte loads, no longer go through an
integer. GVN bitcasts the stored value to `bN`, takes the loaded bits with
`bitextract`, and bitcasts the result to the load type. Byte vector stores
take the same path.
[lldb] Introduce DynamicRegisterInfo::RegisterSetWithStorage (#225555)
The RegisterSet struct is created in 2 different ways:
1.) Statically in headers/source files for register sets that are known
ahead of time.
2.) Dynamically according to input from outside of LLDB. Usually this is
through the gdb-remote stub, but may also come from a python script or
by determining an ISA variant's features (e.g. in RISCV).
This PR aims to address the lifetime of strings in RegisterSet. In
scenario (1), the lifetime of all data in a RegisterSet is static and
there is no concern about dangling pointers. However, in scenario (2),
DynamicRegisterInfo maintains a vector of RegisterSets. Until now, it
has relied on ConstString to persist the storage for the strings
indefinitely. As part of my quest to remove ConstString, I am
introducing a new struct wrapping RegisterSet that is responsible for
the storage and lifetime of the underlying RegisterSet strings.
Mips: Remove redundant Triple copy from the subtarget (#226528)
MCSubtargetInfo already stores the target triple, so MipsSubtarget's own
copy is unnecessary.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
[Clang][OpenMP] Fix crash on `_BitInt` loop bounds and counters in loop analysis (#226464)
Fixes #140074
When building the iteration count of an OpenMP loop, Sema derives a few
integer types from bit widths, e.g. to promote the upper bound to an
unsigned type as wide as the wider bound so that `upper - lower` cannot
overflow. Those types came from `ASTContext::getIntTypeForBitwidth`,
which only knows the standard integer widths and returns a null type for
anything else. With a bound or loop counter of type `_BitInt(931)` the
request was for a 960-bit type, the result was null, and it went
straight into `PerformImplicitConversion`, which asserted. The
`collapse(2)` in the reduced reproducer is incidental; a plain `#pragma
omp for` on the same loop crashes the same way.
The loop analysis now goes through a small helper that asks for the
standard type first and otherwise builds the `_BitInt` type of that
width and signedness with `ASTContext::getBitIntType`. It is used at the
three places that derive a type from a loop width: the upper-bound
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[AMDGPU] merge 16bit mov pairs in post-RA peephole (#208625)
Address https://github.com/llvm/llvm-project/issues/207011. Add 5
patterns to merge 16bit mov pairs.
Since we hoist instruction which might cross the waitcnt boundary,
insert a new pass before waitcnt for this transformation
Co-Authored-By: Claude
[AMDGPU] Make GFX1250VALUBlockingCycles a feature.
Included (intentional) behavior change: gfx1251 (w/ FullRate64Ops) does not have
GFX1250VALUBlockingCycles feature --- table is only partially usable for gfx1251.
[lld][test] Use LLVM helpers for input file discovery (#220404)
This was a suggestion on #220340 to avoid the custom env var handling
and use the `getInputFileDirectory` helper from the LLVM support library
[MLIR][XeGPU] Add MXFP fp8 WG GEMM tests and use shared input set (#225944)
Adds four workgroup-level tests, updates two and renames one, so that
seven tests covering bf16, mx-fp4 and mx-fp8 exercise the same
arithmetic on the same operand values and check against the same
expected result.
1. simple_mxfp_gemm -> simple_mxfp_gemm_F4 - renamed, for consistency
with the F4/F8 suffixes used by the quantize and dequantize tests
2. (new) simple_gemm_bf16 - non-quantized bf16 GEMM at the MXFP problem
size, as the unquantized comparison point, and where the shared input
set is documented
3. (new) simple_mxfp_gemm_F8 - f8E5M2 operands with f8E8M0FNU scales
4. (new) simple_mxfp_gemm_dequantizeB_F8
5. (new) simple_mxfp_gemm_quantizeA_F8 - fp8 counterparts of the
existing fp4 tests
6. simple_mxfp_gemm_dequantizeB_F4 and simple_mxfp_gemm_quantizeA_F4 are
updated in place.
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[Analysis][RISCV] More accurately estimate the cost of strided vector loads (#175135)
For small constant strides, attempt to predict the amount of coalescing
that will be done by the target machine to give a better cost estimate.
Currently, strided loads/stores are costed as having a cost of 1 per
element (i.e. being equivalent to scalar loads/stores).
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
[CIR] Added fast-math flags to LLVM intrinsic calls (#224899)
Added fast-math flags attribute to CIR which cir.call_llvm_intrinsic now
carries through DirectToLLVM lowering. CIR now preserves fast-math flags
such as reassoc when lowering to llvm.call_intrinsic.
Added test for the same.
Mips: Remove redundant Triple copy from the subtarget
MCSubtargetInfo already stores the target triple, so MipsSubtarget's own
copy is unnecessary.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
