LLVM/project f546c51clang/test/OpenMP target_teams_distribute_simd_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector unmerge-crash-1.ll unmerge-crash-0.ll

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+1,413-1,413clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+1,403-1,403clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+1,403-1,403clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+1,173-1,173llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
+1,172-1,172llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
+1,031-1,031clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
+7,595-7,595796 files not shown
+47,443-34,209802 files

LLVM/project 6a77aa4llvm/test/MC/AMDGPU gfx12_asm_vop3_err.s gfx12_asm_features.s

[AMDGPU][MC] Upstream gfx11/gfx12 true16 assembler test coverage

Upstream new assembler test cases, covering true16 .l/.h operands and op_sel
handling that had no upstream coverage.
DeltaFile
+75-0llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
+69-0llvm/test/MC/AMDGPU/gfx11_asm_opsel.s
+59-0llvm/test/MC/AMDGPU/gfx11_asm_t16.s
+6-0llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s
+3-0llvm/test/MC/AMDGPU/gfx12_asm_features.s
+2-0llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
+214-06 files

LLVM/project b33f5efllvm/test/MC/Disassembler/AMDGPU gfx12_dasm_vop2.txt gfx12_dasm_vop3_from_vop2_dpp8.txt

[AMDGPU][MC] Upstream gfx12 true16 disassembler test coverage (#223825)

Upstream new gfx12 disassembler test cases, covering true16 operand
(.l/.h)
and op_sel decoding for f16 opcodes that had no upstream coverage:
DeltaFile
+168-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
+84-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
+84-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
+84-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
+84-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
+70-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
+574-05 files not shown
+711-011 files

LLVM/project 4648d33lldb/source/Plugins/Process/minidump MinidumpParser.cpp, lldb/unittests/Process/minidump MinidumpParserTest.cpp

[lldb] Bounds check minidump location descriptors (#223911)

MinidumpParser::GetModuleUUID sliced the file with the RVA and DataSize
taken straight from a module's CvRecord. ArrayRef::slice asserts, but a
build without assertions still reads out of bounds.

Route both through MinidumpFile::getRawData, which range checks in 64
bits, and log the error rather than returning a slice that looks valid.

rdar://186889966
rdar://186890172
DeltaFile
+68-0lldb/unittests/Process/minidump/MinidumpParserTest.cpp
+16-4lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
+84-42 files

LLVM/project cde1115flang-rt/unittests/Runtime Assign.cpp

[flang-rt][unittests] Define MAP_ANONYMOUS fallback for AIX in Assign tests (#224675)

We ran into 
```
flang-rt/unittests/Runtime/Assign.cpp:497:21: error: use of undeclared identifier 'MAP_ANONYMOUS'
  497 |       MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)};
  ```
  
On AIX, `flang-rt` is built with `_XOPEN_SOURCE=700` and without `_ALL_SOURCE`, which prevents `<sys/mman.h> `from exposing `MAP_ANONYMOUS` / `MAP_ANON`. Provide a fallback definition so mmap unit tests introduced in PR #222101 compile successfully on AIX.
DeltaFile
+26-8flang-rt/unittests/Runtime/Assign.cpp
+26-81 files

LLVM/project 583e39ellvm/lib/DebugInfo/DWARF DWARFAcceleratorTable.cpp, llvm/test/tools/llvm-dwarfdump/X86 apple-names-overflowing-entry-count.s

[DebugInfo] Fix 32-bit overflow in AppleAcceleratorTable::equal_range (#224866)

Computing the end offset overflowed 32 bits before widening to 64 bits.
Because SameNameIterator stops on exact equality, a wrapped offset
caused an infinite loop.

Compute the product in 64 bits and return an empty range if the end
offset exceeds the section size.

rdar://186839483
DeltaFile
+78-0llvm/test/tools/llvm-dwarfdump/X86/apple-names-overflowing-entry-count.s
+5-1llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
+83-12 files

LLVM/project 8010f19llvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/CodeGen/AMDGPU frem.ll mad-mix-lo-bf16.ll

[AMDGPU] Fold fpround of fadd and fsub into v_mad/fma_mixlo and mixhi

MadFmaMixFP32Pats turns (fadd x, y) into (fma x, 1.0, y) and (fsub x, y)
into (fma (-y), 1.0, x) so the mix instructions absorb the operation along
with the f16 or bf16 source modifiers. MadFmaMixFP16Pats and
MadFmaMixFP16Pats_t16 only did this for fmul, so a rounded result still
needed a separate convert for a rounding the mix instructions perform
themselves.

Unlike the f32 patterns these do not require an operand to be an fpextend
of an f16, since an fpround on the result always removes the convert. The
rewrite is exact because the mix instructions round the f32 result again
when they write the 16-bit destination, so it stays f32_to_f16(fma(x, 1.0,
y)).

Assisted-by: Claude Code Opus 5


DeltaFile
+192-285llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+61-311llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+62-145llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+55-36llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
+26-52llvm/test/CodeGen/AMDGPU/frem.ll
+70-0llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+466-8294 files not shown
+496-88510 files

LLVM/project 22e70f6llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU mad-mix-hi-bf16.ll mad-mix-lo-bf16.ll

[AMDGPU] Do not match an f16 extension as a bf16 mix source

Assisted-by: Claude Code Opus 5



DeltaFile
+51-18llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
+17-6llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+70-253 files

LLVM/project f048dc9llvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/CodeGen/AMDGPU mad-mix-lo.ll mad-mix-fptrunc-rounding.ll

[AMDGPU] Require flushed FP16 denormals for the mad-mix f16 results

v_mad_mixlo_f16 and v_mad_mixhi_f16 are the unfused gfx900 forms and flush
16-bit denormals, so a denormal half result is written as zero even when the
FP16 mode asks for it to be kept, while the patterns only required the FP32
mode to flush and that is the one a HIP compile turns off on its own.

Assisted-by: Claude Code Opus 5



DeltaFile
+16-6llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+3-3llvm/test/CodeGen/AMDGPU/mad-mix-fptrunc-rounding.ll
+2-1llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+2-0llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+23-104 files

LLVM/project 9d73c09llvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/CodeGen/AMDGPU mad-mix-bf16-t16-inline-imm.mir

[AMDGPU] Use a bf16 operand profile for v_fma_mix_bf16_t16 (#224910)

Assisted-by: Claude Code Opus 5
DeltaFile
+68-0llvm/test/CodeGen/AMDGPU/mad-mix-bf16-t16-inline-imm.mir
+1-1llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+69-12 files

LLVM/project 82fb38ellvm/test/Transforms/SLPVectorizer/X86 trimmed-subtree-schedule.ll

[SLP][NFC]Add a test for deleted nodes but still scheduled, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/225154
DeltaFile
+60-0llvm/test/Transforms/SLPVectorizer/X86/trimmed-subtree-schedule.ll
+60-01 files

LLVM/project 771f094llvm/include/llvm/MC MCContext.h, llvm/lib/MC MCContext.cpp

[SystemZ][z/OS] Do not cache section definitions

If a section was seen before, `MCContext::getGOFFSection()` returns
that section for reuse. However, in most cases this is the wrong
behaviour. ED symbols, e.g. C_WSA64, need to be recreated instead of
being reused. The current code attempted that by constructing a
unique name including the name of the SD symbol. But this fails for
the DWARF EH data, because teh SD symbol is always the same. Therfore
the C_WSA64 section is shared across all DWARF tables, resulting in
a "invalid data" binder error.
To fix this, the caching of section object is removed.
DeltaFile
+39-0llvm/test/CodeGen/SystemZ/zos-eh-2.ll
+2-14llvm/lib/MC/MCContext.cpp
+2-1llvm/include/llvm/MC/MCContext.h
+43-153 files

LLVM/project 7357fd9llvm/lib/Target/ARM Thumb2SizeReduction.cpp

Address comments
DeltaFile
+11-19llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+11-191 files

LLVM/project 150f899clang/include/clang/Basic BuiltinsAMDGPU.td, llvm/lib/Target/AMDGPU MIMGInstructions.td AMDGPU.td

[AMDGPU][NFC] Introduce TDMInsts feature for tensor load/store (#225123)
DeltaFile
+9-3llvm/lib/Target/AMDGPU/AMDGPU.td
+3-3llvm/lib/Target/AMDGPU/MIMGInstructions.td
+2-2clang/include/clang/Basic/BuiltinsAMDGPU.td
+14-83 files

LLVM/project 7cfa348llvm/lib/Target/ARM Thumb2SizeReduction.cpp, llvm/test/CodeGen/ARM cmse-harden-call-returned-values.ll

ARM: Track CPSR liveness in Thumb2SizeReduction without kill flags

Thumb2SizeReduction narrows a 32-bit instruction to its flag-setting
16-bit form only when CPSR is dead afterwards. It determined this from
kill flags on CPSR operands. Kill flags have been semi-deprecated
for over a decade, so avoid relying on them. Liveness should be evaluated
as a reverse walk over a block.

The existing forward walk over the block is still necessary as a separate
step for the different A9 avoidCPSRPartialUpdate optimization.

Co-Authored-By: Claude claude-opus-4.8 <noreply at anthropic.com>
DeltaFile
+122-0llvm/test/CodeGen/Thumb2/thumb2-reduce-size-cpsr.mir
+40-69llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+2-2llvm/test/CodeGen/ARM/cmse-harden-call-returned-values.ll
+164-713 files

LLVM/project 56c938ellvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

ARM: Use divmod type signatures from RuntimeLibcallsInfo

Start moving towards an API to emit calls from RuntimeLibcallsInfo's
knowledge about the type signature of a function instead of manually
computing an IR type from the EVT of the operation.

Also change the swap of arguments to be based on the libcall impl,
rather than the ABI since it's logically a property of the function
itself.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+85-27llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+38-41llvm/lib/Target/ARM/ARMISelLowering.cpp
+9-0llvm/include/llvm/CodeGen/TargetLowering.h
+132-683 files

LLVM/project 4eb8384llvm/lib/IR RuntimeLibcalls.cpp, llvm/test/Transforms/Util/DeclareRuntimeLibcalls divmod.ll

RuntimeLibcalls: Describe register-returning divmod libcall ABIs

Teach RuntimeLibcallsInfo::getFunctionTy about the ARM AEABI
(__aeabi_*divmod) and Windows (__rt_*div*) divmod sigantures. Currently
the custom lowering to these calls hardcodes the call signature information,
but in the future this should be automatically handled.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+58-0llvm/lib/IR/RuntimeLibcalls.cpp
+26-0llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
+84-02 files

LLVM/project 3a0c646llvm/lib/Transforms/Vectorize VPlanAnalysis.cpp, llvm/test/Transforms/LoopVectorize revec-reg-usage.ll

[LV][REVEC] Correctly compute register usage

For REVEC, the initial types might already be vectors, so make sure the
right register class is picked.
DeltaFile
+39-0llvm/test/Transforms/LoopVectorize/revec-reg-usage.ll
+17-12llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+56-122 files

LLVM/project 4f18ef3llvm/test/Transforms/LoopVectorize revec-predication.ll revec-invalid.ll

Harmonise tests by renaming IR values
DeltaFile
+54-54llvm/test/Transforms/LoopVectorize/revec-memory-interleaved.ll
+41-41llvm/test/Transforms/LoopVectorize/revec-memory-gather-scatter.ll
+36-36llvm/test/Transforms/LoopVectorize/revec-invalid.ll
+15-15llvm/test/Transforms/LoopVectorize/revec-predication.ll
+146-1464 files

LLVM/project 309a5cfllvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Analysis VectorUtils.cpp

Use updated vector.repeat intrinsic
DeltaFile
+37-0llvm/lib/Analysis/VectorUtils.cpp
+33-1llvm/test/Transforms/LoopVectorize/revec-livein.ll
+0-20llvm/lib/IR/IRBuilder.cpp
+11-0llvm/include/llvm/Analysis/VectorUtils.h
+2-2llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-2llvm/lib/Transforms/Vectorize/VPlan.cpp
+84-251 files not shown
+85-267 files

LLVM/project 6460a56llvm/lib/Target/AArch64 AArch64SMEInstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sme-streaming-mode-landingpads.ll

AArch64: Fix duplicating VG def operands in isel pseudo expansion (#225113)

Previously MSRpstatePseudo's handling would produce a duplicate VG operand. 
AdjustInstrPostInstrSelection added an implicit VG use/def and an FPMR def. It's 
dubious to introduce a def in the output which wasn't already present in the input, 
so fix the missing FPMR def. Also guard against re-introducing the operands for 
instructions which already have the defs. Ideally  there would not be any of these m
anual def add calls, but that is a larger fix.

This removes the duplicate operand and fixes potentially inconsistent
dead flags, avoiding a failure in a future verifier check.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+3-3llvm/test/CodeGen/AArch64/sme-streaming-mode-landingpads.ll
+3-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+7-63 files

LLVM/project 2c429b5llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp

WebAssembly: Don't duplicate implicit CALL operands in LowerCallResults (#225069)

When recombining the CALL_PARAMS/CALL_RESULTS pseudo-pair into a real
CALL, LowerCallResults copied CallParams.uses() onto the new instruction.
uses() includes the implicit operands (implicit-def $arguments and the implicit
$sp32/$sp64 uses), which the freshly created CALL already carries. This
resulted in a duplicated implicit-def of $arguments. This avoids a
future verifier error.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-1llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+2-11 files

LLVM/project 8c5c2ccclang/lib/CodeGen CGCleanup.cpp EHScopeStack.h, clang/test/CodeGen compound-literal-lifetime.c

[clang][CodeGen] Exempt lifetime marker cleanups in musttail check (#224731)

PR #219045 started emitting @llvm.lifetime.start and @llvm.lifetime.end
markers for block-scoped compound literals in C via
pushCleanupAfterFullExpr<CallLifetimeEnd>.

When a compound literal is evaluated inside a conditional branch,
pushCleanupAfterFullExpr wraps CallLifetimeEnd inside
EHScopeStack::ConditionalCleanup, which did not override
EHScopeStack::Cleanup::isRedundantBeforeReturn(). Consequently,
CodeGenFunction::EmitCall rejected [[clang::musttail]] calls when a
conditional compound literal was in scope at -O1 and above.

Because EHScopeStack::ConditionalCleanup wraps cleanups by composition,
virtual methods on EHScopeStack::Cleanup other than Emit() do not work
for conditional cleanups. Replace the virtual
EHScopeStack::Cleanup::isRedundantBeforeReturn() method with a
StackRestore bit on CleanupKind/EHCleanupScope alongside the existing
LifetimeMarker bit, and check EHCleanupScope::isRedundantBeforeReturn()

    [5 lines not shown]
DeltaFile
+12-10clang/lib/CodeGen/CGCall.cpp
+12-0clang/test/CodeGen/compound-literal-lifetime.c
+11-0clang/lib/CodeGen/CGCleanup.h
+2-2clang/lib/CodeGen/EHScopeStack.h
+2-2clang/lib/CodeGen/CGDecl.cpp
+3-0clang/lib/CodeGen/CGCleanup.cpp
+42-141 files not shown
+42-167 files

LLVM/project f0159c8clang/include/clang/AST DeclContextInternals.h, clang/lib/AST ASTImporter.cpp

[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#225022)

Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:

  // FIXME: Replace the uses of is(), get() and dyn_cast() with
  //        isa<T>, cast<T> and the llvm::dyn_cast<T>

Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
where the operands are known to be nonnull.

The operands are known to be nonnull in one of three ways:

- Preceding checks: A null check, assertion, or dereference a few
  lines above guarantees the PointerUnion is nonnull.

- Downstream code: The else or fallthrough branch unconditionally
  calls cast<...>, dereferences the pointer, or reaches

    [6 lines not shown]
DeltaFile
+10-10clang/lib/Analysis/LifetimeSafety/Checker.cpp
+4-4clang/include/clang/AST/DeclContextInternals.h
+3-4clang/lib/AST/ASTImporter.cpp
+2-2clang/lib/Serialization/ASTWriterDecl.cpp
+2-2clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
+2-2clang/lib/Sema/SemaSYCL.cpp
+23-2410 files not shown
+35-3716 files

LLVM/project f12afd1llvm/lib/Target/AArch64 AArch64ExpandPseudoInsts.cpp, llvm/test/CodeGen/AArch64 kcfi-bti.ll blr-bti-preserves-operands.mir

AArch64: Don't duplicate the branch's implicit defs in call pseudo expansion (#225064)

These pseudo expansions started with an implicit LR def and are replaced
with a new instruction with a different LR def. Previously this would copy the
old instruction's operand list, merging with the newly build instruction def
list. Avoid creating a redundant def with inconsistent dead flags. This avoids
failing a future verifier check.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+12-12llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
+8-4llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+2-2llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
+1-1llvm/test/CodeGen/AArch64/kcfi-bti.ll
+23-194 files

LLVM/project 7198d33llvm/test/Transforms/LoopVectorize revec-liveout.ll revec-unroll.ll

Update test checks after rebase
DeltaFile
+3-4llvm/test/Transforms/LoopVectorize/revec-unroll.ll
+2-3llvm/test/Transforms/LoopVectorize/revec-liveout.ll
+5-72 files

LLVM/project 15a7907llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.cpp, llvm/test/Transforms/LoopVectorize revec-maximize-bandwidth.ll

Revert REVEC-specific useMaxBandwidth() change and add tests
DeltaFile
+50-0llvm/test/Transforms/LoopVectorize/AArch64/revec-maximize-bandwidth.ll
+45-0llvm/test/Transforms/LoopVectorize/revec-maximize-bandwidth.ll
+1-3llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+96-33 files

LLVM/project 70ba1a3llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/unittests/Transforms/Vectorize VPlanTest.cpp

Test recipe execution for vector types

And ensure a value is correctly detected as "widened", even when
VF == VFScaleFactor
DeltaFile
+50-0llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
+8-3llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+58-32 files

LLVM/project 5807cc2llvm/lib/Transforms/Vectorize VPlanRecipes.cpp

Restore type checks in computeScalarTypeForInstruction()
DeltaFile
+7-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+7-01 files

LLVM/project 98cb88dllvm/lib/Transforms/Vectorize VPlan.h VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize revec-liveout.ll

Test get(VPV, LaneIdx) for "vector lanes"

This requires a slight adjustment to type asserts in
VPInstruction::execute to be safe for REVEC.
DeltaFile
+77-0llvm/test/Transforms/LoopVectorize/revec-liveout.ll
+8-4llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+2-1llvm/lib/Transforms/Vectorize/VPlan.h
+87-53 files