LLVM/project 0da0163llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp SelectionDAG.cpp

[SelectionDAG] Preserve poison in IS_FPCLASS folds (#193246)

Handle poison explicitly in `IS_FPCLASS` so the fold preserves poison
semantics instead of turning the result into `false`.

Prep work to help with https://github.com/llvm/llvm-project/pull/190307
DeltaFile
+4-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+3-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+7-02 files

LLVM/project 43fbaf3clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenBuiltin.cpp

[CIR] Fix __builtin_clz/__builtin_ctz poison_zero to respect target

CIR was hardcoding poisonZero=true for all clz/ctz builtins, ignoring
the target's isCLZForZeroUndef(). This caused incorrect UB on targets
like AArch64 where clz/ctz of zero is well-defined.

Also add support for __builtin_c[lt]zg fallback (2-arg) variants with
compare+select, and add NYI stubs for elementwise variants.
DeltaFile
+104-0clang/test/CIR/CodeGenBuiltins/builtin-bit-clz-ctz-target.cpp
+58-24clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+1-0clang/include/clang/CIR/MissingFeatures.h
+163-243 files

LLVM/project 4aecd04libcxx/test/std/atomics/atomics.types.generic cas_non_power_of_2.pass.cpp

[libcxx][test] Skip cas_non_power_of_2.pass.cpp in Picolibc build (#191415)

Relates to #191388

This test is currently being run and failing to link, however this is
masked by the XFAIL for clang 21. It is also marked unsupported for 22,
for now.

I ran it with 23 and got this linker error:
```
| ld.lld: error: undefined symbol: __atomic_load
<...>
| ld.lld: error: undefined symbol: __atomic_compare_exchange
```

This happens because for 5 and 6 byte variables, we can't simply
generate code for the atomic, so we emit a library call, and the
picolibc build does not provide implementations of these functions.


    [11 lines not shown]
DeltaFile
+4-0libcxx/test/std/atomics/atomics.types.generic/cas_non_power_of_2.pass.cpp
+4-01 files

LLVM/project 7af4283llvm/lib/Target/SPIRV SPIRVGlobalRegistry.cpp SPIRVInstructionSelector.cpp

[NFC][SPIR-V] Use getScalarOrVectorComponent{Count,Type} instead of raw operand access (#193410)

Replace direct accesses to SPIR-V type instruction operands with the
existing getScalarOrVectorComponentCount() and
getScalarOrVectorComponentType() helpers
DeltaFile
+21-30llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+11-33llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+10-10llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+7-6llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+1-1llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+50-805 files

LLVM/project 9ec6788lldb/packages/Python/lldbsuite/test decorators.py, lldb/source/Plugins/SymbolLocator/SymStore SymbolLocatorSymStore.cpp SymbolLocatorSymStoreProperties.td

[lldb] Add HTTPS tests for SymbolLocatorSymStore (#192274)

Using self-signed certificates is the only way forward for testing 
security features on the HTTPS path. As we don't want to allow
any arbitrary certificate, we add a new property that pins a
fingerprint and any self-signed certificate is only accepted if it
matches this fingerprint.
DeltaFile
+162-2lldb/test/API/symstore/TestSymStore.py
+62-4llvm/lib/HTTP/HTTPClient.cpp
+21-0lldb/source/Plugins/SymbolLocator/SymStore/SymbolLocatorSymStore.cpp
+11-0lldb/packages/Python/lldbsuite/test/decorators.py
+4-0llvm/include/llvm/HTTP/HTTPClient.h
+3-0lldb/source/Plugins/SymbolLocator/SymStore/SymbolLocatorSymStoreProperties.td
+263-61 files not shown
+264-77 files

LLVM/project fb6963allvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 arm64-vmul.ll

[AArch64][DAG] Copy flags when narrowExtractedVectorBinOp-ing

The `extract (binop B0, B1), N` fold above already copies flags, use the same for
the `extract (binop (concat X1, X2), Y), N` version. In this case it is helping
copy disjoint or flags.
DeltaFile
+26-26llvm/test/CodeGen/AArch64/arm64-vmul.ll
+2-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+28-272 files

LLVM/project e5ba0a5llvm/test/CodeGen/AArch64 neon-rshrn.ll

[AArch64] Add disjoint or tests for rshrn and raddhn. NFC

These should already be OK, as the os disjoint or connot round up.
DeltaFile
+76-0llvm/test/CodeGen/AArch64/neon-rshrn.ll
+76-01 files

LLVM/project eaf8336llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 arm64-vmul.ll

[AArch64] Use add_like for UMLAL / SMLAL

Similar to the others, this allows us to generate UMLAL and SMLAL from add-like
disjoint ors. There are some cases where we lose the disjoint from the or,
those will be fixed separately.
DeltaFile
+90-90llvm/test/CodeGen/AArch64/arm64-vmul.ll
+4-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+94-942 files

LLVM/project bb6b6a2llvm/test/CodeGen/AArch64 arm64-vmul.ll

[AArch64] Addition tests for add_like Or of smlal/umlal. NFC
DeltaFile
+333-25llvm/test/CodeGen/AArch64/arm64-vmul.ll
+333-251 files

LLVM/project 35480b2llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp SPIRVEmitNonSemanticDI.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-type-basic.ll debug-type-pointer.ll

[SPIRV] Migrate NSDI emission from a machine pass to DebugHandlerBase (#191212)

This PR implements the basic harness for the migration I discussed in
https://discourse.llvm.org/t/hlsl-spirv-nsdi-debug-info-support-for-clang-dxc/90149.
DeltaFile
+377-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+0-366llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+173-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+22-46llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll
+48-4llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
+9-43llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
+629-4599 files not shown
+738-49115 files

LLVM/project e9ce480clang/lib/Driver Driver.cpp

Merge remote-tracking branch 'official/users/meinersbur/flang_builtin-mods_3' into users/meinersbur/flang_builtin-mods_3
DeltaFile
+2-2clang/lib/Driver/Driver.cpp
+2-21 files

LLVM/project 80eb53dllvm/test/CodeGen/AArch64 hadd-combine-scalar.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

Merge branch 'main' into users/meinersbur/flang_builtin-mods_3
DeltaFile
+4,805-4,811llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,871-1,882llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+837-855llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+1,139-456llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+664-508llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+868-0llvm/test/CodeGen/AArch64/hadd-combine-scalar.ll
+10,184-8,512515 files not shown
+29,648-15,754521 files

LLVM/project 22bb938clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-across.c neon-intrinsics.c

[CIR][AArch64] Lower NEON vminv intrinsics (#192901)

### Summary

part of : https://github.com/llvm/llvm-project/issues/185382

Lower all intrinsics in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#minimum-across-vector
and
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#minimum-across-vector-(IEEE754)

Add ClangIR (CIR) codegen support for the NEON minimum-across-vector
builtins on AArch64. This covers the ACLE sections 2.1.1.13.4 Minimum
across vector (signed/unsigned integer + float) and 2.1.1.13.6 Minimum
across vector (IEEE 754, NaN-ignoring). Corresponding
classic-CodeGen-only tests are migrated into the shared CIR+LLVM test
file so both pipelines are checked from the same RUN lines.

These builtins are already registered in AArch64SISDIntrinsicMap

    [6 lines not shown]
DeltaFile
+226-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-119clang/test/CodeGen/AArch64/neon-across.c
+0-60clang/test/CodeGen/AArch64/neon-intrinsics.c
+18-0clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+244-1794 files

LLVM/project 83b4c5cllvm/docs NVPTXUsage.rst, llvm/lib/Target/NVPTX NVPTXInstrInfo.td NVPTXIntrinsics.td

[NVPTX] Add intrinsics for narrow-fp to bf16 conversions (#191376)

Adds the following intrinsics for narrow-fp to bf16 conversions
introduced in PTX 9.2:
-
llvm.nvvm.{e4m3x2/e5m2x2}.to.bf16x2.rn{.relu}{.satfinite}.scale.n2.ue8m0
-
llvm.nvvm.{e2m3x2/e3m2x2}.to.bf16x2.rn{.relu}{.satfinite}.scale.n2.ue8m0
- llvm.nvvm.e2m1x2.to.bf16x2.rn{.relu}{.satfinite}.scale.n2.ue8m0

Tests have been verified through `ptxas-13.2`.

PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
DeltaFile
+135-0llvm/test/CodeGen/NVPTX/convert_fp6x2_to_bf16x2.ll
+135-0llvm/test/CodeGen/NVPTX/convert_fp8x2_to_bf16x2.ll
+87-0llvm/test/CodeGen/NVPTX/convert_fp4x2_to_bf16x2.ll
+43-12llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+41-0llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+18-5llvm/docs/NVPTXUsage.rst
+459-175 files not shown
+487-1911 files

LLVM/project e049ab7

Merge commit '8e132f78bfb070effd247e85b19e3c84b9e84bac' into users/meinersbur/flang_builtin-mods_3
DeltaFile
+0-00 files

LLVM/project be04a45clang/test/CIR/CodeGen paren-list-agg-init.cpp, llvm/test/CodeGen/AArch64 clmul-scalable.ll

Merge commit '8e132f78bfb070effd247e85b19e3c84b9e84bac^' into users/meinersbur/flang_builtin-mods_3
DeltaFile
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+764-1,425llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+428-526llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
+884-0clang/test/CIR/CodeGen/paren-list-agg-init.cpp
+5,420-4,372860 files not shown
+25,698-11,289866 files

LLVM/project cd14598llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp

[AMDGPU][NFC] Eliminates the redundant code in the AMDGPUTargetMachine.cpp (#193169)
DeltaFile
+6-9llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+6-91 files

LLVM/project 5ef29d1

[ADT] Add predicate based match support to StringSwitch (#188046)

This introduces `Predicate` and `IfNotPredicate` case selection to
StringSwitch to allow use cases like

```
StringSwitch<...>(..)
  .Case("foo", FooTok)
  .Predicate(isAlpha, IdentifierTok)
...
```

This is mostly useful for improving conciseness and clarity when
processing generated strings, diagnostics, and similar.
DeltaFile
+0-00 files

LLVM/project f4cc934llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[LV] NFCI: Create VPExpressions in transformToPartialReductions. (#182863)

With this change, all logic to generate partial reductions and
recognising them as VPExpressions is contained in
`transformToPartialReductions`, without the need for a second transform
pass.
The PR intends to be a non-functional change.
DeltaFile
+68-52llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+68-521 files

LLVM/project 9435160mlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/test/Dialect/LLVMIR nvvm_check_target_sm.mlir nvvm_check_target_sm_trait.mlir

[MLIR][NVVM] Update SM version requirements of Ops (#192257)

This change updates the SM version requirements of Ops with the
`NVVMRequiresSM` trait to include family-specific SM versions wherever
applicable.
DeltaFile
+229-0mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir
+160-0mlir/test/Dialect/LLVMIR/nvvm_check_target_sm_trait.mlir
+0-160mlir/test/Dialect/LLVMIR/nvvm-check-targetSM.mlir
+21-20mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+410-1804 files

LLVM/project 2af998bllvm/include/llvm/IR LLVMContext.h ValueDeletionListener.h

review: make listener api's private
DeltaFile
+9-13llvm/include/llvm/IR/LLVMContext.h
+3-3llvm/include/llvm/IR/ValueDeletionListener.h
+12-162 files

LLVM/project a6d14dbclang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode cxx20.cpp

[clang][bytecode] Fix DefaultInitExpr base pointer in IndirectFieldDecls (#193149)

We built up an in correct set of init chain links, causing a
`DefaultInitExpr` later to pick the wrong base pointer. Fix this by
adding one link per decl (-1) in the `IndirectFieldDecl`.
DeltaFile
+10-6clang/lib/AST/ByteCode/Compiler.cpp
+13-0clang/test/AST/ByteCode/cxx20.cpp
+23-62 files

LLVM/project 1edcd74clang-tools-extra/clangd ModulesBuilder.cpp, clang-tools-extra/clangd/unittests PrerequisiteModulesTest.cpp

[clangd] [Modules] Refactor cache to support duplicated module name (#193413)

Following of https://github.com/llvm/llvm-project/pull/193158

Although https://github.com/llvm/llvm-project/pull/193158 handles
duplicated module name, the cache in ModulesBuilder still uses the old
assumption.

This patch tries to resolve the problem while not affecting original use
cases as much as possible. As the duplicated module name should be rare
in real world case.

AI Assisted
DeltaFile
+178-46clang-tools-extra/clangd/ModulesBuilder.cpp
+71-0clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
+249-462 files

LLVM/project a61de4bmlir/lib/Dialect/SPIRV/IR SPIRVTypes.cpp, mlir/test/Conversion/FuncToSPIRV types-to-spirv.mlir

[mlir][spirv][nfc] Clean up FP8 and BF16 SPIR-V type tests (#193196)

Rename the non-emulation check prefixes for clarity, expand FP8/BF16
test coverage in SPIR-V type and TensorArm tests, and simplify a few
type predicates in SPIRVTypes.cpp.

No functional change intended.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+146-146mlir/test/Conversion/FuncToSPIRV/types-to-spirv.mlir
+28-7mlir/test/Dialect/SPIRV/IR/types.mlir
+21-1mlir/test/Target/SPIRV/tensorARM.mlir
+4-4mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
+199-1584 files

LLVM/project bfd6ea0lld/test/ELF/linkerscript header-alloc.test sizeofheaders.s

[ELF] Improve allocateHeaders tests (#193419)
DeltaFile
+57-0lld/test/ELF/linkerscript/header-alloc.test
+0-17lld/test/ELF/linkerscript/sizeofheaders.s
+0-11lld/test/ELF/linkerscript/header-phdr2.s
+57-283 files

LLVM/project cfa6745clang-tools-extra/clangd FindTarget.cpp, clang-tools-extra/clangd/unittests FindTargetTests.cpp

[clangd] Add go-to-definition support for fields in offsetof expressions (#192953)

clangd had no handling for OffsetOfExpr in FindTarget.cpp, so
go-to-definition and find-references on field names inside
__builtin_offsetof(Type, field) produced no results.

Fix this by adding VisitOffsetOfExpr to both visitors:
- The TargetFinder visitor in add(const Stmt*) so that allTargetDecls()
resolves the referenced FieldDecl(s).
- The refInStmt visitor so that findExplicitReferences() emits a
ReferenceLoc per field component, enabling find-references and rename to
locate each field at its source position.

Each OffsetOfNode of kind Field is visited; Identifier nodes (unresolved
dependent-type designators) and Base nodes (implicit base-class
indirections) are intentionally skipped.

Repro:
```                                                                                                                                                                                                                                             

    [2 lines not shown]
DeltaFile
+62-0clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+22-0clang-tools-extra/clangd/FindTarget.cpp
+84-02 files

LLVM/project efa0f22llvm/lib/Target/RISCV/MCTargetDesc RISCVELFStreamer.cpp RISCVELFStreamer.h, llvm/test/MC/RISCV mapping-isa-option-rv32.s mapping-isa-option-rv64.s

[RISCV][MC] Emit ISA mapping symbols on .option arch/rvc/norvc/pop (#193123)

When .option arch, .option rvc, .option norvc, or .option pop changes
the active ISA, emit a "$x<ISAString>" mapping symbol before the next
instruction so that tools can determine the ISA in effect for each code
region.

Also emit ISA mapping symbols on begin of first instruction to make sure
link with different object still can disassemble correctly.

Based on #67541

---------

Co-authored-by: Joseph.Faulls <Joseph.Faulls at imgtec.com>
DeltaFile
+70-8llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+75-0llvm/test/MC/RISCV/mapping-isa-option-rv32.s
+75-0llvm/test/MC/RISCV/mapping-isa-option-rv64.s
+30-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+28-0llvm/test/MC/RISCV/mapping-isa-option-rvc-dedup.s
+17-0llvm/test/MC/RISCV/mapping-isa-attribute.s
+295-83 files not shown
+320-159 files

LLVM/project fde2e27clang/lib/Sema SemaDeclCXX.cpp, clang/test/SemaCXX warn-weak-vtables.cpp

[clang][modules] Fix false positive -Wweak-vtables in named modules (#193136)

The -Wweak-vtables warning was incorrectly firing for classes defined in
C++20 module units. This warning does not apply to module units as the
vtable should be owned by the module and emitted only once.

Fixes #193004
DeltaFile
+102-82clang/test/SemaCXX/warn-weak-vtables.cpp
+4-1clang/lib/Sema/SemaDeclCXX.cpp
+106-832 files

LLVM/project bb76209llvm/lib/Passes PassBuilderPipelines.cpp, llvm/test/Other new-pm-defaults.ll new-pm-thinlto-postlink-pgo-defaults.ll

Reapply "[JTS][Passes] Enable JTS By Default" (#193409)

Reverts llvm/llvm-project#193399

The last assertion failure seen on the BOLT buildbot should be fixed by
ee06802dc4a85b4a05ae75c1853bca8e58f76f6d.
DeltaFile
+1-5llvm/test/Other/new-pm-defaults.ll
+2-2llvm/lib/Passes/PassBuilderPipelines.cpp
+1-0llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
+7-72 files not shown
+9-78 files

LLVM/project 0f4fb3bllvm/include/llvm/MC MCPseudoProbe.h

[NFC] [MC] Fixed rule-of-five for MCPseudoProbeDecoder class (#193181)

- Added destructor for **MCPseudoProbeDecoder** class as rule of five
(https://en.cppreference.com/cpp/language/rule_of_three)
DeltaFile
+1-0llvm/include/llvm/MC/MCPseudoProbe.h
+1-01 files