[flang] Fix diagnostic order for invalid coarray dimension declarations (#219282)
Summary: Drop spurious "expected entity declarations" after missing '::'
#215886 made `withMessage()` anchor its message at the parser's start
location when no tokens matched. The nonstandard "`,` in place of `::`"
fallback for type declaration statements wraps its `,` in
`withMessage()`,
so when no `,` followed the attribute list it reported "expected entity
declarations" at the same location as the standard "expected '::'". The
two
messages tied and came out in the wrong order:
```fortran
integer :: d
real, dimension (0:d)[0:d] :: ra
end
```
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[LLDB][NativePDB] Set IsDynamicCXXType metadata for records (#155853)
All records were marked as not being a dynamic C++ type - even ones that
contain virtual methods. However, these _are_ dynamic C++ types.
With this PR, the metadata for dynamic C++ types is now set when a
record is completed and a type is considered dynamic if it has any
virtual method (e.g. destructor).
I'm not sure how to test this. I noticed this when implementing a
Microsoft ABI runtime to resolve types based on their vtables (PR TBD).
[Offload] Avoid invoking liboffload functions when uninitialized (#234645)
When libomptarget reads/detects `OMP_TARGET_OFFLOAD=disabled`, it skips
invoking `olInit()`, so subsequent calls to liboffload functions return
errors in most cases. This change adds minimal tracking of liboffload to
avoid such type of errors.
Assisted by Claude
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
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[SelectionDAG] Fix get_active_lane_mask expansion on 32-bit targets
On e.g. wasm32, OpVT can be 32 bits whilst the StepVector type can be v2i64. When this happens DAG.getConstant asserts because maxUIntN doesn't fit into the 32 bits. Fix this by clamping it to OpVT's max size.
[SelectionDAG] Handle splitting in get_active_lane_mask expansion
Split when the type is legal, e.g. v64i1, but the step vector needed for expansion needs split, e.g. v64i8.
This can happen on avx512 when the 512 bit registers are disabled.
[ConstantFolding] Add constant folding for mask.beforefirst (#234472)
Poison lanes poison the entire result, and undef elements are ignored
Assisted-by: Opus 5.5
[TableGen] Remove unused AllowSelfAssignment parameter of SetValue. NFC. (#234917)
This was added in 1e23ed9eaa7c to allow setting NAME to a reference to
itself when instantiating multiclass defs. That caller was removed in
420e28c78c9f, and since then every caller has passed false.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[clang][CFG] Fix range-for iterator initialization order (#234467)
The CFG builder adds statements in reverse execution order. Add the
range-for end declaration before the begin declaration so that the
resulting CFG initializes begin before end.
This bug was introduced in **Clang 3.9.0**. Correcting the
initialization order also restores CFGScopeBegin markers for the hidden
range and begin variables. All three hidden variables now have matching
scope-begin and scope-end markers, with scopes ending in reverse order
in the loop’s scope-exit block.
Add a regression covering distinct iterator and sentinel types with
non-trivial destructors, checking initialization and reverse destruction
order with rich constructors both enabled and disabled. Update the
affected CFG dump expectations and lifetime-safety diagnostic
expectations.
Validation: all 28 selected CFG and range-for Analysis tests and all 24
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[CIR][AArch64] Use CIR float types in getSVEType
getSVEType built the bf16 and f32 vectors from mlir::Builder's
getBF16Type() and getF32Type(), which return builtin MLIR types.
!cir.vector only accepts CIR element types, so an assertions build
aborts in VectorType::get and a release build creates an invalid type.
Use getBfloat16Ty() and getSingleTy(), as the f16 and f64 cases do.
No SVE builtin reaches these cases yet, so a lit test can't cover them.
Instead, CIRBaseBuilderTy now deletes mlir::Builder's builtin float
getters, so this mistake fails to compile.
Assisted-by: Claude Code (Claude Opus 5.5)
[LAA] Keep known dependences on retry with runtime checks (#231454)
Retrying with runtime checks cleared all recorded dependences, including
known dependences whose accesses are not checked against each other.
Interleaved access analysis could then reorder those accesses and hoist
a strided load across a store it depends on.
Drop only unknown dependences, which the runtime checks cover, and keep
known dependences to constrain reordering. This also keeps the ordering
for safe pairs that #232530 stops checking within erased classes.
The new case in `interleaved-accesses-retry-runtime-checks.ll` has an
interleave group that hoists the load of `A[2i]` above the previous
iteration's store to it; the existing case is fixed too. The LAA print
tests now list the kept dependences.
Assisted-by: Claude Code, Codex
[CIR] Restrict union tail padding to integers (#233897)
CIRGen pads a union's tail with !u8i or !cir.array<!u8i x N>, but the
verifier accepted any padding type. Other types broke consumers that
size the union: incomplete-record padding asserted in
computeStructSize, and scalable-vector padding made CallConvLowering
emit a byval of meaningless size.
The verifier now requires the padding to be an integer or an array of
integers. This also covers the earlier void-padding check.
Assisted-by: Claude Code (Claude Opus 5.5)
Reland "[mlir] Fix false positive loops in RegionBranchOpInterface::hasLoop"
Relands #233784, reverted in #234573 because it broke two CIR unit
tests.
Those tests expected hasLoop() to be true for cir.await and
cir.coroutine, although neither has a cycle: resume is reachable from
ready both directly and through suspend, and the coroutine reaches exit
and destroy along several paths. That was the false positive this change
fixes. The relanded change updates both expectations to false.
Original description:
`RegionBranchOpInterface::hasLoop` reported a loop whenever its
traversal popped a region it had already visited. The worklist gets one
entry per successor of each terminator, so a region reachable along two
paths was popped twice even without a cycle, for example when two
terminators of a region branch to the same successor region.
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[X86] Expand f32-to-bf16 conversions without libcalls (#221225)
This adds a libcall-free fallback for f32-to-bf16 conversions when
native bf16 instructions are unavailable. It was split from #221052 so
it can be reviewed independently of the denormal-mode policy discussed
there.
X86 currently lowers these conversions to `__truncsfbf2`. Vector
conversions may be scalarized into one call per lane:
```asm
callq __truncsfbf2 at PLT
callq __truncsfbf2 at PLT
; ...
```
This change reuses the generic round-to-nearest-even `expandFP_ROUND`
implementation, producing ordinary integer operations instead:
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[BOLT] Hand over test infra maintainer duties (#234103)
Former maintainer Paschalis Mpeis has handed over test infra maintainer
duties to Asher Dobrescu.
[llvm-c][IRBuilder] Restore LLVMBuilderRef unwrap (#234902)
This restores the public export of `unwrap(LLVMBuilderRef)` removed in
https://github.com/llvm/llvm-project/pull/234620. Rust uses it to extend
the C API with additional functions, which seems like a reasonable
enough use-case to support.
[clang][SPIR-V] Treat AMDGCN builtin pointers in AS 0 as generic (#234504)
In AMDGCN builtins AS 0 means flat, but SPIR-V reads it as Function
This broke flat atomics such as __builtin_amdgcn_flat_atomic_fadd_v2f16
