[LoopVectorize][NFC] Add tests for runtime checks with a widened IV index
In
if (start <u len && start - 32 <u len)
for (int32_t i = start; i < n; i++) a[i] = a[i - 32];
the distance between a[i] and a[i - 32] is always 32, but
if the vectorizer receives this loop with a widened IV to i64,
the vectorization is applied, but a runtime alias check is inserted
because widened loop may contain trunc/zext through which the
vectorizer cannot infer constant access distance.
If the loop IV is not widened, no runtime check is inserted.
Add tests for both forms.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[IndVarSimplify][NFC] Add tests for samesign compares of an IV
Add tests for folding a samesign compare of an IV with a loop-invariant
value, when the compared operands may have different signs on loop entry,
and so they can be poison.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[flang][OpenMP] Improve diagnosing invalid operators in DECLARE_REDUCTION
Move the check out of the common MakeNameFromOperator function and
into OmpStructureChecker. Remove the no longer needed SemanticsContext
parameter in MakeNameFromOperator.
This will allow reusing at least some parts of the the name-mangling
code in DECLARE_INDUCTION.
[OpenMP] Add definition of task_iteration directive (#235293)
This just adds the basic definitions of the directive (specifically the
definitions of the OMPD_task_iteration enum).
This isn't used or handled anywhere at the moment.
[OpenMP] Add definition of begin/end metadirective (#235286)
This just adds the basic definitions of the directives (specifically the
definitions of the OMPD_begin_metadirective and OMPD_end_metadirective
enums).
This isn't used or handled anywhere at the moment.
[InferAddressSpaces] Track constant-expression inttoptr/ptrtoint round trips (#234354)
Extends the existing instruction-level inttoptr/ptrtoint round-trip
tracking (introduced by #173244) to also recognize the pattern when it
appears as a constant expression, e.g. an inttoptr(ptrtoint(cast)) built
entirely out of ConstantExprs rather than instructions. This closes the
TODO left in collectIntToPtrPointerOperand() for the constant-expression
case.
---------
Co-authored-by: mmalavika <mmalavika at nvidia.com>
Co-authored-by: Sarthak Gupta <sarthagupta at nvidia.com>
perf(selectiondag): pack promoted vector bitcasts
# Symptom
Promoting an integer vector widens each element, leaving padding between
the original values. `PromoteIntOp_BITCAST` falls back to
`CreateStackStoreLoad` for these inputs, even when the result can be
assembled directly in registers.
For example:
```llvm
define <2 x i32> @pack(<16 x i4> %x) {
%r = bitcast <16 x i4> %x to <2 x i32>
ret <2 x i32> %r
}
```
# Fix
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[llubi] Add support for llvm.masked.expandload (#235867)
This is handled the same as `llvm.masked.load` except that the pointer
only increments when the mask is true.
Tests are based on the existing masked.load support.
[LLDB][Minidump] Fix BSD's unsupport failure (#235360)
BSD should also support Minidump naturally. For platform_id, we don't
see any difference between different BSD deriviatives. Set it to Unix
generic so that at least test works.
[AMDGPU] Use GFX1250Gen for gfx1250 tensor reals (NFC)
VIMAGE_TENSOR_Real_gfx1250 spelled out the predicate, decoder
namespace and encoding family that GFX1250Gen already provides. Use
Select<GFX1250Gen, ...> like other gen-based reals.
Change-Id: I7b1c70ab05337d42b10759ca78c8395a47bdc3b0
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[CI] Bump deps to Python 3.15 (#235615)
This should work fine for older python versions (e.g. 3.14), while also
working better for Python 3.15 where installation takes forever given
some packages need to build from source.
[RISCV] Remove redundant comment (#235904)
This was pointed out in #235807 and does not do any more to explain the
line of code below it than the code does.
[TableGen] Store template arguments separately from fields (#234933)
Record used to store template arguments as RecordVals in Values, along
with the fields, and keep a separate list of their names. Store them in
their own vector of RecordVals instead. getValues() now only returns
fields, so the code that skipped template arguments when inheriting,
instantiating, printing or dumping fields goes away. getValue() looks up
only fields and the new getTemplateArg() looks
up only template arguments.
A template argument is added after its default value is parsed, so that
it is still not in scope in its own default value. Duplicate template
arguments are now diagnosed in ParseDeclaration, which also avoids a
misleading type error when the duplicate has a different type.
The only change in output is that --print-detailed-records prints
"Fields: (none)" for a class with template arguments but no fields.
Parser memory usage decreases by about 1% on AMDGPU.td because
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[AMDGPU] Fix sc1 encoding of gfx940 fp atomics with AGPR results (#232060)
The *_F64 FLAT and GLOBAL atomics have separate VI and GFX940 reals,
because the VI reals are defined with has_sccb=0 and so do not encode
bit 25, which is SC1 on GFX940. However:
- #129668 removed the isGFX90AOnly predicate from the VI reals, so on
GFX940+ both the VI and GFX940 reals matched in the assembler. The
GFX940 ones happened to win because they were defined later.
- The GFX940 multiclasses did not define *_RTN_agpr reals, so the AGPR
forms of the returning atomics always used the VI reals on GFX940+.
The assembler silently dropped sc1 for these, the disassembler could
not decode them with sc1 set, and codegen dropped sc1 from the
*_RTN_agpr pseudos.
Fix this by adding *_RTN_agpr (and *_SADDR_RTN_agpr) reals to the GFX940
atomic multiclasses, and restricting the VI f64 reals to
isGFX8GFX9NotGFX940, like the neighbouring f32 and pk_f16 ones.
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