LLVM/project e1c1adaclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded vpairo.c vpaire.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded vpairo.c

Merge branch 'users/ziqingluo/PR-172429193-2-split-4' into users/ziqingluo/PR-172429193-3

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
        clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
DeltaFile
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+3,167-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
+23,549-0681 files not shown
+87,717-9,864687 files

LLVM/project 7bb5287llvm/test/CodeGen/AMDGPU minimumnum.bf16.ll maximumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

rebase

Created using spr 1.3.7
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,937 files not shown
+181,759-66,5661,943 files

LLVM/project 7a9558dllvm/test/CodeGen/AMDGPU minimumnum.bf16.ll maximumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,937 files not shown
+181,759-66,5661,943 files

LLVM/project 353a4e3llvm/test/CodeGen/AMDGPU minimumnum.bf16.ll maximumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

rebase

Created using spr 1.3.7
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,893 files not shown
+181,521-66,2151,899 files

LLVM/project ea663afllvm/test/CodeGen/AMDGPU minimumnum.bf16.ll maximumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,893 files not shown
+181,521-66,2151,899 files

LLVM/project a45b6b0llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

rebase

Created using spr 1.3.7
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,896 files not shown
+181,885-66,3201,902 files

LLVM/project 77a2da1llvm/test/CodeGen/AMDGPU minimumnum.bf16.ll maximumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,896 files not shown
+181,885-66,3201,902 files

LLVM/project a218593llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

rebase

Created using spr 1.3.7
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,894 files not shown
+181,522-66,2791,900 files

LLVM/project 8863fd3llvm/test/CodeGen/AMDGPU minimumnum.bf16.ll maximumnum.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+2,843-799llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+26,290-12,3011,894 files not shown
+181,522-66,2791,900 files

LLVM/project 6643213mlir/lib/Dialect/SPIRV/IR SPIRVOps.cpp, mlir/test/Dialect/SPIRV/IR structure-ops.mlir

[mlir][SPIR-V] Reject initializer on Import-linkage GlobalVariable (#192302)

Per the SPIR-V spec, a module-scope OpVariable with Import linkage must
not have an initializer
DeltaFile
+13-0mlir/test/Dialect/SPIRV/IR/structure-ops.mlir
+11-0mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
+24-02 files

LLVM/project e7ef07bclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded vpaire.c vpairo.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded vpaire.c

Merge branch 'users/ziqingluo/PR-172429193-2-split-3' into users/ziqingluo/PR-172429193-2-split-4

 Conflicts:
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
DeltaFile
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+3,167-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
+23,549-0681 files not shown
+87,725-9,867687 files

LLVM/project 47f1c1aclang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel EntityPointerLevel.h, clang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.cpp SSAFAnalysesCommon.h

clean up
DeltaFile
+3-6clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
+2-2clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
+1-1clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
+1-1clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
+7-104 files

LLVM/project 90f53aallvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU add.v2i16.ll sub.v2i16.ll

[AMDGPU] Add true16 patterns for build_vector (vgpr, 0)

It is shorter than VOP3 and instruction and in some cases
can save a second move.
DeltaFile
+8-10llvm/test/CodeGen/AMDGPU/add.v2i16.ll
+8-10llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
+7-5llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
+4-8llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+10-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2-8llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
+39-414 files not shown
+48-5010 files

LLVM/project cbe6493llvm/test/CodeGen/AMDGPU minimumnum.bf16.ll maximumnum.bf16.ll

[AMDGPU] Enable true16 pattern to build vectors (0, vgpr) (#191896)

Fixes: https://github.com/llvm/llvm-project/issues/190796
DeltaFile
+3,326-2,794llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,326-2,794llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+695-1,374llvm/test/CodeGen/AMDGPU/bf16.ll
+434-423llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+342-360llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+342-360llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+8,465-8,10541 files not shown
+12,940-12,86847 files

LLVM/project ae4a02fllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU asyncmark-gfx12plus.ll llvm.amdgcn.global.load.async.to.lds.ll

AMDGPU/GlobalISel: RegBankLegalize rules for async LDS loads (#192179)

Add RegBankLegalize rules for async LDS load intrinsics:
llvm.amdgcn.asyncmark
llvm.amdgcn.wait.asyncmark
llvm.amdgcn.global.load.async.to.lds.b8
llvm.amdgcn.global.load.async.to.lds.b32
llvm.amdgcn.global.load.async.to.lds.b64
llvm.amdgcn.global.load.async.to.lds.b128
DeltaFile
+94-76llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
+34-13llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
+129-903 files

LLVM/project 5c92853clang/include/clang/Serialization InMemoryModuleCache.h, clang/lib/Frontend CompilerInstance.cpp

[clang] Store size & mtime in in-memory module cache (#190207)

In this PR, the in-memory module cache now stores the size and
modification time of PCM files. This is needed so that the
`ModuleManager` doesn't need to consult the file system to obtain this
information, which _might_ be in a different state than when we stored
the PCM file buffer into the in-memory cache.
DeltaFile
+22-14clang/unittests/Serialization/InMemoryModuleCacheTest.cpp
+24-11clang/include/clang/Serialization/InMemoryModuleCache.h
+9-25clang/lib/Serialization/ModuleManager.cpp
+13-5clang/lib/Serialization/InMemoryModuleCache.cpp
+13-3clang/lib/Serialization/ModuleCache.cpp
+5-3clang/lib/Frontend/CompilerInstance.cpp
+86-614 files not shown
+100-6910 files

LLVM/project 1202ddcllvm/lib/Target/AMDGPU AMDGPUSearchableTables.td, llvm/test/Analysis/UniformityAnalysis/AMDGPU always_uniform.ll

[AMDGPU] Mark s_get_*_barrier_state intrinsics always uniform (#192190)

Both intrinsics return a 32-bit SGPR value containing the barrier's
member count and signal count.
DeltaFile
+16-0llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
+2-0llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+18-02 files

LLVM/project c859d7ellvm/lib/DebugInfo/DWARF DWARFAcceleratorTable.cpp

[llvm][DebugInfo] Use formatv in DWARFAcceleratorTable (#191981)

This relates to #35980.
DeltaFile
+9-9llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
+9-91 files

LLVM/project 957f6f6llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.buffer.prefetch.data.ll

AMDGPU/GlobalISel: RegBankLegalize rules for G_AMDGPU_S_BUFFER_PREFETCH (#191315)
DeltaFile
+16-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
+12-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+3-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+32-14 files

LLVM/project 7c08b8ecompiler-rt/lib/hwasan hwasan_mapping.h

[compiler-rt][Fuchsia] Use dynamic shadow global in hwasan runtime (#192148)

For now, the global is still default initialized to zero.
DeltaFile
+1-1compiler-rt/lib/hwasan/hwasan_mapping.h
+1-11 files

LLVM/project 35dcb5cclang/lib/CIR/CodeGen CIRGenDecl.cpp CIRGenFunction.h, clang/test/CIR/CodeGen cleanup-automatic-eh.cpp

[CIR] Add EH handling for lifetime extended cleanups (#192305)

This adds code to call pushDestroyAndDeferDeactivation from the
pushLifetimeExtendedDestroy function. This was needed to generate the
correct code for lifetime extended cleanups when exceptions are enabled.
An extended version of the cleanup with automatic storage duration is
used as a test case.

To make this work correctly, I had to add a CleanupDeactivationScope to
RunCleanupsScope and force deactivation when forceCleanup is called.
This matches the corresponding code in classic codegen.

I surveyed other places where classic codegen is using
CleanupDeactivationScope and added a MissingFeatures marker in one
location where it was not previously marked. Other places where it was
missing were already marked in this way.
DeltaFile
+62-0clang/test/CIR/CodeGen/cleanup-automatic-eh.cpp
+4-9clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+3-1clang/lib/CIR/CodeGen/CIRGenFunction.h
+1-0clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
+70-104 files

LLVM/project e540f80flang/include/flang/Optimizer/Dialect FIROps.td, flang/lib/Optimizer/Dialect FIROps.cpp

[flang] implements a rewrite pattern to constant fold fir::BoxEleSizeOp (#192320)

Implements a rewrite pattern to constant fold an `fir::BoxEleSizeOp`
when possible.
DeltaFile
+105-0flang/test/Fir/box-elesize-canonicalize.fir
+61-0flang/lib/Optimizer/Dialect/FIROps.cpp
+1-2flang/test/Lower/volatile-string.f90
+2-0flang/include/flang/Optimizer/Dialect/FIROps.td
+169-24 files

LLVM/project 89e736dflang/lib/Optimizer/Analysis AliasAnalysis.cpp, flang/test/Analysis/AliasAnalysis modref-call-memory-effects.fir

[flang][test] Experimental support of MemoryEffectOpInterface for fir.call. (#191580)

I would like to experiment with `fir.call` implementing
`MemoryEffectOpInterface`. So the main change is the fall-through
path in FIR AA. It should be NFC for Flang.
DeltaFile
+49-0flang/test/lib/Analysis/AliasAnalysis/TestAliasAnalysis.cpp
+28-0flang/test/Analysis/AliasAnalysis/modref-call-memory-effects.fir
+7-2flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+84-23 files

LLVM/project 25ccdfaclang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.h

fix build issue
DeltaFile
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
+1-01 files

LLVM/project bae2eadclang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.cpp

fix merge issues
DeltaFile
+4-1clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
+4-11 files

LLVM/project 1f93b92clang/lib/Sema SemaAttr.cpp

concise findCXXNewExpr
DeltaFile
+2-3clang/lib/Sema/SemaAttr.cpp
+2-31 files

LLVM/project cdfd0b6clang/lib/Headers __clang_cuda_runtime_wrapper.h

[CUDA] Change __CUDACC__ definition to 1 (#189457)

I recently encountered an issue where `nccl` used `#if __CUDACC__` ,
assuming `__CUDACC__` is not only defined but having a #if-able value.


https://github.com/NVIDIA/nccl/blob/v2.28.3-1/src/include/nccl_device/coop.h#L18

Looking at nvcc invocation, I see that:
```
echo "" | nvcc -x cu -E -Xcompiler -dM - | grep __CUDACC__
#define __CUDACC__ 1
```

Changing __CUDACC__ to 1 to match what NVIDIA downstream code
assumptions.
DeltaFile
+5-5clang/lib/Headers/__clang_cuda_runtime_wrapper.h
+5-51 files

LLVM/project 7b24f05clang/lib/Sema SemaAttr.cpp

format
DeltaFile
+5-5clang/lib/Sema/SemaAttr.cpp
+5-51 files

LLVM/project e9c0b9cclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded vpaire.c vpairo.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded vpairo.c

Merge branch 'users/ziqingluo/PR-172429193-2-split-2' into users/ziqingluo/PR-172429193-2-split-3

 Conflicts:
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
DeltaFile
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+3,167-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
+23,549-0680 files not shown
+87,720-9,859686 files

LLVM/project f95a9b3clang/lib/Sema SemaAttr.cpp

add docs
DeltaFile
+4-0clang/lib/Sema/SemaAttr.cpp
+4-01 files