[libc][math] Add iscanonical functions to math.yaml
Surface the existing iscanonical, iscanonicalbf16, iscanonicalf, iscanonicalf128, iscanonicalf16, and iscanonicall
implementations through the generated math.h.
To test:
`cmake -Bbuild -Sruntimes -GNinja -DLLVM_ENABLE_RUNTIMES=libc -DLLVM_LIBC_FULL_BUILD=ON`
`pip install pyyaml`
`ninja -C build libc.include.math.__generated_hdr__`
Then check `build/libc/include/math.h` for their signatures.
Add `-DLIBC_TYPES_HAS_FLOAT128=ON` to test for iscanonicalf128
in cmake invocation if host does not support it.
And `LIBC_TYPES_HAS_FLOAT16=ON` for iscanonicalf16.
[RISCV][TTI] Make getShuffleCost check we have a vector before querying getVectorElementCount (#199286)
Fixes the assert reported here:
<https://github.com/llvm/llvm-project/pull/198446#issuecomment-4522589671>
I believe this happens when the element type isn't a legal RVV element
type and so has been scalarised by type legalisation.
Adding this guard also matches the AArch64 implementation.
The test change is LLM generated.
[Clang][CodeGen] map `noescape` to capture(address) (was capture(none)) (#199281)
`capture(none)` has very restrictive semantics and an easy footgun to
accidentally fire some UB into your code with. Most significantly it
does not allow any visible side-effects of whether a pointer was null or
not to escape the function. This means that the function cannot perform
different side effects depending on whether a pointer marked `noescape`
is null. Relax this to `captures(address)`, which allows information
about the numerical address to escape the function, but no provenance
(i.e. nothing that could be dereferenced) may escape.
As discussed in
https://discourse.llvm.org/t/rfc-updating-the-semantics-of-the-noescape-attribute/90326.
[MLIR][XeGPU]Extend load_matrix/store_matrix to support 1D SLM access (#198652)
This PR extended xegpu.load_matrix and xegpu.store_matrix to support 1D
mem_desc for contiguous SLM access
- Added unit tests for 1D load/store (valid ops and invalid cases)
- Added integration test verifying both 1D (<4096xbf16>) and 2D
(<64x128xbf16>), correctly lower through the full WG→SG→WI→XeVM pipeline
---------
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
[libc][math] Add iscanonical functions to math.yaml
Surface the existing iscanonical, iscanonicalbf16, fiscanonicalf, iscanonicalf128, iscanonicalf16, and iscanonicall
implementations through the generated math.h.
To test:
`cmake -Bbuild -Sruntimes -GNinja -DLLVM_ENABLE_RUNTIMES=libc -DLLVM_LIBC_FULL_BUILD=ON`
`pip install pyyaml`
`ninja -C build libc.include.math.__generated_hdr__`
Then check `build/libc/include/math.h` for their signatures.
Add `-DLIBC_TYPES_HAS_FLOAT128=ON` to test for iscanonicalf128
in cmake invocation if host does not support it.
[VPlan][test] Fix use-after-free in dumpRecipeInPlan/dumpRecipeUnnamedVPValuesInPlan tests (#199275)
https://github.com/llvm/llvm-project/pull/195891 exposed a
use-after-free in the tests: `BinaryOperator *AI` [*] is deleted prior
to VPlan's destructor, which expects all the operands to still be alive.
This patch fixes the test (suggested by a Florian in
https://github.com/llvm/llvm-project/pull/199252#pullrequestreview-4348337988),
by preemptively detaching AI from the VPlan.
[*] No AI was harmed or used during the creation of this patch.
[Instrumentor] Add Cast instruction instrumentation support
We now allow to have instrumentation opportunities for many instructions
(=opcodes) to bundle common classes together. Users can use filters on
the opcode, type-id, and size to statically select what they are
interested in.
[X86] Stop claiming f128 CT_SELECT Custom; regen ctselect tests
X86's LowerCT_SELECT falls through to X86ISD::CT_SELECT for any FP
type it claims Custom but doesn't special-case (only f80 has the
three-i32-chunk path, and scalar f32/f64 the SSE register path).
For f128 the fall-through produces an X86ISD::CT_SELECT with f128
result type, for which no isel pattern exists, and selection
ICEs with "Cannot select".
Drop f128 from the CT_SELECT Custom loop so the generic legalizer's
memory-blend path (recently added in the core PR) handles it.
Regenerate CHECK lines for all X86 ctselect tests to reflect the
expanded coverage (half/bfloat/fp80/fp128) introduced upstream.
[X86] Restore combineSelect BLENDV sign-bit fold
The optimization that folds X86ISD::BLENDV away when the condition's
sign bit is statically known was inadvertently dropped during a prior
rebase conflict resolution. Its absence caused unrelated CHECK lines
in combine-sdiv.ll, vector-compress.ll, vector-idiv-{u,s}div-*.ll to
fail because main expects the post-optimization codegen.
Restores the block at llvm/lib/Target/X86/X86ISelLowering.cpp line
~49587 (after combineLogicBlendIntoConditionalNegate, before the
VSELECT/BLENDV shuffle handling), matching origin/main verbatim.
[LLVM][X86] Add f80 support for ct.select
Add special handling for x86_fp80 types in CTSELECT lowering by splitting
them into three 32-bit chunks, performing constant-time selection on each
chunk, and reassembling the result. This fixes crashes when compiling
tests with f80 types.
Also updated ctselect.ll to match current generic fallback implementation.
[LLVM][X86] Add native ct.select support for X86 and i386
Add native X86 implementation with CMOV instructions and comprehensive tests:
- X86 ISelLowering with CMOV for x86_64 and i386
- Fallback bitwise operations for i386 targets without CMOV
- Post-RA expansion for pseudo-instructions
- Comprehensive test coverage:
- Edge cases (zero conditions, large integers)
- i386-specific tests (FP, MMX, non-CMOV fallback)
- Vector operations
- Optimization patterns
The basic test demonstrating fallback is in the core infrastructure PR.
[ARM] Regen ctselect tests for new core legalization
The core PR moved CT_SELECT lowering into the generic legalizer
(memory-blend for FP types without a legal same-size integer,
scalar-mask+splat for vectors). ARM tests' CHECK lines need to
reflect the new codegen.
No functional change in ARM target lowering itself; only test
expectations updated to match generated output.
[ARM] Restore STRICT FP setup, byval pre-load fix, bundle predicate
A prior rebase conflict resolution accidentally dropped several
unrelated pieces of upstream ARM code:
- ARMISelLowering: STRICT_FP_ROUND/FMINNUM/FMAXNUM/FP_EXTEND
setOperationAction calls (from d08b0f7240aa "Disable strict node
mutation"), the STRICT_FP_TO_SINT/UINT i32 unconditional setup,
the STRICT_FP16_TO_FP Expand fallback (reverted from LibCall), the
byval pre-load fix in LowerCall (from a01a921004c1), and the
IsStrictFPEnabled=true line at the end of the constructor.
- ARMTargetMachine: broadened createUnpackMachineBundlesLegacy from
the Thumb2/KCFI predicate to nullptr (unconditional).
These deletions caused CHECK-line mismatches in fp16-fullfp16.ll,
fp-intrinsics-vector.ll, and byval_struct_copy_tailcall.ll. None of
the affected tests use llvm.ct.select.
Restores the upstream code verbatim; ct.select work is unaffected.
[LLVM][ARM] Add native ct.select support for ARM32 and Thumb
This patch implements architecture-specific lowering for ct.select on ARM
(both ARM32 and Thumb modes) using conditional move instructions and
bitwise operations for constant-time selection.
Implementation details:
- Uses pseudo-instructions that are expanded Post-RA to bitwise operations
- Post-RA expansion in ARMBaseInstrInfo for BUNDLE pseudo-instructions
- Handles scalar integer types, floating-point, and half-precision types
- Handles vector types with NEON when available
- Support for both ARM and Thumb instruction sets (Thumb1 and Thumb2)
- Special handling for Thumb1 which lacks conditional execution
- Comprehensive test coverage including half-precision and vectors
The implementation includes:
- ISelLowering: Custom lowering to CTSELECT pseudo-instructions
- ISelDAGToDAG: Selection of appropriate pseudo-instructions
- BaseInstrInfo: Post-RA expansion of BUNDLE to bitwise instruction sequences
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