LLVM/project c35e66elibc/test/src/__support/wctype CMakeLists.txt

reduce constexpr steps
DeltaFile
+2-2libc/test/src/__support/wctype/CMakeLists.txt
+2-21 files

LLVM/project 40fb302flang/test/Parser/OpenMP nonblock-do-nested-omp.f90

Remove OpenMP version from test
DeltaFile
+2-2flang/test/Parser/OpenMP/nonblock-do-nested-omp.f90
+2-21 files

LLVM/project 9931b78clang/lib/Driver/ToolChains Cuda.cpp AMDGPU.cpp, clang/test/Driver amdgpu-multilib.yaml nvptx-multilib.yaml

[Clang] Add multilib support for GPU targets (#192285)

Summary:
This PR uses the new, generic multilib support added in
https://github.com/llvm/llvm-project/pull/188584
to also function for GPU targets. This will allow toolchains to easy
provide variants of these GPU libraries (for debug or asan). In
practice, this will look something like this:

```console
  -DRUNTIMES_amdgcn-amd-amdhsa+debug_CMAKE_BUILD_TYPE=Debug \
  -DRUNTIMES_amdgcn-amd-amdhsa+debug_LIBOMPTARGET_ENABLE_DEBUG=ON \
  -DRUNTIMES_amdgcn-amd-amdhsa+debug_LLVM_ENABLE_RUNTIMES=openmp \
  -DLLVM_RUNTIME_MULTILIBS=debug \
  -DLLVM_RUNTIME_MULTILIB_debug_TARGETS="amdgcn-amd-amdhsa" \
```

This will then install it into the tree like this:
```

    [7 lines not shown]
DeltaFile
+80-0clang/test/Driver/amdgpu-multilib.yaml
+80-0clang/test/Driver/nvptx-multilib.yaml
+15-1clang/lib/Driver/ToolChains/Cuda.cpp
+14-0clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-0clang/lib/Driver/ToolChains/Clang.cpp
+190-15 files

LLVM/project 02589e1flang/lib/Parser openmp-parsers.cpp, flang/test/Parser/OpenMP nonblock-do-nested-omp.f90

[flang][OpenMP] Get final label from nested constructs

Non-block DO loops can share termination statements. When parsing
a non-block DO loop, account for labels on terminating statements
from recursively parsed ExecutionPartConstructs.

Fixes https://github.com/llvm/llvm-project/issues/188892
DeltaFile
+88-0flang/test/Parser/OpenMP/nonblock-do-nested-omp.f90
+6-0flang/lib/Parser/openmp-parsers.cpp
+94-02 files

LLVM/project 8d8be91libc/src/__support/wctype perfect_hash_map.h, libc/test/src/__support/wctype wctype_perfect_hash_test.cpp

Apply code review
DeltaFile
+67-62libc/src/__support/wctype/perfect_hash_map.h
+6-0libc/test/src/__support/wctype/wctype_perfect_hash_test.cpp
+73-622 files

LLVM/project ca3bc44flang/lib/Optimizer/Builder IntrinsicCall.cpp, flang/test/Lower/Intrinsics transfer.f90

[flang] Inline scalar-to-scalar TRANSFER for same-size trivial types (#191589)

Inline the TRANSFER intrinsic for scalar-to-scalar cases where the
result is a trivial type (integer, real, etc.) and source and result
have the same storage size. Instead of calling _FortranATransfer, the
lowering now emits a fir.convert on the source address followed by a
fir.load, effectively performing a reinterpret cast.
DeltaFile
+105-8flang/test/Lower/Intrinsics/transfer.f90
+33-2flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+138-102 files

LLVM/project 38f3d0bllvm/lib/CodeGen MachineCopyPropagation.cpp, llvm/test/CodeGen/X86 machine-copy-prop.mir

[MCP] Never eliminate frame-setup/destroy instructions (#186237)

Presumably targets only insert frame instructions which are significant,
and there may be effects MCP doesn't model. Similar to reserved
registers this
is probably overly conservative, but as this causes no codegen change in
any lit test I think it is benign.

The motivation is just to clean up #183149 for AMDGPU, as we can spill
to physical registers, and currently have to spill the EXEC mask purely
to enable debug-info.

Change-Id: I9ea4a09b34464c43322edd2900361bf635efd9f7
DeltaFile
+22-0llvm/test/CodeGen/X86/machine-copy-prop.mir
+11-5llvm/lib/CodeGen/MachineCopyPropagation.cpp
+33-52 files

LLVM/project 2086b87clang/docs ReleaseNotes.rst, clang/include/clang/AST CommentSema.h

[clang] Fix false positive with -Wdocumentation and explicit instanti… (#178223)

…ations

Solves a use case listed in #64087.
DeltaFile
+19-0clang/lib/AST/CommentSema.cpp
+10-0clang/test/Sema/warn-documentation.cpp
+3-0clang/docs/ReleaseNotes.rst
+1-0clang/include/clang/AST/CommentSema.h
+33-04 files

LLVM/project 45dd0d7clang/cmake/caches Fuchsia-stage2.cmake

Revert "[Fuchsia] Stack analysis flags for runtimes (#175677)"

This reverts commit aacda8da6bc66287f45712c7b334ed552f315fcc.
DeltaFile
+5-5clang/cmake/caches/Fuchsia-stage2.cmake
+5-51 files

LLVM/project 23dcca9llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.cluster.id.ll llvm.amdgcn.workitem.id.ll

Revert "[AMDGPU] InstCombine: fold invalid calls to amdgcn intrinsics into poison values" (#192514)

Reverts llvm/llvm-project#191904
DeltaFile
+0-80llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.cluster.id.ll
+0-57llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workitem.id.ll
+0-57llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workgroup.id.ll
+0-55llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+0-48llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
+0-48llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.queue.ptr.ll
+0-3452 files not shown
+0-4098 files

LLVM/project 5aea02aoffload/test/api omp_indirect_func_struct.c omp_indirect_call_table_manual.c, openmp/device/src Misc.cpp

[OpenMP][Device] Fix __llvm_omp_indirect_call_lookup function pointer types (#192502)

`__llvm_omp_indirect_call_lookup` takes in and returns a function
pointer, so make sure the types are correct, which includes the correct
address space.

The FE was recently changed to generate the correct code
[here](https://github.com/llvm/llvm-project/pull/192470).

With this change, three function pointer tests start passing.

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+4-4openmp/device/src/Misc.cpp
+0-1offload/test/api/omp_indirect_func_struct.c
+0-1offload/test/api/omp_indirect_call_table_manual.c
+0-1offload/test/api/omp_indirect_func_array.c
+4-74 files

LLVM/project 6b054fdclang/lib/CIR/CodeGen CIRGenDecl.cpp CIRGenFunction.h, clang/test/CIR/CodeGen field-init-eh.cpp

[CIR] Implement EH handling for field initializers (#192360)

This implements the handling to call the dtor for any previously
initialized fields of destructed type if an exception is thrown later in
the initialization of the containing class.

The basic infrastructure to handle this was already in place. We just
needed a function to push an EH-only destroy cleanup on the EH stack and
a call to that function.
DeltaFile
+83-0clang/test/CIR/CodeGen/field-init-eh.cpp
+11-0clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+3-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+1-2clang/lib/CIR/CodeGen/CIRGenClass.cpp
+98-24 files

LLVM/project 0bbfddfllvm/test/Transforms/SLPVectorizer/AArch64 spillcost-call-between-operands.ll

[SLP][NFC]Add a test with the incorrect spill cost calculation between operands



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/192509
DeltaFile
+45-0llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-call-between-operands.ll
+45-01 files

LLVM/project 2427dc4llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC] Remove unused PtrN parameter from analyzeConstantStrideCandidate() (#191567)
DeltaFile
+6-6llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+6-61 files

LLVM/project 95389ddllvm/lib/Target/AMDGPU AMDGPUMCInstLower.cpp SIInstrInfo.cpp

AMDGPU: Implement getInstSizeVerifyMode

Replace the custom instruction size check.
DeltaFile
+0-22llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+7-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+10-223 files

LLVM/project af01d27llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen TargetInstrInfo.cpp

Bundle size in all targets
DeltaFile
+1-12llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+1-12llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+1-12llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+0-12llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+12-0llvm/lib/CodeGen/TargetInstrInfo.cpp
+8-0llvm/include/llvm/CodeGen/TargetInstrInfo.h
+23-4812 files not shown
+40-5518 files

LLVM/project 81c4cebmlir/include/mlir/Dialect/SPIRV/IR SPIRVLogicalOps.td SPIRVBase.td, mlir/test/Dialect/SPIRV/IR logical-ops.mlir

[mlir][SPIR-V] Add spirv.Any and spirv.All ops (#192286)
DeltaFile
+94-0mlir/test/Dialect/SPIRV/IR/logical-ops.mlir
+64-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
+10-0mlir/test/Target/SPIRV/logical-ops.mlir
+3-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+171-04 files

LLVM/project 8b15fc1clang/lib/CIR/Dialect/Transforms FlattenCFG.cpp

[CIR] Fix FlattenCFG pattern rewriter contract violations (#192359)

Fix patterns in CIRFlattenCFGPass that modify IR but return failure(),
violating the MLIR greedy pattern rewriter contract. The contract
requires that if a pattern modifies IR, it must return success().

- CIRCleanupScopeOpFlattening: always return success() since IR is
modified (blocks split, regions inlined) before error paths
- Ternary op flattening: return success() instead of falling through
after emitError, since splitBlock/createBlock already modified IR
- Use rewriter.moveOpBefore() instead of direct defOp->moveBefore() to
properly notify the rewriter of IR mutations

Found by MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
Test: flatten-cleanup-scope-nyi.cir (a silly one since it's testing an
error, but point still valid)
DeltaFile
+18-5clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+18-51 files

LLVM/project 6c2bf97llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.cluster.id.ll llvm.amdgcn.workgroup.id.ll

[AMDGPU] InstCombine: fold invalid calls to amdgcn intrinsics into poison values (#191904)

Replace a call to amdgpu intrinsic into a poison value when the call is
invalid because of "amdgpu-no-<xyz>" attribute in the caller function.

Upon
https://github.com/llvm/llvm-project/pull/186925#pullrequestreview-3983414064

Assisted by claude-4.6-sonnet-medium through CURSOR.
DeltaFile
+80-0llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.cluster.id.ll
+57-0llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workgroup.id.ll
+57-0llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.workitem.id.ll
+55-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+48-0llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.queue.ptr.ll
+48-0llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
+345-02 files not shown
+409-08 files

LLVM/project 9ff4276llvm/utils/gn/secondary/llvm/lib/Transforms/Utils BUILD.gn

[gn build] Port ffde06f4c119 (#192498)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
+1-01 files

LLVM/project 0feabfallvm/utils/gn/secondary/llvm/lib/Target/AMDGPU BUILD.gn

[gn build] Port b9ae01500d8b (#192496)

[gn build] Port b9ae01500d8b
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
+1-01 files

LLVM/project 7937297libsycl/include/sycl/__impl queue.hpp, libsycl/include/sycl/__impl/detail unified_range_view.hpp get_device_kernel_info.hpp

single_task on top of getKernelInfo

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+111-0libsycl/src/detail/queue_impl.cpp
+99-0libsycl/include/sycl/__impl/queue.hpp
+51-0libsycl/include/sycl/__impl/detail/unified_range_view.hpp
+43-0libsycl/include/sycl/__impl/detail/get_device_kernel_info.hpp
+39-0libsycl/src/detail/queue_impl.hpp
+19-0libsycl/src/queue.cpp
+362-04 files not shown
+391-010 files

LLVM/project 6ee930cclang/include/clang/Options Options.td, clang/test/Driver cl-options.c

[clang] Expose -fdiagnostics-show-inlining-chain to clang-cl (#192241)
DeltaFile
+2-2clang/include/clang/Options/Options.td
+2-0clang/test/Driver/cl-options.c
+4-22 files

LLVM/project db9132elldb/include/lldb/Interpreter OptionGroupVariable.h, lldb/source/Interpreter OptionGroupVariable.cpp

[lldb] Reformat OptionGroupVariable.{h,cpp}, NFC. (#192395)


This patch runs clang-format on OptionGroupVariable.{h,cpp}.
DeltaFile
+84-21lldb/source/Interpreter/OptionGroupVariable.cpp
+3-3lldb/include/lldb/Interpreter/OptionGroupVariable.h
+87-242 files

LLVM/project 53368bfclang/lib/CIR/CodeGen CIRGenAsm.cpp, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Fix InlineAsmOp roundtrip parse crash on cir.asm (#186588)

Fix InlineAsmOp parser/printer roundtrip for cir.asm and avoid null
operand_attrs entries that crash alias printing during
--verify-roundtrip.

- Parse attr-dict before optional result arrow to match print order.

- Use non-null sentinel attributes for non-maybe_memory operands and
check UnitAttr explicitly.

- Keep lowering semantics by treating only UnitAttr as maybe_memory
marker.

- Update inline-asm CIR IR test to run with --verify-roundtrip and add
an attr+result coverage case.

Fix https://github.com/llvm/llvm-project/issues/161441
DeltaFile
+15-1clang/test/CIR/IR/inline-asm.cir
+5-5clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+1-1clang/lib/CIR/CodeGen/CIRGenAsm.cpp
+1-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+22-84 files

LLVM/project f666cf5llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

CodeGen: Fix double counting bundles in inst size verification

The AMDGPU implementation handles bundles by summing the
member instructions. This was starting with the size of the
bundle instruction, then re-adding all of the same instructions.

This loop is over the iterator, not instr_iterator, so it should
not be looking through the bundled instructions. Most of the other
uses of getInstSizeInBytes are also on the iterator, not the
instr_iterator so the convention seems to be targets need to handle
BUNDLE correctly themselves.
DeltaFile
+0-7llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+0-71 files

LLVM/project a109303compiler-rt/lib/tysan tysan.cpp

[TySan] Set and cache tool name. (#192410)

Partial reland of [sanitizer common
support](https://github.com/llvm/llvm-project/pull/183310)
DeltaFile
+3-0compiler-rt/lib/tysan/tysan.cpp
+3-01 files

LLVM/project 3091b98clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGen global-array-dtor.cpp global-init.cpp

[CIR] Add noundef to __cxx_global_array_dtor parameter (#191529)

The synthetic __cxx_global_array_dtor helper created by
LoweringPrepare was missing noundef on its ptr parameter,
causing a mismatch with classic codegen.
DeltaFile
+10-0clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+1-1clang/test/CIR/CodeGen/global-array-dtor.cpp
+1-1clang/test/CIR/CodeGen/global-init.cpp
+12-23 files

LLVM/project 796302aclang/test/CIR global-var-simple.cpp

[CIR][NFC] Remove redundant global-var-simple.cpp test (#192354)

This early smoke test is fully covered by
`clang/test/CIR/CodeGen/globals.cpp` and is no longer needed.

Per @andykaylor's feedback on #191521.

Made with [Cursor](https://cursor.com)
DeltaFile
+0-101clang/test/CIR/global-var-simple.cpp
+0-1011 files

LLVM/project fd8b58cmlir/test/Dialect/SPIRV/IR group-ops.mlir non-uniform-ops.mlir

[mlir][spirv][nfc] Move GroupNonUniformBallotBitCount tests to `non-uniform-ops.mlir` (#192115)

Tests were incorrectly placed in `group-ops.mlir` since the op is
defined in `SPIRVNonUniformOps.td`.
DeltaFile
+0-60mlir/test/Dialect/SPIRV/IR/group-ops.mlir
+60-0mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
+60-602 files