LLVM/project 5ae6537mlir/lib/Conversion/MemRefToEmitC MemRefToEmitC.cpp, mlir/test/Conversion/FuncToEmitC func-to-emitc-failed.mlir

[mlir][EmitC] Add rank-0 MemRef conversion (#205774)

Add rank-0 memref support to MemRefToEmitC and the EmitC TypeConverter,
needed for lowering the models generated by:
- `llvm/lib/Analysis/models/gen-inline-oz-test-model.py`
- `llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py`

Rank-0 memrefs are no longer rejected by `isMemRefTypeLegalForEmitC`.
The EmitC type converter maps `memref<T>` to `!emitc.ptr<T>`, giving
rank-0 memrefs addressable scalar storage.

`memref.alloc` now allocates one element for rank-0 memrefs.
`memref.dealloc` frees the pointer-backed value. `memref.load` and
`memref.store` lower rank-0 accesses through `emitc.subscript %ptr[0]`,
followed by `emitc.load` or `emitc.assign`. `memref.copy` lowers rank-0
copies as scalar load plus assign.

`memref.alloca` still rejects rank-0 memrefs because this patch only
supports pointer-backed rank-0 lowering.

    [11 lines not shown]
DeltaFile
+77-35mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
+48-0mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
+26-0mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
+21-0mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
+0-15mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
+9-0mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
+181-502 files not shown
+183-598 files

LLVM/project 73a43a8llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp SPIRVNonSemanticDebugHandler.h, llvm/test/CodeGen/SPIRV/debug-info debug-global-variable-path-null.ll debug-global-variable-static-member.ll

Remove dead code and add missing tests.
DeltaFile
+49-0llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-path-null.ll
+40-0llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-static-member.ll
+11-10llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+3-6llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+103-164 files

LLVM/project 4b32060llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 bitreverse.ll

[X86] Use BMM for bitreverse without GFNI (#209223)

For the scalar path bitreverse currently doesn't lower to vbitrevb on
AVX512-BMM unless GFNI is specified as well. However, GFNI isn't
required at all for this and only BMM needs to be present.

See https://godbolt.org/z/xr61xYzYr
DeltaFile
+169-0llvm/test/CodeGen/X86/bitreverse.ll
+7-2llvm/lib/Target/X86/X86ISelLowering.cpp
+176-22 files

LLVM/project cd75ff0llvm/lib/Transforms/Vectorize VPlan.h, llvm/unittests/Transforms/Vectorize VPlanTest.cpp

[VPlan] Type VP(Recipe|Block)Ty SubclassID (NFC) (#209132)

With the advantage that switching over the SubclassID would give better
compile-time diagnostics.

Co-authored-by: Luke Lau <luke at igalia.com>
DeltaFile
+36-35llvm/lib/Transforms/Vectorize/VPlan.h
+1-1llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
+37-362 files

LLVM/project f5a55b5mlir/include/mlir/TableGen Format.h

[MLIR][NFC] Fix tgfmt compilation with MSVC (#209446)

Apparently older MSVC has problems with inferring template argument
types. Provide them explicitly.

Fixes https://github.com/llvm/llvm-project/issues/209303.
DeltaFile
+3-3mlir/include/mlir/TableGen/Format.h
+3-31 files

LLVM/project 2698209llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.umax.ll llvm.amdgcn.reduce.umin.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (21) (#209212)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+108-10894 files not shown
+491-491100 files

LLVM/project 0c36950utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fixes 16094a8 (#209435)

This fixes 16094a86a6cfe79fa50dcca39b539ab6465b8ac0.

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=16094a86a6cfe79fa50dcca39b539ab6465b8ac0

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project 42d52dfllvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/GlobalISel Utils.cpp

[SelectionDAG] Update MemOp to distinguish memmove from memcpy (#206005)
DeltaFile
+44-27llvm/include/llvm/CodeGen/TargetLowering.h
+5-4llvm/lib/CodeGen/GlobalISel/Utils.cpp
+2-2llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+2-1llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+2-1llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+56-362 files not shown
+58-388 files

LLVM/project edd94b8lldb/include/lldb/Utility Log.h, lldb/source/Commands CommandObjectLog.cpp

[lldb] Return llvm::Error from DisableLogChannel (#207004)

Follow up to #206479.

llvm:Error better describes the success exor error message states that
we were previously doing with a boolean plus an error stream.
DeltaFile
+13-19lldb/unittests/Utility/LogTest.cpp
+8-13lldb/source/Utility/Log.cpp
+4-6lldb/source/Commands/CommandObjectLog.cpp
+2-3lldb/include/lldb/Utility/Log.h
+27-414 files

LLVM/project ad3c1efclang/lib/Analysis LiveVariables.cpp

[clang][Analysis] Speed up LiveVariables set merge (#209430)

LiveVariables' mergeSets built the union by unconditionally inserting
every element of B into A. Apply the two cheap tricks the
lifetime-safety analysis uses in its dataflow join:

* Return early when both operands are the same tree (an O(1) pointer
comparison), skipping the merge entirely. Merged liveness values are
canonicalized, so two predecessors with identical liveness share the
same tree -- common at confluence points.
* Insert the smaller set into the larger one, so the number of O(log n)
insertions is min(|A|, |B|) rather than always |B|.

The result is unchanged: set union is commutative and order-independent.

On a pathological function (1000 simultaneously-live locals across 5000
control-flow merges of identical sets) the liveness computation is ~18%
faster, essentially all from the identical-set short circuit. On real
translation units the merge is a small fraction of the analysis, so the

    [7 lines not shown]
DeltaFile
+10-8clang/lib/Analysis/LiveVariables.cpp
+10-81 files

LLVM/project d2804dfmlir/include/mlir/TableGen Format.h

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+3-3mlir/include/mlir/TableGen/Format.h
+3-31 files

LLVM/project 367d196clang/lib/Lex Preprocessor.cpp

[clang][Diagnostics] Fix check-point recording under default colors (#209355)

`getShowColors() != ShowColorsKind::Off` is also true for the default
Auto, so ordinary non-TTY compiles where colors are never actually
emitted kept recording check points, leaving the original 718aac9f cost
in place.
DeltaFile
+1-2clang/lib/Lex/Preprocessor.cpp
+1-21 files

LLVM/project 5d5dd83flang/lib/Optimizer/Passes Pipelines.cpp, llvm/include/llvm/Passes OptimizationLevel.h

[Passes] Replace OptimizationLevel with an enum (#209424)

Now that OptimizationLevel no longer has a size dimension, replace it
with a simple enum class.
DeltaFile
+6-25llvm/include/llvm/Passes/OptimizationLevel.h
+15-16flang/lib/Optimizer/Passes/Pipelines.cpp
+14-14llvm/lib/Passes/PassBuilderPipelines.cpp
+0-16llvm/lib/Passes/OptimizationLevel.cpp
+3-3llvm/lib/Passes/PassBuilder.cpp
+2-2llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+40-764 files not shown
+43-8210 files

LLVM/project a01c83dllvm/include/llvm/Analysis CGSCCPassManager.h, llvm/include/llvm/CodeGen MachinePassManager.h

more cleanup, wrap PassModel construction in function

Created using spr 1.3.8-wip
DeltaFile
+9-27llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
+5-17llvm/include/llvm/Analysis/CGSCCPassManager.h
+3-10llvm/include/llvm/IR/PassManager.h
+6-2llvm/include/llvm/IR/PassManagerInternal.h
+1-4llvm/include/llvm/CodeGen/MachinePassManager.h
+24-605 files

LLVM/project b4b19c8llvm/test/CodeGen/AMDGPU llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll llvm.amdgcn.reduce.and.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (20) (#209211)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+20-20llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+18-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+17-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+17-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+10-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
+100-10094 files not shown
+456-456100 files

LLVM/project da99ce2libc/include/llvm-libc-macros/linux signal-macros.h, libc/test/src/signal sigaction_test.cpp

[libc] Implement SA_NODEFER and SA_RESETHAND signal flags (#209429)

Defined SA_NODEFER and SA_RESETHAND in Linux signal-macros.h.

Added unit tests in sigaction_test.cpp to verify the behavior of the new
flags. Also added a test case for SA_SIGINFO.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+105-0libc/test/src/signal/sigaction_test.cpp
+2-0libc/include/llvm-libc-macros/linux/signal-macros.h
+107-02 files

LLVM/project cba0124llvm/test/CodeGen/AMDGPU llvm.amdgcn.intersect_ray.ll llvm.amdgcn.image.sample.noret.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (19) (#209122)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
+10-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+10-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
+9-9llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
+66-6693 files not shown
+451-45199 files

LLVM/project cce3371llvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Stop using changeTo in legaizer actions

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
DeltaFile
+855-425llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+783-389llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+759-377llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+253-160llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+232-138llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+58-80llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+2,940-1,56911 files not shown
+3,066-1,65117 files

LLVM/project 48636d1llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AArch64 aarch64-known-bits-hadd.ll

[GlobalISel] Add G_UAVGFLOOR/G_UAVGCEIL/G_SAVGFLOOR/G_SAVGCEIL to computeKnownBits (#209171)

Add known-bits handling for the averaging (halving add) opcodes G_UAVGFLOOR,
G_UAVGCEIL, G_SAVGFLOOR and G_SAVGCEIL in GISelValueTracking, using the
existing `KnownBits::avg{Floor,Ceil}{S,U}` helpers. This matches
SelectionDAG's handling of the corresponding ISD::AVGFLOOR*/AVGCEIL*
nodes.

This lets GlobalISel drop the redundant masking around hadd/rhadd of
zero-extended operands on AArch64 (see aarch64-known-bits-hadd.ll, where the
GlobalISel output now matches SelectionDAG). The sign-extended cases are
unaffected, since the masking is not redundant there.

Part of #150515.

---
Assisted by Claude (Anthropic).
DeltaFile
+131-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-avg.mir
+32-0llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+6-23llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
+169-233 files

LLVM/project c0c94fdllvm/test/CodeGen/AMDGPU memset-param-combinations.ll shrink-add-sub-constant.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll saddsat.ll

AMDGPU/GlobalISel: Fix G_MERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,801-1,013llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
+1,584-1,032llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+1,583-1,004llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+1,449-654llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+1,314-625llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+989-704llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+8,720-5,032186 files not shown
+29,006-19,794192 files

LLVM/project 03b4714flang/test/Driver function-attr-readonly.f90

[flang][NFC] Fix function-attr-readonly test on PowerPC (#209431)

Follow-up fix for the newly added test, which was not exercised on all
targets. PowerPC adds llvm.target_features between the function argument
list and the body. Stop requiring the opening brace to immediately
follow the argument list so that the checks remain target-independent.
DeltaFile
+3-3flang/test/Driver/function-attr-readonly.f90
+3-31 files

LLVM/project b565dballvm/lib/CodeGen Rematerializer.cpp

Remove llvm:: prefixes and try fix includes as well
DeltaFile
+5-6llvm/lib/CodeGen/Rematerializer.cpp
+5-61 files

LLVM/project b1c29d8lldb/docs/resources lldbgdbremote.md

[lldb][docs] Fix some formatting in the packets doc (#209440)
DeltaFile
+11-14lldb/docs/resources/lldbgdbremote.md
+11-141 files

LLVM/project 23a32bcllvm/lib/Analysis ScalarEvolutionDivision.cpp

[SCEVDivision] Remove unnecessary integer casts (NFCI) (#208155)

Since #204146 requires callers of SCEVDivision to pass the numerator and
the denominator with the same type, the bitwidth check in
`visitConstant` no longer makes sense.
DeltaFile
+2-7llvm/lib/Analysis/ScalarEvolutionDivision.cpp
+2-71 files

LLVM/project 24c3eaallvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.f32.fp8.err.ll llvm.amdgcn.cvt.fp8.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (18) (#209121)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+24-24llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
+85-8594 files not shown
+409-409100 files

LLVM/project 6795dc6

Revert "clang-linker-wrapper: Use AMDGPU::TargetID for device-image compatibi…"

This reverts commit dc1273beba1c70cb74d03c760958ee625d8aecf5.
DeltaFile
+0-00 files

LLVM/project c608088llvm/lib/CodeGen Rematerializer.cpp

Move includes to .cpp
DeltaFile
+2-0llvm/lib/CodeGen/Rematerializer.cpp
+2-01 files

LLVM/project 3def39fllvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Fine-grained LIS updates on remat and dead-def handling

This replaces the rematerializer's manual bulk LIS update paradigm in
favor of an automated fine-grained one that

1. performs LIS updates as rematerializations happen and
2. handles the removal of dead-definitions properly (this replaces the
   prior partial handling of live interval splitting).

The new approach should be less error-prone (clients do not have to
periodically update the LIS, which is now up-to-date at all times from
the clients's perspective) and faster in general (live intervals aren't
fully re-created every time a def or use of a register changes).

Handling dead-definitions (through a `LiveRangeEditor`) adds some
complexity to the rematerializer since unrematerializable MIs can now
also be deleted. This is exposed to listeners through a new event.
Furthermore, rematerializable registers can now become "permanently
dead" if all their users were unrematerializable MIs that became dead as

    [11 lines not shown]
DeltaFile
+307-100llvm/lib/CodeGen/Rematerializer.cpp
+135-50llvm/unittests/CodeGen/RematerializerTest.cpp
+66-22llvm/include/llvm/CodeGen/Rematerializer.h
+0-2llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+508-1744 files

LLVM/project 9582f71llvm/lib/Target/X86 X86WinEHUnwindV3.cpp, llvm/test/CodeGen/X86 win64-eh-unwindv3-split-large.ll

[UnwinderV3] Include padding in spliting calculations (#208458)

As in title. This is achieved by making the pass count split points in
bytes and making the average instruction size a variable.

PR done with usage of Claude Code
DeltaFile
+48-41llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
+2-2llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
+50-432 files

LLVM/project 64de40ellvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen][AMDGPU] Prepare rematerializer for multi-def remat support (NFC) (#197579)

This makes some NFCs to the rematerializer before adding initial support
for rematerializing registers with multiple defs. The main change is
that, in the representation of (un)rematerializable register
dependencies, we drop references to machine operand indices which lose
meaning in the multi-def case.

Other minor changes listed below.

- Removal of `DefRegion` argument to `Rematerializer::recreateReg`.
Registers are always re-created in their original region so there is no
need to set their region again.
- Removal of `InsertPos` unused argument to
`Rematerializer::postRematerialization`.
- Refactor of how AMDGPU's scheduler checks whether a given register is
rematerializable.
DeltaFile
+101-78llvm/lib/CodeGen/Rematerializer.cpp
+28-32llvm/include/llvm/CodeGen/Rematerializer.h
+21-14llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+23-3llvm/unittests/CodeGen/RematerializerTest.cpp
+173-1274 files