[X86][GlobalISel] Map a store of an FP-banked load to the FP bank (#215371)
`G_LOAD` and `G_STORE` didn't agree when to select the FP regbank, which
inserted a PSR -> GPR copy, hitting a "FP register expected" assertion.
Apply the load's rule in the store case as well so the two agree.
Co-authored-by: Claude (Claude-Opus-5) <noreply at anthropic.com>
[orc-rt] Update orc_rt::sps_ci::addAll to include new SPS CI. (#215973)
sps_ci::addAll should add all SPS CI (Controller Interface) symbols to
the given map.
Update it to include recently added SPS CI (Calls, GDBJITRegistrar,
MemoryAccess, NativeDylibManager, and
StandaloneMachOUnwindInfoRegistrar)
[flang][MIF] Adding common features related to coarray (#215576)
These features are included in PRs #212777 and #210283.
They add utilities for constructing a cosubscripts vector from a
`CoarrayRef`, a function for retrieving the index image in the initial
team, and the lowering for an `hlfir.designate` of a `CoarrayRef`, which
is treated the same way as an `ArrayRef`.
---------
Co-authored-by: Dan Bonachea <dobonachea at lbl.gov>
[GlobalISel][Docs] Fix known-bits example and code snippet in KnownBits.rst (#213090)
- The simplified example annotates `%5 = G_CONSTANT i32 0x0F0` with the
value `0x00000FF0` (from %1 line); correct value is `0x000000F0`.
- `GISelValueTrackingAnalysisLegacy::get(MF)` returns a reference, so
call should be `VT.getKnownBits(...)` not `VT->getKnownBits(...)`.
- `KnownBits` members are `Zero` and `One`, not `Zeros`; use
`Known.Zero[0]` to test bit 0.
[Polly] Narrow IV to lower type when possible (#212708)
This patch tries to lower the LLVM-IR type of IVs which are set to i64
by default during polly codegen. This is specially beneficial for
Hexagon as it uses Hardware Loops which requires 32 bit wide IVs.
---------
Co-authored-by: Anilava Kundu <anilkund at hu-anilkund-blr.qualcomm.com>
Co-authored-by: Santanu Das <santdas at qti.qualcomm.com>
[LoongArch] Fold shifted vector extract comparisons
Fold comparisons of the form:
(shl (extract_vector_elt X, I), GRLen - EleBits) ==/!= 0
into:
(extract_vector_elt X, I) ==/!= 0
When the shift amount equals `GRLen - EleBits`, the left shift only moves
the extracted element into the most significant bits without affecting
whether the value is zero. This canonicalization exposes
EXTRACT_VECTOR_ELT to later combines and enables selecting
VPICKVE2GR_* instructions directly.
[SCEV][SCEVExpander] Avoid querying SCEV for non-SCEVable instructions (#214902)
`getStrengthenedNoWrapFlagsFromBinOp()` expects instructions with
SCEVable operands.
For non-SCEVable vector-typed operands, this triggers the assertion in
`getSCEV()`.
This PR guards the caller in
`dropPoisonGeneratingAnnotationsAndReinfer()` so that
nowrap flags are only re-inferred for SCEVable instructions.
The added test is a crash regression test.
Fixes #214782
Fixes #215251
Fixes #114029
[Lanai] Default to NewPM
Lanai should be fully functional with the NewPM, so try defaulting to
it. Also remove the now duplicate test coverage.
Setting this flag makes both clang and llc default to the NewPM.
Reviewers: jpienaar
Pull Request: https://github.com/llvm/llvm-project/pull/214574
[MSP430] Default to NewPM
MSP430 should be fully complete with the NewPM, so default to it.
This flag makes both clang and llc default to using the NewPM for
CodeGen.
Reviewers: asl
Pull Request: https://github.com/llvm/llvm-project/pull/214573
[CodeGen] Avoid querying allocation order for every CSR alias (#215752)
Profiling tramp3d-v4 on aarch64-O0-g shows ~0.30% of compile-time is
spent in RegisterClassInfo::runOnMachineFunction.
It currently walks every alias of every callee-saved register for every
MachineFunction, doing a virtual call to ignoreCSRForAllocationOrder for
each alias. ARM is the only target that overrides this hook; all other
targets construct a full-sized BitVector and perform the alias traversal
only to fill it with zeroes.
Replace the per-register hook with a target-populated mask. Most targets
leave the mask empty, avoiding the allocation and alias traversal. The
mask is also only consulted after getLastCalleeSavedAlias confirms the
physical register aliases a CSR, so ARM can populate all GPR bits
directly without rediscovering the CSR aliases.
Improves CTMark geomean by -0.10%, with tramp3d-v4 -0.34%.
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[SandboxVectorizer] Dispatch LoadStoreVec::runOnRegion on seed kind
runOnRegion() previously assumed its seed slice was always a store chain,
unconditionally casting Bndl[0] to StoreInst. This crashed (assertion in
areConsecutive<StoreInst>) whenever -sbvec-collect-seeds included "loads",
since a load-seeded region's Aux holds LoadInsts.
Add a symmetric top-level path for load-kind seed slices: createVectorLoad()
builds the vector load, and vectorizeLoads() -- unlike a load that merely
feeds a store -- has to handle arbitrary uses, so it replaces each original
load with an extract from the vector load (VecUtils::unpack()) rather than
just discarding it. runOnRegion() determines the seed kind from Bndl[0]
(asserting the slice is homogeneous, which SeedCollection guarantees) and
dispatches to vectorizeStores()/vectorizeLoads() accordingly.
No sub-run search yet: vectorizeStores()/vectorizeLoads() are each still
tried once over the whole seed slice, same as before this commit for
stores. Sub-bundle partitioning for both kinds is a separate follow-up.
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[llc] Respect shouldDefaultToNewPM
This makes llc respect the new TM flag that allows targets to opt in to
defaulting to the NewPM.
Reviewers: vikramRH, aengelke, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/214572
[Clang] Make NewPM switch respect shouldDefaultToNewPM
shouldDefaultToNewPM is a new target flag that allows targets to specify
that the NewPM should be used by default for compilation. Wire it up
into clang.
Reviewers: arsenm, efriedma-quic, jansvoboda11
Pull Request: https://github.com/llvm/llvm-project/pull/214571
