[AMDGPU] Prefer a safe V_PERM_PK16 follower in the scheduler (gfx1250)
Stacked on the post-RA V_PERM_PK16 hazard fixup. V_PERM_PK16 must be
immediately followed by a "safe" instruction (see
SIInstrInfo::isVPermPk16SafeInstr) or the post-RA fixup has to insert a
forced-EXEC V_NOP. Teach GCNHazardRecognizer to bias a safe follower into
the slot right after a V_PERM_PK16 so that V_NOP can be avoided.
Assisted-by: Opus 4.8 Medium
[ORC] Hoist Caller state into the base; add operator bool (#214483)
Move the ExecutionSession reference and callee address up from the SPS
implementation into the rt::Caller base, together with their constructor
and new executionSession() / calleeAddr() accessors. The named callers
(MainCaller, VoidVoidCaller, ...) become plain aliases of Caller rather
than subclasses, and rt::sps::Caller inherits the base constructor.
Add an explicit operator bool() reporting whether the caller has a
non-null callee address.
Give rt::sps::Caller::Create a SymbolLookupFlags parameter. Looking the
callee up as a weakly-referenced symbol now yields a caller with a null
callee (operator bool == false) when the symbol is absent, rather than
an error -- so callers for optional runtime functions can be constructed
and then tested for availability.
Adds SPSCallersTest coverage for operator bool and the accessors, and
for the required/weak x present/absent Create paths.
[NVPTX][AsmPrinter] Allow fp128 aggregate types in NVPTX backend (#214546)
Fixes an issue where aggregate types containing fp128 non-zero elements
would cause "unsupported type" due to missing case in bufferLEByte. Adds
fp128-global.ll test.
[AMDGPU][GISel] Match constrained shifts across register bank copies
The constrained shift PatFrags (csh_mask_* wrapped by cshl_/csrl_/csra_)
supply GISelPredicateCode and are imported into the GlobalISel match
table, but they never fired for a divergent shift. AMDGPURegBankLegalize
places a cross-bank COPY in two positions inside the shape they match:
- the mask constant stays in the SGPR bank, so a divergent G_AND reads
it through a COPY and the frag's imm operand is not a G_CONSTANT;
- a uniform G_AND feeding a divergent shift is copied to the VGPR bank,
so the shift's amount operand is not a G_AND.
Either way GIM_CheckOpcode rejects the rule before isUnneededShiftMask
is ever consulted, and the redundant v_and_b32 survives into the output.
Set GIIgnoreCopies so the matcher emits GIM_RecordInsnIgnoreCopies for
those operands. A frag's flags only govern how its own operands are
found, so the first position needs the flag on csh_mask_* while the
second needs it on the node holding the shift; split the masked
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workflows: Merge release-doxygen into release-documenation
These two workflows use the same script and have the same structure,
so it's easier just to have one job that builds both.
