LLVM/project 760f707mlir/include/mlir/Dialect/XeGPU/Transforms XeGPULayoutImpl.h, mlir/lib/Dialect/XeGPU/Transforms XeGPULayoutImpl.cpp XeGPUPropagateLayout.cpp

[MLIR][XeGPU] Use the `setupDpasLayout` utility for dpas layout propagation (#180937)

DeltaFile
+219-1mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+30-186mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+91-1mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
+8-0mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h
+348-1884 files

LLVM/project 02fcdc3llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen MachineUniformityAnalysis.cpp

review: address suggestion
DeltaFile
+8-1llvm/include/llvm/CodeGen/TargetInstrInfo.h
+2-5llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+5-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-2llvm/lib/Target/AMDGPU/SIInstrInfo.h
+19-94 files

LLVM/project 82447b9clang/lib/CIR/Dialect/Transforms TargetLowering.cpp, clang/test/CIR/CodeGen atomic-scoped.c

[CIR] Add cir.atomic.xchg to target lowering (#180744)

This patch adds the `cir.atomic.xchg` operation to the TargetLowering
pass. The synchronization scope attached to the operation will be
canonicalized there.
DeltaFile
+8-2clang/test/CIR/CodeGen/atomic-scoped.c
+1-1clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
+9-32 files

LLVM/project 838be78llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 clmul-fixed.ll

[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)

NEON's PMULL/PMULL2 can be used and its lower bits taken to lower CLMUL
intrinsics, so long as +aes is present.
DeltaFile
+648-629llvm/test/CodeGen/AArch64/clmul-fixed.ll
+13-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+3-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+664-6313 files

LLVM/project abc48e0bolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp

[BOLT][BTI] Patch ignored functions in place when targeting them with
indirect branches

When applying BTI fixups to indirect branch targets, ignored functions are
considered a special case:
- these hold no instructions,
- have no CFG,
- and are not emitted in the new text section.

The solution is to patch the entry points in the original location.

If such a situation occurs in a binary, recompilation using the
-fpatchable-function-entry flag is required. This will place a nop at all
function starts, which BOLT can use to patch the original section.

Without the extra nop, BOLT cannot safely patch the original .text section.

An alternative solution could be to also ignore the function from which
the stub starts. This has not been tried as LongJmp pass - where most

    [3 lines not shown]
DeltaFile
+45-16bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+39-0bolt/test/AArch64/long-jmp-bti-ignored-nop.s
+2-4bolt/test/AArch64/bti-long-jmp-ignored.s
+5-0bolt/include/bolt/Core/MCPlusBuilder.h
+91-204 files

LLVM/project 3fd8e21clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded vabd_vv.c vabdu_vv.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded vabd_vv.c vabdu_vv.c

Use RVVOutBuiltinSet for vabd/vabdu to match Intrinsics

Created using spr 1.3.6-beta.1
DeltaFile
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd_vv.c
+78-783 files not shown
+106-1069 files

LLVM/project 8111a6cllvm/test/CodeGen/AArch64 qmovn.ll qshrn.ll

[AArch64][GlobalISel] Add some extra sqxtn test coverage. NFC
DeltaFile
+282-4llvm/test/CodeGen/AArch64/qmovn.ll
+65-16llvm/test/CodeGen/AArch64/qshrn.ll
+347-202 files

LLVM/project b8534e0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded vabs_v.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded vabs_v.c

Address comments

Created using spr 1.3.6-beta.1
DeltaFile
+0-202llvm/test/CodeGen/RISCV/rvv/vwabdacc.ll
+0-202llvm/test/CodeGen/RISCV/rvv/vwabdaccu.ll
+179-0llvm/test/CodeGen/RISCV/rvv/vwabda.ll
+179-0llvm/test/CodeGen/RISCV/rvv/vwabdau.ll
+66-67clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs_v.c
+66-67clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs_v.c
+490-53832 files not shown
+1,746-1,89138 files

LLVM/project 79ec0cemlir/lib/Target/LLVMIR ModuleImport.cpp, mlir/test/Target/LLVMIR/Import constant.ll

[MLIR][LLVMIR] Add support for importing ConstantInt/FP vector splats. (#180946)

Updates LLVM IR importing to remove the assumption that
ConstantInt/ConstantFP are always scalar.
DeltaFile
+14-0mlir/lib/Target/LLVMIR/ModuleImport.cpp
+9-0mlir/test/Target/LLVMIR/Import/constant.ll
+23-02 files

LLVM/project 3c8016cllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 vec-combine-trunc-dup-ext.ll

[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)

Combine:
  sext(duplane(insert_subvector(undef, trunc(X), 0), idx))
Into:
  duplane(X, idx)

This avoids XTN/SSHLL instruction sequences that occur when splatting
elements from boolean vectors after type legalization, which is common
when using shufflevector with comparison results.
DeltaFile
+119-0llvm/test/CodeGen/AArch64/vec-combine-trunc-dup-ext.ll
+65-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+184-02 files

LLVM/project db26124llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/MC/AArch64 armv9.7-scr2.s

[AArch64]Add SCR2_EL3 system register (#180918)

The link to the system register:


https://developer.arm.com/documentation/111107/2025-12/AArch64-Registers/SCR2-EL3--Secure-Configuration-Register?lang=en
DeltaFile
+24-0llvm/test/MC/AArch64/armv9.7-scr2.s
+4-0llvm/lib/Target/AArch64/AArch64SystemOperands.td
+28-02 files

LLVM/project fe532d0llvm/test/tools/llvm-reduce unconditional-br-phi.ll, llvm/tools/llvm-reduce/deltas ReduceUsingSimplifyCFG.cpp

[review] Add test case with phi-nodes and switch
DeltaFile
+89-0llvm/test/tools/llvm-reduce/unconditional-br-phi.ll
+1-1llvm/tools/llvm-reduce/deltas/ReduceUsingSimplifyCFG.cpp
+90-12 files

LLVM/project bf4635fllvm/test/tools/llvm-reduce unconditional-br.ll reduce-invoke.ll, llvm/tools/llvm-reduce DeltaPasses.def

[llvm-reduce] Add a pass to replace unconditinal branches with returns

Unconditional branches could end up in infinite loops in the reduced code,
while the code could have been reduce furter.

This patch implements a simple pass that replaces unconditional branches
with returns.
DeltaFile
+40-0llvm/test/tools/llvm-reduce/unconditional-br.ll
+37-0llvm/tools/llvm-reduce/deltas/ReduceUsingSimplifyCFG.cpp
+2-2llvm/test/tools/llvm-reduce/reduce-invoke.ll
+2-0llvm/tools/llvm-reduce/DeltaPasses.def
+1-0llvm/tools/llvm-reduce/deltas/ReduceUsingSimplifyCFG.h
+82-25 files

LLVM/project ce6dd9cllvm/test/CodeGen/AArch64 switch-cases-to-branch-and.ll

[AArch64][GlobalISel] Update and regnerate switch-cases-to-branch-and.ll. NFC
DeltaFile
+438-543llvm/test/CodeGen/AArch64/switch-cases-to-branch-and.ll
+438-5431 files

LLVM/project 9eed43blldb/examples/python/templates scripted_frame_provider.py

[lldb][doc] Improve documentation for `ScriptedFrameProvider` (#179996)

* Provide a minimal, working example
* Document the instance variables
* Remove mention of `thread.SetScriptedFrameProvider` (which doesn't exist)
* add missing `@staticmethod` annotation
* fix rendering of bullet-pointed lists
DeltaFile
+42-14lldb/examples/python/templates/scripted_frame_provider.py
+42-141 files

LLVM/project 907eb11libc/src/stdio/baremetal file_internal.cpp CMakeLists.txt

[libc] Add getc, ungetc, fflush to enable libc++ iostream on baremetal (#175530)

After https://github.com/llvm/llvm-project/pull/168931 landed getc,
ungetc and fflush are still missing at link time while trying to make
libc++ std::cout work with LLVM libc on baremetal.

ungetc implementation is very minimal only to cover the current standard
streams implementation from the patch above.
DeltaFile
+52-0libc/src/stdio/baremetal/file_internal.cpp
+37-1libc/src/stdio/baremetal/CMakeLists.txt
+31-0libc/src/stdio/baremetal/getc.cpp
+27-3libc/src/stdio/baremetal/file_internal.h
+22-0libc/src/stdio/baremetal/fflush.cpp
+20-0libc/src/stdio/baremetal/ungetc.cpp
+189-43 files not shown
+198-69 files

LLVM/project 8d63e89libcxx/include/__functional hash.h

[libc++] Avoid including pair in <__functional/hash.h> (#179635)

We already have `_PairT`, which is just a pair of two `size_t`s, so we
might as well use that throughout the file. This avoids the `pair`
include altogether, reducing header parse times a bit in some cases.
DeltaFile
+14-12libcxx/include/__functional/hash.h
+14-121 files

LLVM/project 4a11680llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

Address comments
DeltaFile
+3-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+3-91 files

LLVM/project 6420099llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp DAGCombiner.cpp, llvm/test/CodeGen/LoongArch/lasx vxi1-masks.ll

[SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (#180727)

DAGCombiner can fold a chain of INSERT_VECTOR_ELT into a vector AND/OR
operation. This patch adds protection to avoid that we end up making the
vector more poisonous by freezing the source vector when the elements
that should be set to 0/-1 may be poison in the source vector.

The patch also fixes a bug in SimplifyDemandedVectorElts for
MUL/MULHU/MULHS/AND that could result in making the vector more
poisonous. Problem was that we skipped demanding elements from Op0 that
were known to be zero in Op1. But that could result in elements being
simplified into poison when simplifying Op0, and then the result would
be poison and not zero after the MUL/MULHU/MULHS/AND. The solution is to
defensively make sure that we demand all the elements originally
demanded also when simplifying Op0.

This bugs were found when analysing the miscompiles in
https://github.com/llvm/llvm-project/issues/179448


    [6 lines not shown]
DeltaFile
+24-22llvm/test/CodeGen/X86/vector-fshr-512.ll
+40-0llvm/test/CodeGen/X86/insertelement-zero.ll
+20-18llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
+12-9llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+10-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+8-0llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
+114-5011 files not shown
+159-5417 files

LLVM/project 62cc0b2mlir/tools/mlir-tblgen DialectGen.cpp

[MLIR][ODS] Make dialect attribute helper member functions const (NFC)

This commit marks member functions of dialect attribute helpers as
constant. This ensures that these helpers can be added as members of
rewrite patterns, whose `matchAndRewrite` functions are marked as const
as well.
DeltaFile
+6-6mlir/tools/mlir-tblgen/DialectGen.cpp
+6-61 files

LLVM/project 847558elibcxx/include/__filesystem path.h

[libc++][NFC] use void_t instead of a custom implementation in fs::path (#181050)

DeltaFile
+4-6libcxx/include/__filesystem/path.h
+4-61 files

LLVM/project a437809libcxx/include iomanip, libcxx/include/__filesystem path.h

[libc++][NFC] Use std::quoted in fs::path and remove the private __quoted (#181043)

We've provided `std::filesystem` before C++17 in the past, but we don't
anymore, so we can use `std::quoted`.
DeltaFile
+2-16libcxx/include/iomanip
+3-3libcxx/include/__filesystem/path.h
+5-192 files

LLVM/project 22985feclang/lib/CodeGen/TargetBuiltins ARM.cpp

[clang][Builtins][ARM] NFC updates in ARM.cpp (#180966)

Updates the logic in `CodeGenFunction::EmitAArch64BuiltinExpr` so that
we always start with the general code and we only fall-back to
specialised cases (i.e. `switch` stmts) for intrinsics for which the
general code does no apply.

BEFORE (only high-level:
```cpp
Value *CodeGenFunction::EmitAArch64BuiltinExpr() {
  (...)
  /// 1. SWITCH STMT FOR NON-OVERLOADED INTRINSIS
  switch (BuiltinID) {
    default break:
    case NEON::BI__builtin_neon_vabsh_f16:
    (...)
  }

  /// 2. GENERAL CODE

    [58 lines not shown]
DeltaFile
+24-31clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+24-311 files

LLVM/project d49060alldb/test/API/functionalities/data-formatter/compactvectors TestCompactVectors.py

[lldb][test] TestCompactVectors.py: skip for older Clang

Was failing on the Clang 17 green dragon matrix bot:
```
/Applications/Xcode_26.2.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX26.2.sdk/System/Library/Frameworks/vecLib.framework/Headers/Sparse/SolveImplementationTyped.h:678:9: error: use of undeclared identifier '__builtin_verbose_trap'
07:28:37    678 |         __builtin_verbose_trap("unsupported", "LU factorization is not supported on this OS version");
07:28:37        |         ^
07:28:37  /Applications/Xcode_26.2.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX26.2.sdk/System/Library/Frameworks/vecLib.framework/Headers/Sparse/SolveImplementationTyped.h:888:95: error: unrecognized platform name visionOS
07:28:37    888 |       if(__builtin_available(macOS 15.5, macCatalyst 18.5, iOS 18.5, watchOS 11.5, tvOS 18.5, visionOS 2.5, *)) {
07:28:37        |
```
DeltaFile
+1-0lldb/test/API/functionalities/data-formatter/compactvectors/TestCompactVectors.py
+1-01 files

LLVM/project 6117bddllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/ARM stlf-vector-extract.ll

[DAGCombiner] Fix subvector extraction index for big-endian STLF (#180795)

This PR fixes a big-endian regression in `ForwardStoreValueToDirectLoad`
where the wrong subvector was being extracted. In big-endian, memory
offset 0 corresponds to the high bits, so the extraction index needs to
be adjusted.

As suggested by @KennethHilmersson, calculate the extraction index as
the difference between the number of elements in the intermediate vector
and the load vector when in big-endian mode.

Special thanks to Kenneth Hilmersson for providing the fix logic and the
ARM regression test.
https://github.com/llvm/llvm-project/pull/172523#issuecomment-3878065191
https://github.com/llvm/llvm-project/pull/172523#issuecomment-3879575092
DeltaFile
+28-0llvm/test/CodeGen/ARM/stlf-vector-extract.ll
+13-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+1-2llvm/test/CodeGen/X86/avx512-shuffles/shuffle-chained-bf16.ll
+42-43 files

LLVM/project b20d7d0mlir/include/mlir/Interfaces DialectFoldInterface.td FoldInterfaces.h, mlir/lib/IR CMakeLists.txt

[MLIR][IR] Convert `DialectFoldInterface` to ODS (#180833)

This PR converts `DialectFoldInterface` to ODS.
DeltaFile
+46-0mlir/include/mlir/Interfaces/DialectFoldInterface.td
+2-27mlir/include/mlir/Interfaces/FoldInterfaces.h
+5-0mlir/include/mlir/Interfaces/CMakeLists.txt
+1-0mlir/lib/IR/CMakeLists.txt
+54-274 files

LLVM/project 9250d4ellvm/lib/Analysis ValueTracking.cpp, llvm/test/Analysis/BasicAA range.ll

[ValueTracking] Extend computeConstantRange for add/sub, sext/zext/trunc

Recursively compute operand ranges for add/sub and propagate ranges
through sext/zext/trunc.
For add/sub, the computed range is intersected with any existing range
from setLimitsForBinOp, and NSW/NUW flags are used via addWithNoWrap/
subWithNoWrap to tighten bounds.

The motivation is to enable further folding of reduce.add expressions
in comparisons, where the result range can be bounded by the input
element ranges.

Compile-time impact on llvm-test-suite is <0.1% mean.
DeltaFile
+92-0llvm/unittests/Analysis/ValueTrackingTest.cpp
+66-0llvm/test/Analysis/BasicAA/range.ll
+28-0llvm/lib/Analysis/ValueTracking.cpp
+186-03 files

LLVM/project daa9017llvm/lib/Analysis ValueTracking.cpp, llvm/test/Analysis/BasicAA range.ll

[ValueTracking] Extend computeConstantRange for add/sub and sext/zext/trunc

Recursively compute operand ranges for add/sub and propagate ranges
through sext/zext/trunc.
For add/sub, the computed range is intersected with any existing range
from setLimitsForBinOp, and NSW/NUW flags are used via addWithNoWrap/
subWithNoWrap to tighten bounds.

The motivation is to enable further folding of reduce.add expressions
in comparisons, where the result range can be bounded by the input
element ranges.

Compile-time impact on llvm-test-suite is <0.1% mean.
DeltaFile
+92-0llvm/unittests/Analysis/ValueTrackingTest.cpp
+66-0llvm/test/Analysis/BasicAA/range.ll
+28-0llvm/lib/Analysis/ValueTracking.cpp
+186-03 files

LLVM/project c6bb1afmlir/lib/Dialect/Math/IR MathOps.cpp, mlir/test/Dialect/Math canonicalize.mlir

[mlir][Math] Fix IPowIOp folding crash for i1 (#179684)

Fixes #179380: an assertion/crash in math.ipowi constant folding when the result type is i1. 

`IPowIOp::fold` constructed `APInt(width=1, val=1, isSigned=true)`. Signed i1 cannot represent +1 (range [-1, 0]), so APInt asserts (isIntN).

This commit deactivates folding for `i1`.

---------

Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
DeltaFile
+23-0mlir/test/Dialect/Math/canonicalize.mlir
+4-1mlir/lib/Dialect/Math/IR/MathOps.cpp
+27-12 files

LLVM/project f6f0503clang/lib/Parse ParseTentative.cpp, clang/test/Interpreter access.cpp disambiguate-decl-stmt.cpp

[clang-repl] Fix disambiguation of out-of-line member with private types (#178842)

This patch fixes a bug in clang-repl where out-of-line member function
definitions were incorrectly identified as statements when they involved
private type aliases.

The issue occurred because `isCXXDeclarationStatement` would trigger
immediate access checks during tentative parsing. Since the context of
an out-of-line definition isn't fully established during this phase,
Sema would incorrectly flag private members as inaccessible, causing
the parser to fail the declaration check and fall back to statement
parsing.

Changes:
- In `isCXXDeclarationStatement`, use `TentativeParsingAction` to
  ensure the token stream is fully restored.
- Use `SuppressAccessChecks` during the tentative disambiguation phase
  to prevent premature access errors.
- Ensure that formal access verification still occurs during the

    [5 lines not shown]
DeltaFile
+16-0clang/lib/Parse/ParseTentative.cpp
+15-0clang/test/Interpreter/access.cpp
+2-3clang/test/Interpreter/disambiguate-decl-stmt.cpp
+33-33 files