LLVM/project 17bace6llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

Revert "[SLP]Recalculate copyable-element deps after tree reordering"

This reverts commit dd19d5210352f004758d0a877b396ea9f04cfd70 to fix
buildbot https://lab.llvm.org/buildbot/#/builders/195/builds/29633

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/216415
DeltaFile
+0-188llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+0-16llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+0-2042 files

LLVM/project 12f8c22clang/test/CIR/CodeGen long-double-inc-dec.cpp fp-contract.c, clang/test/CIR/CodeGenBuiltins/X86 xop-builtins.c sse41-builtins.c

[CIR] Run callconv lowering in the tests that opted out of it (#216396)

48 CIR tests carried `-fno-clangir-call-conv-lowering` with a TODO to
drop it once the pass handled vector types, the long double wrapper,
f16, and f128. The classifier takes all of those now, so the opt-out and
its TODO go and the tests exercise the pass.

No CHECK line moves, so the IR these tests already pinned is what the
pass produces.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+8-10clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c
+8-10clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c
+8-10clang/test/CIR/CodeGenBuiltins/X86/avx2-builtins.c
+8-10clang/test/CIR/CodeGenBuiltins/X86/avx-builtins.c
+6-9clang/test/CIR/CodeGen/fp-contract.c
+6-8clang/test/CIR/CodeGen/long-double-inc-dec.cpp
+44-5742 files not shown
+159-25648 files

LLVM/project f7bb060llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 combine-i64-trunc-srl-add.ll icmp-range-check-shift.ll

[SelectionDAG] SimplifySetCC - Improve shifted range checks with add offsets (#207955)

SelectionDAG currently shrinks large unsigned compare immediates by
shifting the compare operand as a whole. For top-bit range checks that
have been canonicalized to `icmp ult (add x, C), Width`, this can
preserve the pre-shift add and lead to extra masks, zero-extends, or
large immediates.

When the add offset and range width are aligned to the selected shift
and the original unsigned range does not wrap, move the offset after the
shift instead. This lets cases such as checking whether `x >> 48` is in
`[10, 20)` lower to shift/add/cmp.

Fixes #172674
DeltaFile
+181-0llvm/test/CodeGen/X86/icmp-range-check-shift.ll
+24-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+5-7llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
+210-73 files

LLVM/project 0f54f2ellvm/lib/DebugInfo/DWARF DWARFContext.cpp

Drop const in local
DeltaFile
+1-1llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
+1-11 files

LLVM/project dd19d52llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

[SLP]Recalculate copyable-element deps after tree reordering

Reordering permutes the operand columns of the entries and may move an
operand between copyable-covered and plain edges, making the computed
dependency counts stale and tripping the unscheduled-deps assertion.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/216410
DeltaFile
+188-0llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+16-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+204-02 files

LLVM/project eb27c49clang/test/CIR/CodeGen record-member-kinds.cpp

[CIR] Test bit-field access units split by register size

A span of bit-fields wider than one register splits into two access units, each
marked on its own.  Nothing covered that path: every bit-field in these tests is
24 bits or narrower, and the splits already covered come from a zero-length
bit-field instead.

Two of the three cases are worth having for a reason beyond coverage.  When a
record carries both a data unit and an empty one it is not ABI-empty either way,
so the differential assert cannot see a wrong mark on an individual unit, and
these checks are the only thing that can.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+12-0clang/test/CIR/CodeGen/record-member-kinds.cpp
+12-01 files

LLVM/project 5122b08clang/lib/Driver/ToolChains WebAssembly.cpp

[clang][WebAssembly] Remove `OPT_no_pthread` handling (#216378)

`-no-pthread` was originally added to Clang in 425b1a5106def (D11087)
simply to prevent "unknown argument" errors when building winpthreads in
mingw-w64.

It was subsequently used in `WebAssembly.cpp` when thread options were
made consistent in 9d5a089bf544e (D57874) via `Args.hasFlag`.

No other Clang toolchains handle `OPT_no_pthread` (they all use
`Args.hasArg(options::OPT_pthread)`), and `-pthread` is not typically
treated as a negatable boolean option in GCC/Clang drivers.

Align WebAssembly with all other Clang toolchains by removing the
`OPT_no_pthread` check.
DeltaFile
+1-2clang/lib/Driver/ToolChains/WebAssembly.cpp
+1-21 files

LLVM/project 58700a8clang/test/Analysis lifetime-bound.cpp

Remove HEAD.
DeltaFile
+0-3clang/test/Analysis/lifetime-bound.cpp
+0-31 files

LLVM/project c5962a9clang/test/Analysis lifetime-bound.cpp

Correct CHECK-NEXT lines.
DeltaFile
+4-4clang/test/Analysis/lifetime-bound.cpp
+4-41 files

LLVM/project 940c007clang/test/Analysis lifetime-bound.cpp

Resolve merge conflicts.
DeltaFile
+4-1clang/test/Analysis/lifetime-bound.cpp
+4-11 files

LLVM/project 2ebc505clang/test/Analysis lifetime-bound.cpp

Correct CHECK-NEXT lines.
DeltaFile
+4-4clang/test/Analysis/lifetime-bound.cpp
+4-41 files

LLVM/project 60b10efclang/test/Analysis lifetime-bound.cpp

Remove strict whitespace indentations.
DeltaFile
+5-5clang/test/Analysis/lifetime-bound.cpp
+5-51 files

LLVM/project 5f68218clang/lib/StaticAnalyzer/Checkers UseAfterLifetimeEnd.cpp, clang/test/Analysis lifetime-bound.cpp

[analyzer] Highilght variables range in emitted reports from UseAfterLifetimeEnd
DeltaFile
+28-0clang/test/Analysis/lifetime-bound.cpp
+4-2clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
+32-22 files

LLVM/project bfbac54clang/lib/StaticAnalyzer/Checkers UseAfterLifetimeEnd.cpp, clang/test/Analysis lifetime-bound.cpp

[analyzer] Only underline the exact parameter that is bound to the return value in UseAfterLifetimeEnd (#215651)

Currently the `UseAfterLifetimeEnd` checker highlights always the first
argument that is annotated with the `[[clang::lifetimebound]]`
annotation. Like:
```text
temp.cpp:5:31: note: Value's lifetime bound to the lifetime of 'y' here
    4 |   int x = 1, y = 2;
      |   ~~~~~~~~~~~~~~~~
    5 |   return multi_param_test_ref(x, y);
      |                               ^
```

As seen even when checker correctly notes that the value's lifetime is
bound to the lifetime of the `y` parameter, it incorrectly highlights x
since that is the first annotated parameter. In order to fix this I have
added a logic which checks which annotated parameter's region is bound
to the return's region and do the highlight based on that.


    [16 lines not shown]
DeltaFile
+41-1clang/test/Analysis/lifetime-bound.cpp
+17-7clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
+58-82 files

LLVM/project 947565aclang/include/clang/Basic HLSLIntrinsics.td, clang/test/CodeGenHLSL/builtins abs.hlsl

[HLSL][longvec][Tablegen] Use templates to define Vector api's larger than 4 (#216143)

resolves #216139
resolves #216140

This change adds a templatized vector emitter to TableGen's HLSLEmitter.
We add tests for the tablegen and confirm we did it right by
implementing the abs api.

Assisted by GPT-5.6 sol via co-pilot
DeltaFile
+26-0clang/test/TableGen/hlsl-intrinsics.td
+16-1clang/utils/TableGen/HLSLEmitter.cpp
+5-0clang/include/clang/Basic/HLSLIntrinsics.td
+3-0clang/test/CodeGenHLSL/builtins/abs.hlsl
+50-14 files

LLVM/project c6107fbclang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp

[CIR] Address more reviewer feedback

Remove droppedFieldHoldingData.  The differential asserts allow for an error
having already been reported instead, which covers any NYI in record lowering
rather than just the one.

Mark a bit-field access unit by promoting its storage member when a named
occupant is emitted, rather than pre-scanning the unit first.  Both bit-field
paths now do it the same way, and the unit's fields are walked once.

Rename runStorageIdx to storageIdx.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+27-38clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+27-381 files

LLVM/project 5e8490allvm/include/llvm/DWARFLinker AddressesMap.h, llvm/lib/DWARFLinker/Classic DWARFLinker.cpp

[DWARFLinker] Constrain a function's high_pc to its own symbol (#215952)

Mach-O objects built with .subsections_via_symbols make every symbol an
independently placeable atom, and the linker packs atoms without
preserving the spacing they had in the object file.

I have an example where the compiler describes such a subprogram as
extending past its own atom. While it's debatable whether that's a good
idea, it's not invalid in the object file. However, once linked, it is
invalid.

We can make dsymutil resilient against this by looking at the size of
the symbol in the debug map and adjusting the end_pc. I'm doing so
conservatively so that only a collision is repaired. Already
overlapping/invalid ranges remain untouched.

rdar://184768778
DeltaFile
+28-15llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
+35-4llvm/test/tools/dsymutil/subprogram-high-pc-past-symbol.test
+20-15llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.cpp
+14-9llvm/include/llvm/DWARFLinker/AddressesMap.h
+9-0llvm/lib/DWARFLinker/Parallel/DIEAttributeCloner.h
+2-3llvm/tools/dsymutil/DwarfLinkerForBinary.h
+108-466 files

LLVM/project cf98a4bllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize vector-loop-backedge-elimination-tail-folding-interleave-only.ll

[LV] Simplify the latch branch before rewriting ALM for a scalar VF (#216257)

Run simplifyBranchConditionForVFAndUF before replaceMaskWithCompare
before, so the simplification triggers before replaceMaskWithCompare
writes the plan.

PR: https://github.com/llvm/llvm-project/pull/216257
DeltaFile
+16-42llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-tail-folding-interleave-only.ll
+3-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+19-442 files

LLVM/project 99690a3lldb/source/API CMakeLists.txt

[LLDB] Remove fallthrough (#216398)

Address post-commit feedback on
https://github.com/llvm/llvm-project/commit/8ad0f7cf78f12b51e91d3799593a1d766b6ab6a6.
DeltaFile
+2-1lldb/source/API/CMakeLists.txt
+2-11 files

LLVM/project 048fb28lldb/cmake/modules LLDBConfig.cmake

[lldb] Disable C4250 warning on MSVC (#215304)

When compiling LLDB with MSVC, there are a lot of
[C4250](https://learn.microsoft.com/en-us/cpp/error-messages/compiler-warnings/compiler-warning-level-2-c4250)
warnings (A inherits B::func via dominance). One for every subclass of
`ScriptedPythonInterface`. This PR disables the warning on MSVC.
DeltaFile
+1-0lldb/cmake/modules/LLDBConfig.cmake
+1-01 files

LLVM/project fc14552lldb/source/API CMakeLists.txt

[lldb][CMake] Give the staged lldb-defines.h a build rule (#216394)

a05b232076ed dropped lldb-defines.h from the header staging loop so that
the source header is never copied, leaving the staged copy to be
produced by a POST_BUILD command on liblldb-header-staging. Ninja cannot
see files produced that way, and LLDBRPCHeaders.cmake depends on the
staged path directly, so a clean build with LLDB_BUILD_LLDBRPC enabled
fails to even load the graph:

  ninja: error: 'include/lldb/lldb-defines.h', needed by
  'tools/lldb-rpc/DerivedHeaders/lldb-rpc-defines.h', missing and no
  known rule to make it

Dropping the header from the loop also removed it from
lldb_staged_headers and from LLDB.framework/Headers, even though
SBDefines.h includes it.

Stage the header through version-header-fix.py from inside the loop
instead. The script reads the source header and writes a fresh staged

    [3 lines not shown]
DeltaFile
+6-6lldb/source/API/CMakeLists.txt
+6-61 files

LLVM/project 8f61453clang/test/CodeGen/RISCV riscv64-abi.c riscv32-abi.c

[RISCV][NFC] add `_Complex {integer}` ABI tests (#216386)

based on https://github.com/llvm/llvm-project/pull/215222, RISCV has the
same bug.

The fix is basically identical, I'll put up a PR once this merges.
DeltaFile
+46-0clang/test/CodeGen/RISCV/riscv64-abi.c
+46-0clang/test/CodeGen/RISCV/riscv32-abi.c
+92-02 files

LLVM/project 1d15190mlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/test/Dialect/LLVMIR nvvm.mlir

[MLIR][NVVM] Spell strict assembly properties directly

NVVM strict property assembly currently uses prop-dict for many ops. Some
formats already bind every inherent field, and a few small groups can spell
their inherent attributes more naturally in the assembly syntax.

Spell the transcendental ftz flag, redux abs/nan flags, cluster aligned flag,
and small fence attributes directly. Drop prop-dict from formats whose
inherent fields are fully covered by the declarative format.

Adapt test coverage added since the original patch to the same strict
property spelling.

Assisted-by: Codex
DeltaFile
+74-74mlir/test/Target/LLVMIR/nvvm/tcgen05-ld.mlir
+48-48mlir/test/Target/LLVMIR/nvvm/tma_store_reduce_im2col_w.mlir
+28-27mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+12-12mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-tensor.mlir
+12-12mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-shared.mlir
+12-12mlir/test/Dialect/LLVMIR/nvvm.mlir
+186-18517 files not shown
+322-32123 files

LLVM/project 6686c94libc/src/__support/math ceilf128.h, libc/test/src/math ceilf128_test.cpp CMakeLists.txt

nits
DeltaFile
+1-1libc/test/src/math/smoke/CMakeLists.txt
+1-1libc/test/src/math/CMakeLists.txt
+2-0libc/src/__support/math/ceilf128.h
+1-0libc/test/src/math/ceilf128_test.cpp
+5-24 files

LLVM/project 03687a0mlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/test/Target/LLVMIR/nvvm tcgen05-mma-shared.mlir tma_load_cluster_im2col.mlir

[MLIR][NVVM] Enable strict property assembly format

Enable strict property assembly format mode for the NVVM dialect and update
custom assembly formats to expose property dictionaries explicitly.

Refresh NVVM tests so inherent operation properties are printed and parsed
through the property dictionary while non-property attributes remain in the
attribute dictionary.

Assisted-by: Codex
DeltaFile
+144-144mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-tensor.mlir
+144-144mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-tensor.mlir
+128-128mlir/test/Target/LLVMIR/nvvm/tma_store_reduce.mlir
+108-108mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_im2col.mlir
+107-107mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+96-96mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared.mlir
+727-72773 files not shown
+2,262-2,26279 files

LLVM/project cc6f111llvm/include/llvm/ProfileData SampleProf.h, llvm/lib/ProfileData SampleProfWriter.cpp

[ProfileData] Remove toCompress and setToCompress from ProfileSymbolList (NFC) (#216236)

This patch removes toCompress, setToCompress, and ToCompress in
ProfileSymbolList.  Nobody calls setToCompress, so ToCompress is
always false.
DeltaFile
+0-7llvm/include/llvm/ProfileData/SampleProf.h
+0-2llvm/lib/ProfileData/SampleProfWriter.cpp
+0-92 files

LLVM/project 4ebdce4llvm/test/tools/llvm-shlib typeids.test

[NFC] Remove obsolete typeids.test after fa23198d685b (#216379)

fa23198d685b replaced llvm::Any with IRUnitRef in
PassInstrumentation. IRUnitRef uses an enum discriminator instead of
address-based TypeId, so the visibility guard this test enforced no
longer applies.
DeltaFile
+0-14llvm/test/tools/llvm-shlib/typeids.test
+0-141 files

LLVM/project 55bed95mlir/include/mlir/Dialect/SPIRV/IR SPIRVGraphOps.td SPIRVControlFlowOps.td, mlir/test/Dialect/SPIRV/IR graph-ops.mlir control-flow-ops.mlir

[MLIR][SPIRV] Enable strict property assembly format (#196282)

Enable strict property assembly format mode for SPIR-V and add property
dictionaries to declarative formats that still carry inherent attributes
outside explicit operands or clauses.

Refresh ARM graph and TOSA tests so GraphConstant uses prop-dict
spelling for its inherent constant identifier.

Assisted-by: Codex
DeltaFile
+8-8mlir/test/Target/SPIRV/graph-debug-info.mlir
+6-6mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
+6-1mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir
+3-3mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
+4-1mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
+2-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
+29-215 files not shown
+36-2711 files

LLVM/project ce7c9adllvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-fma-unmerge-values.mir combine-fma-add-mul-post-legalize.mir

[GlobalISel] Propagate fast-math flags when fusing fmul+fadd into fma (#215150)
DeltaFile
+148-40llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
+54-25llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+32-32llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
+250-1134 files

LLVM/project 55dc49amlir/include/mlir/Dialect/SPIRV/IR SPIRVGraphOps.td SPIRVControlFlowOps.td, mlir/test/Dialect/SPIRV/IR graph-ops.mlir control-flow-ops.mlir

[MLIR][SPIRV] Enable strict property assembly format

Enable strict property assembly format mode for SPIR-V and add property
dictionaries to declarative formats that still carry inherent attributes outside
explicit operands or clauses.

Refresh ARM graph and TOSA tests so GraphConstant uses prop-dict spelling for
its inherent constant identifier.

Assisted-by: Codex
DeltaFile
+8-8mlir/test/Target/SPIRV/graph-debug-info.mlir
+6-6mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
+6-1mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir
+3-3mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
+4-1mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
+2-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
+29-215 files not shown
+36-2711 files