LLVM/project 58d9e47bolt/test lit.local.cfg

[NFCI][bolt][test] Use AT&T syntax explicitly (#167225)

This enables building LLVM with `-mllvm -x86-asm-syntax=intel` in one's
Clang config files (i.e. a global preference for Intel syntax).

`-masm=att` is insufficient as it doesn't override a specification of `-mllvm -x86-asm-syntax`.
DeltaFile
+1-1bolt/test/lit.local.cfg
+1-11 files

LLVM/project 669c30cmlir/docs/Dialects NVVMDialect.md, mlir/docs/Dialects/NVVM _index.md

[MLIR][NVVM] Move docs to correct folder
DeltaFile
+87-0mlir/docs/Dialects/NVVMDialect.md
+0-84mlir/docs/Dialects/NVVM/_index.md
+87-842 files

LLVM/project ec90912clang/include/clang/Basic BuiltinsNVPTX.td, clang/test/CodeGen builtins-nvptx.c

[clang][NVPTX] Add remaining float to fp16 conversions (#167641)

This change adds intrinsics and clang builtins for the remaining float
to fp16 conversions. This includes the following conversions:

- float to bf16x2 - satfinite variants
- float to f16x2 - satfinite variants
- float to bf16 - satfinite variants
- float to f16 - all variants

Tests are added in `convert-sm80.ll` and `convert-sm80-sf.ll` for the
intrinsics and in `builtins-nvptx.c` for the clang builtins.
DeltaFile
+260-0llvm/test/CodeGen/NVPTX/convert-sm80-sf.ll
+65-0llvm/test/CodeGen/NVPTX/convert-sm80.ll
+49-0clang/test/CodeGen/builtins-nvptx.c
+29-1llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+21-0clang/include/clang/Basic/BuiltinsNVPTX.td
+11-6llvm/include/llvm/IR/IntrinsicsNVVM.td
+435-71 files not shown
+449-77 files

LLVM/project 208be48llvm/lib/Target/LoongArch LoongArchLateBranchOpt.cpp

update isLoadImm
DeltaFile
+17-11llvm/lib/Target/LoongArch/LoongArchLateBranchOpt.cpp
+17-111 files

LLVM/project 50e7702llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs loongarch_generated_funcs.ll.generated.expected loongarch_generated_funcs.ll.nogenerated.expected

tests passed
DeltaFile
+1-1llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.generated.expected
+1-1llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.nogenerated.expected
+2-22 files

LLVM/project ac68dd5llvm/lib/Target/RISCV RISCVCodeGenPrepare.cpp RISCVPassRegistry.def, llvm/test/CodeGen/RISCV riscv-codegenprepare.ll

[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)

As suggested in the review for #160536 it would be good to follow up and
port the RISC-V passes to the new pass manager. This PR starts that
task. It provides the bare minimum necessary to run RISCVCodeGenPrepare
with opt -passes=riscv-codegenprepare. The approach used is modeled on
my observations of the AMDGPU backend and the recent work to port the
X86 passes.

The testing approach is to add a `-passes=riscv-foo` RUN line to at
least one test, if an appropriate test exists.
DeltaFile
+53-29llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+20-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+10-2llvm/lib/Target/RISCV/RISCV.h
+5-2llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
+89-335 files

LLVM/project 5109f2allvm/utils profcheck-xfail.txt

Exclude from profcheck a vplan test under phase ordering (#168669)

DeltaFile
+1-0llvm/utils/profcheck-xfail.txt
+1-01 files

LLVM/project ed1c8d7lld/test/ELF dso-undef-extract-lazy.s

ELF,test: Test unversioned undefined symbols of index 0 and 1

My 2020 change that added versioned symbol recognition
(reviews.llvm.org/D80059) checks both VER_NDX_LOCAL and VER_NDX_GLOBAL,
though test coverage was missing. lld/test/ELF/dso-undef-extract-lazy.s
checks that the undefined symbol is indeed considered unversioned.
DeltaFile
+41-0lld/test/ELF/dso-undef-extract-lazy.s
+41-01 files

LLVM/project 5bba4fdlibc/test/src/stdio fileop_test.cpp

[libc] Fix -Wshorten-64-to-32 in fileop_test. (#168451)

Explicitly cast 0 to size_t type to match fread() return type. This
follows the pattern used elsewhere in this file, and fixes
-Wshorten-64-to-32 warnings when building the test.
DeltaFile
+2-2libc/test/src/stdio/fileop_test.cpp
+2-21 files

LLVM/project be1a504orc-rt/include/orc-rt Session.h, orc-rt/lib/executor Session.cpp

[orc-rt] Simplify Session shutdown. (#168664)

Moves all Session member variables dedicated to shutdown into a new
ShutdownInfo struct, and uses the presence / absence of this struct as
the flag to indicate that we've entered the "shutting down" state. This
simplifies the implementation of the shutdown process.
DeltaFile
+18-25orc-rt/lib/executor/Session.cpp
+8-7orc-rt/include/orc-rt/Session.h
+26-322 files

LLVM/project 9dc4ebfmlir/include/mlir/Dialect/XeGPU/IR XeGPUTypes.td XeGPUOps.td, mlir/lib/Conversion/XeGPUToXeVM XeGPUToXeVM.cpp

[MLIR][XeGPU] Allow create mem desc from 2d memref (#167767)

This PR relax the create_mem_desc's restriction on source memref,
allowing it to be a 2d memref.
DeltaFile
+52-29mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir
+9-29mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
+21-0mlir/test/Dialect/XeGPU/ops.mlir
+11-0mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
+3-8mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+1-1mlir/test/Dialect/XeGPU/invalid.mlir
+97-676 files

LLVM/project f38cf01libclc/opencl/lib/amdgcn/cl_khr_int64_extended_atomics minmax_helpers.ll, libclc/opencl/lib/generic/atomic atom_min.cl atom_max.cl

[libclc] Use CLC atomic functions for legacy OpenCL atom/atomic builtins (#168325)

Main changes:
* OpenCL legacy atom/atomic builtins now call CLC atomic functions
(which use Clang __scoped_atomic_*), replacing previous Clang __sync_*
functions.
* Change memory order from seq_cst to relaxed; keep device scope (spec
permits broader than workgroup). LLVM IR for _Z8atom_decPU3AS1Vi in
amdgcn--amdhsa.bc:
  Before:
%2 = atomicrmw volatile sub ptr subrspace(1) %0, i32 1
syncscope("agent") seq_cst
  After:
%2 = atomicrmw volatile sub ptr subrspace(1) %0, i32 1
syncscope("agent") monotonic
* Also adds OpenCL 1.0 atom_* variants without volatile on the pointer.
They are added for backward compatibility.
DeltaFile
+0-55libclc/opencl/lib/amdgcn/cl_khr_int64_extended_atomics/minmax_helpers.ll
+20-25libclc/opencl/lib/generic/atomic/atom_min.cl
+20-25libclc/opencl/lib/generic/atomic/atom_max.cl
+19-16libclc/opencl/lib/generic/atomic/atom_xor.cl
+19-16libclc/opencl/lib/generic/atomic/atom_xchg.cl
+19-16libclc/opencl/lib/generic/atomic/atom_sub.cl
+97-15320 files not shown
+208-28326 files

LLVM/project f7f4135llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/AArch64 interleave-with-gaps.ll store-costs-sve.ll

[LV]: Skip Epilogue scalable VF greater than RemainingIterations. (#156724)

Consider skipping epilogue scalable VF when they are greater than
RemainingIterations same as fixed VF.
And skip scalable RemainingIterations from that comparison because
SCEV ATM can't evaluate non-canonical vscale-based expressions.
DeltaFile
+17-119llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
+28-27llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
+18-7llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+63-1533 files

LLVM/project c942ebd.github new-prs-labeler.yml, .github/workflows new-prs.yml

Reapply "[Github] Update PR labeller to v6.0.1 (#167246)"

This reverts commit d772663a9f003a08ee76414397963c58e80b27d7.

This fixes the final issue with the labeller landing. There were
two remaining issues:
1. There was an extra quote on one of the globs
2. Some of the yaml keys were named incorrectly (should have been
   plural)
DeltaFile
+1,130-812.github/new-prs-labeler.yml
+1-4.github/workflows/new-prs.yml
+1,131-8162 files

LLVM/project fa50a68llvm/lib/Target/PowerPC PPCISelLowering.cpp PPCISelLowering.h, llvm/test/CodeGen/PowerPC saddo-ssubo.ll

[PowerPC] Add custom lowering for SADD overflow for i32 and i64 (#159255)

This patch improves the codegen for saddo on i32 and i64 in both 32-bit
and 64-bit modes by custom lowering. It implements signed-add overflow
detection using the `(x eqv y) & (sum xor x)`bit-level sequence.
DeltaFile
+37-1llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+10-12llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
+1-0llvm/lib/Target/PowerPC/PPCISelLowering.h
+48-133 files

LLVM/project 56c9655compiler-rt/test/asan/TestCases/Darwin lit.local.cfg.py interface_symbols_darwin.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+25-0compiler-rt/test/asan/TestCases/Darwin/lit.local.cfg.py
+11-7compiler-rt/test/asan/TestCases/Darwin/interface_symbols_darwin.cpp
+2-13compiler-rt/test/asan/TestCases/Darwin/dyld_insert_libraries_reexec.cpp
+38-203 files

LLVM/project ae8c0e1compiler-rt/test/asan/TestCases/Darwin lit.local.cfg.py interface_symbols_darwin.cpp, compiler-rt/test/asan/TestCases/Darwin/Inputs check-syslog.sh

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+25-0compiler-rt/test/asan/TestCases/Darwin/lit.local.cfg.py
+11-7compiler-rt/test/asan/TestCases/Darwin/interface_symbols_darwin.cpp
+2-13compiler-rt/test/asan/TestCases/Darwin/dyld_insert_libraries_reexec.cpp
+3-7compiler-rt/test/asan/TestCases/Darwin/duplicate_os_log_reports.cpp
+6-0compiler-rt/test/asan/TestCases/Darwin/Inputs/check-syslog.sh
+47-275 files

LLVM/project 725ef09compiler-rt/test/asan/TestCases/Darwin interface_symbols_darwin.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+11-7compiler-rt/test/asan/TestCases/Darwin/interface_symbols_darwin.cpp
+11-71 files

LLVM/project afdc509compiler-rt/test/asan/TestCases/Darwin lit.local.cfg.py interface_symbols_darwin.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+25-0compiler-rt/test/asan/TestCases/Darwin/lit.local.cfg.py
+11-7compiler-rt/test/asan/TestCases/Darwin/interface_symbols_darwin.cpp
+2-13compiler-rt/test/asan/TestCases/Darwin/dyld_insert_libraries_reexec.cpp
+38-203 files

LLVM/project f4354b3compiler-rt/test/asan/TestCases/Darwin interface_symbols_darwin.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+11-7compiler-rt/test/asan/TestCases/Darwin/interface_symbols_darwin.cpp
+11-71 files

LLVM/project 52ed0f2clang/lib/Basic/Targets Sparc.cpp, clang/test/CodeGen/Sparc inline-asm-gcc-regs.c

[SPARC][clang] Add condition code register names for inline asm (#168498)

This follows the list of names used by GCC.
DeltaFile
+13-0clang/test/CodeGen/Sparc/inline-asm-gcc-regs.c
+5-0clang/lib/Basic/Targets/Sparc.cpp
+18-02 files

LLVM/project 5ee95f4llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fshr-new-regbank-select.ll

[AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR (#159818)

DeltaFile
+35-0llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+39-02 files

LLVM/project 52a58a4clang/include/clang/Basic BuiltinsAMDGPU.def, clang/test/CodeGenOpenCL amdgpu-features.cl builtins-amdgcn-fiji.cl

[AMDGPU] Adding instruction specific features (#167809)

DeltaFile
+100-8llvm/lib/Target/AMDGPU/AMDGPU.td
+49-49clang/test/CodeGenOpenCL/amdgpu-features.cl
+86-0clang/test/CodeGenOpenCL/builtins-amdgcn-fiji.cl
+0-67clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+51-1llvm/lib/TargetParser/TargetParser.cpp
+11-11clang/include/clang/Basic/BuiltinsAMDGPU.def
+297-13611 files not shown
+356-17117 files

LLVM/project b4aa3d3llvm/lib/Target/AMDGPU SIFoldOperands.cpp GCNSubtarget.h

[NFC] Check operand type instead of opcode (#168641)

A folow-up of #168458.
DeltaFile
+13-21llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+1-1llvm/lib/Target/AMDGPU/GCNSubtarget.h
+14-222 files

LLVM/project a3ab110llvm/utils/TableGen/Common CodeGenTarget.cpp

[TableGen] Silence a warning (NFC)

/llvm-project/llvm/utils/TableGen/Common/CodeGenTarget.cpp:286:12:
 error: variable 'SkippedInsts' set but not used [-Werror,-Wunused-but-set-variable]
  unsigned SkippedInsts = 0;
           ^
1 error generated.
DeltaFile
+1-1llvm/utils/TableGen/Common/CodeGenTarget.cpp
+1-11 files

LLVM/project 719c41amlir/include/mlir/Pass Pass.h, mlir/lib/Pass Pass.cpp

[mlir][Pass] Fix crash when applying a pass to an optional interface
DeltaFile
+33-1mlir/test/Dialect/Transform/test-pass-application.mlir
+8-0mlir/include/mlir/Pass/Pass.h
+3-3mlir/lib/Pass/Pass.cpp
+1-1mlir/test/Pass/pipeline-invalid.mlir
+45-54 files

LLVM/project 961940ellvm/include/llvm/Analysis TargetTransformInfo.h, llvm/include/llvm/CodeGen BasicTTIImpl.h

[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029)

- Split from #165532. This is a step toward a unified interface for
masked/gather-scatter/strided/expand-compress cost modeling.
- Replace the ad-hoc parameter list with a single attributes object.

API change:
```
- InstructionCost getMaskedMemoryOpCost(Opcode, Src, Alignment,
-                                       AddressSpace, CostKind);

+ InstructionCost getMaskedMemoryOpCost(MemIntrinsicCostAttributes,
+                                       CostKind);
```
Notes:
- NFCI intended: callers populate MemIntrinsicCostAttributes with the
same information as before.
- Follow-up: migrate gather/scatter, strided, and expand/compress cost
queries to the same attributes-based entry point.
DeltaFile
+27-1llvm/include/llvm/Analysis/TargetTransformInfo.h
+14-10llvm/include/llvm/CodeGen/BasicTTIImpl.h
+13-6llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+10-7llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+8-6llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+8-4llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+80-3411 files not shown
+107-6217 files

LLVM/project 54f9084clang/lib/CodeGen BackendUtil.cpp, llvm/include/llvm/Transforms/Instrumentation BoundsChecking.h

fmt

Created using spr 1.3.7
DeltaFile
+2-2clang/lib/CodeGen/BackendUtil.cpp
+2-1llvm/include/llvm/Transforms/Instrumentation/BoundsChecking.h
+4-32 files

LLVM/project 676ae65clang/include/clang/Basic CodeGenOptions.def, clang/include/clang/Options Options.td

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+6-0clang/lib/Driver/SanitizerArgs.cpp
+5-0clang/include/clang/Options/Options.td
+5-0clang/test/Driver/fsanitize.c
+2-0clang/include/clang/Basic/CodeGenOptions.def
+1-0compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
+38-01 files not shown
+39-07 files

LLVM/project f9f9aa7clang/lib/CodeGen CGExpr.cpp, clang/test/CodeGen cfi-icall-trap-recover-runtime.c

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+36-0clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
+24-0clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+16-0llvm/test/Instrumentation/BoundsChecking/runtimes.ll
+10-0llvm/lib/Passes/PassBuilder.cpp
+7-0clang/lib/CodeGen/CGExpr.cpp
+112-010 files not shown
+148-316 files