[Support] Remove cl::Sink (#224953)
Nothing uses it: the last users, clang's offloading linker wrappers,
moved to OptTable. The feature would block migration to TableGen based
representation. An unknown option is now always an error.
LLM-aided
[AMDGPU][InstCombine] Fold zero dot operands to accumulator
Fold AMDGPU dot intrinsics when either operand is zero.
`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
[AMDGPU][InstCombine] Fold constant add/sub into the dot accumulator
`amdgcn.{s,u}dot{2,4,8}(a, b, C) +/- K -> dot(a, b, C +/- K)` when both the
accumulator C and K are constants. The new constant is computed with
wrapping APInt arithmetic to match the non-clamping accumulate.
Only applies when clamp is false (the saturating accumulate does not
reassociate) and the dot has a single use. K - dot is left alone since it
would need the dot product negated.
[AMDGPU][InstCombine] Fold zero dot operands to accumulator
Fold AMDGPU dot intrinsics when either operand is zero.
`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
[AMDGPU][InstCombine] Fold constant add/sub into the dot accumulator
`amdgcn.{s,u}dot{2,4,8}(a, b, C) +/- K -> dot(a, b, C +/- K)` when both the
accumulator C and K are constants. The new constant is computed with
wrapping APInt arithmetic to match the non-clamping accumulate.
Only applies when clamp is false (the saturating accumulate does not
reassociate) and the dot has a single use. K - dot is left alone since it
would need the dot product negated.
[flang][cuda] Record implicit managed attribution in module files
An attribute the compiler applied under -gpu=mem:managed is written into the
module file the same way a user-written one is, so a reader cannot tell them
apart. It then treats the attribute as a user requirement: allocating such a
component in a DEVICE object is rejected, and the memory space the user did
ask for on the object no longer wins.
Spell the distinction in the module file as MANAGED(IMPLICIT), modelled on
INTENT(IN): CUDA-data-attr gains an optional parenthesized qualifier, carried
by a new CUDADataAttrSpec parse-tree node in AttrSpec and ComponentAttrSpec.
ATTRIBUTES(...) keeps the bare attribute, so the qualifier cannot be written
there.
The attribute itself is still written out, so a component keeps the same
memory space no matter which options a consumer is compiled with.
Also stop an implicitly applied attribute from making a module a definer of
CUDA symbols. Without this, adding -gpu=mem:managed to a module's build
rejects its OpenACC-only consumers over an attribute the user never wrote.
[flang][cuda] Implicitly attribute ALLOCATABLE/POINTER components as managed (#223087)
Under `-gpu=mem:managed`, `resolve-names` implicitly attributes
allocatables and
pointers declared in an ordinary scope as managed.
Apply the same attribution to components in `Post(ComponentDecl)`. An
explicitly
attributed component keeps its own attribute, and a translation unit
without
CUDA Fortran enabled is left alone.
[SandboxVec][LoadStoreVec] Support mixed type vectorization of loads
vectorizeLoads() bailed out unless every load in the chain had the same
element type. Vectorize mixed-type chains too: the chain is loaded with a
single vector load of its combined vector type, whose element type is an
integer when the types differ, and each lane is reinterpreted as the type of
the load it replaces. A load wider than one lane, e.g. a double in a
<N x i32>, spans several lanes and is unpacked with a shuffle.
Lanes are counted in bits rather than elements, since with mixed types a lane
no longer corresponds to one load. Chains whose loads do not cover a whole
number of lanes, or that involve non-integral pointers, are left alone.
Assisted by Claude Opus 5
[SandboxVec][LoadStoreVec][NFC] Generalize reinterpretConstant to values
reinterpretConstant() reinterprets the bits of a constant as another type of
the same size, which is needed for any value once mixed-type load chains are
unpacked, not just for constants. Split the cast logic out into
reinterpretValue(), which works on any Value, and keep reinterpretConstant()
as a wrapper for the constant callers.
While here, handle vectors of pointers by going through <N x iM>, so that the
helper covers every type a lane can have. Casts of constants fold, so the
constant path emits no instructions, as before.
Assisted by Claude Opus 5
[SandboxVec][VecUtils] Use an integer element type for mixed-type bundles
This PR enhances getCombinedVectorTypeFor() to return an integer type
to fit the narrowest element in the bundle, for mixed type bundles.
NFC for homogenously-typed bundles.
[LoongArch] Introduce PseudoAddUpperImm to deduplicate stack-frame base address materialization (#217250)
This is largely inspired by
https://github.com/llvm/llvm-project/pull/211748, except some LoongArch
specific changes, which includes merge 12-bit signed immediate into
`ld/st` instructions while materializing the frame index first to
generate a `lu12i.w + add` combo if we could, instead of a `lu12i.w +
ori + add`. So that we could use a `PseudoAddUpperImm` to replace them
for `MachineLateInstrsCleanup` to deduplicate them later on.
This patch improves SPEC CPU2026 `709.cactus_r` performance by 27% (from
1.64 to 2.09).
**edit:** After replacing some `ld/st` with `ldptr/stptr` as long as
their address offset could not fit in 12-bit imm but could fit in 14-bit
one, the `709.cactus_r` slightly improved from **2.09** to **2.16**,
however this is done by `-O3 -mlasx`, with `-O3 -mlsx`, the score
remains at **2.31**, which shows its bottleneck is no longer on address
materialization.
[clang][bytecode] Check diagnosing() before calling diagnoseUnknownDecl() (#224906)
We can save some small preparations this way, e.g. calling
`getRootVarDecl()`.
[CIR][ABI] Honor abi::ArgInfo::CanBeFlattened in the call-conv lowering (#220579)
**Summary:**
- CanBeFlattened landed on abi::ArgInfo in main
(llvm/llvm-project#220558).
- Consume the abi::ArgInfo::CanBeFlattened flag in the CIR
call-convention lowering bridge.
Assisted by: Claude Opus 4.8
[MLGO] Diagnose unavailable ML advisors under the new pass manager (#224585)
Without an ML model there is no release or development advisor
The legacy pass manager says so and uses the default advisor, but the
new one just crashed
[compiler-rt] Use integers for __gnu_h2f_ieee and __gnu_f2h_ieee (#220167)
In libgcc, these conversion routines use integers in the signature. In
practice compiler-rt's definition has worked because the AAPCS calling
convention passes and returns floats the same as the same-sized integer,
but this may not be the case on all platforms. Thus, update the
signatures to match GCC.
This new version calls the inlined functions directly., changing the
generated code from:
00000000 <__extendhfsf2>:
0: ee100a10 vmov r0, s0
4: e1a01000 mov r1, r0
<snip>
60: e1800001 orr r0, r0, r1
64: ee000a10 vmov s0, r0
68: e12fff1e bx lr
[28 lines not shown]
[C++20] [Modules] Profiling non dependent noexcept expression by pointer (#224528)
Another approach to solve
https://github.com/llvm/llvm-project/issues/191361 and
https://github.com/llvm/llvm-project/issues/224180 than
https://github.com/llvm/llvm-project/pull/222148
I want to avoid competing PR but I do feel the original one's approach
seems too workaround. And I want to emphasize that, in my experience,
finding the root cause is much more harder than find the solution to me.
Many thanks to @ispeters
For the approach itself, I described them in the comments of the PR.
Note that the real problem is we were profiling something is not
completely deserialized, so that even if it is not crash, the logic is
not correct.
[AMDGPU] Fold 24 bit multiply with zero low bits
Fold `MUL_I24` and `MUL_U24` to zero when either operand has known zero
low 24 bits.
For example:
```
llvm.amdgcn.mul.i24(x, 0x01000000) -> 0
```
[SelectionDAG][AMDGPU] Fold mul24 with an AND operand whose low bits are zero
Use SimplifyMultipleUseDemandedBits to simplify AND operands based on the
low 24 bits consumed by mul24.
Fold the multiply to zero when the simplified operand is zero.
This folds cases such as:
mul24(x & 0xff000000, y) -> 0
[SelectionDAG] Handle constants in SimplifyMultipleUseDemandedBits
Replace a non-zero constant with zero when none of its set bits are
demanded.
This allows users of `SimplifyMultipleUseDemandedBits` to eliminate
irrelevant constant bits while preserving the convention that a null
SDValue indicates no simplification.
[AMDGPU] Return zero LDS encoding granularity for dummy targets
Remove the redundant early return and assertion from getLDSEncodingGranule. Return zero when the target has no encoding granularity feature, and document and test the result for unknown and legacy generic targets.
Keep the existing 256-byte default in the assembly printer so compiling without a GPU still produces valid LDS sizes. Test default-target Mesa and PAL encodings and HSA metadata.
Change-Id: Ia0c69a0d7ce2858b31ee64100d37ae34bba6c42c
[AMDGPU] Add LDS encoding granularity to TargetParser
Model LDS encoding granularity with dedicated features and expose the
byte-valued getLDSEncodingGranule query for GPUKind and subarch. Keep
encoding independent of the hardware allocation granularity used for
occupancy; GFX10.3, GFX11 and GFX12.0 encode in 512-byte units while
allocating 1024-byte blocks.
Migrate program resource register and PAL metadata encoding to the new
query and remove getLdsDwGranularity from AMDGPUBaseInfo. gfx9-4-generic
uses gfx950's 1280-byte encoding granule independently of LDS capacity.
Test encoding queries, feature membership, generic-target validation and
encoded LDS sizes, including the GFX10.3 allocation/encoding distinction.
Change-Id: I9d3c2c041605e9a45fa8fbda09fc3460a74953ea
[SelectionDAG] Fix FP8 conversions to half for subnormals and overflow
Preserve subnormal values when the source format and destination have the
same exponent bias. Normalizing these inputs previously produced a
nonpositive destination exponent and an invalid floating-point encoding.
Convert finite values beyond the destination exponent range to infinity,
while preserving the existing NaN handling. This fixes Float8E5M3FNU to
half conversions that previously produced NaNs on overflow.
Add scalar and vector coverage for subnormals, signed zeros, normal
boundaries, all seven overflowing E5M3FNU encodings, and NaNs.
