1,045,191 commits found in 55 milliseconds
LLVM /project be18ac8 — llvm/lib/Target/SPIRV SPIRVGlobalRegistry.cpp, llvm/test/CodeGen/SPIRV memset-large-size.ll [SPIRV] Fix APInt overflow in memset constant array creation (#180189)
In getOrCreateConstIntArray(), the cache UniqueKey encoded the array
size (Num) using the array element type (e.g. i8 for memset). Since Num
is a size_t that can exceed 255, this caused an APInt overflow when Num
> 255. Use i64 for Num in the UniqueKey. LLVM /project 9e355c8 — llvm/include/llvm/IR IntrinsicsSPIRV.td, llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp SPIRVLegalizePointerCast.cpp [SPIRV] Fix alignment overflow in memory intrinsics (#180184)
Per SPIR-V spec alignment is 32-bit integer, so it should be encoded as
i8 in the intrinsics'
def. LLVM /project b74f8ad — clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp [NFC] [FlowSensitive] [StatusOr] Add tests for member accesses
Reviewers: jvoung
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/180077
LLVM /project 1c3ed97 — clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp address comment
Created using spr 1.3.7
LLVM /project b2f7508 — llvm/utils/gn/secondary/clang/lib/Analysis BUILD.gn, llvm/utils/gn/secondary/clang/unittests/Analysis BUILD.gn [gn build] Port ec15bddde5cb
[gn build] Port eff21afae01f
[gn build] Port 66f9ffbb2c28
LLVM /project 9fe8e8b — llvm/utils/gn/secondary/llvm/lib/CAS BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/CAS BUILD.gn [gn build] Port 60ecb3789606
[gn build] Port 28042a87022b
LLVM /project ec15bdd — clang/include/clang/Analysis CFGBackEdges.h, clang/lib/Analysis CFGBackEdges.cpp CMakeLists.txt [clang][analysis][dataflow] Detect goto backedges to trigger Widen (#179546)
Currently, the Clang Dataflow Framework only does Widen on backedges
from structured loops.
Missing some Widen calls (e.g., when there are backedges from gotos)
could cause some analyses to iterate ~forever (until the max visits
limit is hit).
This adds a simple search for backedges, and triggers Widen on the
additional backedge nodes. Fixes [issue 179083.
](https://github.com/llvm/llvm-project/issues/179083 ) LLVM /project 60ecb37 — llvm/include/llvm/CAS OnDiskGraphDB.h, llvm/lib/CAS OnDiskGraphDB.cpp BuiltinObjectHasher.cpp [llvm/CAS] Add file-based APIs to `OnDiskGraphDB` (#179782)
These allow performing optimizations that reduce I/O and disk space
consumption. For example, when applicable, a file can be cloned directly
into the database directory, instead of needing to load it in memory and
then copy its contents into a new file.
These APIs are then used to optimize importing data from an upstream DB
by using file cloning where applicable. LLVM /project 1bb916c — clang/test/CodeGenHLSL matrix-member-one-based-accessor-scalar-load.hlsl matrix-member-zero-based-accessor-scalar-load.hlsl, clang/test/CodeGenHLSL/BasicFeatures MatrixExplicitTruncation.hlsl MatrixImplicitTruncation.hlsl [HLSL] Represent Matrix as arrays of vectors in memory (#179861)
fixes https://github.com/llvm/llvm-project/issues/179859
For matrix types we need to check the language mode so we can change the
matrix memory layout to arrays of vectors. To make this play nice with
how the rest of clang treats matrices we need to modify the
MaybeConvertMatrixAddress and the CreateMemTemp function to know how to
reconstruct a flattened vector.
Rest of changes is just test updates. LLVM /project 703c276 — llvm/lib/Analysis IVDescriptors.cpp, llvm/lib/Transforms/Vectorize VPlanConstruction.cpp Revert "[LV] Support conditional scalar assignments of masked operations" (#180275)
Reverts llvm/llvm-project#178862
revert to unblock bot:
https://lab.llvm.org/buildbot/#/builders/206/builds/13225 LLVM /project 66f9ffb — llvm/lib/Target/Hexagon HexagonLiveVariables.cpp HexagonLiveVariables.h, llvm/test/CodeGen/Hexagon nbench1.ll [Hexagon] Add post-RA live variables analysis (#179531)
This patch adds HexagonLiveVariables, a post-RA liveness analysis for
physical registers, to keep block live-ins/live-outs and operand
kill/dead markers consistent after late Hexagon transforms; it is run
after GenMux in the pre-emit pipeline.
Author: Sergei Larin <slarin at qti.qualcomm.com>
Patch By: Fateme Hosseini <fhossein at qti.qualcomm.com>
Co-authored-by: Sergei Larin <slarin at qti.qualcomm.com> LLVM /project bd40d1d — llvm/include/llvm/Analysis ScalarEvolutionPatternMatch.h, llvm/lib/Transforms/Utils ScalarEvolutionExpander.cpp Reapply "[SCEVExp] Use SCEVPtrToAddr in tryToReuseLCSSAPhi if possible. (#180257)"
This reverts commit cb905605b2e95f88296afe136b21a7d2476cb058 .
Recommit the patch with a small change to check the destination
type matches the address type, to avoid a crash on mismatch.
Original message:
This patch updates tryToReuseLCSSAPhi to use SCEVPtrToAddr, unless using
SCEVPtrToInt allows re-use, because the IR already contains a re-usable
phi using PtrToInt.
This is a first step towards migrating to SCEVPtrToAddr and avoids
regressions in follow-up changes.
PR: https://github.com/llvm/llvm-project/pull/178727
LLVM /project 5f644d9 — lld/test/wasm import-attribute-mismatch.s, lld/test/wasm/Inputs import-attributes.s [lld][WebAssembly] Improve import mismatch error reporting (#178715)
Followup to #178550 LLVM /project 543b949 — llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/Target/WebAssembly BUILD.gn [gn] port 9976e5702f05a40 more
LLVM /project 604ccfd — clang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeAnnotations.h, clang/lib/Analysis/LifetimeSafety LifetimeAnnotations.cpp FactsGenerator.cpp handle unique_ptr::release
LLVM /project 863b071 — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll update
Created using spr 1.3.7
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 881 files not shown +48,234 -22,426 887 files
LLVM /project 891cc07 — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 881 files not shown +48,234 -22,426 887 files
LLVM /project 0f2a3aa — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll update
Created using spr 1.3.7
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 881 files not shown +48,234 -22,426 887 files
LLVM /project c692bd1 — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 881 files not shown +48,234 -22,426 887 files
LLVM /project ec8706c — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll update
Created using spr 1.3.7
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 882 files not shown +48,277 -22,426 888 files
LLVM /project 1b542d8 — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 882 files not shown +48,277 -22,426 888 files
LLVM /project 178bda4 — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll update
Created using spr 1.3.7
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 882 files not shown +48,277 -22,426 888 files
LLVM /project eb03e2e — llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/Transforms/LoopVectorize vplan-printing-reductions.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Delta File +5,528 -5,528 llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +4,314 -4,314 llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +1,260 -1,260 llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +902 -902 llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +927 -613 llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +1,380 -72 llvm/test/CodeGen/AMDGPU/div_v2i128.ll +14,311 -12,689 882 files not shown +48,277 -22,426 888 files
LLVM /project 21fb35b — clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp [NFC] [FlowSensitive] [StatusOr] Add test for move assignment
Reviewers: jvoung
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/180080
LLVM /project 233976c — clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp [NFC] [FlowSensitive] [StatusOr] Add test for more complicated Status logic
Reviewers: jvoung
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/180075
LLVM /project 29d374b — clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp [NFC] [FlowSensitive] [StatusOr] Add tests for StatusOr ctors
Reviewers: jvoung
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/180076
LLVM /project bf4f5d2 — llvm/test/CodeGen/X86 cfi-inserter-callee-save-register-2.mir cfi-epilogue-without-return.mir [X86][test] Auto-generate test checks for some cfi tests. NFC (#177248)
