[mlir][tosa] Add integer bitwidth conversion pass (#232853)
Add tosa-convert-integer-types-bitwidth to convert i4 to i8 and/or i48
to i64. This is useful to facilitate lowering to backends that do not
support i4 and/or i48.
Add a host byte-order lit feature to gate tests with little-endian
resource data.
Assisted-by: Codex
[SLP] Freeze undef operand of shl X, 1 expanded to add X, X
add X, X reads X twice, so it does not refine shl X, 1 when X is
undef. Freeze the operand and blend the frozen lanes into the other
operand, unless X is proven not undef or undef X triggers UB.
Assisted-by: Cursor
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/237207
[CIR][AMDGPU] Lower cir.offload.printf to AMDGPU printf (#231563)
Add lowering for cir.offload.printf to the AMDGPU printf logic employed
by OGCG. Most of the functions added in
clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOffloadPrintf.cpp are CIR
equivalents to the functions in
llvm/lib/Transforms/Utils/AMDGPUEmitPrintf.cpp.
Assisted-by: Claude Opus 5.5
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
[libc++] Add a few _LIBCPP_HIDE_FROM_ABI which have been accidentally removed in #201722 (#236733)
These annotations should have stayed, since the functions are in a spot
where explicit annotation are required.
[libc++][NFC] Move checks whether mutex/condition_variable are trivial to their headers (#236806)
The moved macros are only used as implementation details of `mutex` and
`condition_variable` aren't used widely within the library, so they can
be moved to be more local.
[compiler-rt] Remove dlsym interceptor and support `-shared-libsan` for CSan
Summary:
Follow the UBSan offload runtime. Offload now resolves HSA through the
global scope, so the `dlsym` interceptor is no longer needed. The real
HSA entry points are still taken from the loaded HSA library rather than
`RTLD_NEXT`, since every DSO with a static runtime exports the same
wrappers and they would otherwise chain back into each other.
Build `libclang_rt.csan.so` with the offload objects folded in. The
exported HSA wrappers report failure when HSA is absent and warn when HSA
was loaded ahead of the runtime. The preinit hook moves to a separate
`csan_offload-preinit` archive for executables.
[compiler-rt] Add 'csan' library for the concurrency sanitizer
Summary:
Adds the runtime for the concurrency sanitizer, both CPU and GPU.
Fundamentally, this works using the following pseudocode:
```c
static u64 watchpoints[N]; // Hash-indexed, zero is empty.
// Emitted before the access, so we never trip on our own write.
void check_access(volatile void *addr, u32 size, u32 type) {
// Every access probes. A read conflicts only with a watched write, a
// write conflicts with either.
if (u64 *wp = find_watchpoint(addr, size, type))
consume(wp, this_pc()); // Hand our location to the owner.
if (!should_sample()) // Wave-uniform, 1-in-N chance.
return;
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[Clang] Add support for the `-fsanitize=concurrency` runtime
Summary:
Add the frontend sanitizer kind, function attributes, pass pipeline
integration, predefined macro, driver handling, and documentation for
ConcurrencySanitizer.
[Clang] Support `-shared-libsan` for offload CSan
Summary:
Follow the UBSan handling. The shared runtime embeds the HSA
interceptors, so `csan_offload` is only linked with static runtimes and
executables pull in `csan_offload-preinit` to initialize early.
[clang][bytecode][NFC] Remove reflection indirection in builtins (#237106)
The additional indirection through InterpretReflectionBuiltin adds
nothing other than more complexity and a function call that returns
`false` for basically ALL cases.
Remove the call to InterpretReflectionBuiltin and just add the
reflection builtin to the existing switch. If this file gets to big, we
can still move the individual reflection functions in a different file.
Keep distinguished volatile reads before a later write
A volatile write is reported as atomic, so it does not cover an earlier
plain read. A smaller write or an intervening acquire still drops the
read, matching ThreadSanitizer.
[AMDGPU] Add tests for misaligned AGPR tuples in memory-op operands, NFC (#236205)
Pre-commit test: on gfx90a, misaligned AGPR tuples in DS/FLAT/global
atomics are currently rejected by the generic validateVGPRAlign scan
("invalid register class: vgpr tuples must be 64 bit aligned"), unlike
their VGPR counterparts which are rejected by the operand register class
("invalid operand for instruction"). A following change routes the AGPR
memory-op operands through the aligned operand class to match.
---------
Co-authored-by: Claude <noreply at anthropic.com>
[AMDGPU] Add tests for misaligned packed-f64 source operands, NFC (#236872)
Pre-commit test: cover the remaining source positions of the packed
64-bit VALU instructions with a misaligned VGPR tuple -- src1 of
v_pk_add_f64 and src2 of v_pk_fma_f64 / v_pk_lshl_add_u64. Like the
existing cases, these are currently rejected only by the generic
validateVGPRAlign scan, because the assembler operand predicates for
VSrc_v2f64 / VSrc_v2b64 use the plain VS_128 class.
Co-authored-by: Claude <noreply at anthropic.com>
[offload] Add direct-write memcpys to liboffload and implement them on AMDGPU (#231922)
Let olMemcpy transparently use direct H2D writes. These are unordered
with respect to currently enqueued operations, so only employ them if no
queue is given. The direct transfers are not unordered with respect to
operations that get enqueued afterwards, since they will be completed
upon completion of the corresponding olMemcpy call.
The AMDGPU implementation is a transfer of the ROCr/HIP implementation.
It more or less boils down to a std::memcpy with fences around it.
Claude assisted with this patch.
