CodeGen: Prefer getting the Triple from the Module when convenient
Take the triple from the contextual module rather than TargetMachine
when it's already readily available.
CodeGen: Run LiveIntervals before PHIElimination and drop LiveVariables from it
Move LiveIntervals to run before PHIElimination in the optimized register
allocation pipeline, and make PHIElimination maintain LiveIntervals only.
This removes the last explicit use of LiveVariables. The actual analysis is no
longer used. There are implicit dependencies on the side effects of running the
analysis due to adjustments of dead flags, so further work is still needed to
complete the removal.
This perturbs register allocation in a number of tests. The same codegen result
can be achieved by not preserving the analysis and recomputing fresh. Greedy is
just sensitive to the exact slot index and value numbering with identical MIR.
Measured across every affected test the emitted instruction count goes from
145124 to 145196, +0.050%, with changes in both directions. The largest
regression is AArch64/phi.ll, where the GlobalISel output gains about 30
instructions and no longer matches the SelectionDAG output; the largest
improvements are ARM/fpclamptosat.ll and PowerPC/common-chain.ll.
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[ClangIR] Support __builtin_coro_noop (#227573)
Support `__builtin_coro_noop` in ClangIR:
- Add `CIR_CoroNoopOp` (`cir.coro.intrinsic.noop`) in `CIROps.td` with
TableGen lowering to `llvm.coro.noop`.
- Handle `Builtin::BI__builtin_coro_noop` in `CIRGenBuiltin.cpp`.
- Add roundtrip (`clang/test/CIR/IR/coro-noop.cir`) and DirectToLLVM
lowering (`clang/test/CIR/Lowering/coro-noop.cir`) tests.
- Uncomment and test `__builtin_coro_noop()` in
`clang/test/CIR/CodeGenCoroutines/coro-builtins.cpp` with both CIR and
LLVM checks for parity with classic Clang CodeGen.
Closes #227561
DAG: Gracefully diagnose missing fp-compare libcall when softening (#228416)
Avoid fatal errors, and legalize to poison with a proper context error.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[SPIRV] Don't treat noipa aliasees as interposable in SPIRVPrepareGlobals (#228178)
SPIRVPrepareGlobals replaces aliases with their aliasee because the
backend can't lower GlobalAlias. It must skip aliasees that may be
replaced at link time, but `isInterposable()` also returns true for
`noipa` function definitions by default. `noipa` doesn't change which
definition is used at link time, so query
`isInterposable(/*CheckNoIPA=*/false)` so aliases of `noipa` functions
are still replaced.
This is one of a few refinements of noipa identified while working on
making optnone imply noipa - without these refinements,
optnone-implies-noipa, might substantially change clang -O0 codegen. I'm
open to discussing whether these refinements are the right direction,
though.
Assisted-By: Claude
[llvm][Support] Remove stale `ErrorOr` documentation regarding user data. (#227796)
Optional user data support was removed from `ErrorOr` in ca35ffe6a239 in November 2013.
[TableGen][AArch64] Relax EnforceVectorSubVectorTypeIs for mixing fixed and scalable vectors. (#228552)
The minimum elements of a fixed subvector may be greater than or equal
to the minimum elements of the scalable vector when vscale is greater
than 1. With a fixed subvector and a scalable vector we now allow the
subvector to have the same minimum elements as the vector. That covers a
NEON subvector and a SVE vector.
It is possible to have a subvector with more minimum elements than the
vector when vscale is known to be greater than 1, but both RISC-V
vectors and SVE use custom isel rather than tablegen for those cases.
With that fixed, migrate AArch64 to use
extract_subvector/insert_subvector instead of
vector_extract_subvec/vector_insert_subvec. A follow up will remove
vector_extract_subvec/vector_insert_subvec.
[KnownFPClass] Refine positive zero result for sqrt (#214987)
Refines `KnownFPClass::sqrt` for positive zero:
- Only `sqrt(x) == +0.0` iff `x` is `+0.0` or `x` flushes to `+0.0` in
the current denormal mode. The `-0.0` case was handled in a prior
commit.
AI disclosure:
I used OpenAI Codex (GPT-5.6-sol) to help generate the test updates,
which I reviewed and tested locally.
CodeGen: Prefer getting the Triple from the Module when convenient
Take the triple from the contextual module rather than TargetMachine
when it's already readily available.
[ARM] Use extract_subvector instead of vector_extract_subvec in ARMInstrNEON.td. NFC (#228542)
extract_subvector has a stricter SDTypeProfile than
vector_extract_subvec.
I'm investigating why we need vector_extract_subvec. The only other
users are in AArch64SVEInstrInfo.td so maybe something to do with
scalable vectors.
[lldb/Interpreter] Read Scripted Process addressable bits from its metadata (#227515)
This patch addresses post-merge feedback on #224701.
That change added a dedicated `get_addressable_bits` affordance to
scripted processes, which duplicates a property the process already has.
This patch removes it and reads the addressable bits from an optional
"addressable_bits" key in the dictionary returned by
`get_process_metadata` instead. `ScriptedProcess::DidLaunchOrAttach`
still passes the value to `SetAddressableBitMasks` before the first stop
is reported. When the key is missing, the setter is never called and the
process keeps the masks it inherits from the target.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
[LiveDebugVariables] Repair stale SlotIndexes
The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.
SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
[SlotIndexes] Add queries for stale indexes
An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.
NFC. No caller yet. LiveDebugVariables is next.
