LLVM/project c138fc9llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 ragreedy-csr.ll br-cond-merging-loaded-operands.ll

[AArch64] Don't merge branch conditions that both compare memory loads (#206504)

`shouldKeepJumpConditionsTogether` decides whether to fold two integer
branch conditions into a CMP/CCMP chain by pricing the RHS
dependency-chain latency. That ignores register pressure: when both
conditions compare loaded values, merging pins all the loaded operands
live at once to feed the chain instead of consuming them at each split
compare-and-branch. On a load-store target that extends their live
ranges across the region the branch dominates.

Decline to merge when both sides are integer compares of loaded values,
mirroring the machine CCMP pass (which won't speculate loads).

Reference:
https://github.com/llvm/llvm-project/pull/201486#issuecomment-4812845942
DeltaFile
+55-51llvm/test/CodeGen/AArch64/ragreedy-csr.ll
+99-0llvm/test/CodeGen/AArch64/br-cond-merging-loaded-operands.ll
+25-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+179-513 files

LLVM/project b388c7allvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64/Atomics aarch64_be-atomic-load-lse2.ll aarch64_be-atomic-load-lse2_lse128.ll

[AArch64] acquire fence for LSE2 128-bit SC loads
DeltaFile
+8-8llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2.ll
+8-8llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2_lse128.ll
+8-8llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-lse2.ll
+8-8llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-lse2_lse128.ll
+7-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+39-355 files

LLVM/project 3d59bccllvm/docs/CommandGuide lit.rst, llvm/utils/lit/lit cl_arguments.py util.py

[lit] Add configurable slowest-test limit to --time-tests

Bare --time-tests still defaults to 20; --time-tests=N and --time-tests=all optionally control the slowest-test list shown in the histogram.
DeltaFile
+40-6llvm/utils/lit/tests/time-tests.py
+43-2llvm/utils/lit/lit/cl_arguments.py
+9-4llvm/utils/lit/lit/util.py
+7-3llvm/docs/CommandGuide/lit.rst
+4-4llvm/utils/lit/lit/main.py
+103-195 files

LLVM/project 274a345clang/lib/Driver OffloadBundler.cpp, clang/test/Driver clang-offload-bundler-magic-collision.c

[OffloadBundler] Bound compressed bundles by header size, not magic scan (#206745)

When multiple offload bundles are concatenated, the unbundler
(clang-offload-bundler) and llvm-objdump --offloading located the end of
a compressed bundle, and the start of the next one, by scanning for the
next "CCOB" magic string starting right after the current header.

A zstd/zlib-compressed payload can legally contain those four bytes, so
the scan could stop in the middle of the compressed data and truncate
the bundle, corrupting the embedded code object. In practice this
produced a "decomposition" failure for hipBLASLt bf16 GEMMs on gfx942.

Use the authoritative total-size field recorded in the compressed bundle
header (format V2/V3) to compute the exact bundle boundary, and only
scan for the next magic past that point. Legacy bundles without a
recorded size (V1) keep the previous magic-scan fallback.

A skippable-frame fixture that embeds "CCOB" inside the compressed
payload is added to exercise the boundary logic from both
clang-offload-bundler and llvm-objdump --offloading.
DeltaFile
+104-0clang/test/Driver/Inputs/clang-offload-bundler-magic-collision.py
+37-4clang/lib/Driver/OffloadBundler.cpp
+35-0llvm/test/tools/llvm-objdump/Offloading/fatbin-magic-collision.test
+28-5llvm/lib/Object/OffloadBundle.cpp
+27-0clang/test/Driver/clang-offload-bundler-magic-collision.c
+0-0clang/test/Driver/Inputs/clang-offload-bundler-magic-collision.co
+231-96 files

LLVM/project d3d18callvm/lib/CodeGen AtomicExpandPass.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ISelLowering.h

[AArch64] ldiapp for 128-bit SC load with rcpc3
DeltaFile
+30-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+8-16llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc3.ll
+8-16llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-rcpc3.ll
+10-13llvm/lib/CodeGen/AtomicExpandPass.cpp
+4-0llvm/lib/Target/AArch64/AArch64ISelLowering.h
+60-485 files

LLVM/project daaf105llvm/docs/CommandGuide lit.rst, llvm/utils/lit/lit cl_arguments.py util.py

[lit] Add configurable slowest-test limit to --time-tests

Bare --time-tests still defaults to 20; --time-tests=N and --time-tests=all optionally control the slowest-test list shown in the histogram.
DeltaFile
+40-6llvm/utils/lit/tests/time-tests.py
+43-2llvm/utils/lit/lit/cl_arguments.py
+9-4llvm/utils/lit/lit/util.py
+6-4llvm/utils/lit/lit/main.py
+7-3llvm/docs/CommandGuide/lit.rst
+105-195 files

LLVM/project 6da162ellvm/test/CodeGen/DirectX/ContainerData SourceInfo-Strip.ll

Skip checking the size
DeltaFile
+1-2llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Strip.ll
+1-21 files

LLVM/project d405259clang/lib/Driver/ToolChains Clang.cpp, llvm/lib/Target/DirectX DXILTranslateMetadata.cpp DXContainerGlobals.cpp

Add /Qsource_in_debug_module flag
DeltaFile
+110-0llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Strip.ll
+15-9llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
+7-4llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
+4-0clang/lib/Driver/ToolChains/Clang.cpp
+4-0llvm/test/CodeGen/DirectX/embed-ildb.ll
+2-1llvm/lib/Target/DirectX/DXContainerGlobals.cpp
+142-142 files not shown
+147-148 files

LLVM/project 092f445clang/include/clang/AST DeclTemplate.h, clang/lib/AST DeclTemplate.cpp

Revert "[clang] Reland: fix getTemplateInstantiationArgs (#208285)" (#208426)

It caused various breakages; see comments on the PR.

This reverts commit 031b773b01700acf82f5977a5aa6024621b8211c.
DeltaFile
+429-194clang/lib/Sema/SemaTemplateInstantiate.cpp
+165-301clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
+146-150clang/lib/Sema/SemaTemplate.cpp
+95-96clang/include/clang/AST/DeclTemplate.h
+129-59clang/lib/Sema/SemaConcept.cpp
+92-60clang/lib/AST/DeclTemplate.cpp
+1,056-86064 files not shown
+1,729-1,62470 files

LLVM/project 099ffadllvm/test/CodeGen/X86 combine-pmadd.ll combine-pmaddwd.ll

[X86] combine-pmadd.ll - split into combine-pmaddwd.ll and combine-pmaddubsw.ll (#208430)

Allows better SSE2 test coverage for PMADDWD combines
DeltaFile
+0-474llvm/test/CodeGen/X86/combine-pmadd.ll
+339-0llvm/test/CodeGen/X86/combine-pmaddwd.ll
+173-0llvm/test/CodeGen/X86/combine-pmaddubsw.ll
+512-4743 files

LLVM/project d2395c4clang/include/clang/Sema DeclSpec.h, clang/lib/Parse ParseDecl.cpp

Revert "[clang] Reject 'auto' storage class with type specifier in C++" (#208436)

Reverts llvm/llvm-project#166004.

Breaks stage 2 build, see comments on PR.
DeltaFile
+0-163clang/lib/Sema/DeclSpec.cpp
+48-57clang/test/CXX/dcl.dcl/dcl.spec/dcl.stc/p2.cpp
+2-51clang/include/clang/Sema/DeclSpec.h
+6-38clang/lib/Parse/ParseDecl.cpp
+7-9clang/test/CXX/drs/cwg3xx.cpp
+6-6clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
+69-3249 files not shown
+79-36815 files

LLVM/project d934200clang/include/clang/Sema DeclSpec.h, clang/lib/Parse ParseDecl.cpp

Revert "[clang] Reject 'auto' storage class with type specifier in C++ (#166004)"

This reverts commit d7ccd02c9c78b6576ca2caa3f4d2435ebda50744.
DeltaFile
+0-163clang/lib/Sema/DeclSpec.cpp
+48-57clang/test/CXX/dcl.dcl/dcl.spec/dcl.stc/p2.cpp
+2-51clang/include/clang/Sema/DeclSpec.h
+6-38clang/lib/Parse/ParseDecl.cpp
+7-9clang/test/CXX/drs/cwg3xx.cpp
+6-6clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
+69-3249 files not shown
+79-36815 files

LLVM/project cfa5d6fclang/lib/CodeGen CodeGenModule.cpp CGCall.cpp, llvm/include/llvm/ABI TargetInfo.h

[LLVMABI] Implement the System V X86-64 ABI (#194718)

This PR implements the System V X86-64 ABI for the LLVM ABI Library
prototyped in https://github.com/llvm/llvm-project/pull/140112, and
wires it into clang's Codegen.

`X86_64TargetInfo` is a direct parallel to
`clang::CodeGen::X86_64ABIInfo`, but operates entirely on the
`llvm::abi` type system.
The AMD64 ABI classification spec, argument/return lowering , and the
supporting helpers are all reproduced against `llvm::abi::Type` and
FunctionInfo, keeping the ABI logic frontend-independent.

This, similar to the [BPF ABI implementaiton
](https://github.com/llvm/llvm-project/pull/194031/changes)is gated
under the `-fexperimental-abi-lowering` flag.
DeltaFile
+1,501-0llvm/lib/ABI/Targets/X86.cpp
+63-8clang/lib/CodeGen/CodeGenModule.cpp
+30-0llvm/lib/ABI/Types.cpp
+12-6llvm/lib/ABI/IRTypeMapper.cpp
+9-4clang/lib/CodeGen/CGCall.cpp
+13-0llvm/include/llvm/ABI/TargetInfo.h
+1,628-187 files not shown
+1,650-2013 files

LLVM/project 24a5231llvm/docs AMDGPUUsage.rst, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

AMDGPU: Introduce amdgpu triple arch (#206480)

Move towards using the triple for representing incompatible
ISA changes. Use the subarch field to represent the various
incompatible cases. Previously we pretended a single triple arch
was universally compatible, and only distinguished by function
level subtargets. Move towards using distinct triples to enable
more sophisticated toolchain handling in the future, like proper
runtime library linking.

Introduce a new subarch per unique ISA, but also introduce
"major subarches" which are compatible by a set of covered
minor ISA versions. These map to the existing generic targets.
There are a few placeholder subarch entries, which currently
have missing backing generic arches for codegen.

This should be the preferred triple arch name going forward,
but is treated as an alias of amdgcn. This does not yet change
clang to emit the new triples.

Part of #154925
DeltaFile
+602-481llvm/docs/AMDGPUUsage.rst
+427-0llvm/unittests/TargetParser/TargetParserTest.cpp
+241-11llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+200-12llvm/unittests/TargetParser/TripleTest.cpp
+177-0llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll
+147-15llvm/lib/TargetParser/Triple.cpp
+1,794-51975 files not shown
+2,637-73581 files

LLVM/project 7919d61llvm/test/CodeGen/X86 sat-add.ll

[X86] sat-add.ll - regenerate test check to reduce diff in #189971 (#208418)
DeltaFile
+19-19llvm/test/CodeGen/X86/sat-add.ll
+19-191 files

LLVM/project 05c0a29llvm/test/CodeGen/X86 subvectorwise-store-of-vector-splat.ll

[X86] subvectorwise-store-of-vector-splat.ll - regenerate test checks to reduce diff in #189971 (#208419)

Add AVX1ORAVX2 check prefix to distinguish from AVX512 codegen
DeltaFile
+91-183llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll
+91-1831 files

LLVM/project 1008b48llvm/cmake/modules LLVMConfig.cmake.in

cmake: Remove cmake_crosscompiling check on LLVMSupport target export (#208420)

Revert exported target check added in
00b2f81418233397e601afaeea6d62c47a6c368a
to fix reported mingw cross compile regression. This is the quick fix
which restores the cmake warnings when building libc for amdgpu.
DeltaFile
+1-1llvm/cmake/modules/LLVMConfig.cmake.in
+1-11 files

LLVM/project d855251orc-rt/test/unit SessionTest.cpp ErrorTest.cpp, orc-rt/unittests SessionTest.cpp ErrorTest.cpp

[orc-rt] Move the unit tests into test/unit (#208431)

Move unit tests from orc-rt/unittests into orc-rt/test/unit, completing
the consolidation of the runtime's tests under orc-rt/test (alongside
test/regression and test/tools).
DeltaFile
+0-831orc-rt/unittests/SessionTest.cpp
+831-0orc-rt/test/unit/SessionTest.cpp
+0-502orc-rt/unittests/ErrorTest.cpp
+502-0orc-rt/test/unit/ErrorTest.cpp
+378-0orc-rt/test/unit/TaskGroupTest.cpp
+0-378orc-rt/unittests/TaskGroupTest.cpp
+1,711-1,71195 files not shown
+8,394-8,392101 files

LLVM/project 62a6f96flang/lib/Optimizer/Builder IntrinsicCall.cpp, flang/lib/Optimizer/Transforms MIFOpConversion.cpp

[flang][MIF] Fix COSHAPE and THIS_IMAGE(coarray) type mismatch for non-i64 kinds

Both COSHAPE and THIS_IMAGE(coarray [,team]) return integer arrays whose
element type is determined by the Fortran KIND argument (default: i32).
The lowering code was ignoring resultType in both cases and hardcoding i64,
which caused downstream type mismatches:

- COSHAPE: SimplifyHLFIRIntrinsics assertion in PRODUCT(COSHAPE(y)) when
  the product input type (i64) did not match the declared result type (i32).
- THIS_IMAGE(coarray): MLIR verifier error on arith.cmpi with mismatched
  operand types (i64 vs i32) in comparisons like THIS_IMAGE(a) /= [5,0,-7].

Fix: derive eleTy from resultType in both genCoshape and genThisImage and
propagate it into the mif.* op's result type. In MIFOpConversion, extract
a shared convertI64SeqToEleTy helper that post-converts the i64 scratch
buffer written by the PRIF runtime into the declared-element-type buffer
when the two types differ. Both MIFCoshapeOpConversion and
MIFThisImageOpConversion call this helper.

Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
DeltaFile
+54-0flang/test/Fir/MIF/coshape.mlir
+54-0flang/test/Fir/MIF/this_image.mlir
+46-0flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
+15-6flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+9-2flang/test/Lower/MIF/coshape.f90
+1-1flang/test/Lower/MIF/this_image.f90
+179-96 files

LLVM/project 724ad11llvm/lib/MC MCDXContainerWriter.cpp, llvm/lib/Target/DirectX DXContainerGlobals.cpp

[DirectX] Add `--dx-embed-debug` and `--dx-pdb-path` flags (#204166)

Add flags for DirectX in `llc`:
* `--dx-embed-debug` to embed debug info into ILDB part of DXContainer
* `--dx-pdb-path` to specify filename/path for PDB file output

This patch does not add flags for clang Driver, they will be implemented
later.
DeltaFile
+30-40llvm/lib/Target/DirectX/DXContainerGlobals.cpp
+38-0llvm/test/CodeGen/DirectX/ContainerData/ContainerFlags.ll
+22-0llvm/test/CodeGen/DirectX/ContainerData/DebugName.test
+15-0llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
+14-0llvm/lib/MC/MCDXContainerWriter.cpp
+9-0llvm/test/CodeGen/DirectX/ContainerData/DebugName-user-specified.test
+128-409 files not shown
+142-5315 files

LLVM/project eceb9d5orc-rt/test CMakeLists.txt, orc-rt/test/regression smoke-check.test lit.cfg.py

[orc-rt] Add regression test-tool infrastructure (#208398)

Set up the infrastructure for regression tests that build and run a
helper tool, in preparation for testing the logging backends.

- Add test/tools/ for test-support binaries, with a first tool,
orc-rt-smoke-check, wired into ORC_RT_TEST_DEPS and onto lit's PATH.
- Add test/regression/smoke-check.test, which runs the tool and matches
its output with FileCheck, exercising the tool-build and lit plumbing
end to end.
DeltaFile
+21-0orc-rt/test/tools/orc-rt-smoke-check.cpp
+5-0orc-rt/test/regression/smoke-check.test
+5-0orc-rt/test/regression/lit.cfg.py
+4-0orc-rt/test/tools/CMakeLists.txt
+4-0orc-rt/test/CMakeLists.txt
+39-05 files

LLVM/project fcee294flang/lib/Optimizer/Builder IntrinsicCall.cpp, flang/lib/Optimizer/Transforms MIFOpConversion.cpp

[flang][MIF] Fix COSHAPE and THIS_IMAGE(coarray) type mismatch for non-i64 kinds

Both COSHAPE and THIS_IMAGE(coarray [,team]) return integer arrays whose
element type is determined by the Fortran KIND argument (default: i32).
The lowering code was ignoring resultType in both cases and hardcoding i64,
which caused downstream type mismatches:

- COSHAPE: SimplifyHLFIRIntrinsics assertion in PRODUCT(COSHAPE(y)) when
  the product input type (i64) did not match the declared result type (i32).
- THIS_IMAGE(coarray): MLIR verifier error on arith.cmpi with mismatched
  operand types (i64 vs i32) in comparisons like THIS_IMAGE(a) /= [5,0,-7].

Fix: derive eleTy from resultType in both genCoshape and genThisImage and
propagate it into the mif.* op's result type. In MIFOpConversion, extract
a shared convertI64SeqToEleTy helper that post-converts the i64 scratch
buffer written by the PRIF runtime into the declared-element-type buffer
when the two types differ. Both MIFCoshapeOpConversion and
MIFThisImageOpConversion call this helper.

Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
DeltaFile
+54-0flang/test/Fir/MIF/coshape.mlir
+54-0flang/test/Fir/MIF/this_image.mlir
+48-0flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
+15-6flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+9-2flang/test/Lower/MIF/coshape.f90
+1-1flang/test/Lower/MIF/this_image.f90
+181-96 files

LLVM/project 841e01dllvm/lib/Target/X86 X86InstrCompiler.td, llvm/test/CodeGen/X86 insert.ll

[ISEL] Fix x86-64 instruction selection bug leaking upper 32 bits (#205600)

The x86 backend had optimization patterns that matched:
  `(or (and GR32:$dst, -256), (i32 (zextloadi8 addr:$src)))`
and lowered it to:
  `(INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm  i8mem:$src), sub_8bit)`

INSERT_SUBREG for sub_8bit emits a movb instruction which preserves the
upper 56 bits. Now, if the GR32 dst came from a node that does not zero
the upper 32 bits (like IMPLICIT_DEF or EXTRACT_SUBREG), those upper 32
bits would be leaked into the resulting register without being zeroed.

This fixes it by ensuring the input operand satisfies def32 which
requires the upper 32 bits of the register to be set.
DeltaFile
+58-2llvm/test/CodeGen/X86/insert.ll
+28-7llvm/lib/Target/X86/X86InstrCompiler.td
+86-92 files

LLVM/project 2fef65cclang/lib/Headers acev1intrin.h, llvm/lib/Target/X86 X86InstrACE.td X86ISelLowering.cpp

[X86] Add ACE v1 (AI Compute Extensions) support

ACE v1 introduces new tile-based matrix operations with fixed 16x64
tile dimensions (Palette 2), unlike AMX's configurable dimensions.

Key features:
- New __acetile type with fixed 16x64 dimensions
- __tile_ace_* intrinsics for ACE tile operations
- Outer product instructions: TOP4BUUD, TOP4BUSD, TOP4BSSD, TOP4BSUD, TOP2BF16PS
- Mixed precision FP8 instructions: TOP4MX variants
- Tile movement: TILEMOVROW, TILEMOVCOL for ZMM<->tile transfers
- BSR (Block Scale Register) operations for scaling factors
- ACE tile spill/reload using TILEMOVROW + VMOVUPS row-by-row
  (ACE doesn't have TILELOADD/TILESTORED instructions)

Backend changes:
- X86LowerTileCopy handles ACE tile copies
- X86PreTileConfig/X86FastPreTileConfig for ACE register allocation
- Palette 2 tile configuration support

    [8 lines not shown]
DeltaFile
+766-0clang/lib/Headers/acev1intrin.h
+417-0llvm/lib/Target/X86/X86InstrACE.td
+282-8llvm/lib/Target/X86/X86ISelLowering.cpp
+244-0llvm/test/CodeGen/X86/ACE/ace-intrinsics.ll
+155-51llvm/lib/Target/X86/X86LowerTileCopy.cpp
+204-0llvm/test/CodeGen/X86/ACE/acev1-outer-product.ll
+2,068-5952 files not shown
+4,365-13458 files

LLVM/project 5b9fa24flang/lib/Optimizer/OpenMP HostOpFiltering.cpp, flang/test/Lower/OpenMP function-filtering-4.f90 host-eval.f90

[Flang][MLIR][OpenMP] Move host op filtering to the omp dialect (#208189)

The MLIR pass that removes operations exclusively intended for the host
from OpenMP target offload modules is currently defined as part of
Flang. However, this is a feature that would benefit from being reusable
by other frontends, as removing such operations is a requirement for all
OpenMP target device modules prior to LLVM IR translation.

By moving the `omp-host-op-filtering` pass out of Flang, it had to be
updated to work on a lower-level LLVM dialect-based representation,
rather than FIR. This simplified some of the existing edge cases, such
as `fir.declare` ops and `fir.boxchar` type handling. In addition, new
function arguments are introduced as placeholders and return values from
host-only functions are removed, producing a cleaner result and
simplifying the pass as compared to previously.

As a result of a later execution of this pass, dynamic dispatch of host
functions via dispatch table using `fir.dispatch`, `fir.type_info` and
`fir.dt_entry` ops would break due to the removal of `fir.dt_entry`

    [6 lines not shown]
DeltaFile
+0-560flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir
+500-0mlir/test/Dialect/OpenMP/host-op-filtering.mlir
+0-422flang/lib/Optimizer/OpenMP/HostOpFiltering.cpp
+292-0mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
+63-0flang/test/Lower/OpenMP/function-filtering-4.f90
+18-32flang/test/Lower/OpenMP/host-eval.f90
+873-1,0147 files not shown
+920-1,04613 files

LLVM/project 50d1864mlir/lib/Dialect/OpenACC/Transforms ACCRecipeMaterialization.cpp, mlir/test/Dialect/OpenACC acc-recipe-materialization-reduction.mlir

[OpenACC] apply par dims to reductions in parallel regions (#208258)

For reductions that come from parallel constructs, explicitly set the
GPU parallel dimensions attribute to blockXDim on the acc.reduction_init
and acc.reduction_combine* ops since they will always be gang private
DeltaFile
+37-16mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
+2-2mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
+39-182 files

LLVM/project a6a016cclang/cmake/modules ClangConfig.cmake.in, llvm/cmake/modules LLVMConfig.cmake.in

cmake: Gate host library targets on shared library support

This avoids cmake warnings about importing unsupported shared libraries (which
are also host build artifacts) when building libc for amdgpu.

00b2f81 guarded exported library targets and host find_package() calls behind
"if(NOT CMAKE_CROSSCOMPILING)". The intent was to avoid importing the always-shared
targets (LTO, Remarks) on targets which will warn due to not supportind shared
libraries. However CMAKE_CROSSCOMPILING is too broad since it is also set for
usable cross-built libraries.

Change to check if the consuming platform supports shared libraries instead. This
feels not quite precise though, since the found libraries could still be static.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+59-42llvm/cmake/modules/LLVMConfig.cmake.in
+3-3clang/cmake/modules/ClangConfig.cmake.in
+62-452 files

LLVM/project 015162dflang/lib/Optimizer/OpenMP HostOpFiltering.cpp, flang/test/Transforms/OpenMP function-filtering-host-ops.mlir

[Flang][MLIR][OpenMP] Fix declare_target globals visibility (#208188)

This patch introduces various changes to the handling of
`declare_target` global variables in Flang:
- Non-`declare_target` globals are unconditionally made "internal" when
compiling for an OpenMP offload target. This prevents potential symbol
redefinition issues related to globals that don't actually exist on the
device.
- Local SAVE variables handling for OpenMP offloading programs is fixed
to prevent their associated "internal" linkage from producing broken
device code for `declare_target enter(...)`.
- When globals are indirectly accessed from the target device (e.g.
`declare_target link(...)`), the associated and unused full-storage
global is marked with "internal" linkage to facilitate later removal.
- `declare_target device_type(host) enter(...)` variables are set to
external linkage when compiling for a target device, causing linker
errors if accessed. This mirrors Clang's behavior.

Fixes #195188, fixes #195468.

Assisted-by: Claude Opus 4.8.
DeltaFile
+252-0mlir/test/Target/LLVMIR/omptarget-declare-target-all-device-types-device.mlir
+44-9mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+20-5flang/lib/Optimizer/OpenMP/HostOpFiltering.cpp
+17-4flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir
+1-0mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-device.mlir
+334-185 files

LLVM/project 541d637llvm/cmake/modules LLVMConfig.cmake.in

cmake: Remove cmake_crosscompiling check on LLVMSupport target export

Revert exported target check added in00b2f81418233397e601afaeea6d62c47a6c368a
to fix reported mingw cross compile regression. This is the quick fix which
restores the cmake warnings when building libc for amdgpu.
DeltaFile
+1-1llvm/cmake/modules/LLVMConfig.cmake.in
+1-11 files

LLVM/project 58eaa33llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU peephole-fold-imm.mir sdiv64.ll

AMDGPU: Fold inline immediates in peephole-opt

Currently the AMDGPU implementation of foldImmediate handles a small
set of special cases that require rewriting the instruction opcode
(COPY -> mov, and fma-like to fmac-like). Most general immediate folding
is handled in SIFoldOperands. Teach PeepholeOpt to fold all inline
immediates into target instructions which should always be an improvement.

This is to help alleviate some phase ordering problems in future changes.
I've also never liked how SIFoldOperands is written and it could use a
rewrite, and this will alleviate some of its responsibilties. It will
always be necessary since some operand folds require additional context
that foldImmediate won't have (namely, we have to make contextually aware
tradeoffs for which operands are worth folding to respect constant bus
restrictions, considering other users of the values).

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+94-9llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
+58-10llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-6llvm/test/CodeGen/AMDGPU/sdiv64.ll
+4-4llvm/test/CodeGen/AMDGPU/optimize-compare.mir
+160-294 files