[AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0,1}_EL2 system registers
Add GICv5 `ICH_PPI_HVIR{0,1}_EL2` system registers (Interrupt
Controller PPI Hide Virtual Interrupt Registers). These registers
are added because a hypervisor may want to only expose a subset of the
PPIs to the virtual machine and hide the remaining PPIs.
The only way the hypervisor can do this is by trapping all the PPI ICV
registers which leads to additional code complexity and adds performance
overhead especially for nested virtualization.
These are documented here:
https://developer.arm.com/documentation/111107/latest/AArch64-Registers/ICH-PPI-HVIR-n--EL2--Interrupt-Controller-PPI-Hide-Virtual-Interrupt-Registers
[ORC] Add MachOBuilder support for LC_UUID load commands. (#191807)
Enables LC_UUID load commands to be added with the addLoadCommand
method.
This will be used in future MachOPlatform changes to add support for
adding UUIDs to MachO JITDylibs.
[Support] Remove address-extraction methods from DataExtractor (NFC) (#190519)
Most clients don't have a notion of "address" and pass arbitrary values
(including `0` and `sizeof(void *)`) to `DataExtractor` constructors.
This makes address-extraction methods dangerous to use.
Those clients that do have a notion of address can use other methods
like `getUnsigned()` to extract an address, or they can derive from
`DataExtractor` and add convenience methods if extracting an address is
routine. `DWARFDataExtractor` is an example, where the removed methods
were actually moved.
This does not remove `AddressSize` argument of `DataExtractor`
constructors yet, but makes it unused and overloads constructors in
preparation for their deletion. I'll be removing uses of the
to-be-deleted constructors in follow-up patches.
[GISel] Use GISelValueTracking in isKnownNeverNaN (#190542)
Pass GISelValueTracking* through isKnownNeverNaN and isKnownNeverSNaN so
that the implementation can call computeKnownFPClass to derive NaN
information from value tracking, rather than only looking at flags and
direct constant definitions. Update all callers.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
[mlir] transform dialect; add pre/post-condition type
Add a transform dialect type denoting additional invariants on payload
IR usable for pre/post-conditions of a transformation. The invariants
are defined as a list of attributes in the type parameter, where the
attribute implements the interface for invariant-checking. This allows
clients to factor out, explicify and deduplicate precondition
verification logic.
This required adding support for Transform dialect extensions injecting
attributes into the dialects similarly to how they already do this for
operations and types.
Co-authored-by: Tim Gymnich <tim at gymni.ch>
Co-authored-by: Martin Lücke <martin.luecke at amd.com>
Assisted-by: Claude Opus 4.3 / Cursor
[SPIR-V] Fix type mismatch in scalar-to-vector promotion for mixed-type builtins (#190969)
When promoting scalar arguments to vectors for builtins like `ldexp`,
`pown`, and `rootn`, use the correct vector type matching the argument
element type instead of always using the return type: these builtins
take an integer argument but at the same time have floating point return
type
Fix `ldexp` test that does not pass spirv-val and add similar tests for
`pown` and `rootn`
related to https://github.com/llvm/llvm-project/issues/190736
[LV] Extend epilogue vectorization test coverage with dead FORs/FMinMax. (#191799)
Extend test coverage with dedicated epilogue vectorization tests for
dead first-order recurrences and FMinMaxNum reductions.
Add users to FORs in existing tests where the dead FORs appeared
unintentional.
[clang][bytecode] Fix activating primitive array elements (#191772)
For primitive array elements, we would accidentally activate the element
and then immediate de-activate the array root, which is wrong. Ignore
the element from the beginning to the later check never even compares
with the element.
[AArch64][clang][llvm] Add support for Armv9.7-A lookup table intrinsics
Add support for the following Armv9.7-A Lookup Table (lut)
instruction intrinsics:
SVE2.3
```c
// Variant is also available for: _u8 _mf8
svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);
```
SVE2.3 and SME2.3
``` c
// Variants are also available for _u16_x2 and _f16_x2.
svint16_t svluti6_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx);
```
SME2.3
```c
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