LLVM/project 64df5bbllvm/lib/Target/X86 X86InstrInfo.cpp X86.td, llvm/test/CodeGen/X86 slow-indirect-call.ll

[X86] Adding slow indirect call tuning to zen5 (#195221)
DeltaFile
+170-0llvm/test/CodeGen/X86/slow-indirect-call.ll
+12-6llvm/lib/Target/X86/X86InstrInfo.cpp
+13-2llvm/lib/Target/X86/X86.td
+2-1llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+2-1llvm/lib/Target/X86/X86InstrPredicates.td
+3-0llvm/lib/Target/X86/X86TargetTransformInfo.h
+202-102 files not shown
+206-108 files

LLVM/project e312afbclang/docs ReleaseNotes.rst, clang/lib/Sema SemaTemplateInstantiate.cpp SemaExprCXX.cpp

[clang] make evaluation of type constraint a SFINAE context (#197523)

Otherwise, errors when substituting a type constraint could
unintentionally make the program ill-formed.

This also strenghtens the assert which checks, when we are instantiating
templates, that we either have a code synthesis context, or that we are
in a SFINAE context.
DeltaFile
+12-32clang/lib/Sema/SemaTemplateInstantiate.cpp
+21-0clang/test/SemaTemplate/instantiate-requires-expr.cpp
+4-0clang/lib/Sema/SemaExprCXX.cpp
+2-0clang/docs/ReleaseNotes.rst
+39-324 files

LLVM/project 4c37624llvm/lib/Transforms/Vectorize VPlan.h

[VPlan] Add helper to define CastInfo for casting to VP mixins (NFC) (#197494)

Add new generic VPMixinCast that can be used to define CastInfo from a
base class (like VPRecipeBase) to a mixin class (like VPIRMetadata)
through a list of supported recipe types.

Overall that makes defining the cast machinery quite a bit more compact.
It also adds a static_assert to prevent mis-use using std::is_base_of_v

PR: https://github.com/llvm/llvm-project/pull/197494
DeltaFile
+31-68llvm/lib/Transforms/Vectorize/VPlan.h
+31-681 files

LLVM/project 09bc64allvm/test/Transforms/LoopVectorize/AArch64 cmp_cost.ll

[LV] Add test for icmp/fcmp cost calculation (NFC) (#197504)

Co-authored-by: Florian Hahn <flo at fhahn.com>
DeltaFile
+440-0llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
+440-01 files

LLVM/project 6edd183clang/include/clang/DependencyScanning DependencyGraph.h ModuleDepCollector.h, clang/lib/DependencyScanning DependencyGraph.cpp ModuleDepCollector.cpp

[clang][deps] Consolidate types into new `DependencyGraph.h` (#197567)

This PR pulls the types forming the dependency graph from three
different headers into a single new header `DependencyGraph.h`. This
makes the code organization a bit clearer, and is NFC otherwise.
DeltaFile
+220-0clang/include/clang/DependencyScanning/DependencyGraph.h
+1-145clang/include/clang/DependencyScanning/ModuleDepCollector.h
+0-48clang/include/clang/DependencyScanning/DependencyScanningUtils.h
+35-0clang/lib/DependencyScanning/DependencyGraph.cpp
+9-20clang/lib/DependencyScanning/ModuleDepCollector.cpp
+0-8clang/include/clang/DependencyScanning/DependencyScanningWorker.h
+265-2211 files not shown
+266-2217 files

LLVM/project 131ac51bolt/lib/RuntimeLibs HugifyRuntimeLibrary.cpp, bolt/lib/Utils CommandLineOpts.cpp

[BOLT] Define hugify option in CommandLineOpts.cpp (#197702)

#195272 added a reference to opts::Hugify from LongJmp.cpp. This
broke shared-library builds because LLVMBOLTPasses does not link
against LLVMBOLTRuntimeLibs, where the option was previously defined.

Move the opts::Hugify definition to CommandLineOpts.cpp, alongside
the other global BOLT command-line options. This keeps the option
available to LLVMBOLTPasses through its existing LLVMBOLTUtils
dependency without adding a dependency on the runtime library layer.
DeltaFile
+0-7bolt/lib/RuntimeLibs/HugifyRuntimeLibrary.cpp
+7-0bolt/lib/Utils/CommandLineOpts.cpp
+7-72 files

LLVM/project 190b73fllvm/lib/Target/PowerPC/GISel PPCLegalizerInfo.cpp

[PowerPC][GlobalISel] Remove dependency on legal ruleset (#197375)

This fills in always legal rules, to remove the dependency on the legacy
ruleset. This is not guaranteed to be all the rules, just the ones that
appear in tests.
DeltaFile
+5-0llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+5-01 files

LLVM/project 7bfb4d9llvm/test/Transforms/LoopVectorize pr39417-optsize-scevchecks.ll

[LV] Add store to test case to prevent dead code. nfc (#197703)
DeltaFile
+7-2llvm/test/Transforms/LoopVectorize/pr39417-optsize-scevchecks.ll
+7-21 files

LLVM/project 721db09clang/include/clang/AST DeclTemplate.h TypeBase.h, clang/lib/AST DeclTemplate.cpp ASTContext.cpp

[clang] NFC: add asserts and fixes for enforcing template parameters have valid positions (#197598)

Some tests are violating these assertions, so they are commented out.

For the test in `clang/test/SemaTemplate/concepts.cpp`, that was broken
by #195995 and needs a partial revert at least.
DeltaFile
+25-34clang/include/clang/AST/DeclTemplate.h
+14-15clang/lib/AST/DeclTemplate.cpp
+6-3clang/lib/AST/ASTContext.cpp
+7-2clang/include/clang/AST/TypeBase.h
+5-2clang/test/SemaTemplate/concepts-lambda.cpp
+3-1clang/test/SemaTemplate/concepts.cpp
+60-572 files not shown
+64-608 files

LLVM/project f5e00eallvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU andorn2.ll

Update for comments use foreach and add some tests
DeltaFile
+482-9llvm/test/CodeGen/AMDGPU/andorn2.ll
+5-6llvm/lib/Target/AMDGPU/SIInstructions.td
+487-152 files

LLVM/project 00559c2lldb/source/Plugins/Process/Windows/Common NativeProcessWindows.cpp

[lldb][windows] Keep int3 breakpoints inside the debugger on lldb-server (#197669)
DeltaFile
+14-1lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+14-11 files

LLVM/project 277372bllvm/docs GettingInvolved.rst

[docs] Add "LLVM Memory Safety" and "Lifetime Safety" working Groups (#197692)
DeltaFile
+10-1llvm/docs/GettingInvolved.rst
+10-11 files

LLVM/project 31ec3d8llvm/lib/Target/ARM ARMLegalizerInfo.cpp, llvm/test/CodeGen/ARM/GlobalISel select-fp.mir arm-regbankselect.mir

[ARM][GlobalISel] Remove dependency on legal ruleset. (#197370)

This fills in always legal rules, to remove the dependency on the legacy
ruleset. The trunc rule might make some differences but it looks like
i64 zext / sext are not well supported at the moment. This is not
guaranteed to be all the rules, just the ones that appear in tests.
DeltaFile
+0-32llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
+0-25llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+4-0llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+4-573 files

LLVM/project db71167libc/include string.yaml, libc/src/string strcpy_s.cpp strcpy_s.h

[libc] Annex K: strcpy_s

This patch adds Annex K's `strcpy_s`.
DeltaFile
+122-0libc/test/src/string/strcpy_s_test.cpp
+71-0libc/src/string/strcpy_s.cpp
+22-0libc/src/string/strcpy_s.h
+19-0libc/src/string/CMakeLists.txt
+13-0libc/test/src/string/CMakeLists.txt
+9-0libc/include/string.yaml
+256-05 files not shown
+261-011 files

LLVM/project 0ac83dcclang/lib/Driver/ToolChains/Arch AArch64.cpp

[clang][AArch64] Use structured bindings in feature parsing code (#197689)

Clearer than having to know that first is a CPU and second is the
feature list.
DeltaFile
+10-11clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+10-111 files

LLVM/project fb4d033llvm/lib/Target/PowerPC PPCInstrInfo.td PPCISelLowering.cpp

[PowerPC] Match intrinsics ppc_amo_st[dw]at with a pattern

The intrinsics are 1:1 to the instructions except for the order of
the operands, thus it is easy to match them with a pattern.

However, the intrinsics are defined as reading and writing to
memory, but the instructions explicitly set mayLoad to false.
Looking at the ISA description it seems to me that the latter
is not true. In any case, the side effect flags must be the
same, otherwise the pattern is rejected.
DeltaFile
+2-9llvm/lib/Target/PowerPC/PPCInstrInfo.td
+0-10llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+2-2llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+4-213 files

LLVM/project dc4f489libc/test/UnitTest ConstraintHandlerCheckingTest.h CMakeLists.txt

[libc] Annex K: Add constraint handler unit test class

This unit test class will be useful for the tests related to Annex K.
The functions in Annex K may call a constraint handler, so this new unit
test class will facilitate the checks that the constraint handling
mechanism is working as expected.
DeltaFile
+44-0libc/test/UnitTest/ConstraintHandlerCheckingTest.h
+11-0libc/test/UnitTest/CMakeLists.txt
+55-02 files

LLVM/project 692b8fdlibcxx/include/__format format_functions.h

[libc++] Replace ranges::find_first_of with std::find_first_of in __try_constant_folding (#197641)

This reduces the time it takes to instantiate `std::format` from ~160ms
to ~120ms in my testing.
DeltaFile
+7-3libcxx/include/__format/format_functions.h
+7-31 files

LLVM/project 54fb441llvm/include/llvm/Target Target.td, llvm/test/TableGen aarch64-apple-tuning-features.td

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+11-11llvm/test/TableGen/aarch64-apple-tuning-features.td
+1-1llvm/include/llvm/Target/Target.td
+12-122 files

LLVM/project 0f79ba2llvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp SPIRVSymbolicOperands.td, llvm/test/CodeGen/SPIRV/linkage weak-linkage.ll

Adjust SPV_AMD_weak_linkage (#197484)

Linkage was renamed + a capability added following review in
https://github.com/KhronosGroup/SPIRV-Registry/pull/401
DeltaFile
+6-5llvm/test/CodeGen/SPIRV/linkage/weak-linkage.ll
+3-1llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+2-1llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+1-1llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+12-84 files

LLVM/project db9b7f2llvm/lib/Target/AMDGPU AMDGPU.td AMDGPURegisterBankInfo.cpp

[AMDGPU][NFC] Add VMulU64Inst SubtargetFeature for v_mul_u64 support.
DeltaFile
+5-0llvm/lib/Target/AMDGPU/AMDGPU.td
+2-2llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+0-3llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+10-81 files not shown
+11-97 files

LLVM/project f2a9f41llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp GCNSubtarget.h

[AMDGPU][NFC] Remove redundant hasMadU64U32NoCarry helper (#197682)

Use hasMadNC64_32Insts() (backed by SubtargetFeature) for MAD 64_32
no-carry and drop the old helper.
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+0-4llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+3-73 files

LLVM/project e30151eclang/test/Driver openmp-offload-gpu.c

one more fix
DeltaFile
+1-2clang/test/Driver/openmp-offload-gpu.c
+1-21 files

LLVM/project 7206901libc/src/__support/CPP/type_traits is_constructible.h is_assignable.h

[libc] Include correct headers in type_traits (#197691)

Otherwise we end up with errors like the following when building with
bazel:
```c++
In file included from external/+_repo_rules+llvm-project/libc/src/__support/CPP/type_traits/is_move_constructible.h:12:
external/+_repo_rules+llvm-project/libc/src/__support/CPP/type_traits/is_constructible.h:32:14: error: no template named 'bool_constant'
   32 |     : public bool_constant<__is_constructible(T, Args...)> {};
```
DeltaFile
+1-1libc/src/__support/CPP/type_traits/is_constructible.h
+1-1libc/src/__support/CPP/type_traits/is_assignable.h
+2-22 files

LLVM/project d1a6d7bllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AArch64 aarch64-mulv.ll

[DAG] SimplifyMultipleUseDemandedBits - fold (mul X, 1) -> X (#197677)

Use DemandedElts + KnownBits to match hidden identity patterns - helps
especially with reduction patterns padded by legalisation

Once #197455 has landed, I'm intending to convert this (plus
SMIN/SMAX/UMIN/UMAX and the existing ISD::ADD case) to use
isIdentityElement directly.
DeltaFile
+14-23llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+13-13llvm/test/CodeGen/X86/srem-vector-lkk.ll
+10-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+3-6llvm/test/CodeGen/AArch64/aarch64-mulv.ll
+2-2llvm/test/CodeGen/X86/dpbusd_const.ll
+42-445 files

LLVM/project 2a110felldb/source/Plugins/Process/Utility RegisterContextWindows_x86_64.cpp

[lldb][windows] fix x86_64 arg register mapping for lldb-server (#197663)
DeltaFile
+6-6lldb/source/Plugins/Process/Utility/RegisterContextWindows_x86_64.cpp
+6-61 files

LLVM/project 290d0f6llvm/test/Transforms/LoopVectorize/AArch64 sve-interleaved-accesses.ll sve-interleaved-masked-accesses.ll

[LV][NFC] Remove instcombine from RUN lines in AArch64 tests (#197448)

This PR continues other work I've been doing trying to remove
unnecessary extra passes from the RUN lines in order to make it easier
to map the expected vectoriser output to the CHECK lines. As a result it
has exposed some potential optimisations that we may be able to perform
in VPlan.

Here is a summary of the changes I've noticed:

1. instcombine likes to canonicalise GEPs into certain forms. I'm not
sure if there is value in VPlan trying to guess what the canonical form
should be.
2. In tests like sve-cond-inv-loads.ll, etc. the pattern sub(urem) is
often replaced with and(sub). This is potentially something the
vectoriser could improve although I don't know if it would change the
cost model.
3. There is poor codegen in gather_nxv4i32_ind64_stride2 in the file
sve-gather-scatter.ll, which is due to

    [19 lines not shown]
DeltaFile
+176-182llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
+141-143llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
+85-82llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+70-53llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
+68-47llvm/test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll
+47-37llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
+587-54411 files not shown
+756-68817 files

LLVM/project d2de1d2clang/include/clang/Basic BuiltinsPPC.def, clang/test/CodeGen/PowerPC builtins-ppc-dmf.c ppc-dmf-mma-builtin-err.c

[PowerPC] Update base crypto builtins and intrinsics (#197017)

Update the base crypto builtins and LLVM intrinsics to drop the mma_
prefix. Also fix the builtin definitions for dmsha2hash, dmsha3hash,
and dmxxshapad to use the correct immediate constraints.
DeltaFile
+33-33clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
+17-17llvm/test/CodeGen/PowerPC/mmaplus-crypto.ll
+15-15clang/include/clang/Basic/BuiltinsPPC.def
+15-0clang/test/Sema/builtins-ppc-crypto.c
+6-6clang/test/CodeGen/PowerPC/ppc-dmf-mma-builtin-err.c
+3-3clang/test/Sema/PowerPC/ppc-dmf-mma-builtin-err.c
+89-744 files not shown
+99-8410 files

LLVM/project 16b2ef3llvm/include/llvm/CodeGen MachineOutliner.h, llvm/lib/CodeGen RegisterScavenging.cpp LiveRegUnits.cpp

[CodeGen] Debug insns must not affect liveness analysis (#193104)

Register references in debug instructions can affect LiveRegUnits
analysis. Skip over debug instructions.

Tests in this PR would fail due to calls to LiveRegUnits::stepBackward
in RegisterScavenging, DeadMachineInstructionElim, and
AArch64InstrInfo.cpp getOutlinableRanges().

Other call-sites to stepBackward may also pass debug instructions to
LiveRegUnits::stepBackward, but LIT testing did not fail when
-debugify-and-strip-all-safe was enabled by default.

---------

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+25-0llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
+4-2llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+2-2llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
+2-1llvm/lib/CodeGen/RegisterScavenging.cpp
+3-0llvm/lib/CodeGen/LiveRegUnits.cpp
+2-1llvm/include/llvm/CodeGen/MachineOutliner.h
+38-68 files not shown
+49-814 files

LLVM/project 439e422flang/lib/Frontend CompilerInvocation.cpp

lowerCamelize variable names
DeltaFile
+12-12flang/lib/Frontend/CompilerInvocation.cpp
+12-121 files