LLVM/project 2fa34a8clang/include/clang/Options Options.td, clang/lib/Driver/ToolChains Flang.cpp

[Flang][OpenMP] Add -fdo-concurrent alias for -fdo-concurrent-to-openmp

Adds the shorter -fdo-concurrent alias to map DO CONCURRENT loops to
OpenMP.

Co-authored-by: Gemini 3.1 Pro
DeltaFile
+17-6flang/test/Driver/do_concurrent_to_omp_cli.f90
+7-2clang/lib/Driver/ToolChains/Flang.cpp
+6-2flang/docs/DoConcurrentConversionToOpenMP.md
+5-1flang/tools/bbc/bbc.cpp
+1-2flang/lib/Frontend/CompilerInvocation.cpp
+2-1clang/include/clang/Options/Options.td
+38-146 files

LLVM/project be2faf8flang/lib/Frontend FrontendActions.cpp

[flang] Remove `do concurrent` mapping experimental warning

Removes the warning downstream for now since the pass has been validated
on both CPUs and to a lesser extent on GPUs.
DeltaFile
+0-7flang/lib/Frontend/FrontendActions.cpp
+0-71 files

LLVM/project 4581593llvm/lib/Analysis AliasAnalysis.cpp, llvm/test/Transforms/DeadStoreElimination atomic.ll atomic-todo.ll

Revert "Revert "[AA] Improve precision for monotonic atomic load/store operat…"

This reverts commit c8941df6a1e4ed5e1ba3287985a60e1d7512c250.
DeltaFile
+67-26llvm/test/Transforms/DeadStoreElimination/atomic.ll
+0-23llvm/test/Transforms/DeadStoreElimination/atomic-todo.ll
+16-3llvm/lib/Analysis/AliasAnalysis.cpp
+83-523 files

LLVM/project af4649fclang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp CIRGenBuiltin.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-logb-scalbn.hip

[CIR][AMDGPU] Adds amdgcn logb and scalebn builtins (#191344)

Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/2065

Support for lowering of `__builtin_amdgcn_logb` and `scalebn` for AMDGPU
builtins to clangIR.
Followed similar lowering from clang->llvmir:
`clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp`.
DeltaFile
+79-10clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+46-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-logb-scalbn.hip
+26-1clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+3-0clang/lib/CIR/CodeGen/TargetInfo.h
+2-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+156-115 files

LLVM/project 3d19371clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenModule.cpp

[CIR] Add calling_conv attribute to FuncOp with lowering support (#189345)

Adds `calling_conv` attribute to `FuncOp` with support
(`cc(amdgpu_kernel)` syntax) and LLVM lowering.

Continuation of #188715 and a partial upstreaming of
[clangir#760](https://github.com/llvm/clangir/pull/760/).
DeltaFile
+38-0clang/test/CIR/IR/calling-conv.cir
+34-0clang/test/CIR/Lowering/calling-conv.cir
+24-4clang/include/clang/CIR/Dialect/IR/CIROps.td
+21-5clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+24-1clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+4-4clang/lib/CIR/CodeGen/CIRGenModule.cpp
+145-142 files not shown
+147-158 files

LLVM/project 57922f9clang/test/CIR/CodeGenCUDA device-stub.cu

[CIR][CUDA][NFC] Add CIR-to-LLVM lowering checks for existing registration support
DeltaFile
+23-0clang/test/CIR/CodeGenCUDA/device-stub.cu
+23-01 files

LLVM/project 874c1caclang/lib/CIR/CodeGen CIRGenBuiltin.cpp CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-logb-scalbn.hip

[CIR][AMDGPU] Fix constrained FP and library calls path
DeltaFile
+26-1clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+9-17clang/test/CIR/CodeGenHIP/builtins-amdgcn-logb-scalbn.hip
+2-3clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+3-0clang/lib/CIR/CodeGen/TargetInfo.h
+2-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+42-215 files

LLVM/project 9827cbaclang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-logb-scalbn.hip

[CIR][AMDGPU] Adds amdgcn logb and scalebn builtins
DeltaFile
+89-10clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+42-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-logb-scalbn.hip
+131-102 files

LLVM/project 8b5a3b4clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-logb-scalbn.hip

[CIR][AMDGPU] Fix FltSemantics, naming convention, and CIR APIs
DeltaFile
+52-61clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+12-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-logb-scalbn.hip
+64-612 files

LLVM/project bcbad84clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode c.c

[clang][bytecode] Only revisit C variables with valid initializers (#194881)

We don't mark them as constexpr-unknown, so check that the initializer
can be evaluated.
DeltaFile
+2-2clang/lib/AST/ByteCode/Compiler.cpp
+4-0clang/test/Parser/pragma-fenv_access.c
+1-2clang/test/AST/ByteCode/c.c
+7-43 files

LLVM/project ad28447clang/include/clang/CIR LoweringHelpers.h, clang/lib/CIR/Lowering LoweringHelpers.cpp

[CIR] Handle unsuported dense attributes conversion
DeltaFile
+27-14clang/lib/CIR/Lowering/LoweringHelpers.cpp
+2-2clang/include/clang/CIR/LoweringHelpers.h
+29-162 files

LLVM/project c1a2360mlir/include/mlir-c IR.h, mlir/include/mlir/Bindings/Python IRCore.h

[mlir][python] expose remaining Location inspection API (#192630)

Addresses #53169. Mirrors the Python bindings pattern used for Attribute
subclasses so that Location discrimination uses `isinstance`, and fills
two small gaps at the same time.

### Approach

Previously `Location` was a single nanobind class with `is_a_file`,
`is_a_name`, etc. predicates, plus field accessors for every kind
defined on the base class. This PR introduces a `PyConcreteLocation<T>`
CRTP template (parallel to `PyConcreteAttribute<T>`) and registers one
subclass per `LocationAttr` kind: `UnknownLoc`, `FileLineColLoc`,
`NameLoc`, `CallSiteLoc`, `FusedLoc`.

TypeID-based downcasting is implemented in `PyLocation::maybeDownCast`
(using `mlirAttributeGetTypeID(mlirLocationGetAttribute(...))`) and
called at the boundaries that return Location objects: `op.location`,
`value.location`, `Location.from_attr`, and the subclass getters

    [83 lines not shown]
DeltaFile
+290-124mlir/lib/Bindings/Python/IRCore.cpp
+104-55mlir/test/python/ir/location.py
+129-0mlir/include/mlir/Bindings/Python/IRCore.h
+19-0mlir/test/CAPI/ir.c
+8-0mlir/lib/CAPI/IR/IR.cpp
+6-0mlir/include/mlir-c/IR.h
+556-1796 files

LLVM/project 8d53d36llvm/lib/Target/LoongArch LoongArchLASXInstrInfo.td LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx vec-zext.ll vec-sext.ll

[LoongArch] Introduce LASX instruction patterns for vector sign/zero extensions (#193727)

This patch introduces LASX only legalization and instruction patterns
for vector sign and zero extension operations, which is basically copy
from the https://github.com/llvm/llvm-project/pull/160810 with some
minor change (e.g. deleted unused tablegen pattern).
DeltaFile
+424-0llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
+423-0llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
+76-5llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+11-27llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
+9-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+943-325 files

LLVM/project c81f883llvm/utils/TableGen AsmMatcherEmitter.cpp

[TableGen] Use isCodeGenOnly field of CodeGenInstruction. NFC (#194942)
DeltaFile
+1-1llvm/utils/TableGen/AsmMatcherEmitter.cpp
+1-11 files

LLVM/project 9f51527llvm/lib/Transforms/Utils LoopUnroll.cpp

Fix typo
DeltaFile
+1-1llvm/lib/Transforms/Utils/LoopUnroll.cpp
+1-11 files

LLVM/project 29d62a9llvm/lib/Transforms/Utils LoopUnroll.cpp

Report unexpected infinite frequency
DeltaFile
+10-3llvm/lib/Transforms/Utils/LoopUnroll.cpp
+10-31 files

LLVM/project 4a91296llvm/lib/Transforms/Utils LoopUnroll.cpp

O(n^2) -> O(n)
DeltaFile
+79-50llvm/lib/Transforms/Utils/LoopUnroll.cpp
+79-501 files

LLVM/project 10e8fe0llvm/lib/Transforms/Utils LoopUnroll.cpp

Address small reviewer suggestions
DeltaFile
+7-3llvm/lib/Transforms/Utils/LoopUnroll.cpp
+7-31 files

LLVM/project 1b5874blld/MachO ConcatOutputSection.cpp

call markBranchAsResolved in more places
DeltaFile
+5-4lld/MachO/ConcatOutputSection.cpp
+5-41 files

LLVM/project e20557eclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

fix fmt
DeltaFile
+6-4clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+6-41 files

LLVM/project 2387cc1clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR] Lower global ConstArrayAttr with string elements to LLVM string constant
DeltaFile
+40-5clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+10-0clang/test/CIR/Lowering/array.cpp
+4-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+54-53 files

LLVM/project 0abb456orc-rt/include/orc-rt NativeDylibManager.h, orc-rt/lib/executor NativeDylibManager.cpp

[orc-rt] Add NativeDylibManager. (#194792)

NativeDylibManager is an orc_rt::Service that supports loading,
unloading, and lookup of symbols via the system dynamic loader's native
APIs.

The current implementation only supports the POSIX dlfcn.h APIs (dlopen,
dlclose, dlsym), but it should be straightforward to extend to Windows.
DeltaFile
+199-0orc-rt/unittests/NativeDylibManagerTest.cpp
+183-0orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
+151-0orc-rt/lib/executor/NativeDylibManager.cpp
+94-0orc-rt/include/orc-rt/NativeDylibManager.h
+53-0orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
+46-0orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
+726-05 files not shown
+776-011 files

LLVM/project 6cad48allvm/include/llvm/CodeGen WasmEHFuncInfo.h WasmEHInfo.h, llvm/lib/CodeGen WasmEHPrepare.cpp

[WebAssembly] Remove WasmEHFuncInfo (NFC) (#194972)

This removes `WasmEHFuncInfo` class.

This class was created to maintain the information of, "If an exception
is not caught by EHPad A, what is its next unwind destination?". Turns
out this information is already in the CFG.

After #130374, we use the common `findUnwindDestination`:
https://github.com/llvm/llvm-project/blob/113479d119a997e4c4c3eae63e087588c9662121/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L2107-L2164

Note that in case of `catchswitch`, we follow its unwind destination
chain and add all of them to the invoke BB's successors until it meets a
`cleanuppad`, which always catches an exception. And the order of the
successor is the order of the unwind destination chain. So an invoke
BB's successor list would be like: [normal destination, unwind EHPad 1,
unwind EHPad 2, unwind EHPad 3, ...] where EHPad 2 is the next unwind
destination if EHPad 1 does not catch an exception and so on. So if we
want to know what the current EHPad's next unwind destination is, we can

    [18 lines not shown]
DeltaFile
+0-65llvm/include/llvm/CodeGen/WasmEHFuncInfo.h
+32-7llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+0-34llvm/test/CodeGen/WebAssembly/function-info.mir
+0-30llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
+1-25llvm/lib/CodeGen/WasmEHPrepare.cpp
+24-0llvm/include/llvm/CodeGen/WasmEHInfo.h
+57-1619 files not shown
+60-22215 files

LLVM/project fbdc27dclang-tools-extra/modularize CoverageChecker.cpp ModularizeUtilities.cpp

[clang][tools] NFC: Replace `auto` with `Module *` (#194977)

This finishes what #194032 started.
DeltaFile
+1-1clang-tools-extra/modularize/CoverageChecker.cpp
+1-1clang-tools-extra/modularize/ModularizeUtilities.cpp
+2-22 files

LLVM/project df32e69llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.fp8.ll

[AMDGPU]/GlobalISel: RegBankLegalize rules for fp8/bf8 cvt intrinsics (#193551)
DeltaFile
+945-7llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
+14-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+959-72 files

LLVM/project 0ba904dclang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowExtractor.cpp PointerFlowFormat.cpp

address comments
DeltaFile
+5-4clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
+2-2clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowFormat.cpp
+7-62 files

LLVM/project 74f3b56llvm/lib/Target/RISCV RISCVInstrInfo.td RISCVInstrInfoV.td

[RISCV] Remove isAsmParserOnly from isPseudo instructions. NFC (#194958)

isAsmParserOnly is only used to suppress DecoderEmiter, but that's
already supressed by isPseudo. The real usage for this should be for
instructions that have encoding information but we don't want to
disassemble.

Many of these pseudos are emitted from codegen meaning they aren't
really assembler only. So you can't argue this flag is good for
documentation either.
DeltaFile
+16-16llvm/lib/Target/RISCV/RISCVInstrInfo.td
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+0-3llvm/lib/Target/RISCV/RISCVInstrFormats.td
+1-2llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+19-234 files

LLVM/project 0177533llvm/lib/Target/RISCV RISCVInstrInfo.td

[RISCV] Remove isAsmParserOnly from LongBccPseudo and LongBcciPseudo.  NFC (#194949)

These instructions are created by assembler relaxation. They aren't
"parsed.". isAsmParserOnly suppresses the disassembler for these, but
that was already suppressed by isPseudo and isCodeGenOnly.
DeltaFile
+0-2llvm/lib/Target/RISCV/RISCVInstrInfo.td
+0-21 files

LLVM/project cf3a327llvm/docs LangRef.rst, llvm/include/llvm/IR FixedMetadataKinds.def

IR: Introduce !elf_section_properties for setting section properties.

This new metadata type may be used to set sh_type and sh_entsize on a
global's section. The intent is that it will be used to mark up
CFI jump table sections.

Reviewers: fmayer, MaskRay, nikic, efriedma-quic

Reviewed By: fmayer

Pull Request: https://github.com/llvm/llvm-project/pull/149260
DeltaFile
+39-23llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+25-0llvm/test/CodeGen/X86/elf-section-properties.ll
+19-0llvm/docs/LangRef.rst
+17-0llvm/lib/IR/Verifier.cpp
+12-0llvm/test/Verifier/elf-section-properties.ll
+1-0llvm/include/llvm/IR/FixedMetadataKinds.def
+113-236 files

LLVM/project 8ba1986llvm/utils/gn/secondary/llvm/lib/DWP BUILD.gn

[gn build] Port caa18a808aa0



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194976
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/DWP/BUILD.gn
+1-01 files