[mlir][x86vector] Lower vector.contract to FMA or packed type dot-product (#168074)
A `transform` pass to lower `vector.contract` to (a) `vector.fma` for
`F32`, (b) `x86vector.avx512.dot` for `BF16`, (c) `x86vector.avx.dot.i8`
for `Int8` packed types.
The lowering works on condition with `m`, `batch`, `k` dims to be `one`
and `vnni` dim should be `2` for `bf16`; `4` for `int8`.
**The lowering pattern**: `batch_reduce.matmul` (input) ->
register-tiling(M, N) -> Vectorization (to `vector.contract`) ->
`unroll` vector.contract (`unit` dims) -> `hoisting` transformation
(move `C` loads/store outside batch/k loop) -> apply `licm`,
`canonicalization`, and `bufferize`.
[Sema] Fix Wunused-but-set-variable warning(NFC) (#169220)
Fix warning:
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp:1455:23: warning:
variable 'Store' set but not used [-Wunused-but-set-variable]
[MLIR][IRDL] Support camelCase segment size attributes in IRDL verifier (#168836)
Two years ago, `operand_segment_sizes` and `result_segment_sizes` were
renamed to `operandSegmentSizes` and `resultSegmentSizes` (check related
commits, e.g.
https://github.com/llvm/llvm-project/commit/363b655920c49a4bcb0869f820ed40aac834eebd).
However, the op verifiers in IRDL loading phase is still using old
attributes like `operand_segment_sizes` and `result_segment_sizes`,
which causes some conflict, e.g. it is not compatible with the OpView
builder in MLIR python bindings (which generates camelCase segment
attributes).
This PR is to support to use camelCase segment size attributes in IRDL
verifier. Note that support of `operand_segment_sizes` and
`result_segment_sizes` is dropped.
I found this issue since I'm working on a new IRDL wrapper in the MLIR
python bindings.
[RISCV] Combine vslide{up,down} x, poison -> x (#169013)
The motivation for this is that it would be useful to express a
vslideup/vslidedown in a target independent way e.g. from the loop
vectorizer.
We can do this today with @llvm.vector.splice by setting one operand to
poison:
- A slide down can be achieved with @llvm.vector.splice(%x, poison,
slideamt)
- A slide up can be done by @llvm.vector.splice(poison, %x, -slideamt)
E.g.:
splice(<a,b,c,d>, poison, 3) = <d,poison,poison,poison>
splice(poison, <a,b,c,d>, -3) = <poison,poison,poison,a>
These splices get lowered to a vslideup + vslidedown pair with one of
the vs2s being poison. We can optimize this away so that we are just
left with a single slideup/slidedown.
[AMDGPU] Propagate AA info in vector load/store splitting. (#168871)
Fixes a bug in `AMDGPUISelLowering` where alias analysis info is not
propagated to split loads and stores.
This is required for #161375
---------
Co-authored-by: Leon Clark <leoclark at amd.com>
[M68k][compiler-rt] Allow compiler-rt builtins to be built for M68k (#169256)
I've tested this locally, and the builtins build proceeds without a
hitch for m68k-none-none. This is part of a larger effort to establish a
working m68k baremetal toolchain.
[TableGen] Simplify MachineValueTypeSet::iterator::find_from_pos. NFC (#169227)
Merge the SkipBits!=0 handling into the first iteration of the word
loop. This is the same code structure used by BitVector::find_first_in.
[mlir][Pass] Fix crash when applying a pass to an optional interface (#169262)
Interfaces can be optional: whether an op implements an interface or not
can depend on the state of the operation.
```
// An optional code block for adding additional "classof" logic. This can
// be used to better enable "optional" interfaces, where an entity only
// implements the interface if some dynamic characteristic holds.
// `$_attr`/`$_op`/`$_type` may be used to refer to an instance of the
// interface instance being checked.
code extraClassOf = "";
```
The current `Pass::canScheduleOn(RegisteredOperationName)` is
insufficient. This commit adds an additional overload to inspect
`Operation *`.
This commit fixes a crash when scheduling an `InterfacePass` for an
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[GlobalOpt] Use `target triple` to fix Buildbot failures, NFCI (#169260)
This supposes to fix LLVM Buildbot failures after #164768. I don't have
the environment to verify though.
[mlir][Pass] Fix crash when applying a pass to an optional interface (#168499)
Interfaces can be optional: whether an op implements an interface or not
can depend on the state of the operation.
```
// An optional code block for adding additional "classof" logic. This can
// be used to better enable "optional" interfaces, where an entity only
// implements the interface if some dynamic characteristic holds.
// `$_attr`/`$_op`/`$_type` may be used to refer to an instance of the
// interface instance being checked.
code extraClassOf = "";
```
The current `Pass::canScheduleOn(RegisteredOperationName)` is
insufficient. This commit adds an additional overload to inspect
`Operation *`.
This commit fixes a crash when scheduling an `InterfacePass` for an
optional interface on an operation that does not actually implement the
interface.
[GlobalOpt] Add TTI interface useFastCCForInternalCall for FASTCC (#164768)
Background: X86 APX feature adds 16 registers within the same 64-bit
mode. PR #164638 is trying to extend such registers for FASTCC. However,
a blocker issue is calling convention cannot be changeable with or
without a feature.
The solution is to disable FASTCC if APX is not ready. This is an NFC
change to the final code generation, becasue X86 doesn't define an
alternative ABI for FASTCC in 64-bit mode. We can solve the potential
compatibility issue of #164638 with this patch.
Revert "[ASTMatchers] Make isExpandedFromMacro accept llvm::StringRef… (#167060)" (#169238)
This reverts commit a52e1af7f766e26a78d10d31da98af041dd66410.
That commit reverted a change (making isExpandedFromMacro take a
std::string) that was explicitly added to avoid lifetime issues. We ran
into issues with some internal matchers due to this, and it probably is
not an uncommon downstream use case. This patch restroes the original
functionality and adds a test to ensure that the functionality is
preserved.
https://reviews.llvm.org/D90303 contains more discussion.
