LLVM/project b15f58cclang/docs ReleaseNotes.md, clang/lib/Sema SemaDecl.cpp

[clang][Sema] Fix false-positive -Wshadow for friend functions (#221249)

A friend function defined inline in a class body has no implicit `this`,
so a parameter with the same name as a field cannot actually shadow it.
`CheckShadow` only exempted static members and members with an explicit
object parameter, it never handled the case where the enclosing function
isn't a member function at all, which fell through to the generic
diagnostic. In this PR I extend the exemption to cover that case and
added the regression test.

In this PR, I used Claude to help navigate the codebase and explain key
functions.
Fixes #221190
DeltaFile
+23-0clang/test/SemaCXX/warn-shadow.cpp
+8-2clang/lib/Sema/SemaDecl.cpp
+4-0clang/docs/ReleaseNotes.md
+35-23 files

LLVM/project b249b47llvm/utils profcheck-xfail.txt

[Profcheck] Exclude two new tests (#223690)

Exclude these tests for now. We haven't gotten to AtomicExpand/ARM yet,
and the AggressiveInstCombine change is overlapping.
DeltaFile
+2-0llvm/utils/profcheck-xfail.txt
+2-01 files

LLVM/project 18b447bllvm/lib/Target/PowerPC PPCMIPeephole.cpp, llvm/test/CodeGen/PowerPC sext_elimination.mir fold-rlwinm.mir

PowerPC: Remove LiveVariables dependency from PPCMIPeephole

PPCMIPeephole only used LiveVariables to keep kill/dead flags valid after its
transforms, and made no real use of the analysis.

A later LiveVariables run recomputes those flags from scratch anyway, so
just clear possbly stale kill/dead flags on changed registers.

PPCMIPeephole was the only user of LiveVariables at this point in the
pipeline, so also drop the explicit LiveVariables run before
PPCTLSDynamicCallPass, whose comment references a > 10 year old build
bot failure.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+140-70llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+40-40llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir
+57-13llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
+24-25llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+30-17llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
+28-14llvm/test/CodeGen/PowerPC/sext_elimination.mir
+319-17916 files not shown
+448-31922 files

LLVM/project 473ea07clang/test/CodeGenHLSL/resources Textures-Load.hlsl, flang/test/Lower/OpenACC acc-parallel-loop.f90

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+1,376-202llvm/test/Transforms/LoopVectorize/predicated-inductions-vs-first-order-recurrences.ll
+752-318llvm/test/Analysis/CostModel/ARM/shuffle.ll
+552-0llvm/test/Analysis/LoopAccessAnalysis/zero-distance-mixed-width.ll
+294-161clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
+448-0flang/test/Lower/OpenACC/acc-parallel-loop.f90
+288-119llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
+3,710-800421 files not shown
+16,758-6,013427 files

LLVM/project 7a40d56llvm/lib/CodeGen RegisterPressure.cpp

Trim comment
DeltaFile
+3-5llvm/lib/CodeGen/RegisterPressure.cpp
+3-51 files

LLVM/project c9fbbd9llvm/test/CodeGen/X86 min-legal-vector-width.ll inline-asm-pr76416.ll

RegisterPressure: Remove dead defs correctly

When an instruction has overlapping register defs where only some carry the
dead flag (for example a dead super-register def alongside a live sub-register
def), the collector left the shared register units in both the live and dead def
sets. That produced a PressureDiff decrement with no matching increment and tripped
the "PSet overflow/underflow" assertion in getUpwardPressureDelta.

A register unit is dead if any def covering it is dead, regardless of operand
order. Reconcile by subtracting the dead defs from the live defs instead of the
reverse: removeRegLanes only clears the overlapping units, so a def keeps any
units a dead def does not cover.

Fixes #155807.
Fixes #149144.
Fixes #76416.
Fixes #205272.

Co-authored-by: XChy <xxs_chy at outlook.com>
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
DeltaFile
+233-216llvm/test/CodeGen/X86/masked-udiv.ll
+106-89llvm/test/CodeGen/X86/vector-idiv-strictfp.ll
+72-60llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
+42-40llvm/test/CodeGen/X86/udiv_fix_sat.ll
+75-0llvm/test/CodeGen/X86/inline-asm-pr76416.ll
+35-35llvm/test/CodeGen/X86/min-legal-vector-width.ll
+563-4409 files not shown
+708-47215 files

LLVM/project eccf6a1llvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Return a SCEVUse from getAddRecExpr and propagate use flags. (#221606)

Same as https://github.com/llvm/llvm-project/pull/220007 but for
getAddRecExpr:

Pass both expression and use specific flags to getAddRecExpr and 
propagate the use flags, if valid conservatively. That is, the final expression
forms an AddRec with the same operands. For example, it is not valid to
propagate the use flags if other (sub-)expressions have been inlined.

It also includes a few mechanical changes, to update users that still
expected const SCEV *.

PR: https://github.com/llvm/llvm-project/pull/221606
DeltaFile
+102-0llvm/unittests/Analysis/ScalarEvolutionTest.cpp
+23-12llvm/lib/Analysis/ScalarEvolution.cpp
+6-6llvm/include/llvm/Analysis/ScalarEvolution.h
+2-1llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+133-194 files

LLVM/project 637ead9mlir/lib/Dialect/Linalg/Transforms Generalization.cpp

[MLIR][Linalg] Fix ASAN bug from #222959 (#223683)
DeltaFile
+9-3mlir/lib/Dialect/Linalg/Transforms/Generalization.cpp
+9-31 files

LLVM/project bc26ee7llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU mai-hazards-gfx90a.mir mai-hazards-gfx942.mir

review
DeltaFile
+128-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
+11-7llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+9-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
+148-73 files

LLVM/project a67d3dallvm/lib/Target/AMDGPU GCNHazardRecognizer.h GCNHazardRecognizer.cpp

Review: fix naming and minor changes
DeltaFile
+18-18llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+5-5llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+23-232 files

LLVM/project 344a8e2llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp

review: address suggestions
DeltaFile
+11-9llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+11-91 files

LLVM/project 96fc618llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU mai-hazards-gfx942.mir

[AMDGPU] Add wait states between different MFMAs sharing an accumulator
DeltaFile
+30-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
+18-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+48-02 files

LLVM/project c9d7b9ellvm/lib/Target/AMDGPU GCNHazardRecognizer.h GCNHazardRecognizer.cpp

[AMDGPU][NFC] Move MFMA overlapped src2/C wait states into a helper
DeltaFile
+63-66llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+5-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+68-662 files

LLVM/project be1ca5fllvm/lib/Target/ARM ARMInstrThumb.td ARMInstrInfo.td, llvm/test/CodeGen/ARM setjmp_longjmp.ll

[ARM] Fix Int_eh_sjlj_longjmp instruction size (#223639)

These pseudos expand to one more instruction on non-darwin/windows
platforms.

See: https://github.com/llvm/llvm-project/blob/88107b203b9e02a2d6ce87bf8ba0d98cb6ff53ec/llvm/lib/Target/ARM/ARMAsmPrinter.cpp#L2738-L2764
DeltaFile
+6-0llvm/test/CodeGen/ARM/setjmp_longjmp.ll
+2-2llvm/unittests/Target/ARM/InstSizes.cpp
+2-2llvm/lib/Target/ARM/ARMInstrThumb.td
+2-2llvm/lib/Target/ARM/ARMInstrInfo.td
+4-0llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+16-65 files

LLVM/project 01979b5llvm/include/llvm/CodeGen SlotIndexes.h, llvm/lib/CodeGen SlotIndexes.cpp

AMDGPU: Maintain LiveIntervals when removing blocks in SILowerControlFlow

removeMBBifRedundant removed a redundant block's instructions from the
LiveIntervals maps but not the block itself, leaving a stale idx2MBBMap entry
that crashed getMBBFromIndex in the verifier.

Add SlotIndexes::removeMBBFromMaps to drop the erased block's slot range, and
recompute the intervals that spanned it.

Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
DeltaFile
+95-0llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir
+24-0llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+23-0llvm/lib/CodeGen/SlotIndexes.cpp
+5-0llvm/include/llvm/CodeGen/SlotIndexes.h
+147-04 files

LLVM/project 52efc8fllvm/lib/CodeGen SlotIndexes.cpp, llvm/lib/Target/AMDGPU SILowerControlFlow.cpp

Review comments
DeltaFile
+3-11llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+1-1llvm/lib/CodeGen/SlotIndexes.cpp
+4-122 files

LLVM/project d16a0fcllvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp

review: address suggestions
DeltaFile
+11-9llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+11-91 files

LLVM/project 39e537fclang/test/CodeGen builtins-arm64.c

clang: Fix a test assuming single digit metadata numbers
DeltaFile
+6-6clang/test/CodeGen/builtins-arm64.c
+6-61 files

LLVM/project 8963be5llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU fptoui.ll fptosi.ll

[AMDGPU] Model the cost of the expanded integer to/from floating point casts

No instruction converts to or from a 64 bit integer, and narrow vector
lanes are converted one at a time. Price these expansions by the FP64
rate, sdwa and 16 bit instruction support, and price i33 to i63 like
i64 and bf16 like f32 plus rounding.

Assisted-by: Claude Code Opus 5
DeltaFile
+322-218llvm/test/Analysis/CostModel/AMDGPU/cast.ll
+212-117llvm/test/Analysis/CostModel/AMDGPU/expanded-int-fp-casts.ll
+107-0llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+66-38llvm/test/Analysis/CostModel/AMDGPU/fptoui.ll
+66-38llvm/test/Analysis/CostModel/AMDGPU/fptosi.ll
+773-4115 files

LLVM/project 9362acallvm/test/Analysis/CostModel/AMDGPU fptoui.ll fptosi.ll

[NFC][AMDGPU] Add cost tests for integer to/from floating point casts (#223571)

Cover i48, i64, i128, bf16, fp128 and narrow vector lanes across FP64
rates, 16 bit instructions, sdwa and both cost kinds.

Assisted-by: Claude Code Opus 5
DeltaFile
+277-0llvm/test/Analysis/CostModel/AMDGPU/expanded-int-fp-casts.ll
+266-0llvm/test/Analysis/CostModel/AMDGPU/cast.ll
+25-0llvm/test/Analysis/CostModel/AMDGPU/fptoui.ll
+25-0llvm/test/Analysis/CostModel/AMDGPU/fptosi.ll
+593-04 files

LLVM/project ecb8a5ellvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp

[NFC][AMDGPU] Fix two code quality issues in AMDGPUSwLowerLDS

- NumStaticLDS is always a positive number, so it was always true
- Potential `Changed = true` was dropped in the loop
DeltaFile
+35-41llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+35-411 files

LLVM/project d940cd6llvm/include/llvm/Demangle MicrosoftDemangleNodes.h Demangle.h, llvm/lib/Demangle MicrosoftDemangleNodes.cpp

[MSVC][Demangling] Respect MSDF_NoCallingConvention for function pointers (#209113)

The goal is to update MSVC demangling so that we control whether we
display a function pointer as `void (__cdecl *funcPtr)(void)` or `void
(*funcPtr)(void)`, by abiding by the `MSDF_NoCallingConvention` flag.

It is not a one-liner because function pointers used to use a trick
where it would unconditionally drop all the flags and pass
`OF_NoCallingConvention` to output the calling convention inside the
parentheses. In order to respect `MSDF_NoCallingConvention`, we need to
get rid of this trick.

A side effect of the trick was that OF_NoReturnType was also lost, which
is actually good because dropping the return type of a named function is
unambiguous, but dropping the return type of a function pointer loses
important information. The fix enforces that behavior explicitly.

This change can have impact for end-users who always passed
MSDF_NoCallingConvention, but I believe that this new behavior is the

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DeltaFile
+29-0llvm/unittests/Demangle/MicrosoftDemangleTest.cpp
+20-6llvm/lib/Demangle/MicrosoftDemangleNodes.cpp
+5-0llvm/include/llvm/Demangle/Demangle.h
+2-0llvm/include/llvm/Demangle/MicrosoftDemangleNodes.h
+56-64 files

LLVM/project 5bf2127llvm/lib/CodeGen MachineScheduler.cpp, llvm/test/CodeGen/AArch64 misched-detail-resource-booking-02.mir misched-detail-resource-booking-01.mir

[MISched] Fix pre-RA pickOnlyChoice tracing (#223182)

Add missing tracePick calls. Now GenericScheduler and
PostGenericScheduler tracing coverage is complete. Add a stable only1
test for pre-RA scheduling.
DeltaFile
+111-0llvm/test/CodeGen/AArch64/misched-prera-only1.mir
+6-2llvm/lib/CodeGen/MachineScheduler.cpp
+7-0llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
+1-0llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
+125-24 files

LLVM/project a4d5c00llvm/docs LangRef.md

Explicitly state that coherence rules don't affect unordered.
DeltaFile
+3-2llvm/docs/LangRef.md
+3-21 files

LLVM/project 92d4f66llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] LowerFP_TO_INT_SAT - use original SDValue directly. NFC. (#223651)

No need to access everything via the SDNode

Cleanup to reduce diff in #199416
DeltaFile
+5-6llvm/lib/Target/X86/X86ISelLowering.cpp
+5-61 files

LLVM/project 184ef35llvm/lib/Transforms/AggressiveInstCombine AggressiveInstCombine.cpp, llvm/test/Transforms/AggressiveInstCombine memset.ll

[AggressiveInstCombine] Guard memset with length in [0, 1] (#213240)

Use computeKnownBits to identify nonconstant memset lengths whose
possible values are limited to zero and one. The check is integrated
into the existing instruction loop in foldUnusualPatterns via the
dedicated helper foldMemSetZeroOrOneLength.

Insert a conditional branch around the memset and specialize the
executed path to a constant length of one. A following InstCombine
pass can then replace it with a byte store, including for a
nonconstant fill value.

Do not transform wider ranges such as [0, 2].

Fixes #213027.

Assisted by GPT-5
DeltaFile
+111-0llvm/test/Transforms/AggressiveInstCombine/memset.ll
+43-4llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+154-42 files

LLVM/project 3a42f8aclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen builtins-arm64.c builtins-arm.c

[ARM] Emit llvm.clear_cache for __clear_cache() (#223398)

It looks like the ARM-specific __clear_cache() builtin emits different
IR than the generic __builtin___clear_cache() builtin (added later),
which uses the llvm.clear_cache intrinsic (which will typically lower to
a __clear_cache libcall, of course).

Use llvm.clear_cache for __clear_cache() as well, for consistency and to
slightly simplify the code.
DeltaFile
+8-18clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-1clang/test/CodeGen/builtins-arm64.c
+1-1clang/test/CodeGen/builtins-arm.c
+10-203 files

LLVM/project d8e5c98llvm/lib/Target/ARM ARMTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/ARM shuffle.ll

[ARM] Add Neon costs for vrev shuffles (#223310)

This, like for AArch64 and MVE, allows some of the legal vrev shuffle
masks to be costed as if they are a single instruction, which can help
prevent the mid end from deoptimizing the code.
DeltaFile
+10-10llvm/test/Analysis/CostModel/ARM/shuffle.ll
+11-0llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+21-102 files

LLVM/project 7162999llvm/lib/Target/AArch64 AArch64PredicateAsCounterLoopRewrites.cpp

Fixup concat
DeltaFile
+13-13llvm/lib/Target/AArch64/AArch64PredicateAsCounterLoopRewrites.cpp
+13-131 files

LLVM/project 68747f2llvm/cmake config-ix.cmake, llvm/include/llvm/Config config.h.cmake

[CMake] Prune dead and unnecessary try_compiles from config.h (#223600)

Several config-ix checks either have no consumer or can be performed
directly by the source that needs the feature. Remove six compiler
invocations from a typical Linux configure:

* HAVE_PTHREAD_MUTEX_LOCK has been unused since LLVM switched its mutex
implementation to std::recursive_mutex in 2019.
* The Linux magic-header results have never been propagated to config.h,
so CMake builds already use Path.inc's fallback constants.
* FE_ALL_EXCEPT and FE_INEXACT can be tested directly after including
cfenv.
* The Valgrind and CrashReporter headers can be detected with
__has_include in their only consuming translation units.

Also remove the obsolete definitions from the GN and Bazel
configurations.

In a fresh minimal LLVM configure, CMake profiling attributed 2067.1 ms

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+0-15llvm/cmake/config-ix.cmake
+6-8llvm/lib/Support/Valgrind.cpp
+4-9utils/bazel/llvm-project-overlay/llvm/config.bzl
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+16-10410 files