LLVM/project 69784acllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll

fixup! Loosen the mask condition
DeltaFile
+5-28llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+14-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+19-342 files

LLVM/project ed554f2mlir/include/mlir/Dialect/XeGPU/IR XeGPUOps.td, mlir/lib/Dialect/XeGPU/IR XeGPUOps.cpp

[mlir][xegpu] Remove chunk_size attribute; infer from types (#205122)

The chunk_size attribute on xegpu.load (LoadGatherOp) and xegpu.store
(StoreScatterOp) was redundant with the operand/result types: the XeVM
lowering never read it, VectorToXeGPU already built these ops with an
empty chunk_size, and the op docs noted it could be inferred from the
type.

Remove the attribute and infer the chunk size from the value/result and
mask types via a computed getChunkSize() op method. The mask carries one
element per lane, so the chunk size is the trailing value dimension when
the value has more elements than the mask, and 1 otherwise. This keeps
the existing op.getChunkSize() call sites working while respecting
library layering (no XeGPUUtils dependency from the IR library).

Update the gather/scatter builders, transforms (propagate-layout,
sg-to-lane, wg-to-sg, unroll), VectorToXeGPU lowerings, and lit tests.
Two invalid.mlir cases that were only invalid because a stated
chunk_size contradicted the type are removed; two others are

    [4 lines not shown]
DeltaFile
+129-0mlir/test/Conversion/XeGPUToXeVM/loadstore_gather_coalesce.mlir
+17-91mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
+58-47mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+39-57mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+48-44mlir/test/Dialect/XeGPU/invalid.mlir
+16-66mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
+307-30517 files not shown
+570-58923 files

LLVM/project ad6f842llvm/lib/CodeGen RegisterPressure.cpp, llvm/test/CodeGen/AMDGPU schedule-pressure-dead-superreg-live-subreg.mir

Partially revert "RegisterPressure: Remove dead defs correctly" (#224371)

This partially reverts the lane-mask collector change from #222627
(bde5e74309f6). That flipped the dead-def reconciliation in both
RegisterOperandsCollector::collectInstr (register units) and
collectInstrLanes (lane masks). Instead of removing units covered by a
live def from the dead def set, it removed units covered by a dead def
from the live def set.

The flip regressed targets that track subregister liveness, which use
the
lane-mask collector path. When a live sub-register def overlaps a dead
super-register def, the shared register unit is flagged live on one
operand and dead on another. Removing the live def then drops the
genuinely-live unit, so the cached PressureDiff under-counts it and
trips
the EXPENSIVE_CHECKS pressure cross-check in GCNSchedStrategy.

Restore the original lane-mask path while keeping the new behavior on

    [14 lines not shown]
DeltaFile
+34-0llvm/test/CodeGen/AMDGPU/schedule-pressure-dead-superreg-live-subreg.mir
+3-5llvm/lib/CodeGen/RegisterPressure.cpp
+37-52 files

LLVM/project 01d1d4dmlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp, mlir/lib/Conversion/ControlFlowToLLVM ControlFlowToLLVM.cpp

[mlir][LowerToLLVM] Pass DataLayoutAnalysis to LowerToLLVMOptions in `ArithToLLVM`, `ControlFlowToLLVM`, and `VectorToLLVM` passes (#206380)

These three conversion passes constructed `LowerToLLVMOptions` without a
`DataLayout`, causing the index bitwidth to be hard-wired to 64 even
when the module declares a narrower index via `dlti.dl_spec`.

```cpp
// Before (all three passes):
LowerToLLVMOptions options(&getContext());
LLVMTypeConverter converter(&getContext(), options);

// After:
const auto &dataLayoutAnalysis = getAnalysis<DataLayoutAnalysis>();
LowerToLLVMOptions options(&getContext(),
                           dataLayoutAnalysis.getAtOrAbove(getOperation()));
LLVMTypeConverter converter(&getContext(), options, &dataLayoutAnalysis);
```

I used AI to investigate this problem and to write the tests.

    [3 lines not shown]
DeltaFile
+74-5mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
+67-0mlir/test/Conversion/VectorToLLVM/vector-load-store-to-llvm.mlir
+59-0mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
+5-2mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
+5-2mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
+5-2mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+215-113 files not shown
+220-119 files

LLVM/project 1b34344llvm/docs/tutorial BuildingAJIT3.md, llvm/docs/tutorial/MyFirstLanguageFrontend LangImpl08.md

docs: Compute the DataLayout from the triple in the tutorials

Update the exmaple code to avoid using TargetMachine::createDataLayout.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-1llvm/examples/Kaleidoscope/Chapter8/toy.cpp
+2-1llvm/docs/tutorial/BuildingAJIT3.md
+1-1llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.md
+5-33 files

LLVM/project 45cb52flldb/source/Plugins/ObjectFile/ELF ObjectFileELF.cpp

[lldb] Remove remaining ConstString section names in ObjectFileELF (#224407)
DeltaFile
+14-13lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+14-131 files

LLVM/project e9e9439utils/bazel/llvm-project-overlay/libc/test libc_test_rules.bzl, utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil BUILD.bazel

[bazel][test][libc] Add tags to tests marking full-build compatibility

This allows Bazel to execute tests based on whether they support full-build mode or not, by running:

```
bazel test @llvm-project//libc/... --test_tag_filters=-llvm-libc-overlay-only --@llvm-project//libc:build_mode=full
```

Bazel is already able to tell which tests need to be skipped by using `target_compatible_with`, but using tags allows consumers to configure their CI so no tests get implicitly skipped.
DeltaFile
+14-1utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl
+3-0utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
+1-0utils/bazel/llvm-project-overlay/libc/test/src/complex/BUILD.bazel
+19-14 files

LLVM/project a51479bmlir/lib/ExecutionEngine ExecutionEngine.cpp, mlir/lib/Target/LLVM ModuleToObject.cpp

mlir: Avoid using TargetMachine::createDataLayout

This should pass in an ABI name, but there doesn't appear to
be one around in context.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-1mlir/lib/Target/LLVMIR/Transforms/TargetUtils.cpp
+1-1mlir/lib/Target/LLVM/ModuleToObject.cpp
+1-1mlir/lib/ExecutionEngine/ExecutionEngine.cpp
+4-33 files

LLVM/project 826f78dlldb/test/Shell/SymbolFile/NativePDB unknown-udt-decl.ll rust-unique-name.ll

lldb: Require x86_64 for x86_64-specific NativePDB tests (#224140)

These tests contained x86_64 datalayout and triples, but only
required system-windows. On an aarch64 windows host, %build will
be an incompatible datalayout, so require exactly x86_64 windows
hosts. Alternatively the test could be changed to not have the
datalayout, but I'm not sure if that's correct here.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+1-1lldb/test/Shell/SymbolFile/NativePDB/unknown-udt-decl.ll
+1-1lldb/test/Shell/SymbolFile/NativePDB/rust-unique-name.ll
+2-22 files

LLVM/project 33594a8.ci all_requirements.txt, clang/test/CodeGen builtin-clear-padding-codegen.c

Merge branch 'main' into users/adams381/cir-explicit-nothrow-willreturn
DeltaFile
+4,402-1,088clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+2,801-612clang/test/CodeGen/builtin-clear-padding-codegen.c
+602-459.ci/all_requirements.txt
+815-0llvm/test/Transforms/PhaseOrdering/ARM/arm_mat_mult_q31.ll
+478-308llvm/utils/git/requirements_linting.txt
+383-393llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+9,481-2,8601,267 files not shown
+49,708-13,2711,273 files

LLVM/project 42a1f57clang/test/CodeGen builtin-clear-padding-codegen.c, clang/test/CodeGenCXX builtin-clear-padding-codegen.cpp

Merge branch 'main' into users/adams381/cir-ptr-mask
DeltaFile
+4,377-4,141llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,753-0llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
+2,822-2,774llvm/test/CodeGen/AMDGPU/bf16.ll
+4,402-1,088clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+2,633-2,496llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,801-612clang/test/CodeGen/builtin-clear-padding-codegen.c
+22,788-11,1112,078 files not shown
+111,378-56,3312,084 files

LLVM/project 870d762clang/lib/StaticAnalyzer/Checkers/WebKit RawPtrRefLambdaCapturesChecker.cpp, clang/test/Analysis/Checkers/WebKit uncounted-lambda-captures.cpp

[webkit.UncountedLambdaCapturesChecker] NOESCAPE is ignored in a template function (#223942)

RawPtrRefLambdaCapturesChecker only consults NOESCAPE when it can find a
FunctionDecl for a call. Because a lambda argument is type-dependent, a
call taking one inside a template is dependent, and its callee is often
still unresolved in the template pattern: an UnresolvedLookupExpr for an
unqualified call or a call to a function template, an
UnresolvedMemberExpr for an overloaded member function or a member
function template, and a CXXDependentScopeMemberExpr for a member of a
dependent object. checkParameters never ran for those, so a lambda was
reported even when the parameter it's passed to is annotated with
NOESCAPE. The same happened for a lambda passed to a constructor which
isn't resolved until the instantiation, which appears as a
CXXUnresolvedConstructExpr or as a dependent ParenListExpr /
InitListExpr.

Whether such a lambda can escape isn't known before the enclosing
template is instantiated, so ignore these lambdas and let the
instantiation check them, matching what RetainPtrCtorAdoptChecker

    [10 lines not shown]
DeltaFile
+165-0clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
+63-5clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
+228-52 files

LLVM/project c3bfaa8llvm/lib/Transforms/Scalar ConstraintElimination.cpp

[ConstraintElim] Move helper to create constraint row (NFC) (#224417)

Move logic to grate a new row for the constraint system to helper, to
more clearly separate logic, and allow re-use in follow-ups.

This includes minor code reodering in the moved logic.
DeltaFile
+56-47llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+56-471 files

LLVM/project 899c261.github/workflows build-ci-container-tooling.yml

[Github] Rename CI Tooling Containers to 26.04 (#224447)

697570d3ca9f99cc30662fc80fd0beb1b715e478 made them actually use Ubuntu
26.04, but I forgot to rename them. Do that in this commit. Everything
is hash pinned so nothing should break even if there are real issues.
DeltaFile
+1-1.github/workflows/build-ci-container-tooling.yml
+1-11 files

LLVM/project 797dfd0llvm/include/llvm/Analysis TargetTransformInfoImpl.h TargetTransformInfo.h, llvm/lib/Analysis TargetTransformInfo.cpp

Revert "[SLP] More accurately cost RISCV scalar splats" (#224426)

Reverts llvm/llvm-project#213104
DeltaFile
+55-133llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+6-42llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+31-11llvm/test/Transforms/SLPVectorizer/RISCV/check-node-without-vector-user.ll
+2-29llvm/include/llvm/Analysis/TargetTransformInfo.h
+3-18llvm/lib/Analysis/TargetTransformInfo.cpp
+5-14llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+102-24723 files not shown
+176-34029 files

LLVM/project 36620f3clang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareExchangeFloatBitwise builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project 87e7118clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareExchangeFloatBitwise coverage to the texture test
DeltaFile
+5-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+5-01 files

LLVM/project d678dc0clang/test/CodeGenHLSL/builtins RWBuffer-Interlocked.hlsl RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl, clang/test/SemaHLSL/BuiltIns ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl InterlockedCompareExchangeFloatBitwise-errors.hlsl

First attempt implementing InterlockedCompareExchangeFloatBitwise



DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-0clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl
+271-05 files not shown
+298-311 files

LLVM/project a610a1dclang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareStoreFloatBitwise builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project f648f6cclang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareStoreFloatBitwise coverage to the texture test
DeltaFile
+7-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+7-01 files

LLVM/project fc74b2bclang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

First attempt implementing InterlockedCompareStoreFloatBitwise



DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+35-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+16-6clang/lib/Sema/SemaHLSL.cpp
+247-66 files not shown
+311-1012 files

LLVM/project 77d897fclang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareExchange builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project b1b2653clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareExchange coverage to the texture test
DeltaFile
+5-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+5-01 files

LLVM/project 81f5cc4clang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareStore builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project 4e70187clang/lib/Sema HLSLExternalSemaSource.cpp SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl RWByteAddressBuffer-InterlockedCompareExchange.hlsl

First attempt implementing InterlockedCompareExchange



DeltaFile
+93-81clang/lib/Sema/SemaHLSL.cpp
+113-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchange-errors.hlsl
+70-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchange.hlsl
+41-24clang/lib/Sema/HLSLExternalSemaSource.cpp
+44-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchange.hlsl
+35-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl
+396-1056 files not shown
+480-12212 files

LLVM/project 65d1a5cflang/lib/Optimizer/OpenACC/Support FIROpenACCUtils.cpp, flang/test/Transforms/OpenACC acc-implicit-routine.fir

[mlir][OpenACC] Error on external calls without acc routine info (#223815)

Implicit routine can only be applied to procedures defined in the
current compilation unit. Diagnose external callees in compute regions
and existing routines, and treat Fortran intrinsics and `BIND(C)`
procedures as valid device symbols.
DeltaFile
+149-0flang/test/Transforms/OpenACC/acc-implicit-routine.fir
+44-10mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitRoutine.cpp
+45-1mlir/test/Dialect/OpenACC/acc-implicit-routine.mlir
+7-0flang/lib/Optimizer/OpenACC/Support/FIROpenACCUtils.cpp
+245-114 files

LLVM/project 08c8722clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Sema HLSLExternalSemaSource.cpp

First attempt implementing InterlockedCompareStore
DeltaFile
+88-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStore-errors.hlsl
+54-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStore.hlsl
+45-7clang/lib/Sema/HLSLExternalSemaSource.cpp
+29-7clang/lib/CodeGen/CGHLSLBuiltins.cpp
+36-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStore.hlsl
+33-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStore.ll
+285-147 files not shown
+393-1613 files

LLVM/project 77e6345clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareStore coverage to the texture test
DeltaFile
+13-8clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+13-81 files

LLVM/project 2d2a68fclang/include/clang/Basic Builtins.td, clang/lib/Sema HLSLBuiltinTypeDeclBuilder.cpp

Remove comments on the float InterlockedExchange declarations
DeltaFile
+0-3clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+0-1clang/include/clang/Basic/Builtins.td
+0-42 files

LLVM/project 40762f3llvm/lib/Object GOFFObjectFile.cpp

Revert "[GOFFObjectFile] replace snprintf with formatv (#224435)" (#224444)

This reverts commit c60745d126c6d521f76e1a6d81a732d53f4b5ad2.
DeltaFile
+3-2llvm/lib/Object/GOFFObjectFile.cpp
+3-21 files