LLVM/project 4327bb4llvm/docs DeveloperPolicy.rst

DeveloperPolicy: Add note about legacy bitcode performance (#174720)

Note that bitcode does not attempt to guarantee performance
parity with upgraded bitcode.
DeltaFile
+3-0llvm/docs/DeveloperPolicy.rst
+3-01 files

LLVM/project 36824e2flang/lib/Lower Bridge.cpp, flang/lib/Parser unparse.cpp parse-tree.cpp

Use "const auto &"
DeltaFile
+4-4flang/lib/Semantics/resolve-names.cpp
+2-2flang/lib/Parser/unparse.cpp
+1-1flang/lib/Lower/Bridge.cpp
+1-1flang/lib/Parser/parse-tree.cpp
+1-1flang/lib/Semantics/check-case.cpp
+1-1flang/lib/Semantics/expression.cpp
+10-106 files

LLVM/project f79f50cflang/lib/Optimizer/OpenACC/Support FIROpenACCOpsInterfaces.cpp, flang/test/Fir/CUDA cuf-offload-livein-value-canonicalization.fir

[mlir][acc] Add OffloadLiveInValueCanonicalization pass (#174671)

Introduce a pass to canonicalize live-in values for regions that will be
outlined for device execution.

When a region is outlined, values defined outside but used inside become
arguments to the outlined function. However, some values cannot or
should not be passed as arguments:
- Synthetic types (shape metadata, field indices)
- Constants better recreated inside the region
- Address-of operations for device-resident globals

This pass identifies such values and either sinks the defining operation
into the region (when all uses are inside) or clones it inside (when
uses exist both inside and outside).

To identify target regions in a dialect-agnostic way, this patch
introduces `OffloadRegionOpInterface`. This marker interface allows the
pass to work uniformly across OpenACC compute constructs, GPU

    [11 lines not shown]
DeltaFile
+302-0mlir/lib/Dialect/OpenACC/Transforms/OffloadLiveInValueCanonicalization.cpp
+255-0flang/test/Fir/OpenACC/offload-livein-value-canonicalization.fir
+240-0mlir/test/Dialect/OpenACC/offload-livein-value-canonicalization.mlir
+79-0flang/test/Fir/CUDA/cuf-offload-livein-value-canonicalization.fir
+76-0mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
+16-8flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
+968-89 files not shown
+1,010-915 files

LLVM/project 8c830d3llvm/lib/Transforms/Vectorize VPlanAnalysis.cpp

[VPlan] Merge cases inferring type of operand 0 (NFC).

Merge all cases that infer the scalar type of operand 0 in
inferScalarTypeForRecipe(const VPInstruction).
DeltaFile
+10-19llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+10-191 files

LLVM/project 6e1acd0llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 multi-parent-instr-copyable-regular.ll

[SLP]Update deps for copyables operands, if the user is used several times in node

If the user instruction is used several times in the node, and in one
cases its operand is copyable, but in another is not, need to check all
operands to be sure we do not miss scheduling
DeltaFile
+85-0llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
+0-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+85-22 files

LLVM/project 708663cllvm/test/CodeGen/AMDGPU local-stack-alloc-sort-framerefs.mir

Precommit test for PR #171012 (#171013)

This patch precommits a test where base offsets are negative. PR
[171012](https://github.com/llvm/llvm-project/pull/171012 ) will
eliminate negative offsets by sorting the scratch instructions.
DeltaFile
+27-0llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
+27-01 files

LLVM/project 2a5bdc6flang/lib/Semantics check-case.cpp resolve-names.cpp

format
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+21-21flang/lib/Semantics/check-case.cpp
+1-2flang/lib/Semantics/resolve-names.cpp
+22-232 files

LLVM/project 5da8336llvm/test/CodeGen/AMDGPU llvm.amdgcn.wmma.gfx1250.w32.ll llvm.amdgcn.wmma.imod.gfx1250.w32.ll

resolve comments
DeltaFile
+246-246llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+220-220llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+212-212llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+174-174llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+166-166llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+103-103llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
+1,121-1,121144 files not shown
+5,383-5,461150 files

LLVM/project b80264bllvm/test/CodeGen/AMDGPU carryout-selection.ll llvm.amdgcn.wmma.gfx1250.w32.ll

[AMDGPU] Handle `s_setreg_imm32_b32` targeting `MODE` register

On certain hardware, this instruction clobbers VGPR MSB `bits[12:19]`, so we need to restore the current mode.
DeltaFile
+713-2llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+246-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+220-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+212-0llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+174-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+166-0llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+1,731-2146 files not shown
+6,212-3152 files

LLVM/project 34101f8llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp

resolve review comments
DeltaFile
+9-6llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+9-61 files

LLVM/project 539ae71flang/include/flang/Parser parse-tree-visitor.h parse-tree.h, flang/lib/Lower Bridge.cpp

[flang] Add traits to several AST nodes, NFC

There are quite a few AST nodes that don't have any of the standard
traits (Wrapper/Tuple/etc). Because of that they require special
handling in the parse tree visitor.

Convert a subset of these nodes to the typical format, and remove
the special cases from the parse tree visitor.
DeltaFile
+0-153flang/include/flang/Parser/parse-tree-visitor.h
+20-44flang/include/flang/Parser/parse-tree.h
+24-20flang/lib/Semantics/resolve-names.cpp
+16-10flang/lib/Parser/unparse.cpp
+7-6flang/lib/Lower/Bridge.cpp
+6-5flang/lib/Semantics/check-case.cpp
+73-2383 files not shown
+81-2439 files

LLVM/project 21a1e6elldb/test/API/python_api/file_handle TestFileHandle.py, lldb/test/Shell/ScriptInterpreter/Python io.test

[lldb] skip the python interactive I/O test on windows (#175055)

There is no indication this ever worked on windows as this is the first
test that checks python interactive console from a file.

Looking at the error from the CI, It closed the interpreter before
running any python commands.
Will reconfirm this when I have access to a windows machine. 


From https://github.com/llvm/llvm-project/pull/174216
DeltaFile
+1-1lldb/test/API/python_api/file_handle/TestFileHandle.py
+2-0lldb/test/Shell/ScriptInterpreter/Python/io.test
+3-12 files

LLVM/project c379a88llvm/lib/Target/AMDGPU AMDGPU.td

[NFC][AMDGPU] Reorganize features for gfx125x (#175054)

DeltaFile
+3-2llvm/lib/Target/AMDGPU/AMDGPU.td
+3-21 files

LLVM/project 289a329llvm/lib/CodeGen EarlyIfConversion.cpp, llvm/test/CodeGen/AArch64 early-ifcvt-likely-predictable.mir

[EarlyIfConversion] Fix loop invariant operands check (#174765)

Fixes a bug in the check which prevented walking up the operands
of the branch condition beyond the operands to the branch instruction
itself.
DeltaFile
+71-0llvm/test/CodeGen/AArch64/early-ifcvt-likely-predictable.mir
+3-3llvm/lib/CodeGen/EarlyIfConversion.cpp
+74-32 files

LLVM/project a0b1799llvm/test/CodeGen/Xtensa mul.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+54-72llvm/test/CodeGen/Xtensa/mul.ll
+54-721 files

LLVM/project 14af55clldb/source/Plugins/SymbolFile/NativePDB PdbAstBuilder.cpp PdbAstBuilder.h

[LLDB][PDB] NFC: Change ToCompilerDecl(Context) signature (#175052)

Follow-up to https://github.com/llvm/llvm-project/pull/173111

`ToCompilerDeclContext` and `ToCompilerDecl` take their arguments as
references, but all callers are pointers. This changes the signature to
take pointers, then addresses the comments at
https://github.com/llvm/llvm-project/pull/173111#discussion_r2673140167
DeltaFile
+12-12lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
+2-2lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.h
+1-1lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
+15-153 files

LLVM/project ce1f3b2llvm/lib/Target/Xtensa XtensaISelLowering.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+1-1llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+1-11 files

LLVM/project 700d1f0llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.cpp, llvm/test/TableGen RegClassByHwModeCompressPat.td RegClassByHwMode.td

[TableGen] Support RegClassByHwMode in CompressPat

This does not yet handle all cases but at least for the simple
cases such as:
```
def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
                  (PTR_MOV_SMALL PtrRC:$dst, PtrRC:$src)>;
```
tablegen generates sensible code instead of emitting confusing errors.

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/171061
DeltaFile
+318-0llvm/test/TableGen/RegClassByHwModeCompressPat.td
+15-9llvm/utils/TableGen/CompressInstEmitter.cpp
+13-0llvm/test/TableGen/RegClassByHwMode.td
+7-5llvm/utils/TableGen/InstrInfoEmitter.cpp
+1-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+354-145 files

LLVM/project 19a8ca3lldb/tools/lldb-dap/extension package-lock.json, llvm/test/CodeGen/RISCV/rvv clmul-sdnode.ll fixed-vectors-clmul.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+0-6,820llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
+5,850-0lldb/tools/lldb-dap/extension/package-lock.json
+5,742-0llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+0-5,599llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+4,888-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
+0-4,727llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+16,480-17,1463,410 files not shown
+250,567-125,4453,416 files

LLVM/project ecab748llvm/lib/Target/AMDGPU AMDGPU.td

[NFC][AMDGPU] Reorganize features for gfx125x
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+3-2llvm/lib/Target/AMDGPU/AMDGPU.td
+3-21 files

LLVM/project 292c613llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus BUILD.gn

[gn build] Port c7c5259f016bdb12c670b1fba84a17417ff8e3a2
DeltaFile
+1-0llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
+1-01 files

LLVM/project 55e508clldb/cmake/modules LLDBConfig.cmake, lldb/test/API CMakeLists.txt

[lldb] Repair lldb-dotest's framework path (#174658)

lldb-dotest was likely getting LLDB_FRAMEWORK_DIR from another place
before. Now it's undefined when lldb-dotest is configured, so it's an
empty string. Some API tests will fail to link against LLDB.
DeltaFile
+0-4lldb/test/API/CMakeLists.txt
+1-0lldb/cmake/modules/LLDBConfig.cmake
+1-42 files

LLVM/project 4c171a2flang/test/Lower allocate-source-pointers.f90 array-constructor-2.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 4) (#174906)

From this point on, the conversion is done to HLFIR, not to FIR.

Tests converted in Lower: allocatables.f90,
allocate-source-pointers.f90, array-constructor-2.f90,
array-elemental-calls-3.f90, array-elemental-calls.f90
DeltaFile
+104-286flang/test/Lower/allocate-source-pointers.f90
+64-83flang/test/Lower/array-constructor-2.f90
+59-53flang/test/Lower/allocatables.f90
+28-50flang/test/Lower/array-elemental-calls.f90
+19-8flang/test/Lower/array-elemental-calls-3.f90
+274-4805 files

LLVM/project 812b3c2llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll simplify-demanded-fpclass-shufflevector.ll

InstCombine: Improve SimplifyDemandedFPClass fabs handling

Try to eliminate the fabs if the source is known positive.
DeltaFile
+4-8llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+5-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll
+10-103 files

LLVM/project 0478103llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Add baseline tests for fabs SimplifyDemandedFPClass improvements
DeltaFile
+49-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+49-01 files

LLVM/project ff4d5b9llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Drop attrs
DeltaFile
+9-7llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+9-71 files

LLVM/project edd9f70llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Only check SignBit
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+2-4llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+2-41 files

LLVM/project 26e6609llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Improve SimplifyDemandedFPClass copysign handling

Recognize cases where the signbit is known.
DeltaFile
+22-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+9-6llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+31-62 files

LLVM/project e59a86cllvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

More tests
DeltaFile
+21-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+21-01 files

LLVM/project 95b2e8allvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Add baseline tests for improved copysign handling
DeltaFile
+64-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+64-01 files