LLVM/project 515ea70llvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp

update

Created using spr 1.3.7
DeltaFile
+1-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+1-01 files

LLVM/project 6ebf78allvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp WebAssembly.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+234-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+29-6llvm/lib/Target/WebAssembly/WebAssembly.h
+21-7llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
+20-7llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
+25-0llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
+8-7llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+337-274 files not shown
+359-2910 files

LLVM/project d4df151llvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp WebAssemblyAddMissingPrototypes.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+234-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+21-7llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
+24-0llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
+20-4llvm/lib/Target/WebAssembly/WebAssembly.h
+9-2llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+6-5llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+314-183 files not shown
+327-189 files

LLVM/project 0b0d79cllvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp WebAssemblyAddMissingPrototypes.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+234-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+21-7llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
+24-0llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
+20-4llvm/lib/Target/WebAssembly/WebAssembly.h
+9-2llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+6-5llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+314-183 files not shown
+327-189 files

LLVM/project cb1cd2cllvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp WebAssemblyPassRegistry.def

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+234-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+18-0llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
+9-2llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+9-2llvm/lib/Target/WebAssembly/WebAssembly.h
+9-0llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+4-3llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+283-71 files not shown
+286-77 files

LLVM/project 00c280dllvm/lib/Target/WebAssembly WebAssembly.h WebAssemblyISelDAGToDAG.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+9-2llvm/lib/Target/WebAssembly/WebAssembly.h
+9-2llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+2-2llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+20-63 files

LLVM/project 060df3bllvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp WebAssemblyPassRegistry.def

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+234-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+18-0llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
+9-2llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+9-2llvm/lib/Target/WebAssembly/WebAssembly.h
+9-0llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+4-3llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+283-71 files not shown
+286-77 files

LLVM/project 189764bllvm/lib/Target/WebAssembly WebAssembly.h WebAssemblyISelDAGToDAG.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+9-2llvm/lib/Target/WebAssembly/WebAssembly.h
+9-2llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+2-2llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+20-63 files

LLVM/project 11191bellvm/lib/Transforms/IPO SampleProfileMatcher.cpp, llvm/test/Transforms/SampleProfile pseudo-probe-stale-profile-lcs-anchor-overwrite.ll

[SampleProfile] Preserve first stale profile CG match

During stale profile LCS matching, the matcher may compare the same IR function against multiple profile candidates. This can happen for overloads that share a demangled basename. The comparison result is useful for the current LCS, but rewriting FuncToProfileNameMap on every successful comparison can replace the profile selected for an IR function with a later candidate.

If another IR function is also matched to that later candidate, both functions can end up using the same stale CFG location map and runStaleProfileMatching asserts that the map is already populated.

Preserve the first selected profile mapping with try_emplace while still caching each pairwise comparison result. Add a regression with a minimal sample profile that used to trigger the assertion.
DeltaFile
+75-0llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-lcs-anchor-overwrite.ll
+7-0llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-stale-profile-lcs-anchor-overwrite.prof
+1-1llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+83-13 files

LLVM/project 9dffcd2lld/ELF Writer.cpp, lld/test/ELF aarch64-reloc-pauth.s

[PAC][lld] Properly handle `.relr.auth.dyn` -> `.rela.dyn` movement (#195649)

Address the following issues reported in #171475:

1. Proper adjustment of `__rela_iplt_end` address if a move from
`.relr.auth.dyn` to `.rela.dyn` took place

2. Set `__rela_iplt_start` properly if prior to such movement from
`.relr.auth.dyn`, the `.rela.dyn` was empty

3. Allocate enough space for both RELA* and AARCH64_AUTH_RELR* tags in
the `.dynamic` section in case we end up with both `.relr.auth.dyn` and
`.rela.dyn`. If one of the sections becomes empty - just pad the
`.dynamic` section with null tags in the end.

Resolves #171475

---------

Co-authored-by: Jessica Clarke <jrtc27 at jrtc27.com>
DeltaFile
+132-8lld/test/ELF/aarch64-reloc-pauth.s
+31-9lld/ELF/Writer.cpp
+163-172 files

LLVM/project e9e21f5llvm/test/CodeGen/X86 buildvec-strided-loads.ll avx512-calling-conv.ll

Revert [X86] EltsFromConsecutiveLoads - handle trunc(wideload()) patterns (#199371) (#208960)

Reverts llvm/llvm-project#199371.

The strided path emits wide loads without checking that the widened
range is dereferenceable. The last wide load reads up to (stride -
element) bytes past the last element and faults when the data ends at a
page boundary. Flagged by @nikic in
https://github.com/llvm/llvm-project/pull/199371#issuecomment-4947406318.

Reproducer on current main **MADE WITH CLAUDE OPUS**

strided.ll, 8 x i16 at a 4 byte stride, the source only touches bytes
[0, 30):
```llvm
define void @strided8i16(ptr %p, ptr %out) {
  %g0 = getelementptr inbounds i8, ptr %p, i64 0
  %g1 = getelementptr inbounds i8, ptr %p, i64 4
  %g2 = getelementptr inbounds i8, ptr %p, i64 8

    [63 lines not shown]
DeltaFile
+0-1,128llvm/test/CodeGen/X86/buildvec-strided-loads.ll
+678-247llvm/test/CodeGen/X86/avx512-calling-conv.ll
+198-88llvm/test/CodeGen/X86/avx512-insert-extract.ll
+194-73llvm/test/CodeGen/X86/avx512-masked_memop-16-8.ll
+164-98llvm/test/CodeGen/X86/vector-compress.ll
+158-100llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
+1,392-1,7348 files not shown
+2,020-2,03014 files

LLVM/project 3a6048dllvm/lib/Target/ARM ARMAsmPrinter.cpp ARMISelLowering.cpp, llvm/test/CodeGen/ARM weak-hidden-pic.ll elf-preemption.ll

Revert "[ARM] Use .reloc for weak symbols in PIC mode instead of GOT indirection" (#208968)

There is a few breakages between `clang-armv8-quick` failing the
`Interpreter/execute-weak.cpp` test and bots failing linking
`libclang_rt.atomic.so`.

Reverts llvm/llvm-project#208372
DeltaFile
+0-30llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+6-8llvm/test/CodeGen/ARM/weak-hidden-pic.ll
+8-3llvm/lib/Target/ARM/ARMISelLowering.cpp
+4-6llvm/test/CodeGen/ARM/elf-preemption.ll
+9-0llvm/lib/Target/ARM/ARMTargetMachine.h
+2-1llvm/lib/Target/ARM/ARMSubtarget.cpp
+29-481 files not shown
+31-497 files

LLVM/project 61b5d78clang/lib/CIR/CodeGen CIRGenStmt.cpp CIRGenDecl.cpp

[CIR][NFC] Add missing enum values related to CXXExpansionStmt (#208919)

Add missing enum values related to CXXExpansionStmt
DeltaFile
+2-0clang/lib/CIR/CodeGen/CIRGenStmt.cpp
+1-0clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+3-02 files

LLVM/project 074c4b3lld/ELF MarkLive.cpp

[ELF] Replace getThreadIndex with explicit shards in markLive. NFC (#208974)

The parallel mark loop appends deeper discoveries to per-thread queues
indexed by `parallel::getThreadIndex()`, the last getThreadIndex user in
lld. Instead, have each worker claim frontier items off a shared
counter, accumulating into an explicit shard.

The finer-grained item claiming improves load balancing: the markLive
--time-trace phase is ~5% faster for a clang --gc-sections link and ~4%
for a larger chromium one.
DeltaFile
+9-6lld/ELF/MarkLive.cpp
+9-61 files

LLVM/project 10955eallvm/lib/Target/ARM ARMAsmPrinter.cpp ARMISelLowering.cpp, llvm/test/CodeGen/ARM weak-hidden-pic.ll elf-preemption.ll

Revert "[ARM] Use .reloc for weak symbols in PIC mode instead of GOT indirect…"

This reverts commit 290279b6b69138f4162cace4865713efa12ec262.
DeltaFile
+0-30llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+6-8llvm/test/CodeGen/ARM/weak-hidden-pic.ll
+8-3llvm/lib/Target/ARM/ARMISelLowering.cpp
+4-6llvm/test/CodeGen/ARM/elf-preemption.ll
+9-0llvm/lib/Target/ARM/ARMTargetMachine.h
+2-1llvm/lib/Target/ARM/ARMFastISel.cpp
+29-481 files not shown
+31-497 files

LLVM/project d6d0ccclldb/tools/lldb-mcp Multiplexer.cpp Multiplexer.h, lldb/unittests/Host JSONTransportTest.cpp

[lldb-mcp] Multiplex across all discovered LLDB instances (#208827)

Connect to every LLDB MCP server advertised under ~/.lldb rather than a
single one, and present them to the client as one server. A stale
registry entry from a crashed instance simply fails to connect and is
skipped.

Each instance is identified by the pid of its lldb process, now recorded
in the ServerInfo registry file. Tools and resources are addressed with
instance-qualified URIs, e.g. lldb-mcp://instance/{pid}/debugger/{id}
and lldb://instance/{pid}/debugger/{id}/target/{idx}. Listing requests
(sessions_list, resources/list) fan out to every backend and aggregate;
targeted requests (command, resources/read) are routed by the pid parsed
from the URI. Backends only know their local lldb-mcp://debugger/{id}
form, so URIs are rewritten in both directions.

Add Binder::FailPendingRequests (and Client::CancelPendingRequests) so
that when the client disconnects with a request still in flight to a
backend, the abandoned reply is satisfied with an error instead of being

    [3 lines not shown]
DeltaFile
+467-0lldb/unittests/tools/lldb-mcp/MultiplexerTest.cpp
+239-30lldb/tools/lldb-mcp/Multiplexer.cpp
+53-13lldb/tools/lldb-mcp/Multiplexer.h
+43-23lldb/tools/lldb-mcp/lldb-mcp.cpp
+20-0lldb/unittests/Host/JSONTransportTest.cpp
+15-0lldb/unittests/tools/lldb-mcp/CMakeLists.txt
+837-667 files not shown
+878-7013 files

LLVM/project 516cff3llvm/lib/Bitcode/Writer BitcodeWriter.cpp, llvm/test/Assembler thinlto-bad-summary-5.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+13-0llvm/test/tools/llvm-reduce/initialize-asm-parsers.ll
+11-0llvm/test/Assembler/thinlto-bad-summary-5.ll
+5-0llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+3-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+32-14 files

LLVM/project b5d4019llvm/lib/Bitcode/Writer BitcodeWriter.cpp, llvm/test/Assembler thinlto-bad-summary-5.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+15-0llvm/test/tools/llvm-reduce/initialize-asm-parsers.ll
+7-5llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+11-0llvm/test/Assembler/thinlto-bad-summary-5.ll
+3-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+36-64 files

LLVM/project c593d94llvm/lib/Bitcode/Writer BitcodeWriter.cpp, llvm/test/Assembler thinlto-bad-summary-5.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+13-0llvm/test/tools/llvm-reduce/initialize-asm-parsers.ll
+11-0llvm/test/Assembler/thinlto-bad-summary-5.ll
+5-0llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+3-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+32-14 files

LLVM/project 57c2cf4llvm/lib/Bitcode/Writer BitcodeWriter.cpp, llvm/test/Assembler thinlto-bad-summary-5.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+11-0llvm/test/Assembler/thinlto-bad-summary-5.ll
+3-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+14-12 files

LLVM/project 410a2a2libcxx/include/__algorithm pstl.h, libcxx/include/__pstl backend_fwd.h

[libc++][pstl] Default implementation of parallel std::reverse_copy (#208085)

This PR adds a default parallel implementation of `std::reverse_copy`
based on `std::reverse_iterator` + parallel `std::copy`.

Effectively it's a one-liner:
```c++
    return _Copy()(__policy,
                   std::reverse_iterator<_BidirectionalIterator>(std::move(__last)),
                   std::reverse_iterator<_BidirectionalIterator>(std::move(__first)),
                   std::move(__result));
```

Included tests check that:

- Semantics of the function is correct.
- The function correctly SFINAE out when the first argument is not an
execution policy.
- The `nodiscard` policy is followed.

    [8 lines not shown]
DeltaFile
+116-0libcxx/test/std/algorithms/alg.modifying.operations/alg.reverse/pstl.reverse_copy.pass.cpp
+18-0libcxx/include/__pstl/backends/default.h
+17-0libcxx/include/__algorithm/pstl.h
+12-2libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
+7-0libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
+7-0libcxx/include/__pstl/backend_fwd.h
+177-21 files not shown
+179-27 files

LLVM/project 905f654lld/ELF Relocations.cpp SyntheticSections.h, lld/ELF/Arch X86_64.cpp Mips.cpp

[ELF] Replace getThreadIndex with explicit shards in RelocScan. NFC (#208959)

Parallel relocation scanning (https://reviews.llvm.org/D133003) appends
dynamic relocations to `relocsVec[parallel::getThreadIndex()]`.
`getThreadIndex` returns -1u on main, which is a known hazard.

Instead, run one scan task per worker via `parallelFor`, with tasks
claiming object files off a shared counter, and pass the task index
through scanSection/RelocScan as the relocsVec shard.
DeltaFile
+38-44lld/ELF/Relocations.cpp
+18-30lld/ELF/SyntheticSections.h
+11-7lld/ELF/RelocScan.h
+9-7lld/ELF/Arch/X86_64.cpp
+9-7lld/ELF/Arch/Mips.cpp
+8-7lld/ELF/Arch/RISCV.cpp
+93-10210 files not shown
+167-16016 files

LLVM/project 63f4d28lld/ELF RelocScan.h, lld/test/ELF i386-tls-ie-shared.s

[ELF] Fix data race when handleTlsIe adds a RELATIVE relocation (#208956)

The ieExpr == R_GOT PIC case (e.g. R_386_TLS_IE in -shared links) calls
the unsynchronized addRelativeReloc from concurrent scanSectionImpl
tasks, racing on relaDyn->relativeRelocs. Use the sharded variant like
processAux. Split i386-tls-ie-shared.s into two input files so that a
ThreadSanitizer build detects the race.
DeltaFile
+54-62lld/test/ELF/i386-tls-ie-shared.s
+2-2lld/ELF/RelocScan.h
+56-642 files

LLVM/project c84e264llvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-v4-instructions.ll

[AArch64][GlobalISel] Add test coverage for bf16 fptosi.sat. NFC (#208955)
DeltaFile
+186-0llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+137-0llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+125-0llvm/test/CodeGen/AArch64/bf16-instructions.ll
+448-03 files

LLVM/project 5742a30llvm/test/CodeGen/AMDGPU buffer-fat-pointer-atomicrmw-fadd.ll atomic_optimizations_struct_buffer.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (8) (#208837)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+11-11llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+11-11llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
+11-11llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+11-11llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+10-10llvm/test/CodeGen/AMDGPU/bf16.ll
+10-10llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
+64-6490 files not shown
+301-30196 files

LLVM/project 8b1da8dllvm/lib/AsmParser LLParser.cpp, llvm/lib/Bitcode/Writer BitcodeWriter.cpp

fix

Created using spr 1.3.7
DeltaFile
+0-14llvm/lib/AsmParser/LLParser.cpp
+3-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+1-1llvm/test/Assembler/thinlto-bad-summary-5.ll
+4-163 files

LLVM/project 030fdcellvm/lib/Transforms/Vectorize VPlanHelpers.h LoopVectorize.cpp

[VPlan] Re-use VPSlotTracker when printing recipes for costs (NFC). (#203386)

VPRecipeBase::dump() constructs a fresh VPSlotTracker instance on each
call. VPSlotTracker construction requires iterating over all recipes in
the plan, to number all VPValues.

To avoid doing lots of unnecessary work when printing VPlan costs,
construct a shared VPSlotTracker in VPCostContext, re-used by all
prints.

This can speed up debug output for large loops.

PR: https://github.com/llvm/llvm-project/pull/203386
DeltaFile
+19-2llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+5-3llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+6-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+30-63 files

LLVM/project 1cdd33allvm/lib/AsmParser LLParser.cpp, llvm/test/Assembler thinlto-bad-summary-5.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+14-0llvm/lib/AsmParser/LLParser.cpp
+11-0llvm/test/Assembler/thinlto-bad-summary-5.ll
+25-02 files

LLVM/project 0979680llvm/lib/Transforms/Vectorize VPlan.h

[VPlan] Remove dead member functions (NFC) (#208936)

Remove member functions with no remaining callers anywhere in the tree:

 - VPExpressionRecipe::getOperandOfResultType
- VPBlockBase::getSingleHierarchicalSuccessor
 - VPIRFlags::hasNonNegFlag
- VPWidenIntOrFpInductionRecipe::getStartValue, which is an exact
duplicate of the inherited VPWidenInductionRecipe::getStartValue.
DeltaFile
+0-20llvm/lib/Transforms/Vectorize/VPlan.h
+0-201 files

LLVM/project 6e01e73libcxx/utils/ci/images libcxx_runners.txt

[libcxx] Bump runner set (#208929)

This pulls in 6d3cf7f436a01f4622fb660e413a4020209777b8, and
8ece73c9f8b54fea6a98e9e4c55f9a2e6ccc9b3c.
DeltaFile
+1-1libcxx/utils/ci/images/libcxx_runners.txt
+1-11 files