LLVM/project d027cacflang/lib/Optimizer/Support Utils.cpp, flang/test/Fir logical-convert.fir convert-to-llvm-openmp-and-fir.fir

[fir] Lower to llvm int constants with appropriately typed int attrs (#195861)

When we lower fir operations to llvm int constants, we used to always
generate `llvm.mlir.constant`s with a i64 integer attribute regardless
of the width of the constant type. This made some llvm dialect level
folding hit assertions in some cases.

Fix this by generating the appropriately typed integer attributes
matching the constant type.
DeltaFile
+46-46flang/test/Fir/logical-convert.fir
+5-5flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
+2-2flang/test/Fir/convert-to-llvm.fir
+1-1flang/test/Fir/tbaa.fir
+1-1flang/test/Fir/global-initialization.fir
+1-1flang/lib/Optimizer/Support/Utils.cpp
+56-566 files

LLVM/project 8513771clang/include/clang/Analysis/Analyses/LifetimeSafety Origins.h, clang/lib/Analysis/LifetimeSafety Origins.cpp FactsGenerator.cpp

[LifetimeSafety] Track per-field origins for record types
DeltaFile
+237-4clang/test/Sema/warn-lifetime-safety.cpp
+82-8clang/lib/Analysis/LifetimeSafety/Origins.cpp
+59-24clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
+47-13clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+21-12clang/lib/Analysis/LifetimeSafety/LiveOrigins.cpp
+4-6clang/test/Sema/warn-lifetime-safety-dangling-field.cpp
+450-672 files not shown
+455-678 files

LLVM/project 1b6cc52clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip

[CIR][AMDGPU] Add lowering for amdgcn ds swizzle builtin.
DeltaFile
+10-1clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+18-12 files

LLVM/project b197418lld/test/ELF why-live.test

[ELF,test] Cover --why-live mark() paths in MarkLive (#196007)

Add cases that exercise the non-parallel mark() loop reached only when
TrackWhyLive is true: cNamedSections.lookup in resolveReloc
(__libc_atexit
via __start_/__stop_), the nextInSectionGroup fallthrough, and the
.eh_frame personality CIE relocation processed by scanEhFrameSection.

MarkLive.cpp coverage on check-lld-elf goes 90.88% -> 92.18% regions,
84.15% -> 86.04% branches.
DeltaFile
+59-0lld/test/ELF/why-live.test
+59-01 files

LLVM/project 95aecf0clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/Lowering fmv-features.cir

use interleaveComma and features.reserve
DeltaFile
+35-0clang/test/CIR/Lowering/fmv-features.cir
+6-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+41-32 files

LLVM/project 3053a3cmlir/lib/Dialect/XeGPU/Transforms XeGPULayoutImpl.cpp, mlir/test/Dialect/XeGPU xegpu-wg-to-sg.mlir sg-to-wi-experimental-unit.mlir

[MLIR][XeGPU] Clean up the temporary layout usage in XeGPU test (#195739)

This PR cleans up the XeGPU test to remove the temporary layout usage.
All distribution and unrolling tests now don't use temporary layout from
the operation and TensorDescriptor, since the recovery process won't
honor the temporary layout and only depends on the anchor layout.
It also refactors the layout function implementation by removing
recursive loops in getDistributeLayoutAttr(), and fixes two issues
surfaced from the test clean up: adding layout recovery support for
Extract/Insert op and tensor descriptor type.
DeltaFile
+314-171mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
+106-217mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+165-42mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+84-95mlir/test/Dialect/XeGPU/sg-to-wi-experimental.mlir
+102-58mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
+75-85mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir
+846-6688 files not shown
+935-73014 files

LLVM/project cb15e67llvm/docs LoopFusion.rst Passes.rst

[LoopFusion] Document LoopFusion Pass (#192926)

The LoopFusion pass, currently disabled by default, lacks documentation. This patch is the first attempt to document the flow and current limitations.

Assisted by : Claude Opus 4.6
DeltaFile
+442-0llvm/docs/LoopFusion.rst
+7-0llvm/docs/Passes.rst
+449-02 files

LLVM/project 9b0d277llvm/lib/CodeGen/LiveDebugValues VarLocBasedImpl.cpp

[LiveDebugValues] Avoid SmallSet for dead registers (#195841)

transferRegisterDef builds a list of dead registers and removes open ranges for
debug locations that use those registers. This list used a SmallSet, so each
insert also does uniquing in the hot per-instruction path. This showed up under
SmallSet<Register, 32>::insertImpl on profiles of sqlite on aarch64-O0-g.

Using a SmallVector instead and uniquing in collectIDsForRegs improves
compile-time.

CTMark geomean:
- stage1-O0-g: -0.35%
- stage1-aarch64-O0-g: -0.72%
- stage2-O0-g: -0.27%

https://llvm-compile-time-tracker.com/compare.php?from=c9d713aa48a714d20b8502d06b9feb24829e6f22&to=6c0d4aafb9e325259c88577d148ac13c643ea993&stat=instructions%3Au

Assisted-by: codex
DeltaFile
+8-9llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+8-91 files

LLVM/project d97c568clang/test/Analysis/Scalable/ssaf-analyzer analyzer.test, clang/test/Analysis/Scalable/ssaf-analyzer/Inputs lu.json

Revert "[clang][ssaf] Add `clang-ssaf-analyzer` (#188881)" (#195993)

This reverts commit 51d2a66d52a95beeb31de81dd819c603062a5770 introduced by PR https://github.com/llvm/llvm-project/pull/188881 because of an HWSan failure.
DeltaFile
+0-141clang/test/Analysis/Scalable/ssaf-analyzer/analyzer.test
+0-134clang/tools/clang-ssaf-analyzer/SSAFAnalyzer.cpp
+0-126clang/test/Analysis/Scalable/ssaf-analyzer/Inputs/lu.json
+0-90clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/all.json
+0-81clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/both.json
+0-70clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/pairs.json
+0-64215 files not shown
+0-93121 files

LLVM/project dfb8d68llvm/include/llvm/CodeGen RegAllocEvictionAdvisor.h, llvm/lib/CodeGen RegAllocEvictionAdvisor.cpp RegAllocGreedy.cpp

[RegAlloc] consider urgent evict in evictInterference (#192631)

This assertion causes a crash in programs with high register pressure
when inline assembly is used.

```
    assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||
            VirtReg.isSpillable() < Intf->isSpillable()) &&
           "Cannot decrease cascade number, illegal eviction");
```

It should account for the case where an urgent eviction may result in
cascade being less than `ExtraInfo->getCascade(Intf->reg())`

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+17-12llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
+17-0llvm/test/CodeGen/RISCV/regalloc-greedy-urgent-evict.ll
+4-0llvm/include/llvm/CodeGen/RegAllocEvictionAdvisor.h
+2-0llvm/lib/CodeGen/RegAllocGreedy.cpp
+40-124 files

LLVM/project d6a1064clang/test/CIR/Transforms mem2reg.cir

[CIR][NFC] Upstream mem2reg.cir from incubator (#194517)

Upstream `mem2reg.cir` from incubator.

Check that stack slots are promoted away after CFG flattening.

Partially addresses #156747.
DeltaFile
+23-0clang/test/CIR/Transforms/mem2reg.cir
+23-01 files

LLVM/project 5f72b7cllvm/docs AMDGPUUsage.rst, llvm/docs/AMDGPU DeveloperGuideline.rst

[NFC][AMDGPU][Doc] Add developer guideline

This guideline covers topics on top of existing LLVM guideline.
DeltaFile
+442-0llvm/docs/AMDGPU/DeveloperGuideline.rst
+1-0llvm/docs/AMDGPUUsage.rst
+443-02 files

LLVM/project 7df4736clang/lib/CIR/CodeGen CIRGenBuiltinRISCV.cpp, clang/test/CIR/CodeGenBuiltins/RISCV riscv-zbkb.c

[CIR][RISCV] Support zbkb builtin codegen (#195401)

Include 4 builtins: __builtin_riscv_brev8_32, __builtin_riscv_brev8_64,
__builtin_riscv_zip_32, __builtin_riscv_unzip_32.
DeltaFile
+50-0clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zbkb.c
+12-3clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+62-32 files

LLVM/project 36122ebllvm/lib/Target/RISCV RISCVCallingConv.cpp

[RISCV] Rename and invert UseGPRForF16_F32/UseGPRForF16_F32. (#195971)

Rename to AllowFPR. We used to set these flags when we ran out of FPRs,
but we haven't for a while. I think rephrasing as allow FPR is a bit
clearer.
DeltaFile
+13-15llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+13-151 files

LLVM/project 9dd7c73llvm/lib/Target/RISCV RISCVInstrInfoP.td

[RISCV][P-ext] Remove VXSAT from SHL/SHLR/SHA/SHAR. Add to PSAS and PSSA. (#195488)
DeltaFile
+10-8llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+10-81 files

LLVM/project 6201b4ebolt/include/bolt/Profile DataAggregator.h DataReader.h, bolt/lib/Profile DataAggregator.cpp DataReader.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4
DeltaFile
+18-55bolt/lib/Profile/DataAggregator.cpp
+1-13bolt/include/bolt/Profile/DataAggregator.h
+9-0bolt/include/bolt/Profile/DataReader.h
+4-0bolt/lib/Profile/DataReader.cpp
+32-684 files

LLVM/project 2e4c72ellvm/docs CodingStandards.rst

[RFC][Docs] Clarify brace omission for single-line bodies

Update the Coding Standards brace guidance to emphasize that braces should be
omitted only for simple bodies that do not wrap across multiple physical lines.
DeltaFile
+22-9llvm/docs/CodingStandards.rst
+22-91 files

LLVM/project d4c0c7bllvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV returnaddress.ll

[SPIRV] Dummy implementation of the `returnaddress` and `frameaddress` intrinsics (#195976)

The SPIR-V specification doesn't define any operations for the
return and frame address. The valid implementation in this case is to
produce a null pointer.

Assisted-by: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+26-0llvm/test/CodeGen/SPIRV/returnaddress.ll
+9-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+35-02 files

LLVM/project 75428e9llvm/lib/Target/SPIRV SPIRVPrepareFunctions.cpp SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort abort-opencl-source.ll abort-post-terminator-suppression.ll

[SPIRV] Add support for SPV_KHR_abort extension (#193037)

This commit adds support for the SPV_KHR_abort extension in the SPIRV
backend. The extension allows shaders to abort execution with a custom
message.

Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>

---------

Co-authored-by: Marcos Maronas <mmaronas at amd.com>
DeltaFile
+113-2llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+91-5llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+81-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-opencl-source.ll
+68-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-post-terminator-suppression.ll
+62-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-opencl.ll
+59-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/no-abort-unaffected.ll
+474-724 files not shown
+1,178-1130 files

LLVM/project a8b0124llvm/include/llvm/TargetParser RISCVTargetParser.h, llvm/lib/Target/RISCV RISCVInstrInfoZvvmm.td

[RISCV][MC] Add experimental `Zvvmm` MC support (#193956)

Add initial MC-layer support for `Zvvmm` from the experimental [RISC-V
Integrated Matrix
Extension](https://github.com/riscv/integrated-matrix-extension/blob/d2e64b4922f5c2c416761f3c7c997d4f0cf814d9/src/integrated-matrix.adoc)
(version
[2026-04-23](https://github.com/riscv/integrated-matrix-extension/releases/tag/riscv-isa-release-d2e64b4-2026-04-23))

This patch:
- Adds the experimental `zvvmm` 0.1 extension feature, depending on
`zve32x`.
- Adds assembler/disassembler definitions for the integer matrix
multiply-accumulate instructions:
  - `vmmacc.vv`
  - `vwmmacc.vv`
  - `vqmmacc.vv`
  - `v8wmmacc.vv`
- Adds IME vtype helper modeling in `RISCVVType`, covering lambda
encoding/decoding, IME vtype field masks,

    [3 lines not shown]
DeltaFile
+89-0llvm/lib/TargetParser/RISCVTargetParser.cpp
+49-0llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+37-0llvm/lib/Target/RISCV/RISCVInstrInfoZvvmm.td
+29-0llvm/include/llvm/TargetParser/RISCVTargetParser.h
+27-0llvm/test/MC/RISCV/rvv/zvvmm.s
+18-0llvm/test/MC/RISCV/rvv/zvvmm-invalid.s
+249-07 files not shown
+266-113 files

LLVM/project d9958cbmlir/lib/Dialect/AMDGPU/Transforms FoldMemRefsOps.cpp, mlir/test/Dialect/AMDGPU amdgpu-fold-memrefs.mlir

fold memref global async to lds

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

nits

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+50-0mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
+40-0mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
+90-02 files

LLVM/project f5186aemlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

format

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+5-2mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+5-21 files

LLVM/project e1ee69bmlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

nit

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+2-2mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+2-21 files

LLVM/project 51d2a66clang/test/Analysis/Scalable/ssaf-analyzer analyzer.test, clang/test/Analysis/Scalable/ssaf-analyzer/Inputs lu.json

[clang][ssaf] Add `clang-ssaf-analyzer` (#188881)

This patch introduces `clang-ssaf-analyzer`, a new SSAF tool that runs whole-program analyses over an `LUSummary` and writes the resulting `WPASuite` to an output file.
DeltaFile
+141-0clang/test/Analysis/Scalable/ssaf-analyzer/analyzer.test
+134-0clang/tools/clang-ssaf-analyzer/SSAFAnalyzer.cpp
+126-0clang/test/Analysis/Scalable/ssaf-analyzer/Inputs/lu.json
+90-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/all.json
+81-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/both.json
+70-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/pairs.json
+642-015 files not shown
+931-021 files

LLVM/project d724231mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp, mlir/test/Conversion/AMDGPUToROCDL sparse-mfma-gfx950.mlir

support gfx942 bf16 sparse mfma in gfx950

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+7-5mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+10-1mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
+17-62 files

LLVM/project b8362b2clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowExtractor.cpp

[SSAF] Fix -Wunused-variable (#195975)

Add [[maybe_unused]] given the operation is side effecting/returns
multiple values.
DeltaFile
+1-1clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
+1-11 files

LLVM/project 2c27433libc/include sched.yaml, libc/test/include sched_test.cpp

[libc][sched] Fix generated scheduler prototypes (#195332)

Fixes generated <sched.h> prototypes for
sched_getscheduler/sched_setscheduler and adds compile-time
public-header coverage
DeltaFile
+8-0libc/test/include/sched_test.cpp
+2-2libc/include/sched.yaml
+10-22 files

LLVM/project 289bef6llvm/include/llvm/MC MCPseudoProbe.h, llvm/lib/MC MCPseudoProbe.cpp MCObjectFileInfo.cpp

[PseudoProbe] Include function hash in descriptor COMDAT key (#190296)

The .pseudo_probe_desc section uses COMDAT to deduplicate descriptors
for the same function across translation units. On COFF, the COMDAT key
is uniquely determined by the function name. The COMDAT selection type
is EXACT_MATCH, which requires byte-identical content. This holds for
applications that strictly follow C/C++ ODR rules.

Unfortunately, we consistently observe .pseudo_probe_desc COMDAT
duplicate symbol errors on Windows (see also #177540). Most of them are
due to hash mismatches, meaning two non-internal functions with the same
name but different bodies — a violation of ODR rules. Some of these
functions are generated by the compiler (e.g., TU-local optimizations
that alter the CFG of a linkonce_odr function), and some are caused by
source code issues (e.g., different preprocessor settings or
optimization pragmas across TUs).

It is hard to fix all of them, but they seriously affect the user
experience of using pseudo probe on Windows due to the endless COFF

    [12 lines not shown]
DeltaFile
+101-0llvm/test/tools/llvm-profgen/pseudo-probe-desc-mismatch.test
+27-2llvm/lib/MC/MCPseudoProbe.cpp
+14-14llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
+17-10llvm/lib/MC/MCObjectFileInfo.cpp
+12-12llvm/test/Transforms/SampleProfile/pseudo-probe-emit-inline.ll
+2-1llvm/include/llvm/MC/MCPseudoProbe.h
+173-394 files not shown
+179-4310 files

LLVM/project 2d7bfcdlld/ELF/Arch TargetImpl.h

ELF: Use dyn_cast to access sym field.

dyn_cast_or_null is unnecessary because this field is non-null.

Reviewers: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/195785
DeltaFile
+1-1lld/ELF/Arch/TargetImpl.h
+1-11 files

LLVM/project 2384593mlir/lib/Dialect/XeGPU/IR XeGPUOps.cpp, mlir/lib/Dialect/XeGPU/Transforms XeGPUUnroll.cpp XeGPUBlocking.cpp

[MLIR][XeGPU] Unroll Dpasmx Op (#195179)

This PR adds support to unroll Dpasmx. 

Assisted by Claude

---------

Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
DeltaFile
+164-47mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+110-39mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
+117-9mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
+92-9mlir/test/Dialect/XeGPU/invalid.mlir
+48-0mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
+32-2mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
+563-1061 files not shown
+589-1067 files