LLVM - FreshBSD

LLVM/project d7d7992 — llvm/test/tools/llubi fp_cast.ll, llvm/tools/llubi/lib Interpreter.cpp

2026-09-12 16:52:54 UTC by Zhige Chen via GitHub on ⎇

main

[llubi] Implement fast-math flags for `uitofp`/`sitofp` (#222858)

Closes #203773

Delta		File
+39	-0	llvm/test/tools/llubi/fp_cast.ll
+3	-1	llvm/tools/llubi/lib/Interpreter.cpp
+42	-1	2 files

LLVM/project 345d699 — llvm/include/llvm/CodeGen SelectionDAG.h, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

2026-09-12 16:51:09 UTC by Kazu Hirata via GitHub on ⎇

main

[SelectionDAG] Remove dead functions and declarations (NFC) (#223126)

SelectionDAG::getStore (with Offset): Added on July 31, 2026 in commit
c57b2b6103cb4bb6c4c2bee901c1eee2b966e5f0 without a definition or any
callers.

SelectionDAG::getIndexedLoadVP, SelectionDAG::getIndexedStoreVP: Added
on August 31, 2021 in commit 524ded7d01a700aa6473d09a877be13fe45b85a3
without any callers.

SelectionDAG::getTruncStridedStoreVP: Added on March 10, 2022 in commit
28cfa764c2e3d36b856b3e70d49f17088b90c1f5 without any callers.

Assisted-by: Antigravity

Delta		File
+0	-95	llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+0	-15	llvm/include/llvm/CodeGen/SelectionDAG.h
+0	-110	2 files

LLVM/project b8d9565 — clang/include/clang/AST DeclBase.h, clang/lib/AST DeclBase.cpp

2026-09-12 16:05:35 UTC by Mehdi Amini on ⎇

users/mamini/clang-speed-declcontext-relationship-cache

[Clang] Do not imply concurrent AST traversal support

Delta		File
+5	-10	clang/include/clang/AST/DeclBase.h
+2	-2	clang/lib/AST/DeclBase.cpp
+7	-12	2 files

LLVM/project e1b6027 — llvm/test/Transforms/LoopVectorize induction-cost.ll

2026-09-12 16:01:51 UTC by Florian Hahn via GitHub on ⎇

main

[LV] Add test for cost of widened pointer induction (NFC). (#223153)

Add a cost test where the pointer induction is used as a value and
remains a VPWidenPointerInductionRecipe.

PR: https://github.com/llvm/llvm-project/pull/223153

Delta		File
+45	-0	llvm/test/Transforms/LoopVectorize/induction-cost.ll
+45	-0	1 files

LLVM/project 66573c1 — llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Analysis/ScalarEvolution pointer-iv-addrec.ll

2026-09-12 15:59:43 UTC by Florian Hahn via GitHub on ⎇

main

[SCEV] Directly form add recurrences for simple pointer IVs. (#222915)

Add support for PN = PHI(Start, gep Self, LoopInvariant) to
createSimpleAffineAddRec.

This allows to handle simple pointer IVs without going through the more
expensive createAddRecFromPHI machinery in many cases.

This is not completely NFC: previously we created SCEVUnknown for a
trivial AddRec with step 0, now we return the start value.

This gives a modest geomean compile-time decrease
 * stage1-O3: -0.05%
 * stage1-ReleaseThinLTO: -0.06%
 * stage1-ReleaseLTO-g: -0.06%
 * stage1-aarch64-O3: -0.07%
 * stage2-O3: -0.05%
 * clang build: -0.08%


    [4 lines not shown]

Delta		File
+343	-0	llvm/test/Analysis/ScalarEvolution/pointer-iv-addrec.ll
+51	-32	llvm/lib/Analysis/ScalarEvolution.cpp
+394	-32	2 files

LLVM/project 25b15dd — llvm/lib/Transforms/Scalar LICM.cpp, llvm/test/Transforms/LICM promote-single-thread.ll

2026-09-12 15:41:43 UTC by Matt Arsenault on ⎇

users/arsenm/thread-model/licm-drop-force-single-opt

LICM: Drop -licm-force-thread-model-single in favor of the module flag

Now that the threading model is carried by the "thread-model" IR module flag,
the hidden -licm-force-thread-model-single override is redundant: a test can
select the single-threaded model by setting the module flag directly.
isThreadLocalObject reads only Module::getThreadModel.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+9	-2	llvm/test/Transforms/LICM/promote-single-thread.ll
+1	-5	llvm/lib/Transforms/Scalar/LICM.cpp
+10	-7	2 files

LLVM/project 6c4e42e — clang/lib/CodeGen BackendUtil.cpp, llvm/lib/CodeGen CommandFlags.cpp AtomicExpandPass.cpp

2026-09-12 15:40:33 UTC by Matt Arsenault on ⎇

users/arsenm/thread-model/consume-module-flag

CodeGen: Replace TargetOptions::ThreadModel with module flag

Migrate the threading-model consumers off TargetOptions::ThreadModel and onto
the "thread-model" module flag. The main user was ARM's pass config, which is
moved into AtomicExpand, which now performs the single-thread expansion
directly.

Few tests use the -thread-model flag, so delete it and migrate those cases
to use the module flag.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+138	-0	llvm/test/Transforms/AtomicExpand/ARM/thread-model-single.ll
+47	-1	llvm/lib/CodeGen/AtomicExpandPass.cpp
+13	-5	llvm/test/CodeGen/ARM/atomic-op.ll
+11	-6	llvm/lib/Transforms/Scalar/LICM.cpp
+0	-11	llvm/lib/CodeGen/CommandFlags.cpp
+0	-8	clang/lib/CodeGen/BackendUtil.cpp
+209	-31	7 files not shown
+210	-54	13 files

LLVM/project 0adddbb — clang/lib/AST/ByteCode Interp.h Interp.cpp

2026-09-12 15:30:24 UTC by Timm Baeder via GitHub on ⎇

main

[clang][bytecode][NFC] Move Remove unused CheckExtern prototype (#223146)

And add an overload taking only a Block.

Delta		File
+8	-2	clang/lib/AST/ByteCode/Interp.cpp
+0	-3	clang/lib/AST/ByteCode/Interp.h
+8	-5	2 files

LLVM/project b86db22 — libcxx/docs conf.py, libcxx/docs/ReleaseNotes 24.rst 23.rst

2026-09-12 15:29:48 UTC by Reid Kleckner on ⎇

users/rnk/libcxx-furo

[libc++][docs] Use Furo theme

Adopt the shared LLVM Furo configuration and wyvern logo, widen the content area on desktop viewports, and remove page-local contents directives that duplicate Furo's navigation.

Delta		File
+8	-17	libcxx/docs/conf.py
+20	-0	libcxx/docs/_static/custom.css
+0	-4	libcxx/docs/ReleaseNotes/24.rst
+0	-4	libcxx/docs/ReleaseNotes/23.rst
+0	-4	libcxx/docs/ReleaseNotes/22.rst
+0	-4	libcxx/docs/ReleaseNotes/21.rst
+28	-33	16 files not shown
+28	-83	22 files

LLVM/project 73cbde9 — libcxx/docs/Status Cxx26Issues.csv

2026-09-12 15:29:47 UTC by Reid Kleckner on ⎇

users/rnk/libcxx-featgen-rewrite

[libc++][docs] Preserve updated Cxx26 issue status

Carry the completed libc++24 status for LWG4013 through the generated-table Markdown conversion.

Delta		File
+1	-1	libcxx/docs/Status/Cxx26Issues.csv
+1	-1	1 files

LLVM/project 1ae00a5 — libc/src/__support/FPUtil float80.h

2026-09-12 15:22:45 UTC by Zorojuro via GitHub on ⎇

main

[libc] Enable Float80-type for x86_32 (#221408)

Enables for x86_32 by using Uint<96> 
```CPP
struct Float80 {
  #if __SIZEOF_LONG_DOUBLE__ == 12
    UInt<96> bits;
  #else
    UInt128 bits;
  #endif
 ```
for testing it on x86_32 
it needs -m32 and --msse2 extra flags other than your usual cmake for x86_32

Delta		File
+4	-1	libc/src/__support/FPUtil/float80.h
+4	-1	1 files

LLVM/project 0070802 — flang/docs Unsigned.md Semantics.md, flang/docs/_static custom.css

2026-09-12 14:29:18 UTC by Reid Kleckner on ⎇

users/rnk/flang-furo

[flang][docs] Use Furo theme

Adopt the shared LLVM Furo configuration and wyvern logo, widen the content area on desktop viewports, and remove page-local contents directives that duplicate Furo's navigation.

Delta		File
+8	-17	flang/docs/conf.py
+20	-0	flang/docs/_static/custom.css
+0	-5	flang/docs/Unsigned.md
+0	-5	flang/docs/Semantics.md
+0	-5	flang/docs/RuntimeTypeInfo.md
+0	-5	flang/docs/RuntimeEnvironment.md
+28	-37	41 files not shown
+28	-240	47 files

LLVM/project baa2354 — clang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGen thread-model.c

2026-09-12 14:22:16 UTC by Matt Arsenault on ⎇

users/arsenm/thread-model/clang-emit

clang: Emit the "thread-model" module flag

Emit the threading model as the "thread-model" IR module flag. This
will eventually replace the TargetOptions field.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+11	-0	clang/test/CodeGen/thread-model.c
+9	-0	clang/lib/CodeGen/CodeGenModule.cpp
+20	-0	2 files

LLVM/project e234b05 — llvm/lib/CodeGen CommandFlags.cpp, llvm/test/CodeGen/AArch64 aarch64-p2align-max-bytes-neoverse.ll aarch64-p2align-max-bytes.ll

2026-09-12 13:56:08 UTC by Matt Arsenault on ⎇

users/arsenm/codegen/remove-targetoptions-loopalignment

CodeGen: Remove TargetOptions::LoopAlignment

Delete the module-wide LoopAlignment override and llc's -align-loops
flag that fed it. Loop alignment is now expressed solely through
per-loop llvm.loop.align metadata.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Delta		File
+135	-5	llvm/test/CodeGen/X86/innermost-loop-alignment.ll
+40	-16	llvm/test/CodeGen/RISCV/align-loops.ll
+2	-25	llvm/test/CodeGen/X86/code-align-loops.ll
+9	-6	llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
+0	-6	llvm/lib/CodeGen/CommandFlags.cpp
+0	-3	llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
+186	-61	4 files not shown
+188	-69	10 files

LLVM/project 0358146 — clang/lib/CodeGen BackendUtil.cpp CGLoopInfo.cpp, clang/test/CodeGen align-loops.c

2026-09-12 13:56:02 UTC by Matt Arsenault on ⎇

users/arsenm/clang/falign-loops-emit-metadata

clang: Emit llvm.loop.align metadata for -falign-loops

Make -falign-loops=N attach per-loop llvm.loop.align metadata instead
of setting the module-wide TargetOptions::LoopAlignment. This reuses
the existing [[clang::code_align]] metadata path, with the source
attribute taking precedence over the flag.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Delta		File
+31	-6	clang/test/CodeGen/align-loops.c
+4	-0	clang/lib/CodeGen/CGLoopInfo.cpp
+0	-1	clang/lib/CodeGen/BackendUtil.cpp
+35	-7	3 files

LLVM/project 7c3884e — lldb/source/ValueObject DILEval.cpp, lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression TestCreateValueFromExpression.py

2026-09-12 13:18:37 UTC by Ilia Kuklin on ⎇

users/kuilpd/DIL-fix-ptr-cast-ctx

[lldb] Fix DIL losing StackFrame context after casting to pointer

Delta		File
+16	-9	lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/TestCreateValueFromExpression.py
+3	-5	lldb/source/ValueObject/DILEval.cpp
+19	-14	2 files

LLVM/project 641cbed — lldb/source/API SBExpressionOptions.cpp

2026-09-12 13:07:59 UTC by Ilia Kuklin on ⎇

users/kuilpd/use-DIL-in-create-variable-from-expr

Remove unused return

Delta		File
+1	-1	lldb/source/API/SBExpressionOptions.cpp
+1	-1	1 files

LLVM/project 5eff11f — orc-rt/include/orc-rt/bedrock/sps SimpleRemoteCA.h, orc-rt/lib/bedrock/sps SimpleRemoteCA.cpp

2026-09-12 12:22:12 UTC by Lang Hames via GitHub on ⎇

main

[orc-rt] Reduce SimpleRemoteCA to transport-independent utils (#223141)

Reduce SimpleRemoteCA to the transport-independent parts: opcodes, setup
and hang-up payload encoding, message validation and dispatch, and the
table of calls awaiting a result. Subclasses are now responsible for the
connection state and synchronization, since they'll usually want to
implement these things for their transports anyway (or the transport
will already manage connection-state/synchronization).

takePendingCall becomes pure virtual, since subclasses must synchronize
access to the pending-call table.

The header moves from orc-rt-internal/ to orc-rt/: with the transport a
subclass concern, there's no reason to preclude library clients from
writing one.

Delta		File
+110	-364	orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
+54	-127	orc-rt/lib/bedrock/sps/SimpleRemoteCA.cpp
+76	-102	orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCA.h
+240	-593	3 files

LLVM/project 3569a1f — llvm/lib/Target/AMDGPU AMDGPU.td

2026-09-12 11:55:30 UTC by Shilei Tian via GitHub on ⎇

main

[AMDGPU] Fix placement of FeatureSupportsXNACK (#223111)

This can't be put into 12_50_Common because of conflict in downstream
code.

Delta		File
+4	-1	llvm/lib/Target/AMDGPU/AMDGPU.td
+4	-1	1 files

LLVM/project d411212 — llvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVISelLowering.cpp, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

2026-09-12 11:13:09 UTC by Jesse Huang via GitHub on ⎇

main

[RISCV] Add PseudoTAILX7, PseudoTAILReg for cf-protection-branch (#220657)

Previously, PseudoTAIL selected between X6 and X7 at encode time by
checking the Zicfilp feature bit via getTailExpandUseRegNo. This is
incorrect for the codegen path because -fcf-protection=branch can emit
lpad without requiring Zicfilp to be enabled.

Add PseudoTAILX7 for codegen: when cf-protection-branch is active,
ISelLowering and the machine outliner now emit PseudoTAILX7 which
always expands using X7. The existing PseudoTAIL behavior is unchanged
— it still selects X6 or X7 based on Zicfilp at encode time, as
documented in the assembler manual.

Also add PseudoTAILReg ("tail address, register") assembly form that
lets users explicitly specify the scratch register for AUIPC+JALR
expansion, per the proposed syntax in
https://github.com/riscv-non-isa/riscv-asm-manual/pull/227.

Delta		File
+37	-0	llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+35	-1	llvm/lib/Target/RISCV/RISCVInstrInfo.td
+13	-13	llvm/test/CodeGen/RISCV/tail-calls.ll
+15	-10	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+18	-3	llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+15	-0	llvm/test/MC/RISCV/tail-call.s
+133	-27	4 files not shown
+159	-34	10 files

LLVM/project 2706780 — llvm/include/llvm/IR PatternMatch.h, llvm/lib/Transforms/InstCombine InstCombineSelect.cpp

2026-09-12 10:46:34 UTC by Andreas Jonson via GitHub on ⎇

main

[InstCombine] support trunc condition in foldSelectICmpAndAnd (#223132)

Reland https://github.com/llvm/llvm-project/pull/220690 with the fix for
asan failure see fixup commit

Delta		File
+101	-11	llvm/test/Transforms/InstCombine/select-of-bittest.ll
+39	-25	llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+11	-0	llvm/include/llvm/IR/PatternMatch.h
+151	-36	3 files

LLVM/project e17b8cb — llvm/docs LangRef.md, llvm/include/llvm/IR Module.h

2026-09-12 10:39:07 UTC by Matt Arsenault via GitHub on ⎇

main

IR: Introduce "thread-model" module flag (#222768)

Introduce the replacement for TargetOptions::ThreadModel, but
does not yet wire up the uses. This maintains the current values,
but I question if it makes sense to retain "posix" as the default.
POSIX sounds very target opinionated, but isn't used in a non-binary
way anywhere. Alternatively we could have a simple singlethread binary
flag, or name this something more general.

Follows the precedent of float-abi. It happens the triple default
is just POSIX, but theoretically targets like AVR should be defaulting
to singlethread.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+37	-0	llvm/test/Verifier/module-flags-thread-model.ll
+29	-0	llvm/docs/LangRef.md
+29	-0	llvm/test/Linker/module-flags-thread-model.ll
+28	-0	llvm/include/llvm/Support/CodeGen.h
+13	-0	llvm/test/Assembler/module-flags-thread-model.ll
+12	-0	llvm/include/llvm/IR/Module.h
+148	-0	7 files not shown
+184	-14	13 files

LLVM/project cad1b33 — libc/cmake/modules LLVMLibCArchitectures.cmake

2026-09-12 10:08:31 UTC by lntue via GitHub on ⎇

main

[libc] Pass correct system include flag for macOS. (#223116)

Delta		File
+1	-1	libc/cmake/modules/LLVMLibCArchitectures.cmake
+1	-1	1 files

LLVM/project 25728f8 — llvm/lib/CodeGen MachineScheduler.cpp, llvm/test/CodeGen/AArch64 misched-postra-only1.mir

2026-09-12 08:20:24 UTC by Tomer Shafir via GitHub on ⎇

main

[MISched] Fix post-RA pickOnlyChoice debug logs (#222927)

On the way, adding a stable test for `pickOnlyChoice()` scheduling paths
directly, which has been missing, while filechecking the fixed tracing.

Delta		File
+114	-0	llvm/test/CodeGen/AArch64/misched-postra-only1.mir
+1	-1	llvm/lib/CodeGen/MachineScheduler.cpp
+115	-1	2 files

LLVM/project 1f13035 — libcxx/docs/Status Cxx26Issues.csv, libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop has_unique_object_representations.verify.cpp

2026-09-12 08:08:53 UTC by A. Jiang via GitHub on ⎇

main

[libc++] Test LWG4113: Disallow `has_unique_object_representations<Incomplete[]>` (#169446)

We have been rejecting `has_unique_object_representations<Incomplete[]>`
since LLVM 6.

Some related change landed in Clang 19 due to
6451806ef73bb033be3f6e1599f3bcb224943206, and then a follow-up change
ae9990ed965118e7274a52399b43e3b9fb419a54 simplified error messages.

Test coverage for incomplete enumeration types is skipped for Clang-cl
mode, because an incomplete enumeration type is incorrectly considered
to be complete. See https://llvm.org/PR169472.

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>

Delta		File
+48	-0	libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.verify.cpp
+1	-1	libcxx/docs/Status/Cxx26Issues.csv
+49	-1	2 files

LLVM/project 18bc801 — llvm/docs LangRef.md, llvm/include/llvm/IR Module.h

2026-09-12 07:26:16 UTC by Matt Arsenault on ⎇

users/arsenm/thread-model/introduce-module-flag

IR: Introduce "thread-model" module flag

Introduce the replacement for TargetOptions::ThreadModel, but
does not yet wire up the uses. This maintains the current values,
but I question if it makes sense to retain "posix" as the default.
POSIX sounds very target opinionated, but isn't used in a non-binary
way anywhere. Alternatively we could have a simple singlethread binary
flag, or name this something more general.

Follows the precedents of float-abi. It happens the triple default
is just POSIX, but theoretically targets like AVR should be defaulting
to singlethread.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+37	-0	llvm/test/Verifier/module-flags-thread-model.ll
+29	-0	llvm/docs/LangRef.md
+29	-0	llvm/test/Linker/module-flags-thread-model.ll
+28	-0	llvm/include/llvm/Support/CodeGen.h
+13	-0	llvm/test/Assembler/module-flags-thread-model.ll
+12	-0	llvm/include/llvm/IR/Module.h
+148	-0	7 files not shown
+184	-14	13 files

LLVM/project cebfe6c — llvm/docs LangRef.md, llvm/lib/CodeGen MachineBlockPlacement.cpp

2026-09-12 07:22:47 UTC by Matt Arsenault via GitHub on ⎇

main

IR: Add verifier checks and LangRef for llvm.loop.align (#221933)

Verify the nested !{!"llvm.loop.align", i32 N} tag.
Require exactly two operands, an integer constant of type i32 or
smaller, and a positive power-of-two value

Co-authored-by: Claude (Claude-Opus-4.8)

Delta		File
+126	-0	llvm/test/Verifier/llvm.loop.align.ll
+28	-0	llvm/test/Assembler/llvm.loop.align.ll
+27	-0	llvm/lib/IR/Verifier.cpp
+15	-0	llvm/docs/LangRef.md
+0	-3	llvm/lib/CodeGen/MachineBlockPlacement.cpp
+196	-3	5 files

LLVM/project eff88db — clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVMOpenCLMetadata.h LowerToLLVM.cpp, clang/test/CIR/CodeGenHIP amdgcnspirv-kernel.hip

2026-09-12 07:21:54 UTC by Akimasa Watanuki via GitHub on ⎇

main

[CIR][OpenCL] Lower OpenCL language version metadata to LLVM dialect (#219689)

Propagate CIR OpenCL language version module attributes as LLVM dialect
named metadata before LLVM IR translation.

Assisted-by: Codex / GPT-5.6 Sol

Delta		File
+43	-0	clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.cpp
+16	-0	clang/test/CIR/CodeGenOpenCL/version.cl
+16	-0	clang/test/CIR/Lowering/opencl-version-metadata.cir
+3	-0	clang/test/CIR/CodeGenHIP/amdgcnspirv-kernel.hip
+2	-0	clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.h
+2	-0	clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+82	-0	6 files

LLVM/project b80b725 — llvm/lib/CodeGen RegisterCoalescer.cpp, llvm/test/CodeGen/AArch64 coalescer-empty-subrange-early-lis.ll

2026-09-12 07:21:12 UTC by Matt Arsenault on ⎇

users/arsenm/codegen/coalescer-remove-empty-subranges

RegisterCoalescer: Remove empty subranges after merging subranges

Merging subranges in joinVirtRegs didn't try to clear empty ranges after
refineSubRanges, manifesting in an assert in overlaps checks later.

Exposed with subregister liveness once LiveIntervals runs before TwoAddress.

Co-authored-by: Claude (Claude-Opus-4.8)

Delta		File
+30	-0	llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
+3	-0	llvm/lib/CodeGen/RegisterCoalescer.cpp
+33	-0	2 files

LLVM/project 7e01a10 — llvm/lib/CodeGen RegisterCoalescer.cpp

2026-09-12 07:21:12 UTC by Matt Arsenault on ⎇

users/arsenm/codegen/coalescer-remove-empty-subranges

Move removeEmptySubRanges into mergeSubRangeInto

Delta		File
+4	-3	llvm/lib/CodeGen/RegisterCoalescer.cpp
+4	-3	1 files