[libc][math] Extend iscanonical macro to _Float16 and float128
iscanonical is a C23 type-generic macro, so the f16/f128 variants are
surfaced through it rather than as functions in the generated math.h.
float128 is only listed when distinct from long double (LDBL_MANT_DIG !=
113) to avoid two _Generic associations with compatible types.
[flang][OpenMP] Move unique clauses to allowedOnceClauses in OMP.td
Many unique clauses were listed in "allowedClauses", which turned off
the single-occurrence check in flang. Move these clauses to the right
category to enable this check.
One exception to this is the IF clause: the IF clause is unique for
all non-compound directives, but is repeatable on compound ones with
the restriction that at most one IF clause can apply to any of the
constituents. This restriction is currently not enforced correctly
in flang, and so the IF clause was left unchanged.
Although this change is applied to a file shared between flang and
clang, clang does not use these categories for its checks, and hence
is not affected by this patch.
Revert "[Legalizer] Add support for promoting integers for s/ucmp (#198554) (#204978)
This reverts commit 91edd87a801fc5c9d12c7f5c6863edd50327cef8.
It was causing CI failures for Linux.
[ARM] Use lo tCMPr opcode when expanding CMP_SWAP (#204567)
We were always generating the tCMPhir even when the registers were both
low, which is an unpredictable instruction. Generating tCMPr instead
when both the registers are low.
Fixes #204519.
[VPlan] Allow plain active lane mask in LastActiveLane verifier. (#204982)
Active lane masks are prefix masks. After simplifying the backedge, we
may end up with an active-lane-mask operand of LastActiveLane that does
not match the header mask predicate.
This fixes a verifier failure for the new test.
[Xtensa] Call isUInt<8> in range-check asserts (#204731)
`printOffset8m8_AsmOperand` and `getSelect_256OpValue` assert on
`isUInt<8>` without calling it, so the expression takes the function's
address and the range check never runs. This also trips
`-Werror,-Wpointer-bool-conversion` in builds with assertions enabled.
Pass the operand value so the bound is actually checked.
[RFC][CodeGen] Add generic target feature checks for intrinsics
This PR adds target-independent infrastructure for annotating LLVM intrinsics
with required subtarget feature expressions.
It introduces a TargetFeatures string field to intrinsic TableGen records.
TableGen emits an intrinsic-to-feature mapping table.
Both SelectionDAG and GlobalISel now perform this check before lowering target
intrinsics. This allows targets to opt in by annotating intrinsic definitions
directly, rather than adding custom checks during lowering, legalization, or
instruction selection.
This PR uses one AMDGPU intrinsic as an example.
[RFC][IR] Extract AMDGPU-specific verification logic into `VerifierAMDGPU.cpp`
`Verifier.cpp` is large and already mixes generic IR verification with
target-specific checks. We also have a growing amount of AMDGPU verifier logic
downstream, which would all end up in the same file if we don't address this,
and that is not ideal.
This patch extracts AMDGPU-specific verification logic into a separate
`VerifierAMDGPU.cpp` file, with shared infrastructure (`VerifierSupport`) moved
into `VerifierInternal.h`.
This is purely a code organization change, not a target-dependent IR verifier.
All checks remain compiled and linked into `LLVMCore` regardless of the target
triple. The extracted functions are called unconditionally at well-defined
extension points in `Verifier.cpp`, and each function internally gates on
target-specific conditions (for example, triple checks or intrinsic IDs) as
needed. The file is strictly limited to AMDGPU-specific IR constructs (amdgcn
intrinsics, AMDGPU module flags, etc.), and does not contain generic IR rules
that vary by target.
[10 lines not shown]
[clang][x86] Add constexpr support for VNNI intrinsics (#190549)
Fixes #161340.
It adds constexpr support for VNNI
intrinsics by modifying their header files, their TableGen definitions,
how they're interpreted in InterpBuiltin.cpp and ExprConstant.cpp, and
adds unit tests in the headers' corresponding unit test files.
[orc-rt] Replace TaskDispatcher with Session-supplied wrapper-runner. (#204965)
TaskDispatcher was only used to run wrapper-function calls that
originated from the controller. Replace it with a callable type:
Session::RunWrapperCall = move_only_function<void(
orc_rt_SessionRef, uint64_t, orc_rt_WrapperFunctionReturn,
orc_rt_WrapperFunction, WrapperFunctionBuffer)>
Each call carries an outstanding ManagedCodeTaskGroup token; the runner
must eventually invoke Fn (which calls Return) or call Return directly
to bail out, otherwise Session shutdown blocks indefinitely.
Clients can supply any callable that satisfies the contract above. The
new QueueingRunner and ThreadPoolRunner classes (replacing
QueueingTaskDispatcher and ThreadPoolTaskDispatcher, respectively) are
provided as off-the-shelf options.
[LV] Avoid zero-width VF in computeVPlanOuterloopVF. (#204918)
RegSize / WidestType may be 0 for types wider than the vector register
size. Clamp VF to at least 1 (scalar), to avoid a crash. This matches
inner loop behavior.
Support for -fsplit-lto-unit option in flang driver (#204904)
Fix for buildbot failures in #202858
This commit fixes a regression introduced in commit
12aefe26cedd9a8f94546cc1f2be285cfddcc861 (Support for -fsplit-lto-unit
option in flang driver). When the compiler is built only for aarch64 one
of the testcase failed.
Added explicit check %if x86-registered-target for this testcase to
resolve the issue.
[tsan] fit Go/s390x mapping under QEMU (#204503)
QEMU linux-user first tries guest_base=0. In that identity-mapped mode,
fixed guest mappings use the same host addresses. On an x86-64 host
with four-level page tables, the Go/s390x meta shadow starts at
144 TiB, beyond the 128 TiB userspace limit, and its mmap fails with
ENOMEM during TSan initialization.
Move the meta shadow down by 32 TiB to
[0x700000000000, 0x780000000000), restoring the 16 TiB gap after the
shadow and placing all Go/s390x TSan regions below 2^47. Correct the
mapping comment's shadow size and ratio.
Failure report and native s390x comparison:
https://github.com/golang/go/issues/67881
QEMU identity guest-base selection:
https://github.com/qemu/qemu/blob/v10.2.3/linux-user/elfload.c#L1036-L1042
[9 lines not shown]
[orc-rt] Sink Session::sendWrapperResult into Session.cpp. NFC. (#204956)
This function is never called inline (except by Session::wrapperReturn,
which is also in Session.cpp), so there's no need for it to be in the
header.
[SimplifyCFG] Avoid threading loop-header branches in convergent functions
SimplifyCFG can fold a conditional branch when the condition is known from
a predecessor. When the destination is a loop header in a convergent function,
this can change the dynamic convergence structure of the loop even though the
scalar CFG rewrite is otherwise valid.
Skip this fold for loop-header branches in convergent functions so convergent
control flow is preserved.
Fixes ROCM-26496.
[clang] Add clang-format-check-format instead to CLANG_TEST_DEPS (#204908)
Ensure that clang-format doesn't break the existing format of its own
source.
Reverts #199169 and #199638.
[AMDGPU][VOPD] Cache load reachability checks in VOPDpairing (#204854)
#201930 causes significant compilation time regression when building
ROCm mathlibs.
Major regressions are caused by repeated queries to `DAG->IsReachable`
to detect possible scalarisation of loads when fusing a pair of
VOPD-capable instructions.
This patch caches the set of reachable loads for every potentially
hazardous load instruction to avoid the need to invoke
`DAG->IsReachable` at all.
[SelectionDAG] Keep split vector atomic store value in a vector register (#201566)
When the value of an ATOMIC_STORE has a vector type whose legalization
action is split (e.g. <4 x half>/<4 x bfloat> on X86 without F16C),
SplitVecOp_ATOMIC_STORE bitcast the value straight to a scalar integer
spanning the memory width. For a split vector that bitcast is expanded
element by element, reassembling the value in GPRs (a long pextrw/shl/or
sequence) before the store.
Instead, keep the value in a vector register when a legal vector form
exists: reinterpret it as a same-shaped integer-element vector (an FP
element type may have no legal vector form, e.g. bfloat on SSE2, while
the integer-of-element-size form does), widen that to a legal vector,
and extract the low integer element of the memory width. This issues the
store directly from a vector register (a single MOVQ/MOVD on X86),
matching the widen-path codegen already produced on AVX targets. Falls
back to the scalar bitcast when no suitable legal vector type exists.
Stacked on top of https://github.com/llvm/llvm-project/pull/197861; and
below of #197862.
