[LV] Use SCEV to compute final value of complex induction variables (#195059)
Extend optimizeInductionLiveOutUsers to handle complex induction
variable by using SCEV analysis. When an induction variable forms an
affine AddRec {Start,+,Step}, compute the final value as Start +
(ResumeTripCount - 1) * Step using VPDerivedIVRecipe.
This patch eliminates unnecessary vector widening for induction
variables only used outside the loop.
Pre-commit test #195055
[AArch64] Mark SP-only register classes as non-allocatable (#211549)
Reserved registers are not allocatable and since these are singleton
classes, they should be marked as such.
Assisted-by: codex
FIX some OMPT tests that fail on RISC-V (#156914)
There is a known issue with these tests (see
https://github.com/llvm/llvm-project/issues/35661).
It looks that the behaviour is very architecture specific and it was
somehow solved for aarch64 but no mention to riscv64.
[AMDGPU] Port Atomic-Optimizer to use Wave Reduction Intrinsics
Currently the atomic optimizer creates reductions via
intrinsics, and introduces new control flows.
Replace this sub-target dependent logic with existing
wave reduction intrinsics, which get lowered in the
backend.
This patch ports the uniform-value and divergent-no-return-value cases.
[NFC][SPIR-V] Remove unused LoopInfo member from structurizer splitter (#211538)
Splitter never used its LoopInfo reference
Based on the discussion in
https://github.com/llvm/llvm-project/pull/211198
[AMDGPU] Add image_atomic_{min,max}_num_flt support to gfx13 (#211564)
GFX13 uses the num_flt suffix as the default assembler name for the
32-bit FP image atomic min/max instructions. Keep flt as a
backward-compatible alias. GFX12 is unchanged (flt default, num_flt
alias).
---------
Co-authored-by: Petar Avramovic <Petar.Avramovic at amd.com>
[AMDGPU] Add synthetic apertures and use them for barriers
Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
Revert "[AArch64] Enable Spillage Copy Elimination by default" (#211572)
Reverts llvm/llvm-project#186093
Issue https://github.com/llvm/llvm-project/issues/206839 shows that
EliminateSpillageCopies is not currently ready to be enabled by default
on AArch64. https://github.com/llvm/llvm-project/pull/207169 was raised
to fix the issue, but concerns were raised around complexity of the
function and change. Until a suitable solution can be found,
EliminateSpillageCopy will be disabled on AArch64 by default.
For those who wish to still use the pass, `-enable-spill-copy-elim=true`
will ensure the pass is run.
[RFC][AMDGPU] Add BARRIER address space
Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.
These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.
The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
[clang][AMDGPU] Clean-up handling of named barrier type
- Allow the type in struct/classes in very limited circumstances. The goal is to enable creating trivial wrappers around the named barrier variable, but ensure we can't get into situations where things would get awkward. Currently this means we only allow the named barrier in RecordDecls with exactly 1 field, that have no base class, and are not inherited.
- Use a `amdgpu_barrier` LangAS for this type that currently maps to the local AS. This allows easy switching to the barrier AS in a future patch.
