[lldb][test] Skip unsupported tests on WebAssembly (#204245)
Mark more tests that rely on features unavailable on wasm32-wasip1 (or
in LLDB's Wasm support): expression evaluation (skipIfWasm), shared
libraries (skipIfTargetDoesNotSupportSharedLibraries), threads
(skipIfTargetDoesNotSupportThreads), and llvm-strip --keep-symbol, which
the Wasm object format doesn't support. Where a test also has supported,
passing cases, the decorator is applied per method.
The "expression" category is already skipped for Wasm, but that only
covers commands/expression/*, where the category is set by a
"categories" file. The tests in this PR live elsewhere and merely use
expression evaluation incidentally, so they aren't in that category and
need skipIfWasm directly.
[Driver] Re-enable -fobjc-constant-literals by default (#204208)
This reverts 4d154f6ea5eb ([Driver] Disable -fobjc-constant-literals by
default (#195000)), which was a temporary measure to unblock a project
that the original constant-literal change (#185130) broke.
For background on the feature and the discussion that led to disabling
and then re-enabling it, see
https://github.com/llvm/llvm-project/pull/185130.
rdar://179823193
[SSAF][WPA] Add a lit test for the WPA improvement of #198889 (#204018)
This commit adds a lit test, which is an example of the issue solved by
#198889 and was discovered independently when applying the analysis to a
real project.
rdar://179754164
[RISC-V][MC] Improve the diagnostic for invalid compressed register number
Instead of a generic `invalid operand for instruction`, print
`register must be a GPR from x8 to x15` instead.
Pull Request: https://github.com/llvm/llvm-project/pull/204237
[BinaryFormat] Fix UBSan negative-shift in identify_magic Mach-O path (#204122)
`identify_magic()` read the Mach-O filetype field at offset 12 by
left-shifting four bytes of the input StringRef:
```
type = Magic[12] << 24 | Magic[13] << 12 | Magic[14] << 8 | Magic[15];
```
`StringRef::operator[]` returns a `signed char`. When a header byte has
its
high bit set (e.g. 0xFA == -6 after promotion to int), the expression
"-6 << 24" is undefined behavior; even positive bytes like 0xFF promote
to a value whose "<< 24" overflows a signed int. UBSan trapped this on a
crafted input found by lldb-target-fuzzer:
```
Magic.cpp:177:26: runtime error: left shift of negative value -6
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior
libFuzzer: deadly signal
```
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AMDGPU: Teach disassembler to produce target id directives (#203979)
Inspect the binary's e_flags to reproduce the .amdgcn_target directive.
This is a step towards round-trip disassembly without depending
on command line state specifying the subtarget. I wasn't sure
where to put the emission to ensure it is always emitted. I
also do not know why it's OK to just write to outs(), but that's
what the other directives here were doing.
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
[lldb][test] Skip watchpoint and expression tests on WebAssembly (#204235)
WebAssembly has no watchpoint support (Process/wasm reports no
watchpoints; the stop reason comes back as a plain signal) and cannot
JIT or interpret expressions (ProcessWasm sets CanJIT to false). Teach
the existing per-platform category checks about wasm so the whole
"watchpoint" and "expression" categories are skipped, rather than
decorating each test individually.
[RFC][CodeGen] Add generic target feature checks for intrinsics
This PR adds target-independent infrastructure for annotating LLVM intrinsics
with required subtarget feature expressions.
It introduces a TargetFeatures string field to intrinsic TableGen records.
TableGen emits an intrinsic-to-feature mapping table.
Both SelectionDAG and GlobalISel now perform this check before lowering target
intrinsics. This allows targets to opt in by annotating intrinsic definitions
directly, rather than adding custom checks during lowering, legalization, or
instruction selection.
This PR uses one AMDGPU intrinsic as an example.
[RFC][CodeGen] Add generic target feature checks for intrinsics
This PR adds target-independent infrastructure for annotating LLVM intrinsics
with required subtarget feature expressions.
It introduces a TargetFeatures string field to intrinsic TableGen records.
TableGen emits an intrinsic-to-feature mapping table.
Both SelectionDAG and GlobalISel now perform this check before lowering target
intrinsics. This allows targets to opt in by annotating intrinsic definitions
directly, rather than adding custom checks during lowering, legalization, or
instruction selection.
This PR uses one AMDGPU intrinsic as an example.
AMDGPU: Refactor AMDGPUTargetID to not store MCSubtargetInfo
Store the triple string and GPUKind instead. The dependence
on checking AMDHSA seems like an anti-feature, but maintain the
behavior of not printing the modifiers for other OSes. Start
parsing the target ID instead of performing a direct string
comparison. Also improve test coverage for the treatment of the
environment component of the triple. The main behavioral change
is this will now produce normalized triples in the output and
diagnostics. Practially, this means all of the places that
currently emit "--" will be expanded into "-unknown-".
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
AMDGPU: Teach disassembler to produce target id directives
Inspect the binary's e_flags to reproduce the .amdgcn_target directive.
This is a step towards round-trip disassembly without depending
on command line state specifying the subtarget. I wasn't sure
where to put the emission to ensure it is always emitted. I
also do not know why it's OK to just write to outs(), but that's
what the other directives here were doing.
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
[AMDGPU] Add flag to control VGPR pressure limits (#203797)
The RP trackers don't accurately measure the RA problem, and can
underestimate the number of registers required. Currently, for VGPR
pressure, we account for these inaccuracies using VGPRLimitBias, and
ErrorMargin. These are used to reduce the VGPRCriticalLimit /
VGPRExcessLimit . During scheduling, we check RP against these limits,
and if we start to see RP exceeding these limits, we will trigger RP
reduction heuristics (when deciding which instructions to schedule
next). Thus VGPRLimitBias + ErrorMargin effectively reduce the amount of
allowable RP during scheduling, as a means to compensate for RP tracker
inaccuracies. Currently, ErrorMargin is set to 3, and VGPRLimitBias is
set to 0.
However, the degree of inaccuracy tends to scale with the number of
registers we have available for allocation. In other words, the RP
trackers inaccuracy is better expressed as a percent of the register
budget, rather than some literal value. This PR adds some functionality
to express this inaccuracy compensation is a percent - and exposes a
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[AMDGPU] NFC: Obviously show isVALU includes LDSDMA instructions (#203548)
In https://reviews.llvm.org/D124472 we started labelling LDSDMA as VALU
-- this was due to SPG stating that these instructions act as both
memory + VALU instructions.
This is buried in the isVALU methods - I'd argue that most users without
knowledge of this characteristic would not expect this behavior, and
looking at the implementation of these methods, there is nothing that
would suggest this behavior. This PR forces users to confront this
characteristic and decide if that is what they want to do for their
usecase.
I've personally seen at least two bugs in upstream code caused by this,
and have seen it cause problems a dozen + times in downstream code / in
WIP things.
[SandboxVec][DAG] Implement UnscheduledPreds API (#201240)
Mirroring UnscheduledSuccs, this patch adds an UnscheduledPreds DAG node
counter that counts how many predecessors are not scheduled yet.
It also renames the existing ready() to readyBottomUp() to help us
differentiate between the two variants that are now available.
[MCJIT] Fix frem.ll test failure with LLVM_ENABLE_RPMALLOC on Windows (#200319)
When compiled with `LLVM_ENABLE_RPMALLOC`, `lli.exe` links statically to
the runtime. With `LLVM_EXPORT_SYMBOLS_FOR_PLUGINS` enabled, `lli.exe`
exports a subset of symbols from the runtime library, but not all. In
particular, `printf()` is exported from the application binary, but
`fflush()` and `exit()` are not. For a JITted module, unresolved
external symbols are loaded either from the application or dynamic
libraries, in this case, from `msvcrt.dll`. The `MCJIT/frem.ll` test
attempts to flush the output, but because the functions resolve to
different CRT instances, the output data is lost.
The patch avoids the test failure by disabling exporting symbols from
`lli.exe` when it is linked with the static runtime library.
