LLVM/project e1ddff1compiler-rt/test/sanitizer_common/TestCases/Linux getpwnam_r_invalid_user.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+1-1compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp
+1-11 files

LLVM/project 0088575lldb/source/Plugins/LanguageRuntime/CPlusPlus CPPLanguageRuntime.cpp

[lldb] Upstream missing FixCodeAddress in CPPLanguageRuntime (#186519)
DeltaFile
+12-0lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
+12-01 files

LLVM/project 696208bllvm/test/CodeGen/RISCV short-forward-branch-opt-with-branch-with-immediates_48_ne.ll short-forward-branch-opt-with-branch-with-immediates_48_eq.ll

[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)

This is a follow-up to #182456. This PR adds support for short forward
branches where branches are from Qualcomm uC `Xqcibi` extension.
DeltaFile
+952-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
+952-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
+948-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
+948-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
+948-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
+948-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
+5,696-010 files not shown
+11,180-616 files

LLVM/project 5d3aae9libclc/clc/include/clc/math clc_ep_decl.inc clc_ep.inc, libclc/opencl/lib/generic/relational relational_binary_def.inc binary_def.inc

[libclc][NFC] Rename three .inc files to avoid name conflicts (#186384)

Follow-up of 9b96ebc. There are binary_def.inc and unary_def.inc in
header directory.
- clc_ep.inc -> clc_ep_decl.inc
- relational/binary_def.inc -> relational/relational_binary_def.inc
- relational/unary_def.inc -> relational/relational_unary_def.inc
DeltaFile
+131-0libclc/clc/include/clc/math/clc_ep_decl.inc
+0-131libclc/clc/include/clc/math/clc_ep.inc
+24-0libclc/opencl/lib/generic/relational/relational_binary_def.inc
+0-24libclc/opencl/lib/generic/relational/binary_def.inc
+23-0libclc/opencl/lib/generic/relational/relational_unary_def.inc
+0-23libclc/opencl/lib/generic/relational/unary_def.inc
+178-17815 files not shown
+193-19321 files

LLVM/project 4409a62llvm/unittests/Support Caching.cpp

[NFC][Support] Don't test UB in Caching.WriteAfterCommit (#186532)

The test expects crash after commit essentially null-dereferencing.
Just check that it's nullptr directly.

Fixes asan/ubsan buildbot.
DeltaFile
+1-3llvm/unittests/Support/Caching.cpp
+1-31 files

LLVM/project de2bf13clang/test/CodeGenHLSL basic_types.hlsl, clang/test/CodeGenHLSL/BasicFeatures VectorElementwiseCast.hlsl InitLists.hlsl

[clang][DirectX] Specify element-aligned vectors in TargetInfo (#185954)

Add a bit to TargetInfo to specify that vectors are element-aligned
rather than naturally aligned. This is needed to match DirectX's Data
Layout in LLVM.

Note that this removes the `Opts.HLSL` early exit from
`checkDataLayoutConsistency` so that we actually get these checks when
compiling HLSL. This check looks like it was put there because of
similarity between OpenCL and HLSL, but it isn't actually necessary.

Resolves #123968
DeltaFile
+48-48clang/test/CodeGenHLSL/builtins/mad.hlsl
+30-30clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
+27-27clang/test/CodeGenHLSL/basic_types.hlsl
+26-26clang/test/CodeGenHLSL/BasicFeatures/InitLists.hlsl
+18-18clang/test/CodeGenHLSL/BasicFeatures/MatrixToAndFromVectorConstructors.hlsl
+18-18clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
+167-16735 files not shown
+377-36141 files

LLVM/project 5e6a6d7libc/src/stdio/gpu file.h

[libc] Reference the proper namespaced variables in the GPU header

Summary:
These linked to the extern "C" versions which did not exist in test
builds.
DeltaFile
+3-1libc/src/stdio/gpu/file.h
+3-11 files

LLVM/project 7bc3bb0llvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis ScalarEvolution.cpp

[ScalarEvolution] Limit recursion in getRangeRef for PHI nodes. (#152823)

Restrict PHI nodes that getRangeRef is allowed to recursively examine so
we don't need a "visited" set. And fix createSCEVIter so it creates all
the relevant SCEV nodes before getRangeRef tries to examine them.

The tests that are affected have induction variables that aren't
AddRecs. (Other cases are theoretically affected, but don't seem to show
up in our tests.)
DeltaFile
+110-31llvm/lib/Analysis/ScalarEvolution.cpp
+8-8llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll
+6-6llvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll
+5-5llvm/test/Analysis/ScalarEvolution/ranges.ll
+0-6llvm/include/llvm/Analysis/ScalarEvolution.h
+2-2llvm/test/Transforms/LICM/update-scev-after-hoist.ll
+131-585 files not shown
+136-6311 files

LLVM/project 60669c1clang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGen call-graph-section-internal.cpp

Fix callee type generation (#186272)

The callee_type metadata is expected to be a list of generalized type
metadata by the IR verifier. But for indirect calls with internal
linkage the type metadata is just an integer. Avoid including them in
callee_type metadata.

This will reduce the precision of the generated call graph as the edges to internal linkage functions whose address were taken will not be present anymore. We need to handle this in the future.
DeltaFile
+37-0clang/test/CodeGen/call-graph-section-internal.cpp
+6-2clang/lib/CodeGen/CodeGenModule.cpp
+43-22 files

LLVM/project a27a504llvm/unittests/Support Caching.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+1-3llvm/unittests/Support/Caching.cpp
+1-31 files

LLVM/project 7449009lldb/tools/darwin-mte-launcher darwin-mte-launcher.cpp

[lldb] Enable SanitizersAllocationTraces=tagged in darwin-mte-launcher (#186326)

Collect allocation traces for tagged memory when using the
`darwin-mte-launcher` to help debug MTE crashes.
DeltaFile
+19-8lldb/tools/darwin-mte-launcher/darwin-mte-launcher.cpp
+19-81 files

LLVM/project 8121900lldb/utils/lldb-dotest CMakeLists.txt lldb-dotest.in

[lldb] Add support for the darwin-mte-launcher to lldb-dotest (#186319)

Add support for the `darwin-mte-launcher` to `lldb-dotest` when LLDB is
configured to run the tests under MTE.
DeltaFile
+5-0lldb/utils/lldb-dotest/CMakeLists.txt
+3-0lldb/utils/lldb-dotest/lldb-dotest.in
+8-02 files

LLVM/project a254ca5clang/include/clang/Basic AttrDocs.td

Remove unicode character from AttrDocs.td (#186521)

PR #185225 introduced a single unicode character, which is the only
unicode character in this file. Change this to a ASCII/Latin1 letter.
DeltaFile
+1-1clang/include/clang/Basic/AttrDocs.td
+1-11 files

LLVM/project a9b944allvm/lib/Transforms/Vectorize LoopIdiomVectorize.cpp, llvm/test/Transforms/LoopIdiom/AArch64 find-first-byte.ll

[LoopIdiomVectorize] Preserve address space in FindFirstByte (#185226)

Fixes #185188

Use SearchStart->getType() instead of Builder.getPtrTy() so that
pointer-typed PHI nodes preserve the address space of the original
pointers.

Assisted-by: Claude (Anthropic)
DeltaFile
+165-0llvm/test/Transforms/LoopIdiom/AArch64/find-first-byte.ll
+2-2llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
+167-22 files

LLVM/project 440a5b5flang/lib/Semantics resolve-names.cpp resolve-directives.cpp, flang/test/Semantics bug2359.f90

[flang] Fix SELECT TYPE in OpenACC construct (#186511)

A routine in Semantics/resolve-directives.cpp was overwriting a symbol
table pointer in a parse tree Name, thereby removing the AssocEntity
with the correct type for a TYPE IS or CLASS IS clause that had been
placed there. I don't really understand why resolve-directives has to
overwrite symbol table pointers in the first place, but it definitely
shouldn't be replacing these.
DeltaFile
+33-0flang/test/Semantics/bug2359.f90
+4-3flang/lib/Semantics/resolve-names.cpp
+2-1flang/lib/Semantics/resolve-directives.cpp
+39-43 files

LLVM/project 5a3d71dutils/bazel/llvm-project-overlay/mlir BUILD.bazel, utils/bazel/llvm-project-overlay/mlir/test BUILD.bazel

[Bazel] Port 717d1a23c978e5fe25063a4a90ee31652b6912bf
DeltaFile
+4-1utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-1utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
+5-22 files

LLVM/project cbddc40clang/lib/Headers/hlsl hlsl_alias_intrinsics.h

[HLSL] Fix intrinsics header file for wave intrinsics using u/int16_t types, updating them to 6.2 (#186218)

This is actually a surprise part 2 to:
https://github.com/llvm/llvm-project/pull/185757

Fully addresses https://github.com/llvm/llvm-project/issues/185756
DeltaFile
+375-372clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+375-3721 files

LLVM/project 42804a5utils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Port b7c4615e137815e2577a4795f33a9bcae2416cb8
DeltaFile
+19-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+19-01 files

LLVM/project 4e2bb58llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.ds.swizzle.ll

AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_ds_swizzle (#186024)
DeltaFile
+55-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
+20-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+79-93 files

LLVM/project 7f538fdllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.getreg.ll

AMDGPU/GlobalISel: RegBankLegalize rules for s_getreg (#186253)
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6-53 files

LLVM/project 717d1a2mlir CMakeLists.txt, mlir/include/mlir/Config mlir-config.h.cmake

[mlir] Replace MLIR_ENABLE_ROCM_CONVERSIONS with LLVM_HAS_AMDGPU_TARGET (#182652)

`LLVM_HAS_NVPTX_TARGET` is already defined in `llvm/Config/Targets.h`
and used to gate NVPTX-related code in MLIR. The same macro exists for
AMDGPU as `LLVM_HAS_AMDGPU_TARGET`, but MLIR defined its own
`MLIR_ENABLE_ROCM_CONVERSIONS` variable for this purpose. This PR
removes `MLIR_ENABLE_ROCM_CONVERSIONS` and replaces it with
`LLVM_HAS_AMDGPU_TARGET`, bringing parity with the NVPTX target.

---------

Co-authored-by: William Moses <gh at wsmoses.com>
DeltaFile
+6-5mlir/lib/Target/LLVM/ROCDL/Target.cpp
+0-8mlir/CMakeLists.txt
+0-4mlir/include/mlir/Config/mlir-config.h.cmake
+2-2mlir/lib/Target/LLVM/CMakeLists.txt
+2-1mlir/unittests/Target/LLVM/SerializeROCDLTarget.cpp
+1-1mlir/test/lit.site.cfg.py.in
+11-212 files not shown
+13-238 files

LLVM/project c9a2f0bllvm/include/llvm/Transforms/Utils UnrollLoop.h, llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp

[LoopUnroll] Remove `computeUnrollCount()`'s return value  (#184529)

`computeUnrollCount()`'s return value is used to communicate whether
unrolling was explicitly requested. However, each of
`computeUnrollCount()`'s two callers can compute this directly:

- `LoopUnrollAndJamPass` already checks for loop unrolling metadata
[before calling
`computeUnrollCount()`](https://github.com/llvm/llvm-project/blob/43dbcdea98f5bb04ae967bdd81ece2d2144f4661/llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp#L308).
The return value only added handling for `-unroll-count`, a testing flag
with no UnrollAndJam test coverage.

- `tryToUnrollLoop()` can use `PragmaInfo(L).ExplicitUnroll` directly at
the `setLoopAlreadyUnrolled()` call site.
- In all but one case where `computeUnrollCount()` explicitly `return`s
`false` instead of `ExplicitUnroll`, `UP.Count = 0` is set. This causes
`tryToUnrollLoop()` to early-exit before reaching
`setLoopAlreadyUnrolled`.
- The remaining case that `return`s false, but does not set `UP.Count =

    [7 lines not shown]
DeltaFile
+75-54llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+0-31llvm/lib/Transforms/Utils/LoopUnroll.cpp
+10-14llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+3-12llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
+2-3llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+90-1145 files

LLVM/project 9210b3aclang/lib/Headers/hlsl hlsl_alias_intrinsics.h, clang/lib/Sema SemaHLSL.cpp

[HLSL][DirectX] Add `transpose` HLSL intrinsic and DXIL lowering of `llvm.matrix.transpose` (#186263)

Fixes #184922

- [x] Implement `transpose` clang builtin in `Builtins.td`
- [x] Link `transpose` clang builtin with `hlsl_alias_intrinsics.h`
- [x] Add sema checks for `transpose` to `CheckHLSLBuiltinFunctionCall`
in `SemaHLSL.cpp`
- [x] Add codegen for `transpose` to `EmitHLSLBuiltinExpr` in
`CGHLSLBuiltins.cpp`
  - `transpose` lowers to the `llvm.matrix.transpose` intrinsic
- [x] Add codegen tests to
`clang/test/CodeGenHLSL/builtins/transpose.hlsl`
- [x] Add sema tests to
`clang/test/SemaHLSL/BuiltIns/transpose-errors.hlsl`
- [x] Implement lowering of the `llvm.matrix.transpose` intrinsic in the
DXIL backend in `DXILIntrinsicExpansion.cpp`
- The intrinsic lowers to a shufflevector like in DXC
https://hlsl.godbolt.org/z/Gj959q6sq

    [3 lines not shown]
DeltaFile
+65-0llvm/test/CodeGen/DirectX/matrix-transpose.ll
+42-0clang/test/CodeGenHLSL/builtins/transpose.hlsl
+32-0clang/test/SemaHLSL/BuiltIns/transpose-errors.hlsl
+21-0llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
+19-0clang/lib/Sema/SemaHLSL.cpp
+17-0clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+196-02 files not shown
+209-08 files

LLVM/project 305dc4emlir/lib/Dialect/Vector/Transforms LowerVectorGather.cpp, mlir/test/Dialect/Vector vector-gather-lowering.mlir

[mlir][vector] Lower vector.gather with delinearization approach (#184706)

The old implementation did not handle n-D memref correctly, which leads
to wrong access. E.g.,

```
 func.func @gather_memref_2d(%base: memref<?x?xf32>, %v: vector<2x3xindex>, %mask: vector<2x3xi1>, %pass_thru: vector<2x3xf32>) -> vector<2x3xf32> {
  %c0 = arith.constant 0 : index
  %c1 = arith.constant 1 : index
  %0 = vector.gather %base[%c0, %c1][%v], %mask, %pass_thru : memref<?x?xf32>, vector<2x3xindex>, vector<2x3xi1>, vector<2x3xf32> into vector<2x3xf32>
  return %0 : vector<2x3xf32>
 }
```

is lowered to

```
  func.func @gather_memref_2d(%arg0: memref<?x?xf32>, %arg1: vector<2x3xindex>, %arg2: vector<2x3xi1>, %arg3: vector<2x3xf32>) -> vector<2x3xf32> {
    %c0 = arith.constant 0 : index

    [26 lines not shown]
DeltaFile
+74-3mlir/test/Dialect/Vector/vector-gather-lowering.mlir
+49-9mlir/lib/Dialect/Vector/Transforms/LowerVectorGather.cpp
+6-1mlir/test/Dialect/XeGPU/xegpu-vector-linearize.mlir
+2-2mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
+131-154 files

LLVM/project b7c4615libc/src/stdio/printf_core string_converter.h CMakeLists.txt, libc/test/src/stdio sprintf_test.cpp

[libc] Support ls in printf (#178841)

Add support for %ls in printf by calling internal string converter and
add relevant end-to-end sprintf test. Additionally, modified printf
parser for recognizing length modifier. This also disables wide string
support on windows
and other unsupported platforms.

Co-authored-by: shubhe25p <shubhp at mbm3a24.local>
DeltaFile
+103-0libc/test/src/stdio/sprintf_test.cpp
+86-7libc/src/stdio/printf_core/string_converter.h
+4-0libc/src/stdio/printf_core/CMakeLists.txt
+1-1libc/src/stdio/printf_core/parser.h
+194-84 files

LLVM/project 55e626cclang/lib/CIR/Dialect/Transforms/TargetLowering/Targets AMDGPU.cpp

Add table-based CIR -> Target AS mapping
DeltaFile
+17-18clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
+17-181 files

LLVM/project a4e6d84llvm/lib/Target/AArch64 AArch64SystemOperands.td

[AArch64][llvm] Rewrite the TLBI multiclass to be much clearer (NFC)

The `tlbi` multiclass is really doing four jobs at once: base TLBI,
synthesized nXS, optional TLBIP, and synthesized TLBIP nXS. Also,
`needsreg` and `optreg` are really just a 3-state operand policy in
disguise. Likewise, the PLBI multiclass has this same issue.

Change `needsreg` and `optreg` into a combined fake enum, so it's
clearer whether the instruction takes no register operand, a required
register operand or an optional register operand.

This improves on my original change 66e8270e8.
DeltaFile
+127-121llvm/lib/Target/AArch64/AArch64SystemOperands.td
+127-1211 files

LLVM/project 836421allvm/include/llvm/IR Intrinsics.td, llvm/test/Transforms/Coroutines coro-async-noduplicate.ll

[coro] [async] There needs to be a one-to-one corespondance between the async resume function value and the suspend intrinsic (#186436)

We need to mark both the async.resume intrinsic function and the
supsend.async function as not duplicatable. The async.resume function
models the continuation after a suspend. It is non sense to not have a
one-to-one correspondance between the two: if the suspend intrinsic is
cloned so needs to be the matching async.resume intrinsic call.

rdar://172130181
https://github.com/swiftlang/swift/issues/87719
DeltaFile
+90-0llvm/test/Transforms/Coroutines/coro-async-noduplicate.ll
+2-2llvm/include/llvm/IR/Intrinsics.td
+92-22 files

LLVM/project 01571f1llvm/lib/CodeGen CodeGenPrepare.cpp ExpandMemCmp.cpp, llvm/lib/Target/AMDGPU AMDGPUUnifyDivergentExitNodes.cpp SIAnnotateControlFlow.cpp

[CodeGen] Drop uses of BranchInst (#186391)

Largely a straight-forward replacement with occasional simplifcations.

For AMDGPU, I assumed that unconditional branches are always uniform and
therefore "simplified"/changed AMDGPUAnnotateUniformValues to only
annotate conditional branches.

Target-specific FastISel only selects conditional branches,
unconditional branches are already handled by the non-target-specific
code.
DeltaFile
+43-44llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+20-22llvm/lib/CodeGen/CodeGenPrepare.cpp
+18-21llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
+15-15llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
+6-13llvm/lib/CodeGen/ExpandMemCmp.cpp
+4-11llvm/lib/CodeGen/HardwareLoops.cpp
+106-12629 files not shown
+168-21435 files

LLVM/project 20d7ae2clang/include/clang/Basic AttrDocs.td

Remove unicode character from AttrDocs.td

PR #185225 introduced a single unicode character, which is the only
unicode character in this file. Change this to a ASCII/Latin1 letter.
DeltaFile
+1-1clang/include/clang/Basic/AttrDocs.td
+1-11 files