[C++20] [Modules] Correct the redecl chain (#219926)
Close https://github.com/llvm/llvm-project/issues/219639
The root cause of the problem is the incorrect redecl chain.
A valid redecl chain should be a circle where each decl refers to the
previous one and the first decl refers to the most recent decl (latest
one). However, in the example, the redecl chain became to:
D2 -> D1 -> D1 ....
so that the range of `for (... : D->redecls())` never ends.
The real cause of the issue is we didn't merge correctly in the
ASTReader. Previous code assumes about the most recent decl while the
new code makes the behavior more clearly.
[Clang] Fix double revert of a keyword token that was cached before the first fallback (#219799)
Fixes #214128
When an undeclared name is followed by `<`, the parser tentatively looks
for a template-argument list and, on invalid input, can skip all the way
to the end of the file. Every token after that point is lexed and cached
while the type-trait keywords still have their keyword kind. The first
`struct __make_unsigned` then reverts the keyword to an identifier, but
the second `struct __make_unsigned` is replayed from the cache with the
stale keyword kind, so `TryKeywordIdentFallback` tries to revert the
same `IdentifierInfo` again and trips the assertion in
`revertTokenIDToIdentifier`. The same thing can happen with any keyword
this hack covers (`__is_pod`, `__is_signed`, the transform traits) and
with any cached token, since a `Token` is just a snapshot of the
classification at lex time.
`TryKeywordIdentFallback` now asks the `IdentifierInfo`, which is the
source of truth, before doing anything: if the keyword has already been
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[MLIR][OpenMP] Replace target-data assert with error (#219228)
If a user incorrectly puts a `target data`, `target enter data`, `target
exit data` or `target update` directive inside of target device code,
this will get lowered to MLIR and trigger an assert while translating
the corresponding operations to LLVM IR.
Part of the issue is that there are no semantics checks to prevent this
but, even if they were added, they wouldn't be able to incorporate
implicit `declare target` information, as that is added later. This
patch replaces the assert with a more informative compile error during
MLIR to LLVM IR translation to catch any of these cases that make it
past semantics.
[mlir][gpu][math] Fix assertion in OpToFuncCallLowering on vector results (#215317)
`OpToFuncCallLowering` asserts that operand and result types match, with
an escape hatch for scalar `i1` results. Math vector FP classification ops
return `vector<...xi1>`, which the escape hatch does not cover, so they trigger
the assertion.
Reject non-scalar results before the assertion, allowing
`ScalarizeVectorOpLowering` to lower them element-wise. This preserves
the existing behavior in non-assert builds, where `OpToFuncCallLowering`
already failed to match vector types. Add regression coverage for vector and
scalar FP classification ops.
Fixes #210855
Assisted-by: Claude (Anthropic)
[AMDGPU][GlobalIsel] Replace wip_match_opcode with MIR patterns with basic match and apply clauses. (#219185)
This patch replaces wip_match_opcode mechanism with MIR-pattern matching
for opcodes with no or partial possibility for declarative pattern
match/apply clause for the AMDGPU-specifc GICombines.
The following opcodes are covered : `G_TRUNC`, `G_AMDGPU_FMED3`,
`G_FCANONICALIZE`, `G_FNEG`, `G_MUL` and `G_SEXT_INREG`.
[AMDGPU][GlobalISel] Use MIR patterns for multi-opcode combiner rules. (#219278)
Match several AMDGPU GlobalISel combiner rules with MIR patterns inplace
of wip_match_opcode mechanism:
- uchar_to_float, cvt_f32_ubyteN, int_minmax_to_med3 and
fp_minmax_to_med3 / fp_minmax_to_clamp now match via a GICombinePatFrag
that fans out over their opcodes with !foreach, keeping the existing C++
match/apply.
- rcp_sqrt_to_rsq becomes fully declarative: a group of four intrinsic
patterns folding rcp(sqrt(x)) and sqrt(rcp(x)) into rsq(x) for both
G_FSQRT and amdgcn.sqrt, removing matchRcpSqrtToRsq.
It also includes some regenerated LIT tests changes which accounts for
making uchar_to_float a MIR pattern resulting in its reorders after the
generic itof_const_zero_fold_ui pattern on the G_UITOFP root; they only
race on uitofp(0), where folding to fconstant 0.0 instead of
cvt_f32_ubyte0 is value-identical.
[mlir][scf] Declare ControlFlow as a dependent dialect (#216852)
The canonicalization of a multi-block `scf.execute_region` creates
`cf.br`, but the SCF dialect does not declare `cf::ControlFlowDialect`
as a dependent dialect.
When nothing else has loaded ControlFlow, `mlir-opt --canonicalize`
fails with
LLVM ERROR: cf.br created with unregistered dialect.
Prepending an unrelated function that merely mentions `cf.br` makes the
same input canonicalize cleanly, which is the symptom `dependentDialects`
prevents.
The test needs a non-`func.func` parent: Func's inliner extension
already loads ControlFlow, which is why no in-tree test caught this.
Assisted-by: Claude (Anthropic)
[CodeGen] Unsized token-like target extension types in GlobalISel
An unsized target-type with IsTokenLike property should be lowered to
LLT::token() since it has no machien representation. Sized token-like types
continue to be lowered to sized non-token types.
This may be seen as a lossy translation, but note that even the semantics of
pure tokens is not enforced in MIR. It is possible to create a PHI or Select in
MIR with a token type. So far, it seems that the GlobalISel flow merely depends
on transforms being well-behaved enough to not produce such MIR.
Added a type `llvm.test.tokenlike` to be able to test the lowering of both sized
and unsized versions.
Assisted-By: AI Code Assistant
[X86] Fix VECREDUCE_XOR to PARITY lowering for 16-bit elements (#219216)
We can't lower vecreduce.xor to parity(movmsk) if the movmsk doesn't
match the element size. For 16-bit elements we'd use movmskb, which
would result in two bits per element, which are always the same. Thus
the parity is always zero.
Disclosure: Test case identified by AI, patch is my own.
[SPIR-V] Honor explicit memory_order/memory_scope in atomic load/store (#215572)
atomic_load_explicit and atomic_store_explicit ignored their
memory_order/memory_scope arguments
Translate the explicit arguments via the existing
buildMemSemanticsReg/buildScopeReg helpers, as buildAtomicRMWInst
already does
[gold] Handle absence of gold linker in tests (#219901)
If we get a NOTFOUND executable, directly report plugin support
as unavailable, instead of trying to invoke the linker.
This fixes a regression from #130981.
[Sema][NFC] Add additional tests for declarations in expansion statements (#211948)
I came up with these additional tests for declarations in expansion
statements that previously failed but now correctly diagnose the errors.
[LAA] Give the symbolic strides map a named type (NFC) (#216731)
LoopAccessInfo collects SCEVUnknown strides, collectStridedAccess casts
to it when inserting, but the map was typed as holding a plain SCEV, so
the invariant had to be restated at each use.
[LoongArch] Add late branch optimization pass (#216261)
The patch adds a late optimization pass that replaces conditional
branches that can be statically evaluated with an unconditinal branch.
This pass is inspired by RISC-V's RISCVLateBranchOpt pass.
[clang][bytecode] Keep sourcemaps smaller (#219878)
Only add new entries if they are different than the currently last
entry. This means we won't have an entry for _all_ opcodes in the source
map anymore.
[libc++] Remove NaCl support from __cxx03 headers (#219787)
Completes the NaCl cleanup started in #148983 by removing the remaining
references from the frozen `__cxx03/` headers.
Changes:
* Remove the `_LIBCPP_USING_NACL_RANDOM` comment block and
`#elif defined(__native_client__)` branch from
`include/__cxx03/__config`
* Remove `defined(__pnacl__)` from the `#if` condition in
`include/__cxx03/limits`
The `_LIBCPP_USING_NACL_RANDOM` macro was defined but never consumed;
its
previous consumer in `src/random.cpp` was already removed in #148983.
Fixes #219588
[CodeGen][AMDGPU] Fixed FileCheck patterns in #212201 regression test (#219683)
Quick follow up to fix failures from merging #212201. Removes `llvm::`
from FileCheck in `si-preallocate-wwm-regs-preserve.mir` test.
[clang][bytecode] Iterate scope only once in Destroy() (#219874)
Call deallocate() here directly instead of iterating the scope again in
`InterpFrame::destroy()`.
[VectorCombine] Allow equal-cost scalarization for single-use loads (#218340)
Allow scalarizeLoadExtract to scalarize a single-use vector load when
the scalarized cost is equal to the original cost.
For a single extract user, this does not increase the number of memory
operations and narrows the memory access, which can expose further
optimizations such as store-to-load forwarding and DSE.
Keep requiring a strict cost improvement for loads with multiple users.
Proof https://alive2.llvm.org/ce/z/YAck5U
Fixes https://github.com/llvm/llvm-project/issues/217598
