LLVM/project ffde4cellvm/test/CodeGen/RISCV orc-b-patterns.ll

[RISCV] Add RV64 RUN lines to orc-b-patterns.ll. NFC (#222424)

Add some i16 and i64 tests.
DeltaFile
+459-135llvm/test/CodeGen/RISCV/orc-b-patterns.ll
+459-1351 files

LLVM/project 5524a21clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenFunction.h CIRGenBuiltin.cpp

[CIR] Add cir.coro.intrinsic.resume/destroy/done Ops (#222210)

Adds CoroResumeOp, CoroDestroyOp, and CoroDoneOp, representing
llvm.coro.resume, llvm.coro.destroy, and llvm.coro.done respectively.
DeltaFile
+43-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+19-0clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
+9-8clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+9-6clang/test/CIR/CodeGenCoroutines/coro-builtins.cpp
+3-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+83-145 files

LLVM/project 6b0c183llvm/lib/Target/RISCV/GISel RISCVRegisterBankInfo.cpp RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel legalizer-info-validation.mir lrint-llrint-f16.ll

[RISCV][GlobalISel] Support G_INTRINSIC_LRINT/G_INTRINSIC_LLRINT (#221992)

Add legalizer rules so llvm.lrint/llrint lower to fcvt.{w,l}.{h,s,d}
with FRM_DYN, mirroring the existing G_LROUND/G_LLROUND handling.
DeltaFile
+268-0llvm/test/CodeGen/RISCV/GlobalISel/lrint-llrint.ll
+41-0llvm/test/CodeGen/RISCV/GlobalISel/lrint-llrint-f16.ll
+13-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+5-4llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+4-0llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+331-45 files

LLVM/project 2c4c9d8llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVLegalizeImplicitBinding.cpp, llvm/test/CodeGen/SPIRV/hlsl-resources ImplicitBinding.ll

[SPIRV] Fix inconsistent operand order for counter resource intrinsic (#221646)

The `llvm.spv.resource.handlefrombinding` intrinsic stores its binding
operands in the order (DescriptorSet, BindingNo, ...). The
`llvm.spv.resource.counterhandlefrombinding` intrinsic should use the
same order.

The `llvm.spv.resource.counterhandlefrombinding` intrinsic is currently
emitted only by the `SPIRVLegalizeImplicitBinding` pass. The pass
previously built its operands in the wrong order, and the instruction
selector repeated the same inversion when emitting decorations.

This change makes the operand order consistent with
`llvm.spv.resource.handlefrombinding`.

Test update closes a coverage gap - there were no tests for explicit
`llvm.spv.resource.counterhandlefrombinding` calls.

Assisted by GPT-5.6 Sol.
DeltaFile
+30-3llvm/test/CodeGen/SPIRV/hlsl-resources/ImplicitBinding.ll
+7-5llvm/lib/Target/SPIRV/SPIRVLegalizeImplicitBinding.cpp
+2-2llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+39-103 files

LLVM/project e6942b4clang/test/CIR/CodeGen call-conv-lowering-x86_64-sret-res-attrs.c

[CIR] Add a C test for the sret res_attrs drop

Assisted-by: Cursor / claude-opus-5
DeltaFile
+41-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-sret-res-attrs.c
+41-01 files

LLVM/project a5ef934clang/docs ReleaseNotes.md, clang/lib/Sema SemaChecking.cpp

[clang] Warn on signed char array constant conversion (#203792)

This resolves #181730: fixes a missing `-Wconstant-conversion`
diagnostic for `signed char` array initialization.

Before this change, Clang warned for `signed char foo = 255;` but did
not
warn for `signed char bar[] = {255};`.

The warning suppression helper did not distinguish between `char`,
`unsigned char`, and `signed char` in brace-initialized arrays. Now it
does.
DeltaFile
+16-5clang/test/Sema/constant-conversion.c
+5-4clang/lib/Sema/SemaChecking.cpp
+3-0clang/docs/ReleaseNotes.md
+24-93 files

LLVM/project 2f704c9clang/docs ReleaseNotes.md, clang/lib/Sema SemaOpenACCClause.cpp

[Clang][OpenACC] Fixed getExtValue Call on Invalid Gang Dim (#221502)

**Problem**
When an invalid 'gang dim' value is used in `CheckGangDimExpr`, the
function prints the value into the diagnostic message by calling
`getExtValue`. This function asserts on values that can't fit into a
signed integer.

**Solution**
`APSInt` has a `<<` operator anyway so just use that.


The fix causes the message to print with the following formatting: 
```
test.cpp:5:40: error: argument to 'gang' clause dimension must be 1, 2, or 3: evaluated to 18'446'744'073'709'551'574
    5 | #pragma acc routine(S::foo) gang(dim : S::foo())
      |                                        ^
1 warning and 1 error generated.
```
Fixes #221418
DeltaFile
+3-3clang/lib/Sema/SemaOpenACCClause.cpp
+3-0clang/test/SemaOpenACC/routine-construct-clauses.cpp
+3-0clang/docs/ReleaseNotes.md
+9-33 files

LLVM/project 3e45797llvm/test/Transforms/LoopVectorize div-exact.ll if-pred-stores.ll, llvm/test/Transforms/LoopVectorize/AArch64 force-target-instruction-cost.ll

[VPlan] Skip branch term in masks for some preserved uniform edges
DeltaFile
+6-425llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll
+90-300llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
+83-117llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+36-129llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
+9-123llvm/test/Transforms/LoopVectorize/div-exact.ll
+29-89llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
+253-1,18345 files not shown
+666-2,04251 files

LLVM/project 18a8d12clang/test/CIR/CodeGen cxx20-module-initializer.cppm, clang/test/CIR/CodeGenCXX typeid-should-throw.cpp typeid-most-derived.cpp

[CIR] Fix CIR tests by adding a triple/Requires. (#222346)

Now that we're trying to build by default, we actually have to be able
to build on other buildbots! But since we still don't have the
ABI/target stuff for non linux, we need to make sure our tests don't hit
that. Tests that execute 'clang' in some way are given a triple, ones
that are on .cir files we just add a 'requires'. Some day we should be
able to remove those, but it'll require us to add the cxxabi/etc for
windows.
DeltaFile
+3-3clang/test/CIR/Transforms/lib-opt.cpp
+2-2clang/test/CIR/CodeGenCXX/typeid-should-throw.cpp
+2-2clang/test/CIR/CodeGenCXX/typeid-most-derived.cpp
+1-1clang/test/CIR/Transforms/idiom-recognizer.cpp
+1-1clang/test/CIR/CodeGen/cxx20-module-initializer.cppm
+1-0clang/test/CIR/Tools/warn-default-triple.cir
+10-96 files not shown
+16-912 files

LLVM/project eadaccellvm/lib/Target/AMDGPU VOPCInstructions.td VOPInstructions.td, llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir

[AMDGPU] Model GFX1250 VALU blocking cycles

Some gfx1250 VALU instructions block the VALU pipe for N cycles, and
the CoExec scheduler must model that occupancy. The existing SchedModel
cannot represent this given current modelling constraints (see #202775).

Attach GFX1250BlockingCycles to the VOP instruction definitions and
emit a searchable table so SIInstrInfo::getBlockingCycles() can report
the occupancy. CoExec uses that to classify multi-cycle VALU and to
account for blocking when computing HWUI cycles.

Authored by Jeffrey Byrnes <jeffrey.byrnes at amd.com>
DeltaFile
+132-6llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+56-38llvm/lib/Target/AMDGPU/VOP3Instructions.td
+23-16llvm/lib/Target/AMDGPU/VOP1Instructions.td
+19-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+15-0llvm/lib/Target/AMDGPU/VOPInstructions.td
+9-2llvm/lib/Target/AMDGPU/VOPCInstructions.td
+254-623 files not shown
+271-679 files

LLVM/project a53bc4fllvm/cmake/modules AddLLVM.cmake, mlir/cmake/modules AddMLIR.cmake

[mlir] Reuse the MLIRIR PCH through dependencies (NFC)

Track whether an MLIR library's link closure reaches MLIRIR and reuse the
MLIRIR PCH for those libraries. Preserve higher-priority local PCHs and add an
explicit opt-out for targets whose sources are incompatible with reuse.

Relative to the core and LLVM dialect PCH parent, clean Release builds of LLVM
and MLIR with Ninja -j16 pinned to CPUs 16-31 improved as follows:

  wall:   398.79s -> 386.47s (-3.09%)
  user:  5789.14s -> 5624.02s (-2.85%)
  system: 455.05s -> 438.45s (-3.65%)

Assisted-by: Codex
DeltaFile
+60-1mlir/cmake/modules/AddMLIR.cmake
+38-0mlir/test/lib/CMake/CMakeLists.txt
+8-1llvm/cmake/modules/AddLLVM.cmake
+1-0mlir/test/lib/CMakeLists.txt
+1-0mlir/test/lib/CMake/Inputs/PCHOptOut.cpp
+1-0mlir/test/lib/CMake/Inputs/PCHOptOut.c
+109-26 files

LLVM/project 707c032mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/test/Dialect/Tosa ops.mlir invalid_extension.mlir

[mlir][tosa] Add support for MXFP SCATTER (#222288)

Tosa specification changes in
https://github.com/arm/tosa-specification/pull/78
DeltaFile
+60-0mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+16-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
+7-0mlir/test/Dialect/Tosa/ops.mlir
+7-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+98-05 files

LLVM/project 81b343fmlir/include/mlir/Dialect/LLVMIR pch.h, mlir/lib CMakeLists.txt

[mlir][LLVM] Reuse a PCH for MLIRLLVMDialect (NFC)

Build a private precompiled header from the LLVM dialect and LLVM IR headers
and use it for MLIRLLVMDialect. Build dialect libraries before conversions so
the PCH is available early and repeated parsing is avoided.

Relative to the MLIRIR PCH parent, clean Release builds of LLVM and MLIR with
Ninja -j16 pinned to CPUs 16-31 improved as follows:

  wall:   420.41s -> 398.79s (-5.14%)
  user:  6125.97s -> 5789.14s (-5.50%)
  system: 481.88s -> 455.05s (-5.57%)

Assisted-by: Codex
DeltaFile
+14-0mlir/include/mlir/Dialect/LLVMIR/pch.h
+3-0mlir/lib/Dialect/LLVMIR/CMakeLists.txt
+1-1mlir/lib/CMakeLists.txt
+18-13 files

LLVM/project 2d70439llvm/utils/gn/secondary/lldb/test BUILD.gn

[gn] port eb5cd179549d68 (#222476)
DeltaFile
+0-1llvm/utils/gn/secondary/lldb/test/BUILD.gn
+0-11 files

LLVM/project cdf702dmlir/include/mlir/IR pch.h, mlir/lib CMakeLists.txt

[mlir] Reuse a precompiled header for MLIRIR (NFC)

Build a private precompiled header from the common MLIR IR headers and use it
for MLIRIR. Build Support and IR first so the PCH is available early, and
qualify the LLVM LSP Location name that the broader header surface exposes.

On current main, clean Release builds of LLVM and MLIR with Ninja -j16 pinned
to CPUs 16-31 improved as follows:

  wall:   535.99s -> 420.41s (-21.56%)
  user:  7550.29s -> 6125.97s (-18.86%)
  system: 569.85s -> 481.88s (-15.44%)

Assisted-by: Codex
DeltaFile
+20-0mlir/include/mlir/IR/pch.h
+8-8mlir/lib/Tools/mlir-lsp-server/LSPServer.cpp
+2-2mlir/lib/CMakeLists.txt
+3-0mlir/lib/IR/CMakeLists.txt
+33-104 files

LLVM/project 265bb9fclang/lib/Basic/Targets AMDGPU.cpp AMDGPU.h, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Migrate R600 onto generated TargetParser bitset (#222461)

Follow the new amdgcn system so we don't have to carry 2 different
forms of this infrastructure.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+80-36llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+12-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+8-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+1-5clang/lib/Basic/Targets/AMDGPU.cpp
+2-4clang/lib/Basic/Targets/AMDGPU.h
+5-0llvm/lib/Target/AMDGPU/R600Processors.td
+108-451 files not shown
+111-457 files

LLVM/project 70e79a0llvm/lib/Target/X86/AsmParser X86AsmParser.cpp, llvm/test/MC/X86 x86_errors.s

[X86] Reject a register where a memory operand displacement belongs (#216068)

Fixes #61438
DeltaFile
+13-0llvm/test/MC/X86/x86_errors.s
+5-1llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+18-12 files

LLVM/project 7c5e5callvm/utils profcheck-xfail.txt

[ProfCheck] Removing passing tests from xfail list (#222473)

These tests appear to be passing/deleted as of 9/9/26.
DeltaFile
+0-4llvm/utils/profcheck-xfail.txt
+0-41 files

LLVM/project f1b62b8clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl

First attempt implementing InterlockedCompareExchangeFloatBitwise
DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-3clang/lib/Sema/SemaHLSL.cpp
+271-35 files not shown
+302-611 files

LLVM/project f861da9clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

First attempt implementing InterlockedCompareStoreFloatBitwise
DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+35-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+20-8clang/lib/Sema/SemaHLSL.cpp
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+251-86 files not shown
+316-1312 files

LLVM/project 31a16a5clang/lib/Sema SemaHLSL.cpp HLSLExternalSemaSource.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl RWByteAddressBuffer-InterlockedCompareExchange.hlsl

First attempt implementing InterlockedCompareExchange
DeltaFile
+113-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchange-errors.hlsl
+70-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchange.hlsl
+43-24clang/lib/Sema/HLSLExternalSemaSource.cpp
+44-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchange.hlsl
+24-12clang/lib/Sema/SemaHLSL.cpp
+35-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl
+329-366 files not shown
+417-5212 files

LLVM/project 92e630bclang/test/AST/HLSL Textures-vector-AST.hlsl Textures-scalar-AST.hlsl, clang/test/CodeGenHLSL/resources Textures-Sample.hlsl Textures-Mips.hlsl

[HLSL] Add Texture3D and RWTexture3D types (#220438)

Fixes https://github.com/llvm/llvm-project/issues/194739 and fixes
https://github.com/llvm/llvm-project/issues/194743

This PR implements Texture3D and RWTexture3D and adds+modifies tests for
the two types.

Assisted by: Claude Opus 5

---------

Co-authored-by: Finn Plummer <mail at inbelic.dev>
DeltaFile
+425-401clang/test/AST/HLSL/Textures-scalar-AST.hlsl
+424-400clang/test/AST/HLSL/Textures-vector-AST.hlsl
+54-20clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
+32-0clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
+16-9clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
+17-0clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
+968-83019 files not shown
+1,145-83325 files

LLVM/project 3cff976clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Sema HLSLExternalSemaSource.cpp

First attempt implementing InterlockedCompareStore
DeltaFile
+88-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStore-errors.hlsl
+54-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStore.hlsl
+45-7clang/lib/Sema/HLSLExternalSemaSource.cpp
+37-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStore.ll
+29-7clang/lib/CodeGen/CGHLSLBuiltins.cpp
+36-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStore.hlsl
+289-147 files not shown
+397-1613 files

LLVM/project ff2b4c2llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Count the intrinsics that really become calls when refusing promotion
DeltaFile
+81-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+30-9llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+111-92 files

LLVM/project d35391ellvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll

Do not add a second lifetime start when allocating VGPRs again
DeltaFile
+21-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+17-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+0-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+38-43 files

LLVM/project 1f7b3e5llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Promote private objects into the VGPR address space via flag
DeltaFile
+279-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+138-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+1-35llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+23-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+19-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+460-395 files

LLVM/project 5bab363llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Carry null operands and intrinsic names across when promoting to VGPRs
DeltaFile
+145-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+42-2llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+187-22 files

LLVM/project f940596llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-private-object-vgprs.mir

Propagate object liveness to every changed successor, not only back edges
DeltaFile
+56-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+14-4llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+70-42 files

LLVM/project ebb7ec3llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-budget.ll

Diagnose an object that does not fit the function's register budget
DeltaFile
+82-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-budget.ll
+36-13llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+118-132 files

LLVM/project cc91d70llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Refuse promotion only when the object is live across a call
DeltaFile
+183-4llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+117-15llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+300-192 files