LLVM/project 2479918flang/test/Integration/OpenMP map-types-and-sizes.f90, mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[MLIR][OpenMP] Add OpenMPToLLVMIRTranslation support for is_device_ptr

This PR adds support for the OpenMP is_device_ptr clause in the MLIR to LLVM IR translation for target regions. The is_device_ptr clause allows device pointers (allocated via OpenMP runtime APIs) to be used directly in target regions without implicit mapping.
DeltaFile
+46-0offload/test/offloading/fortran/target-is-device-ptr.f90
+17-0mlir/test/Target/LLVMIR/omptarget-llvm.mlir
+10-6mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-11mlir/test/Target/LLVMIR/openmp-todo.mlir
+9-0flang/test/Integration/OpenMP/map-types-and-sizes.f90
+82-175 files

LLVM/project d39f524llvm/lib/Target/PowerPC PPCInstrFuture.td PPCRegisterInfo.td, llvm/lib/Target/PowerPC/MCTargetDesc PPCInstPrinter.cpp PPCAsmBackend.cpp

[PowerPC] Implement paddis (#161572)

DeltaFile
+44-0llvm/lib/Target/PowerPC/PPCInstrFuture.td
+19-0llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+12-0llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+11-0llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+9-0llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+6-0llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
+101-06 files not shown
+125-012 files

LLVM/project a1f30c2llvm/test/CodeGen/DirectX/CBufferAccess gep-ce-two-uses.ll

[NFC] [DirectX] Update DirectX codegen test `CBufferAccess/gep-ce-two-uses.ll` due to changes to ReplaceConstant (#169848)

Fixes an LLVM DirectX codegen test after it broke due to #169141

The CBuffer loads and GEPs are no longer duplicated when there are two
or more accesses within the same basic block.
This PR removes the duplicate check for CBuffer load and GEP from the
original test function `@f` and adds a new test function `@g` which
places duplicate CBuffer loads into separate basic blocks.
DeltaFile
+16-0llvm/test/CodeGen/DirectX/CBufferAccess/gep-ce-two-uses.ll
+16-01 files

LLVM/project f5d82d2flang/lib/Lower/OpenMP OpenMP.cpp ClauseProcessor.cpp, flang/test/Lower/OpenMP target.f90

[Flang][OpenMP] Add lowering support for is_device_ptr clause

Add support for OpenMP is_device_ptr clause for target directives.
DeltaFile
+41-4flang/lib/Lower/OpenMP/OpenMP.cpp
+15-27flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+30-0flang/test/Lower/OpenMP/target.f90
+5-0mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+3-1mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td
+1-1flang/lib/Lower/OpenMP/ClauseProcessor.h
+95-336 files

LLVM/project 965c3d7lld/test/wasm wrap_import.s, lld/wasm Driver.cpp SyntheticSections.cpp

[lld][WebAssembly] Fix SEGFAULT when importing wrapped symbol (#169656)

When wrapping a symbol `foo` via `-wrap=foo`, we create the symbol
`__wrap_foo` that replaces all mentions of `foo`. This feature was
implemented for wasm-ld in commit a5ca34e.

So far, no valid signature has been attached to the undefined symbol,
leading to a nullptr dereference in the logic for creating the import
section. This change adds the correct signature to the wrapped symbol,
enabling the generation of an import for it.
DeltaFile
+32-0lld/test/wasm/wrap_import.s
+5-3lld/wasm/Driver.cpp
+3-1lld/wasm/SyntheticSections.cpp
+40-43 files

LLVM/project ee45ba2llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 fixed-length-bf16-arith.ll sve-indexed-arithmetic.ll

[AArch64] Use SVE for fixed-length bf16 operations with +sve-b16b16 (#169329)

This can avoid the promotion bf16 -> f32 -> bf16 round trip (or costly
expansions).
DeltaFile
+936-0llvm/test/CodeGen/AArch64/fixed-length-bf16-arith.ll
+18-85llvm/test/CodeGen/AArch64/sve-indexed-arithmetic.ll
+6-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+960-873 files

LLVM/project 1b7ae0bllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 aarch64-isel-umin.ll arm64-popcnt.ll

[AArch64] Use umin for x != 0 when +cssc is enabled (#169159)

Closes https://github.com/llvm/llvm-project/issues/161584
DeltaFile
+336-0llvm/test/CodeGen/AArch64/aarch64-isel-umin.ll
+6-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-2llvm/test/CodeGen/AArch64/arm64-popcnt.ll
+344-33 files

LLVM/project fd19a20llvm/include/llvm/CodeGen MachineBasicBlock.h, llvm/lib/CodeGen ShrinkWrap.cpp

Revert "[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no-return blocks" (#169852)

Reverts llvm/llvm-project#167548

As commented at
https://github.com/llvm/llvm-project/pull/167548#issuecomment-3587008602
this is causing miscompiles in two-stage RISC-V Clang/LLVM builds that
result in test failures on the builders.
DeltaFile
+0-179llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
+7-5llvm/lib/CodeGen/ShrinkWrap.cpp
+0-7llvm/include/llvm/CodeGen/MachineBasicBlock.h
+7-1913 files

LLVM/project 03c8624clang/lib/AST ExprConstant.cpp

[clang:ast] Avoid warning for unused var without assertions. (NFC) (#169822)

This PR avoids a compiler warning, which turns into an error with
`-Werror`, for a variable introduced in #169276 and only used in an
assertion (which is, thus, unused if compiled without assertions).

Signed-off-by: Ingo Müller <ingomueller at google.com>
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
DeltaFile
+2-2clang/lib/AST/ExprConstant.cpp
+2-21 files

LLVM/project db85babllvm/lib/Transforms/Vectorize VPlanUnroll.cpp VPlanAnalysis.cpp

[VPlan] Use m_Intrinsic to match assumes/noalias_scope_decl (NFC).

Use pattern matching to check for intrinsics to slightly simplify code.
DeltaFile
+4-5llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+3-2llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+7-72 files

LLVM/project 78686bbllvm/include/llvm/CodeGen MachineBasicBlock.h, llvm/lib/CodeGen ShrinkWrap.cpp

Revert "[ShrinkWrap] Modify shrink wrapping to accommodate functions terminat…"

This reverts commit 650eeb867fa95435b7c123e6630eb98934ac5bf3.
DeltaFile
+0-179llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
+7-5llvm/lib/CodeGen/ShrinkWrap.cpp
+0-7llvm/include/llvm/CodeGen/MachineBasicBlock.h
+7-1913 files

LLVM/project bde0665openmp/runtime/src kmp_ftn_cdecl.cpp kmp_ftn_entry.h, openmp/runtime/src/include omp_lib.h.var omp_lib.F90.var

remove Fortran support for this patch
DeltaFile
+0-65openmp/runtime/test/api/omp_device_uid.f90
+30-0openmp/runtime/src/kmp_ftn_cdecl.cpp
+2-27openmp/runtime/src/kmp_ftn_entry.h
+0-21openmp/runtime/src/include/omp_lib.h.var
+0-18openmp/runtime/src/include/omp_lib.F90.var
+0-8openmp/runtime/src/kmp_ftn_os.h
+32-1396 files

LLVM/project 86bdc70mlir/lib/Dialect/Affine/IR AffineOps.cpp

[mlir][Affine] Avoid forcing a non-composable affine Inliner impl
DeltaFile
+2-1mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+2-11 files

LLVM/project 75e4438clang/lib/CodeGen SanitizerHandler.h, clang/test/DebugInfo/Generic ubsan-trap-reason-type-mismatch.c

[ubsan] Change "Type mismatch in operation" trap reason to "Alignment, null, or object-size error" (#169752)

I originally proposed this rewording when trap reasons were introduced
in
https://github.com/llvm/llvm-project/pull/145967#discussion_r2196212344.
This was not adopted because there was a counter-proposal to split the
enum; however, that work appears to have stalled
(https://github.com/llvm/llvm-project/pull/151243). In the meantime,
there has been an additional datapoint that the current wording is
confusing to users. Thus, let's reword it now to prevent further
confusion.
DeltaFile
+1-1clang/lib/CodeGen/SanitizerHandler.h
+1-1clang/test/DebugInfo/Generic/ubsan-trap-reason-type-mismatch.c
+2-22 files

LLVM/project 8397945clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp

[clang][CIR] Fix build after builtins removal. NFC
DeltaFile
+0-10clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+0-101 files

LLVM/project a1ca690llvm/lib/Target/AArch64 AArch64PerfectShuffle.h AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 reduce-shuffle.ll insert-extend.ll

[AArch64] recognise zip1/zip2 with flipped operands (#167235)

Currently, the following two snippets get treated very differently from
each other (https://godbolt.org/z/rYGj9TGz6):
```LLVM
define <8 x i8> @foo(<8 x i8> %x, <8 x i8> %y) local_unnamed_addr #0 {
entry:
  %0 = shufflevector <8 x i8> %x, <8 x i8> %y, <8 x i32>
       <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
  ret <8 x i8> %0
}

define <8 x i8> @bar(<8 x i8> %x, <8 x i8> %y) local_unnamed_addr #0 {
entry:
  %0 = shufflevector <8 x i8> %x, <8 x i8> %y, <8 x i32>
       <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3>
  ret <8 x i8> %0
}
```

    [39 lines not shown]
DeltaFile
+82-84llvm/test/CodeGen/AArch64/reduce-shuffle.ll
+36-36llvm/test/CodeGen/AArch64/insert-extend.ll
+39-22llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
+12-36llvm/test/CodeGen/AArch64/arm64-zip.ll
+11-26llvm/test/CodeGen/AArch64/insert-subvector.ll
+18-7llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+198-2114 files not shown
+207-22010 files

LLVM/project e3a28c0flang-rt/lib/cuda allocator.cpp, flang-rt/unittests/Runtime/CUDA Allocatable.cpp

[flang][cuda][NFC] Fix naming of CUFGetAssociatedStream (#169838)

DeltaFile
+3-3flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
+1-1flang/include/flang/Runtime/CUDA/allocator.h
+1-1flang-rt/lib/cuda/allocator.cpp
+5-53 files

LLVM/project 620f1f1llvm/test/CodeGen/AMDGPU global-address.ll fneg-combines-gfx1200.ll

[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)

DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/global-address.ll
+2-2llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
+2-2llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
+8-83 files

LLVM/project 58fa7e4clang/test/OpenMP irbuilder_nested_parallel_for.c ordered_codegen.cpp, llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h

Revert "[OMPIRBuilder] always leave PARALLEL via the same barrier" (#169829)

Reverts llvm/llvm-project#164586

Reverting due to buildbot failure:
https://lab.llvm.org/buildbot/#/builders/169/builds/17519
DeltaFile
+77-69llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+53-56llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+47-61clang/test/OpenMP/irbuilder_nested_parallel_for.c
+10-30clang/test/OpenMP/ordered_codegen.cpp
+20-20clang/test/OpenMP/cancel_codegen.cpp
+10-27llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+217-26317 files not shown
+263-37023 files

LLVM/project f065583llvm/lib/Transforms/Instrumentation AllocToken.cpp, llvm/test/Instrumentation/AllocToken hot-cold-new.ll

rebase

Created using spr 1.3.8-beta.1
DeltaFile
+25-0llvm/test/LTO/X86/alloc-token-hot-cold-new.ll
+12-12llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+20-0llvm/test/Instrumentation/AllocToken/hot-cold-new.ll
+57-123 files

LLVM/project 25ba298llvm/lib/Transforms/Instrumentation AllocToken.cpp, llvm/test/Instrumentation/AllocToken hot-cold-new.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+25-0llvm/test/LTO/X86/alloc-token-hot-cold-new.ll
+12-12llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+20-0llvm/test/Instrumentation/AllocToken/hot-cold-new.ll
+57-123 files

LLVM/project bcd5787llvm/lib/Transforms/Instrumentation AllocToken.cpp, llvm/test/Instrumentation/AllocToken hot-cold-new.ll

simplify copts, add extra tests

Created using spr 1.3.8-beta.1
DeltaFile
+25-0llvm/test/LTO/X86/alloc-token-hot-cold-new.ll
+12-12llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+20-0llvm/test/Instrumentation/AllocToken/hot-cold-new.ll
+57-123 files

LLVM/project fb94261libc/cmake/modules LLVMLibCArchitectures.cmake, libc/include/sys syscall.h.def

[libc][darwin] add syscall numbers from macos sdk (#166354)

This PR adds support to include syscall.h from MacOS sdk by explicitly including the path to the sdk via `xcrun`.
DeltaFile
+31-0libc/cmake/modules/LLVMLibCArchitectures.cmake
+2-1libc/include/sys/syscall.h.def
+33-12 files

LLVM/project 39f5ff0mlir/include/mlir/Dialect/Tosa/Transforms Passes.td, mlir/lib/Dialect/Tosa/Transforms TosaArithConstantToConst.cpp CMakeLists.txt

[mlir][tosa] Introduce arith.constant -> tosa.const normalization pass (#168370)

Add a standalone pass that rewrites tensor-valued `arith.constant` ops
into `tosa.const`, normalize the TOSA backend contract.

Signed-off-by: Vitalii Shutov <vitalii.shutov at arm.com>
Co-authored-by: Shubham <shubham at arm.com>
DeltaFile
+111-0mlir/lib/Dialect/Tosa/Transforms/TosaArithConstantToConst.cpp
+100-0mlir/test/Dialect/Tosa/tosa-arith-const-to-tosa-const.mlir
+9-0mlir/include/mlir/Dialect/Tosa/Transforms/Passes.td
+1-0mlir/lib/Dialect/Tosa/Transforms/CMakeLists.txt
+221-04 files

LLVM/project 5d6d743bolt/lib/Passes Inliner.cpp, bolt/test/AArch64 inline-bti.s

[BOLT][BTI] Skip inlining BasicBlocks containing indirect tailcalls (#168403)

In the Inliner pass, tailcalls are converted to calls in the inlined
BasicBlock. If the tailcall is indirect, the `BR` is converted to `BLR`.

These instructions require different BTI landing pads at their targets.

As the targets of indirect tailcalls are unknown, inlining such blocks
is unsound for BTI: they should be skipped instead.
DeltaFile
+39-0bolt/test/AArch64/inline-bti.s
+26-0bolt/lib/Passes/Inliner.cpp
+65-02 files

LLVM/project 71290f9flang-rt/lib/runtime CMakeLists.txt

Fix modules-only condition
DeltaFile
+1-1flang-rt/lib/runtime/CMakeLists.txt
+1-11 files

LLVM/project 25d027bmlir/lib/Dialect/SCF/Transforms UpliftWhileToFor.cpp, mlir/test/Dialect/SCF uplift-while.mlir

[MLIR][SCF] Sink scf.if from scf.while before region into after region in scf-uplift-while-to-for (#165216)

When a `scf.if` directly precedes an `scf.condition` in the before
region of an `scf.while` and both share the same condition, move the if
into the after region of the loop. This helps simplify the control flow
to enable uplifting `scf.while` to `scf.for`.
DeltaFile
+78-1mlir/lib/Dialect/SCF/Transforms/UpliftWhileToFor.cpp
+31-0mlir/test/Dialect/SCF/uplift-while.mlir
+109-12 files

LLVM/project 3280227clang/include/clang/Basic BuiltinsAMDGPU.def, clang/test/SemaHIP amdgpu-gfx950-load-to-lds.hip

[HIP][AMDGPU] Remove 't' from all __builtin_*_load_lds builtins

Allows for type checking depending on the builtin signature.

stack-info: PR: https://github.com/llvm/llvm-project/pull/165389, branch: users/jmmartinez/fix/load_lds_typesignature/3
DeltaFile
+15-15clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
+3-3clang/include/clang/Basic/BuiltinsAMDGPU.def
+18-182 files

LLVM/project 48e34d9utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[mlir:bazel] Fix build broken by #169670. (#169804)

This PR adds a dependency to the `BUILD` files overlay silently added by
#169670.

Signed-off-by: Ingo Müller <ingomueller at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project e0c0075llvm/lib/Target/SPIRV SPIRVCommandLine.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2 disabled-on-amd.ll

[SPIRV][AMD] Disable SPV_KHR_float_control2 for AMD flavored SPIRV (#169659)

AMD uses the translator to recover LLVM-IR from SPIRV.

Currently, the translator doesn't implement the
`SPV_KHR_float_controls2` extension (I'm working on it).
If this extension is used by the SPIRV module, we cannot translate it
back to LLVM-IR.

I'm working on the extension, but in the meantime, lets just disable it
when the target triple's vendor is `amd`.
DeltaFile
+22-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll
+6-0llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+28-02 files