[WIP][PAC][libunwind] Handle LR and IP signing around sigreturn frame
Support stepping through sigreturn frame in PtrAuth-protected libunwind.
Unfortunately, this involves signing non-protected IP value from
sigcontext struct saved on the stack by the kernel.
[HLSL] Add WaveActiveAllEqual functions (#183634)
This PR adds the WaveActiveAllEqual function to HLSL.
It also adds extra macro logic to CGHLSLBuiltins so that you can specify
a different intrinsic name for the SPIRV intrinsic.
Fixes https://github.com/llvm/llvm-project/issues/99162
[Clang][UnsafeBufferUsage] Warn about two-arg string_view constructors. (#180471)
"This patch extends the unsafe buffer usage warning to cover
std::string_view constructors that take a pointer and size, similar to
the existing check for std::span.
The warning message has been updated to be generic ('container
construction' instead of 'span construction') and existing tests have
been updated to match.
Fixes #166644."
[flang][NFC] Converted five tests from old lowering to new lowering (part 24) (#184538)
Tests converted from test/Lower/Intrinsics: atan2d.f90, atan2pi.f90,
atand.f90, atanpi.f90, bessel_jn.f90
ValueTracking: Teach computeKnownFPClass to look at bitcast + integer max
The returned class will still be one of the bitpatterns.
This pattern is used in rocm device libraries in assorted functions, e.g.,
https://github.com/ROCm/llvm-project/blob/amd-staging/amd/device-libs/ocml/src/rlen3F.cl#L20
I believe it is blocking the eliminationg of finite checks in some of the more
complex functions.
[RISCV] Allow unsigned immediates for pli.h, pli.dh, pli.w (#184554)
Allow unsigned immediates that look like like simm10 when only
considering the lower 16 or 32 bits. For pli.dh and pli.dh this
[652024,65535]. For pli.w, this is [4294966784,4294967295].
Since we're only inserting 16 or 32 bits, it makes sense to me that only
those 16 or 32 bits matter. This is similar to how we allow `li a0,
0xffffffff` on RV32.
[lldb] Make the PluginManager thread safe (#184452)
In #184273, John pointed out that the PluginManager is currently not
thread safe. While we don't currently provide any guarantees, it seems
desirable to be able to interact safely with the PluginManager from
different threads. For example, we allow dynamically loading plugins
from the command interpreter, which in theory could be coming from
different threads.
[clang-tidy] Don't report unnamed params for misc-const-correctness (#184388)
Previously misc-const-correctness warned about non-const unnamed
parameters; but this commit excludes them because these warnings are not
actually useful. An unnamed parameter cannot be referenced at all, so
marking them as 'const' doesn't add additional information.
Also the diagnostic messages look awkward without a name.
Fixes #184330
Revert "Silence -Wunused-parameter warnings in Unwind-wasm.c" (#175776)
Reverts llvm/llvm-project#125412
See the discussion in #125412 for why this is necessary. The summary is
that:
- Eliding arguments is the C23 extension, but libunwind builds its C
files with `-std=c99`, so this change broke the build.
- `-Wno-unused-parameter` is part of the build for libunwind, so the
codebase does allow them.
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs
These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.
Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
[AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Implement CFI for non-kernel functions
This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.
Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Emit entry function Dwarf CFI
Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.
Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[Clang] Default to async unwind tables for amdgcn
To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.
There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.
Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
[CodeGen] Treat hasOrderedMemoryRef as implying arbitrary loads or stores (#182000)
This prevents MachineSink from sinking loads past fences (or any other instruction marked as hasSideEffects).
Fixes: #181708
[flang][acc] Allow orphaned acc cache directive (#184448)
While the spec allows the cache directive at the top of a loop body, the
directive has also been utilized at the top of an acc routine. This PR
removes the semantic check that rejects the cache directive outside of a
loop, allowing orphaned `!$acc cache` similar to CIR.
The OpenACC.md deviation document is updated to note this extension.
[DebugInfo] Emit DW_AT_const_value for constexpr array static members (#182442)
Clang does not emit a `DW_AT_const_value` in DWARF, while GCC does. This
patch fixes this issue through handling Array `APValues` and respective
handling in the backend through `ConstantDataSequential`
Fixes #165220
[clang-doc] Add a Mustache Markdown generator (#177221)
Adds a Markdown generator that uses Mustache templates. This patch adds
the templates themselves and implements changes to the JSONGenerator to
allow for the creation of specific files needed by the MD tests like
`all-files.json`.
This backend should be considered experimental. It satisfies all the
same tests that the current MD backend is tested against, but those
don't seem to provide full coverage for all functionality inside that
backend. It also doesn't output everything provided by JSON. It doesn't
use the MD unittests because the Mustache templates must currently be
written to files.
[AIX] Sort relocations in XCOFF object writer. (#180807)
Some relocations (like R_REF) are emitted to an offset 0 within the CSECT. If other relocations have already been emitted then the relocations are not in increasing order and the linker will emit an error. Sort the relocations before emitting to fix the problem.
[lld][Hexagon] Fix findMaskR8 missing duplex support (#183936)
findMaskR8() lacked an isDuplex() check, unlike findMaskR6(),
findMaskR11(), and findMaskR16() which all handle duplex instructions.
When the assembler generates R_HEX_8_X on a duplex SA1_addi instruction
(e.g. `{ r0 = add(r0, ##target); memw(r1+#0) = r2 }`), the wrong mask
0x00001fe0 placed relocation bits at [12:5] instead of [25:20],
corrupting the low sub-instruction (e.g. memw became memb).
Add the isDuplex() check returning 0x03f00000, and add a comprehensive
test covering all duplex instruction x relocation type combinations
across findMaskR6, findMaskR8, findMaskR11, and findMaskR16.
