LLVM/project b248569 — mlir/include/mlir/IR OpImplementation.h, mlir/include/mlir/Interfaces FoldInterfaces.h DataLayoutInterfaces.h

[mlir][ODS] Include header required by generated dialect interface declarations

Generated dialect interface declarations derive from
`mlir::DialectInterface::Base` but did not include the header declaring
it. They therefore relied on the surrounding source file to include it
first.

The dialect interface declarations now include `DialectInterface.h`.
Headers that only included it for the generated code no longer need to
and drop the include. Includes of headers that the hand-written code uses
directly are kept, even when the generated code includes them as well.

Similar to #236155 and #238735 but for the dialect interface generator.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+14-0mlir/test/mlir-tblgen/cpp-includes-dialect-interface.td
+4-0mlir/tools/mlir-tblgen/DialectInterfacesGen.cpp
+0-1mlir/include/mlir/Reducer/ReductionPatternInterface.h
+0-1mlir/include/mlir/Interfaces/FoldInterfaces.h
+0-1mlir/include/mlir/Interfaces/DataLayoutInterfaces.h
+0-1mlir/include/mlir/IR/OpImplementation.h
+18-43 files not shown
+18-79 files

LLVM/project 8d64884 — libc/src/signal CMakeLists.txt sigwait.h, libc/src/signal/linux CMakeLists.txt sigwait.cpp

[libc] Implement sigwait (#237572)

This patch implements the POSIX `sigwait` function in LLVM libc, along
with unit tests.

Part of #236167.
DeltaFile
+82-0libc/test/src/signal/sigwait_test.cpp
+43-0libc/src/signal/linux/sigwait.cpp
+26-0libc/src/signal/sigwait.h
+20-0libc/test/src/signal/CMakeLists.txt
+16-0libc/src/signal/linux/CMakeLists.txt
+7-0libc/src/signal/CMakeLists.txt
+194-04 files not shown
+207-310 files

LLVM/project 87a8ba0 — llvm/test/CodeGen/AArch64 neon-rshrn.ll

[AArch64][GlobalISel] Add test coverage to neon-rshrn.ll (#241170)
DeltaFile
+1,069-378llvm/test/CodeGen/AArch64/neon-rshrn.ll
+1,069-3781 files

LLVM/project 40a86f7 — llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/lib/Target/PowerPC PPCAsmPrinter.cpp

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+4-6llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
+5-1llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+1-2llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+1-1llvm/lib/Transforms/Utils/ModuleUtils.cpp
+1-1llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+14-132 files not shown
+17-148 files

LLVM/project 2f02a2b — llvm/test/ThinLTO/X86 cfi-split-lto-sample-profile.ll, llvm/test/Transforms/ThinLTOBitcodeWriter split-internal2.ll split-internal-alias.ll

[ThinLTO] Use .llvm. prefix when promoting split-LTO internals (#240699)

Under `-fsplit-lto-unit` (enabled by CFI), internal-linkage functions
and
globals promoted across split ThinLTO/RegularLTO boundaries received a
bare `.<md5>` module suffix without `.llvm.`, preventing SamplePGO,
InstrProfSymtab, FunctionImport, and MemProf canonicalization from
stripping the promotion suffix.

Co-authored-by: Benedict Schlüter <bschlueter at google.com>
Assisted-by: Gemini
DeltaFile
+111-0llvm/test/ThinLTO/X86/cfi-split-lto-sample-profile.ll
+12-5llvm/tools/llvm-lto2/llvm-lto2.cpp
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal-alias.ll
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/cfi_dso_local_equivalent.ll
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/cfi-relative-vtable.ll
+147-299 files not shown
+180-5515 files

LLVM/project bdd5f76 — clang/include/clang/Basic BuiltinsHexagon.td BuiltinsHexagonDep.td, libcxx/lib/abi arm64-apple-darwin.libcxxabi.v1.stable.noexceptions.nonew.abilist

Merge remote-tracking branch 'origin/main' into users/zero9178/ods-op-partitioning

# Conflicts:
#       mlir/test/lib/Dialect/Test/TestOps.h
DeltaFile
+2,968-0llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/is_fpclass.ll
+2,631-0libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.noexceptions.nonew.abilist
+2,316-0clang/include/clang/Basic/BuiltinsHexagonDep.td
+2,305-0llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
+1-2,137clang/include/clang/Basic/BuiltinsHexagon.td
+644-665llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+10,865-2,8024,307 files not shown
+92,655-46,6234,313 files

LLVM/project 2d3d39b — utils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Fixes 455976e (#241141)

This fixes 455976e75885c36945567a2157b5a9a80cbf032f (#236474).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=455976e75885c36945567a2157b5a9a80cbf032f

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+1-01 files

LLVM/project 8b53b8a — clang/lib/CodeGen CodeGenModule.cpp

Use ArrayRef

Created using spr 1.3.6-beta.1
DeltaFile
+10-8clang/lib/CodeGen/CodeGenModule.cpp
+10-81 files

LLVM/project 4d30350 — libc/cmake/modules LibcParseArguments.cmake LLVMLibCTestRules.cmake, libc/src/stdio/generic CMakeLists.txt

[libc][cmake] Indent hanging CMake lines by 4 spaces (#240832)

Indenting wrapped control-flow headers and header-line keyword lists by
2 spaces makes continuation lines visually indistinguishable from child
control blocks and sibling 2-space keyword sub-stanzas beneath them.

Updated cmake_format.py to indent wrapped control-flow headers and
header-line keyword items by 4 spaces when sibling keywords exist in the
command schema, while keeping positional arguments and single-keyword
property calls at 2 spaces. Corrected elseif base indentation so wrapped
conditions indent 4 spaces rather than 6, and reformatted the libc CMake
files.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+124-1libc/utils/cmake_format_test.py
+32-15libc/utils/cmake_format.py
+9-9libc/cmake/modules/LLVMLibCTestRules.cmake
+8-8libc/cmake/modules/LibcParseArguments.cmake
+5-5libc/utils/MPFRWrapper/CMakeLists.txt
+5-5libc/src/stdio/generic/CMakeLists.txt
+183-4322 files not shown
+216-7628 files

LLVM/project ae3a886 — mlir/tools/mlir-tblgen OpDefinitionsGen.cpp

address review comments: use to_vector_of
DeltaFile
+1-1mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+1-11 files

LLVM/project b410510 — llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx bitset.ll bitrev.ll

[LoongArch] Select [x]vbitset/[x]vbitrev for or/xor of bitcasted shl(splat(1), y)

When the shift of splat(1) is performed in a narrower element type than
the or/xor, e.g.

```llvm
  %s = shl <8 x i16> splat (i16 1), %y
  %m = bitcast <8 x i16> %s to <2 x i64>
  %r = xor <2 x i64> %x, %m
```

the existing [x]vbitset.{b/h/w} and [x]vbitrev.{b/h/w} patterns fail to
match and we emit vrepli + vsll + vor.v/vxor.v.

Fold OP(bitcast(shl(splat(1), y)), x) into
bitcast(OP(shl(splat(1), y), bitcast(x))) for OP in {or, xor} so that
the operation is done in the shift's element type and selected as a
single [x]vbitset or [x]vbitrev.

Assisted-By: LLM
DeltaFile
+39-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+6-18llvm/test/CodeGen/LoongArch/lsx/bitset.ll
+6-18llvm/test/CodeGen/LoongArch/lsx/bitrev.ll
+6-18llvm/test/CodeGen/LoongArch/lasx/bitset.ll
+6-18llvm/test/CodeGen/LoongArch/lasx/bitrev.ll
+63-725 files

LLVM/project b95a6dd — llvm/test/CodeGen/LoongArch/lasx bitset.ll bitrev.ll, llvm/test/CodeGen/LoongArch/lsx bitset.ll bitrev.ll

[LoongArch][NFC] Pre-commit tests for [x]vbitset/[x]vbitrev through bitcast

Add tests where the shift of splat(1) is done in a narrower element type
and then bitcast to the type of the or/xor operation.

Assisted-By: LLM
DeltaFile
+93-0llvm/test/CodeGen/LoongArch/lsx/bitset.ll
+93-0llvm/test/CodeGen/LoongArch/lsx/bitrev.ll
+93-0llvm/test/CodeGen/LoongArch/lasx/bitset.ll
+93-0llvm/test/CodeGen/LoongArch/lasx/bitrev.ll
+372-04 files

LLVM/project 1e9bf68 — llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx bitclr.ll

[LoongArch] Select [x]vbitclr for and-not of bitcasted shl(splat(1), y)

When the shift of splat(1) is performed in a narrower element type than
the and-not, e.g.

```llvm
  %s = shl <8 x i16> splat (i16 1), %y
  %m = bitcast <8 x i16> %s to <2 x i64>
  %n = xor <2 x i64> %m, splat (i64 -1)
  %r = and <2 x i64> %x, %n
```

the VANDN node is created in v2i64 with a bitcast operand, so the
existing [x]vbitclr.{b/h/w} patterns fail to match and we emit
vrepli + vsll + vandn.v.

Fold VANDN(bitcast(shl(splat(1), y)), x) into
bitcast(VANDN(shl(splat(1), y), bitcast(x))) so that the operation is
done in the shift's element type and selected as a single [x]vbitclr.

    [2 lines not shown]
DeltaFile
+6-18llvm/test/CodeGen/LoongArch/lsx/bitclr.ll
+6-18llvm/test/CodeGen/LoongArch/lasx/bitclr.ll
+19-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+31-363 files

LLVM/project 3701e42 — llvm/test/CodeGen/LoongArch/lasx bitclr.ll, llvm/test/CodeGen/LoongArch/lsx bitclr.ll

[LoongArch][NFC] Pre-commit tests for [x]vbitclr through bitcast

Add tests where the shift of splat(1) is done in a narrower element type
and then bitcast to the type of the and-not operation.

Assisted-By: LLM
DeltaFile
+99-0llvm/test/CodeGen/LoongArch/lsx/bitclr.ll
+99-0llvm/test/CodeGen/LoongArch/lasx/bitclr.ll
+198-02 files

LLVM/project 24b1b82 — llvm/docs LangRef.md

Drop the vp.udiv clauses about UB precedence
DeltaFile
+0-12llvm/docs/LangRef.md
+0-121 files

LLVM/project ddf2df6 — llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp

Freeze EVL in both vp.reverse + vp.splice splitting
DeltaFile
+2-2llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+2-21 files

LLVM/project 8ca8aae — llvm/docs LangRef.md, llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp

[LangRef] Make VP intrinsics with EVL > num elements non-UB

For the remaining VP intrinsics which don't access memory:

- vp.merge
- vp.reduce.*
- vp.cttz.elts
- vp.splice
- vp.reverse

These are marked as speculatable. However the LangRef states that if the EVL > the number of elements in the vector then the behaviour is undefined. The two are inconsistent, so this PR tightens the result in this scenario to be poison.

As a result the vp.reverse expansion needs to be updated to clamp the EVL so it doesn't read outside of the stack object.

vp.udiv/vp.sdiv/vp.urem/vp.srem are also included here even though they're not speculatable. They can still cause UB if division by zero or overflow occurs on any lane even when EVL > number of elts, so I've added lines to clarify this.

VP intrinsics that read/write memory need to remain UB to match how backends lower them, they just use the EVL verbatim without any clamping or checks.
DeltaFile
+24-9llvm/docs/LangRef.md
+10-5llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
+8-3llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
+4-4llvm/lib/IR/IntrinsicInst.cpp
+4-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+50-215 files

LLVM/project f21ac5f — llvm/lib/Target/AMDGPU SIOptimizeExecMasking.cpp, llvm/test/CodeGen/AMDGPU vcmp-saveexec-to-vcmpx-set-kill.mir

AMDGPU: Clear v_cmpx source kill flags locally (#240682)

clearKillFlags is potentially expensive and should be avoided. When
the v_cmp is folded into a v_cmpx at the saveexec, only kills of
registers overlapping the compare sources between the v_cmp and the
saveexec become invalid. Clear those directly when applying the fold,
instead of collecting candidate kills during matching and then
clearing every kill of the sources in the function.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+16-35llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+20-0llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
+36-352 files

LLVM/project 21b0f6b — llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/lib/Target/PowerPC PPCAsmPrinter.cpp

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+4-6llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
+5-1llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+1-2llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+1-1llvm/lib/Transforms/Utils/ModuleUtils.cpp
+1-1llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+14-132 files not shown
+17-148 files

LLVM/project 35a4eba — llvm/test/ThinLTO/X86 cfi-split-lto-sample-profile.ll, llvm/test/Transforms/ThinLTOBitcodeWriter split-internal2.ll split-internal-alias.ll

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+111-0llvm/test/ThinLTO/X86/cfi-split-lto-sample-profile.ll
+12-5llvm/tools/llvm-lto2/llvm-lto2.cpp
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal-alias.ll
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/cfi_dso_local_equivalent.ll
+6-6llvm/test/Transforms/ThinLTOBitcodeWriter/cfi-relative-vtable.ll
+147-299 files not shown
+180-5515 files

LLVM/project 5d8b5b1 — llvm/include/llvm/ProfileData InstrProf.h, llvm/lib/ProfileData InstrProf.cpp

[ProfileData] Strip .cfi suffix in InstrProfSymtab (#240955)

Under CFI jump tables, `LowerTypeTests` renames function definitions to
`<name>.cfi`. `InstrProfSymtab::getCanonicalName` did not strip `.cfi`,
preventing canonical GUID lookups from matching `.cfi` function
definitions.

Co-authored-by: Benedict Schlüter <bschlueter at google.com>
Assisted-by: Gemini
DeltaFile
+17-1llvm/unittests/ProfileData/InstrProfTest.cpp
+3-2llvm/lib/ProfileData/InstrProf.cpp
+2-2llvm/include/llvm/ProfileData/InstrProf.h
+22-53 files

LLVM/project 0cabb2d — llvm/lib/Target/AArch64 AArch64RegisterBanks.td AArch64GenRegisterBankInfo.def, llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.h AArch64RegisterBankInfo.cpp

[AArch64] Use generated instruction mappings
DeltaFile
+87-406llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+0-278llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
+136-1llvm/lib/Target/AArch64/AArch64RegisterBanks.td
+2-79llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
+225-7644 files

LLVM/project 3d296e0 — llvm/include/llvm/Target/GlobalISel RegisterBank.td, llvm/test/TableGen RegisterBankEmitter.td RegisterBankEmitter-Check.td

[TableGen] Generate instruction mappings for `RegisterBankInfo`
DeltaFile
+603-3llvm/utils/TableGen/RegisterBankEmitter.cpp
+59-0llvm/include/llvm/Target/GlobalISel/RegisterBank.td
+17-0llvm/test/TableGen/RegisterBankEmitter-Check.td
+16-0llvm/test/TableGen/RegisterBankEmitter.td
+695-34 files

LLVM/project f1185ef — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 merge-input-operands.ll

[SLP] Merge redundant input operands of binary-operator nodes (#208670)

Replaces the merged-input machinery of the preceding commits, kept in
the branch history for reference. Load-only, and restricted to
power-of-two pools: otherwise the gathered-loads path may decline the
wide load and leave the operand stuck as a gather.


Co-authored-by: Cursor <cursoragent at cursor.com>
Co-authored-by: Alexey Bataev <a.bataev at outlook.com>
DeltaFile
+29-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+3-5llvm/test/Transforms/SLPVectorizer/X86/merge-input-operands.ll
+32-62 files

LLVM/project e31360a — clang/include/clang/CIR/Dialect/IR CIRAttrs.td, clang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp

[CIR] Track flexible array members in record layout and pass to ABI
DeltaFile
+111-0clang/test/CIR/Transforms/abi-lowering/amdgpu-flexible-array.cir
+84-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-flexible-array.c
+21-6clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
+11-1clang/test/CIR/IR/record-layout.cir
+5-5clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+8-2clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+240-142 files not shown
+251-158 files

LLVM/project bcd44ae — llvm/lib/Target/BPF BPFASpaceCastSimplifyPass.cpp, llvm/test/CodeGen/BPF addr-space-simplify-6.ll

[BPF] Fix use-after-free in bpf-aspace-simplify (#240996)

BPFASpaceCastSimplifyPass rewrites
`addrspacecast M->N (getelementptr (addrspacecast N->M p))` to
`getelementptr p`. When the inner cast has no other uses, the rewrite
erases it. That cast can also be the outer cast of another chain that is
still in the worklist. The pass then reads the erased cast. Clang
crashes on this code:

```c
#define __arena __attribute__((address_space(1)))

struct hdr { int len; int flags; };
int use(int *p);

int f(void __arena *buf, long off)
{
        struct hdr __arena *h = (struct hdr __arena *)((char *)buf + off);
        return use((int *)&h->flags);

    [22 lines not shown]
DeltaFile
+24-0llvm/test/CodeGen/BPF/addr-space-simplify-6.ll
+14-8llvm/lib/Target/BPF/BPFASpaceCastSimplifyPass.cpp
+38-82 files

LLVM/project 8b147fa — llvm/lib/Target/AArch64 AArch64RegisterBanks.td AArch64GenRegisterBankInfo.def, llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.h AArch64RegisterBankInfo.cpp

[AArch64] Remove AArch64GenRegisterBankInfo.def
DeltaFile
+87-406llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+0-278llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
+135-1llvm/lib/Target/AArch64/AArch64RegisterBanks.td
+2-79llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
+224-7644 files

LLVM/project 2011c02 — llvm/include/llvm/Target/GlobalISel RegisterBank.td, llvm/test/TableGen RegisterBankEmitter.td RegisterBankEmitter-Check.td

[TableGen] Generate instruction mappings for `RegisterBankInfo`
DeltaFile
+604-3llvm/utils/TableGen/RegisterBankEmitter.cpp
+59-0llvm/include/llvm/Target/GlobalISel/RegisterBank.td
+17-0llvm/test/TableGen/RegisterBankEmitter-Check.td
+16-0llvm/test/TableGen/RegisterBankEmitter.td
+696-34 files

LLVM/project 691118c — lldb/source/Target Process.cpp

[lldb][NFC] A small cleanup in Process::ReadModuleFromMemory (#241137)

I added a check for "if corefile" right after a "if live process"
conditional. Initialize both variables in the same cond expr.
DeltaFile
+11-8lldb/source/Target/Process.cpp
+11-81 files

LLVM/project 88c1da8 — llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/lib/Target/PowerPC PPCAsmPrinter.cpp

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+4-6llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
+5-1llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+1-2llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+1-1llvm/lib/Transforms/Utils/ModuleUtils.cpp
+1-1llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+14-132 files not shown
+17-148 files