[BOLT][PAC] Warn about synchronous unwind tables
BOLT currently ignores functions with synchronous PAuth DWARF info.
When more than 10% of functions get ignored for inconsistencies, we
should emit a warning to only use asynchronous unwind tables.
See also: #165215
[BOLT][NFC] Rename Pointer Auth DWARF rewriter passes
Original names were "working titles". After initial patches are merged,
I'd like to rename these passes to names that reflect their intent
better and show their relationship to each other:
InsertNegateRAStatePass renamed to PointerAuthCFIFixup,
MarkRAStates renamed to PointerAuthCFIAnalyzer.
[BOLT] Improve InsertNegateRAStatePass::inferUnknownStates
Previous implementation used a simple heuristic. This can be improved in
several ways:
- If a BasicBlock has instruction both with known RAState and unknown RAState,
use the known states to work out the unknown ones.
- If a BasicBlock only consists of instructions with unknown RAState,
use the last known RAState from its predecessors, or the first known
from its successors to set the RAStates in the BasicBlock. This includes
error checking: all predecessors/successors should have the same RAState.
- Some BasicBlocks may only contain instructions with unknown RAState,
and have no CFG neighbors. These already have incorrect unwind info.
For these, we copy the last known RAState based on the layout order.
Updated bolt/docs/PacRetDesign.md to reflect changes.
[BOLT] Single-pass unittest for InsertNegateRAState
This commit creates a new directory: bolt/unittests/Passes, to be used
by unittests that need to register and run passes with the
BinaryFunctionPassManager.
An example test is created for InsertNegateRAState pass. Actual tests
will be added in followup commits.
[Clang][ASTImporter] Implement AST import for CXXParenListInitExpr, SubstNonTypeTemplateParmPackExpr, PseudoObjectExpr (#160904)
Add new visit functions to ASTImporter for CXXParenListInitExpr,
SubstNonTypeTemplateParmPackExpr and PseudoObjectExpr.
On CTU analysis there are lot of "cannot import unsupported AST node"
for CXXParenListInitExpr, SubstNonTypeTemplateParmPackExpr and
PseudoObjectExpr. Problem occurred after full support of Concepts in
importer.
[BOLT] Simplify RAState helpers (NFCI) (#162820)
- unify isRAStateSigned and isRAStateUnsigned to a common getRAState,
- unify setRASigned and setRAUnsigned into setRAState(MCInst, bool),
- update users of these to match the new implementations.
[MLIR][Python] add/fix docstrings in IRCore (#167063)
This PR adds all the missing doc strings in IRCore.cpp. It also
1. Normalizes all doc strings to have proper punctuation;
2. Inlines non-duplicated docstrings which are currently at the top of
the source file (and thereby possibly out of sync).
Follow-up PRs will do the same for the rest of the modules/source files.
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
[BOLT][BTI] Add MCPlusBuilder::addBTItoBBStart
This function contains most of the logic for BTI:
- it takes the BasicBlock and the instruction used to jump to it.
- then it checks if the first non-pseudo instruction is a sufficient
landing pad for the used call.
- if not, it generates the correct BTI instruction.
Also introduce the isBTIVariantCoveringCall helper to simplify the logic.
[SPIRV] Allow multiple FuncParamAttr decoration on the same id. (#166782)
According to SPIR-V spec:
> It is invalid to decorate any given id or structure member more than
one time with the same
[decoration](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Decoration),
unless explicitly allowed below for a specific decoration.
`FuncParamAttr` explicitly allows multiple uses of the decoration on the
same id, so this patch honors it.
[mlir][NFC] Split registerAndParseCLIOptions() in mlir-opt (#166538)
mlir-opt's registerAndParseCLIOptions() forces users to both register
default MLIR options and parse the command line string. Custom mlir-opt
implementations, however, may need to provide own options or own
parsing. It seems that separating the two functions makes it easier to
achieve necessary customizations.
For example, one can register "default" options, then register custom
options (not available in standard mlir-opt), then parse all of them.
Other cases include two-stage parsing where some additional options
become available based on parsed information (e.g. compilation target
can allow additional options to be present).
[OMPIRBuilder] Fix addrspace of internal critical section lock (#166459)
First, for internal variables, they are always global, so use the global
AS by default unless specified otherwise. We can't really use `0` as a
default like we do now because that has an actual meaning on some
targets, so we really need specified vs unspecified, so I used
`std::optional` which is already used in many places in OMPIRBuilder.
Second, for the critical lock variable, add an addrspace cast if needed.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
[AArch64] Consider COPY between disjoint register classes as expensive
The motivation is to allow passes such as MachineLICM to hoist trivial
FMOV instructions out of loops, where previously it didn't do so even
when the RHS is a constant.
On most architectures, these expensive move instructions have a latency
of 2-6 cycles, and certainly not cheap as a 0-1 cycle move.
[MLIR][XeGPU][TransformOps] Add set_op_layout_attr op (#166854)
Adds `transform.xegpu.set_op_layout_attr` transform op that attaches
`xegpu.layout` attribute to the target op.
[MLIR][XeGPU][TransformOps] Add get_desc_op (#166801)
Add `transform.xegpu.get_desc_op` transform op that finds a
`xegpu.create_nd_tdesc` producer op of a `Value`.
[AArch64][llvm] GICv5 instruction `GIC CDEOI` takes no operand
There was a minor oversight in commit 6836261ee; the AArch64 GICv5
instruction `GIC CDEOI` takes no operands, since the text of the
specification says:
```
The Rt field should be set to 0b11111. If the Rt field is not
set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
* The instruction is UNDEFINED.
* The instruction behaves as if the Rt field is set to 0b11111.
```
[clang][doc] Document and prefer __asm as mangled name attribute (#167226)
It's supported together with the other spellings and results in the same attribute.
Document it and prefer it in the documentation as the `asm()` spelling is C++ and GNU-only.
See: https://github.com/llvm/llvm-project/pull/167221#issuecomment-3508464545
[CodeGenPrepare] sinkCmpExpression - don't sink larger than legal integer comparisons (#166778)
A generic alternative to #166564 - make the assumption that expanding
integer comparisons will be expensive if they are larger than the largest
legal type so avoid sinking if they are also used in the current BB + any phis.
Fixes #166534
