[SPIR-V] Fix scalar to equal-width vector storage casts (#241032)
The HLSL any api recently switch from a target intrinsic to using a
vector reduce intrinsic. This made the intrinsic subject to instcombine
scalar representations of a vector.
Specifically it is possible now to produce an i64 load from <4 x i16>
storage. Pointer-cast legalization then incorrectly changed the
pointer’s element type, generating invalid OpAccessChain instructions.
The fix was to preserve the vector storage type and bitcast values for
equal-width scalar loads and stores.
IR: Add LoadInst::isAtomic and StoreInst::isAtomic
isSimple and the many callers of isAtomic on a LoadInst or StoreInst
went through the out of line opcode switch in Instruction::isAtomic.
Shadow it with an inline ordering check, like isVolatile.
CTMark instructions:u, geomean: O3 -0.05%, ThinLTO -0.08%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
IR: Check willreturn before volatility in Instruction::willReturn
Most calls are not volatile intrinsics, so check the attribute first
and skip the intrinsic volatility switch for calls without
willreturn. Found while trying to squeeze a little more out of
attributor-light, but it shows a tiny improvement with the current
defaults.
CTMark instructions:u, geomean: O3 -0.04%, ThinLTO -0.04%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AArch64][COST]Cost non-pow2 i1 and/or/xor reductions
A non-pow2 i1 vector is padded with the identity and reduced as the
promoted integer vector; the i1 umaxv/uminv lowering does not apply.
Zero identity costs one masking and, all-ones costs lane inserts.
Required to support non-power-of-2 vectorization in SLP
Assisted-by: Cursor
Pull-request: https://github.com/llvm/llvm-project/pull/238380
Reviewers: davemgreen, david-arm, huntergr-arm, paulwalker-arm, sdesmalen-arm
Reviewed-by: paulwalker-arm
ARM: Use inline register class syntax in MIR tests
Delete the registers section when unnecessary.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[Offload][Omp] Manage memory through liboffload APIs (#241895)
Remove the liboffload allocation helpers and use `olMemAlloc` and
`olMemFree`.
For allocations, this means the `HstPtr` is no longer passed and can be
dropped from the internal interfaces (many of the mechanical changes in
this PR are because of this).
For free, the kind is no longer passed and so the wrong pointer kind
errors can longer be detected.
Also, because liboffload checks on its internal structures before
calling the plugins, double_free and free_host pointers errors return
different errors (so tests are adjusted).
After this, parts of the support of `OFFLOAD_TRACK_ALLOCATION_TRACES`
are effectively dead and could be removed in a later PR.
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[lldb][Windows] Skip some tests from TestWatchLocation.py and TestSetWatchlocation.py again (#242039)
These tests are still flaky and were wrongfully re-enabled in
https://github.com/llvm/llvm-project/pull/231502.
Merge cascade
Regenerate FeatureTestMacroTable.md and convert the upstream status CSV
row updates (LWG2166, LWG3973, LWG4015, P3774R1, P3052R2) to Markdown.
LLM-aided
[libc++][docs] Use Furo theme
Adopt the shared LLVM Furo configuration and wyvern logo, widen the content area on desktop viewports, and remove page-local contents directives that duplicate Furo's navigation.
Assisted-by: Codex
[LLD][COFF] Call __delayLoadHelper2 through an absolute address on ARMNT (#240562)
The ARMNT delay-load tail merge called __delayLoadHelper2 with a bl,
which reaches only 16 MiB, and the synthetic chunk gets no range
extension thunk. With LTO the helper, which comes from a regular object
in the CRT, can end up further away than that, and the link failed with
"relocation out of range". Load its address with movw/movt and call it
with blx, with a base relocation for the new pair.
Assisted-by: Claude Opus 5.5 (Anthropic)
X86: Use inline register class syntax in MIR tests
Drop registers section when it's no longer necessary.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[lldb][docs] Rewrite lldb rst docs to md[2/2]- (#234016)
Tracking issue:
[#201242](https://github.com/llvm/llvm-project/issues/201242)
See the [migration
guide](https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines)
for more information.
this is the second part of migrating the lldb man pages from rst to md
the content conversion is provided by this pr, following the rename in
the previous pr
Depends on #234015
the first commit is from the base pr (rename), the second commit
contains the content conversion
this was prepared with rnk's fork of rst2myst and LLM-assisted cleanup.
I manually verified that the documentation renders as expected.
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AArch64: Use inline register class syntax in MIR tests
Avoid using the registers section and delete it when no longer needed.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
