LLVM/project a88b4e7clang/test/CIR/CodeGen delete-destroying.cpp, lldb/source/Symbol Function.cpp

rebase

Created using spr 1.3.7
DeltaFile
+218-9mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+145-0clang/test/CIR/CodeGen/delete-destroying.cpp
+108-0llvm/unittests/TargetParser/TripleTest.cpp
+99-0mlir/test/Dialect/AMDGPU/invalid.mlir
+74-0mlir/test/Dialect/AMDGPU/ops.mlir
+32-35lldb/source/Symbol/Function.cpp
+676-4443 files not shown
+1,373-15349 files

LLVM/project 2ff901aclang/test/CIR/CodeGen delete-destroying.cpp, lldb/source/Symbol Function.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+218-9mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+145-0clang/test/CIR/CodeGen/delete-destroying.cpp
+108-0llvm/unittests/TargetParser/TripleTest.cpp
+99-0mlir/test/Dialect/AMDGPU/invalid.mlir
+74-0mlir/test/Dialect/AMDGPU/ops.mlir
+32-35lldb/source/Symbol/Function.cpp
+676-4443 files not shown
+1,373-15349 files

LLVM/project 032b0dalibcxx/utils/libcxx/test config.py

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+2-2libcxx/utils/libcxx/test/config.py
+2-21 files

LLVM/project cd927a3libcxx/utils/libcxx/test config.py

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+1-1libcxx/utils/libcxx/test/config.py
+1-11 files

LLVM/project aa3f48flibcxx/utils/libcxx/test config.py, lld/test/wasm tls-base-non-shared-memory.s pic-static.s

split

Created using spr 1.3.7
DeltaFile
+37-0lld/test/wasm/tls-base-non-shared-memory.s
+11-4lld/wasm/Writer.cpp
+1-1libcxx/utils/libcxx/test/config.py
+1-1lld/test/wasm/pic-static.s
+50-64 files

LLVM/project c9014d3llvm/lib/Transforms/Utils LowerVectorIntrinsics.cpp, llvm/test/Transforms/PreISelIntrinsicLowering/RISCV expand-fp-math.ll

[PreISelIntrinsicLowering] Use index type for index in intrinsic expansion (#193807)

We'd chosen intptr type for the binary in review, but on reflection the
index type is probably a conceptually better fit. On riscv, these are
going to be the same, so it's purely a conceptual issue.

For the unary case, this is an actual change since we were using i64
unconditionally. This improves codegen for RV32 by avoiding the need for expensive legalization of i64 expressions for the IV.
DeltaFile
+120-0llvm/test/Transforms/PreISelIntrinsicLowering/RISCV/expand-fp-math.ll
+6-6llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
+126-62 files

LLVM/project 94a9efeflang/test/Parser/OpenMP parallel-loop-unparse.f90

Update newly appeared test
DeltaFile
+6-6flang/test/Parser/OpenMP/parallel-loop-unparse.f90
+6-61 files

LLVM/project 5f2841cllvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.7
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,685 files not shown
+875,551-22,4491,691 files

LLVM/project 70a5328llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,685 files not shown
+875,551-22,4491,691 files

LLVM/project bc6402cllvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.7
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,686 files not shown
+875,551-22,4551,692 files

LLVM/project 26ed445llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,675 files not shown
+875,369-22,3051,681 files

LLVM/project a7a7f43llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.7
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,675 files not shown
+875,369-22,3091,681 files

LLVM/project b4310f8llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,675 files not shown
+875,369-22,3091,681 files

LLVM/project 6a12242llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.7
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,675 files not shown
+875,369-22,3091,681 files

LLVM/project b96263cclang/test/CodeGenHLSL/convergence global_array.hlsl

[HLSL] Update global array convergence test (#193380)

Updates global array initialization convergence test to use static array
of resources instead of a user-defined struct with a constructor. The
test will no longer work as is once the support for user-defined
constructors is removed (#193375).
DeltaFile
+3-9clang/test/CodeGenHLSL/convergence/global_array.hlsl
+3-91 files

LLVM/project 768fcebllvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,675 files not shown
+875,369-22,3091,681 files

LLVM/project bd8b993llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/hlsl-intrinsics log10.ll

[SPIR-V] Fix half precision OpConstant for log10/exp10 lowering (#193730)
DeltaFile
+23-4llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
+19-7llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+25-0llvm/test/CodeGen/SPIRV/llvm-intrinsics/exp10-glsl.ll
+67-113 files

LLVM/project 1e690a2clang/include/clang/Basic HLSLIntrinsics.td Builtins.td, clang/lib/CodeGen CGHLSLBuiltins.cpp

[HLSL][DXIL][SPIRV] Added DeviceMemoryBarrier() and AllMemoryBarrier() intrinsics (#190633)

From issue #99105, #99076, #99090, #99106 and adds the implementation of
DeviceMemoryBarrier(WithGroupSync) and AllMemoryBarrier(WithGroupSync)
to DXIL and SPIRV.
DeltaFile
+53-1clang/include/clang/Basic/HLSLIntrinsics.td
+29-6llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+24-0clang/include/clang/Basic/Builtins.td
+22-0clang/lib/CodeGen/CGHLSLBuiltins.cpp
+20-0clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrier.hlsl
+20-0clang/test/CodeGenHLSL/builtins/AllMemoryBarrierWithGroupSync.hlsl
+168-720 files not shown
+363-1026 files

LLVM/project d25a229llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp, llvm/test/CodeGen/AArch64/GlobalISel localizer-arm64-tti.ll

Merge branch 'main' into users/kparzysz/no-begin-loop-directive
DeltaFile
+551-551llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
+33-576llvm/utils/lit/lit/TestRunner.py
+0-577llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
+136-321llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+177-239llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
+342-0llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
+1,239-2,264353 files not shown
+10,468-3,927359 files

LLVM/project b53aeabllvm/test/CodeGen/X86 pr193700.ll

[X86] Add test coverage for #193700 (#193819)

Shows failure to scalarize partial vector code
DeltaFile
+112-0llvm/test/CodeGen/X86/pr193700.ll
+112-01 files

LLVM/project 36d19f5mlir/lib/Transforms Mem2Reg.cpp, mlir/test/Transforms mem2reg.mlir

[MLIR][Mem2Reg] Ensure dominance of default value in regions (#193708)

When we promote an allocation, and a default value for a load from an
uninitialized slot is required, this value used to get inserted in the
same block as the allocation. However, in some cases, the default value
needs to be available in the predecessor blocks so that they can pass it
to the block of the allocation as an argument. For example, this is the
case for loops containing an allocation where the promoted value will
become and IV.

Make sure the default value is always available to all blocks by
creating it in the entry block of the region.

For reference, this is what used to be the output for the test. Note the
use of `%1`.
```
  "func.func"() <{function_type = (f64) -> (), sym_name = "poison_insertion_point"}> ({
  ^bb0(%arg0: f64):
    "cf.br"(%1)[^bb1] : (f64) -> ()

    [16 lines not shown]
DeltaFile
+28-0mlir/test/Transforms/mem2reg.mlir
+1-1mlir/lib/Transforms/Mem2Reg.cpp
+29-12 files

LLVM/project dc36e5dflang/include/flang/Parser parse-tree.h, flang/lib/Parser openmp-parsers.cpp

[flang][OpenMP] Make OpenMPLoopConstruct inherit from OmpBlockConstruct

Conceptually OpenMPLoopConstruct has the exact same structure as
OmpBlockConstruct: directive specification for the begin directive,
optional one for the end directive, and a block of code.
The reason why OpenMPLoopConstruct was not originally made to be
a descendant of OmpBlockConstruct was to preserve the behavior of
AST visitors, where a separate (type-based) visitor could be defined
for the begin/end directives of a block construct, and for a loop
construct. The AST nodes representing the begin/end directives in
block and loop construct had different types: Omp{Begin|End}Directive
for block constructs, and Omp{Begin|End}LoopDirective for loop
constructs.
Today this distinction is not needed anywhere, and so the loop
construct will be represented in the same way as a block construct.
DeltaFile
+15-15flang/test/Parser/OpenMP/order-clause01.f90
+0-26flang/lib/Semantics/check-omp-loop.cpp
+2-22flang/include/flang/Parser/parse-tree.h
+6-6flang/lib/Parser/openmp-parsers.cpp
+6-6flang/test/Parser/OpenMP/loop-transformation-construct02.f90
+11-1flang/lib/Semantics/check-omp-structure.cpp
+40-7646 files not shown
+117-19252 files

LLVM/project a6ab955clang/lib/Driver/ToolChains Darwin.cpp, clang/test/Driver darwin-objc-selector-stubs.m

[Darwin] Remove linker version checks for objc_msgSend selector stubs (#193637)

Remove the getLinkerVersion checks that gated default enablement of
-fobjc-msgsend-selector-stubs and -fobjc-msgsend-class-selector-stubs on
AArch64 Darwin targets.

The linker support for these stubs was added a long time ago, so the
version checks are no longer necessary. Additionally, getLinkerVersion
returns the version of the linker that was used to build clang, which
can differ from the linker actually used at invocation time, making the
check unreliable.
DeltaFile
+14-43clang/test/Driver/darwin-objc-selector-stubs.m
+2-4clang/lib/Driver/ToolChains/Darwin.cpp
+16-472 files

LLVM/project 00d5768llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/CodeGen/AArch64 ldst-opt.ll

rebase

Created using spr 1.3.7
DeltaFile
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+192-2,277llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+950-380llvm/test/CodeGen/AArch64/ldst-opt.ll
+209-906llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+551-551llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
+977-0llvm/test/CodeGen/AMDGPU/packed-dependencies.mir
+3,205-8,740629 files not shown
+17,525-16,853635 files

LLVM/project f63bd03clang/lib/CIR/CodeGen CIRGenExpr.cpp, clang/test/CIR/CodeGen cast-lvalue-conv.cpp

[CIR] Handle CK_UserDefinedConversion and related casts in emitCastLValue (#193611)

`emitCastLValue` was hitting an NYI error for
`CK_UserDefinedConversion`, `CK_ConstructorConversion`,
`CK_CPointerToObjCPointerCast`, `CK_BlockPointerToObjCPointerCast`, and
`CK_LValueToRValue`. Classic codegen handles all of these as a
pass-through to the sub-expression (`CGExpr.cpp:6197`), and CIR should
do the same.

Made with [Cursor](https://cursor.com)
DeltaFile
+57-0clang/test/CIR/CodeGen/cast-lvalue-conv.cpp
+7-5clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+64-52 files

LLVM/project 44a1d74lld/test/wasm tls-base-non-shared-memory.s pic-static.s, lld/wasm Writer.cpp

[lld][WebAssembly] Always initialize fixed `__tls_base` in single threaded mode (#193563)

Without this fix `__tls_base` can remain set to zero which leads
`__builtin_thread_pointer` to return NULL, which is should not.

See https://github.com/emscripten-core/emscripten/pull/26747
DeltaFile
+37-0lld/test/wasm/tls-base-non-shared-memory.s
+11-4lld/wasm/Writer.cpp
+1-1lld/test/wasm/pic-static.s
+49-53 files

LLVM/project 0bdaf63mlir/lib/IR ODSSupport.cpp, mlir/test/IR invalid-properties.mlir

[mlir] Enhance error messages for attribute type mismatch in properties (#193758)
DeltaFile
+8-9mlir/lib/IR/ODSSupport.cpp
+5-5mlir/test/IR/invalid-properties.mlir
+6-2mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+3-1mlir/tools/mlir-tblgen/OpFormatGen.cpp
+22-174 files

LLVM/project 86230d5clang/lib/CIR/CodeGen CIRGenExprComplex.cpp CIRGenDecl.cpp, clang/test/CIR/CodeGen vla.c

[CIR] Implement VLA cast for ComplexType (#193583)

Implement VLA cast support for ComplexType

Issue #192331
DeltaFile
+60-0clang/test/CIR/CodeGen/vla.c
+2-10clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
+1-1clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+63-113 files

LLVM/project 1639ac0llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp

[AMDGPU] Add `.amdgpu.info` section for per-function metadata

AMDGPU object linking requires the linker to propagate resource usage
(registers, stack, LDS) across translation units. To support this, the compiler
must emit per-function metadata and call graph edges in the relocatable object
so the linker can compute whole-program resource requirements.

This PR introduces a `.amdgpu.info` ELF section using a tagged, length-prefixed
binary format: each entry is encoded as:

```
[kind: u8] [len: u8] [payload: <len> bytes]
```

A function scope is opened by an `INFO_FUNC` entry (containing a symbol
reference), followed by per-function attributes (register counts, flags, private
segment size) and relational edges (direct calls, LDS uses, indirect call
signatures). String data such as function type signatures is stored in a
companion `.amdgpu.strtab` section.

    [4 lines not shown]
DeltaFile
+221-0llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll
+185-0llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+155-2llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+126-0llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s
+113-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+106-0llvm/docs/AMDGPUUsage.rst
+906-29 files not shown
+1,215-1415 files

LLVM/project 4b16ba1flang/lib/Lower/OpenMP DataSharingProcessor.cpp OpenMP.cpp, flang/test/Lower/OpenMP metadirective-target-device.f90 metadirective-device-isa.f90

Fix metadirective lowering for spliced DO loop symbols

spliceAssociatedDoEval moves the associated DO eval into the
metadirective's eval tree, but the parse tree is unchanged. Code that
walks the parse tree (DSP symbol collection, genTargetOp implicit
capture) misses loop body symbols entirely.

Teach DataSharingProcessor and genTargetOp to also walk nested evals
when processing a metadirective. Fix test CHECK patterns for delayed
privatization on wsloop and function signatures with arguments.
DeltaFile
+62-1flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
+24-1flang/lib/Lower/OpenMP/OpenMP.cpp
+14-0flang/lib/Lower/OpenMP/Utils.cpp
+4-4flang/test/Lower/OpenMP/metadirective-target-device.f90
+3-3flang/test/Lower/OpenMP/metadirective-device-isa.f90
+2-0flang/lib/Lower/OpenMP/Utils.h
+109-96 files