LLVM/project a1c003emlir/lib/Conversion/ArithAndMathToAPFloat MathToAPFloat.cpp

vectorize fma
DeltaFile
+50-22mlir/lib/Conversion/ArithAndMathToAPFloat/MathToAPFloat.cpp
+50-221 files

LLVM/project 8cfa36dllvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rv32p.ll

[RISCV] Support i32 (S/U)(ADD/SUB)SAT for rv32ip. (#173693)

DeltaFile
+133-0llvm/test/CodeGen/RISCV/rv32p.ll
+11-8llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+4-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+148-83 files

LLVM/project 75dd5b3llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Improve SimplifyDemandedFPClass copysign handling
 (#175026)

Recognize cases where the signbit is known.
DeltaFile
+88-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+26-4llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+114-42 files

LLVM/project 7ac96edcross-project-tests/veclib veclib-sincos.c

Update veclib-sincos.c test checks (NFC)
DeltaFile
+2-2cross-project-tests/veclib/veclib-sincos.c
+2-21 files

LLVM/project dcd11famlir/lib/Conversion/ArithAndMathToAPFloat MathToAPFloat.cpp

vectorize fma
DeltaFile
+48-14mlir/lib/Conversion/ArithAndMathToAPFloat/MathToAPFloat.cpp
+48-141 files

LLVM/project 41bd7d3libc/src/__support/wctype/conversion/utils slice.h

remove explicit U
DeltaFile
+1-1libc/src/__support/wctype/conversion/utils/slice.h
+1-11 files

LLVM/project 690d94bllvm/test/TableGen multiple-type-casts-patfrags.td dag-isel-regclass-emit-enum.td, llvm/utils/TableGen DAGISelMatcherEmitter.cpp

[TableGen] Print MVT name in the isel table when it doesn't require a VBR. NFC (#175128)

If the MVT is small enough, we can emit the enum name instead of
printing its encoding.
DeltaFile
+4-4llvm/test/TableGen/multiple-type-casts-patfrags.td
+6-0llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+2-2llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+2-2llvm/test/TableGen/CPtrWildcard.td
+14-84 files

LLVM/project 7177131llvm/lib/Target/AArch64 AArch64Features.td, llvm/unittests/TargetParser TargetParserTest.cpp

[AArch64][llvm] Add extra dependencies for recently added features

Add a couple of extra dependencies, for recently added features:
```
   FeatureMTETC   -> enable FeatureMTE (aka memtag)
   FeatureMOPS_GO -> enable FeatureMTE and FeatureMOPS
```
DeltaFile
+9-0llvm/unittests/TargetParser/TargetParserTest.cpp
+2-2llvm/lib/Target/AArch64/AArch64Features.td
+11-22 files

LLVM/project 6ca6a32llvm/include/llvm/Analysis VecFuncs.def, llvm/test/Transforms/LoopVectorize/AArch64 veclib-intrinsic-calls.ll

[AArch64][VecLib] Add vector function mappings for the modf, sincos, sincospi vector intrinsics (#175098)

Following the improvements introduced in #109833 and the most recent
development of the libamath library (used by `-fveclib=ArmPL`), this
patch adds the missing mappings for the functions that return literal
struct values.
DeltaFile
+358-1llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
+15-0llvm/include/llvm/Analysis/VecFuncs.def
+373-12 files

LLVM/project 84e97b7libc/src/__support/wctype/conversion/utils slice.h

rename method to `slice_form_range`
DeltaFile
+2-1libc/src/__support/wctype/conversion/utils/slice.h
+2-11 files

LLVM/project cd09aablibc/src/__support/wctype/conversion/utils slice.h

make type size_t
DeltaFile
+1-1libc/src/__support/wctype/conversion/utils/slice.h
+1-11 files

LLVM/project e927f4bclang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp, clang/lib/CIR/Dialect/IR CIRTypes.cpp

[CIR] Handle empty unions in record lowering and LLVM conversion (#172666)

Handle empty unions in CIR record lowering and LLVM conversion by
emitting padding when needed, guarding `getLargestMember` for
empty/padded unions, and lowering to empty or padded LLVM structs based
on language rules.

Added regression tests for C and C++ empty union lowering in
`clang/test/CIR/CodeGen/empty-union.c` and `empty-union.cpp`.
DeltaFile
+35-0clang/test/CIR/CodeGen/empty-union.c
+35-0clang/test/CIR/CodeGen/empty-union.cpp
+7-2clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+4-3clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+2-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+83-55 files

LLVM/project 2bd2bbbllvm/lib/Target/AArch64 AArch64Features.td, llvm/unittests/TargetParser TargetParserTest.cpp

[AArch64][llvm] Add extra dependencies for recently added features

Add a couple of extra dependencies, for recently added features:
```
   FeatureMTETC   -> enable FeatureMTE (aka memtag)
   FeatureMOPS_GO -> enable FeatureMTE and FeatureMOPS
```
DeltaFile
+7-0llvm/unittests/TargetParser/TargetParserTest.cpp
+2-2llvm/lib/Target/AArch64/AArch64Features.td
+9-22 files

LLVM/project 54a1e05compiler-rt/lib/asan asan_allocator.h, compiler-rt/lib/sanitizer_common sanitizer_platform.h sanitizer_allocator_primary32.h

[asan][AIX] Set allocator size and beginning (#144784)

On 64-bit AIX, set allocator size to 256G and set beginning to
0x0a00000000000000.

Issue: #138916

---------

Co-authored-by: Hubert Tong <hubert.reinterpretcast at gmail.com>
DeltaFile
+5-1compiler-rt/lib/sanitizer_common/sanitizer_platform.h
+4-0compiler-rt/lib/asan/asan_allocator.h
+1-0compiler-rt/lib/sanitizer_common/sanitizer_allocator_primary32.h
+10-13 files

LLVM/project 37e3af8llvm/utils/TableGen CodeEmitterGen.cpp

[LLVM][TableGen] Use integers instead of string in CodeEmitterGen CaseMap (#172885)

CodeEmitterGen CaseMap values is always a vector of integer IDs (HwMode
or instruction opcode). So change the map values to be a vector of
integers instead of strings and instead print the string form when
emitting the case statements. This will help reduce the memory footprint
by not storing potentially long strings (for opcode names) in the map.
DeltaFile
+26-17llvm/utils/TableGen/CodeEmitterGen.cpp
+26-171 files

LLVM/project c0da62allvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-unaligned-load-store.ll

[RISCV] Prevent P extension from creating unaligned scalar load/store insructions. (#174878)

The P extension requires us to use base ISA load/store instructions for
small vectors. We need to make sure we don't generate misaligned
instructions.

We'll need to do more work here if we want P and V to be enabled at the
same time, but that's a future problem.
DeltaFile
+1,210-0llvm/test/CodeGen/RISCV/rvp-unaligned-load-store.ll
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1,211-12 files

LLVM/project ddbcffamlir/lib/Conversion/ArithAndMathToAPFloat MathToAPFloat.cpp

vectorize isop and abs (but not tests)
DeltaFile
+44-45mlir/lib/Conversion/ArithAndMathToAPFloat/MathToAPFloat.cpp
+44-451 files

LLVM/project 356f151mlir/lib/Conversion/ArithAndMathToAPFloat ArithToAPFloat.cpp Utils.h

[mlir][math] Add vector support for math-to-apfloat
DeltaFile
+0-67mlir/lib/Conversion/ArithAndMathToAPFloat/ArithToAPFloat.cpp
+56-0mlir/lib/Conversion/ArithAndMathToAPFloat/Utils.h
+23-2mlir/lib/Conversion/ArithAndMathToAPFloat/Utils.cpp
+79-693 files

LLVM/project 17e226flldb/source/Symbol ObjectFile.cpp, lldb/test/Shell/ObjectFile invalid.test

[lldb] Fix crash when passing a folder in as the executable (#175181)

This is another instance where we weren't checking that the result of
FileSystem::CreateDataBuffer and unconditionally accessing it, similar
to the bug in SourceManager last week. In this particular case,
ObjectFile was assuming that we can read the contents non-zero, which
isn't true for directory nodes.

Jim figured this one out yesterday. I'm just putting up the patch and
adding a test.

rdar://167796036
DeltaFile
+8-5lldb/source/Symbol/ObjectFile.cpp
+4-0lldb/test/Shell/ObjectFile/invalid.test
+12-52 files

LLVM/project 964f9c0clang/test/Driver crash-ir-repro.cpp

[Clang][Driver] Disable crash-ir-repro.cpp on UBSan

UBSan causes the test to raise a signal, which violates the not
expectations after recent lit expectations.
DeltaFile
+5-0clang/test/Driver/crash-ir-repro.cpp
+5-01 files

LLVM/project c3a1422llvm/lib/Transforms/Scalar NaryReassociate.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline.ll

Require UniformityAnalysis instead of using cached result to avoid invalidation issues
DeltaFile
+8-8llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+6-3llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+1-1llvm/test/Transforms/NaryReassociate/AMDGPU/nary-add-uniform.ll
+15-123 files

LLVM/project 9ef06e8flang/include/flang/Parser parse-tree-visitor.h

[flang] Visit "source" member in all AST nodes

Some AST nodes had their "source" member visited by the parse tree
visitor, while others, in particular those that were handled by the
trait-based visitors, did not.

Make sure that we call the Walk function on the "source" member for
all classes that have it.
DeltaFile
+31-0flang/include/flang/Parser/parse-tree-visitor.h
+31-01 files

LLVM/project 9de4f4dlibc/src/__support/wctype/conversion/utils slice.h

add docs comment
DeltaFile
+15-0libc/src/__support/wctype/conversion/utils/slice.h
+15-01 files

LLVM/project ceb2365llvm/utils/TableGen DAGISelMatcherEmitter.cpp

[TableGen] Add a helper function for emitting an MVT in the isel table. NFC (#175127)

DeltaFile
+16-33llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+16-331 files

LLVM/project e547376llvm/test/TableGen RegClassByHwMode.td CPtrWildcard.td, llvm/utils/TableGen DAGISelMatcherEmitter.cpp

[TableGen] Change emitted comments for OPC_Scope to be more like OPC_SwitchType/Opcode. NFC (#175124)

DeltaFile
+15-15llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+4-4llvm/test/TableGen/RegClassByHwMode.td
+2-2llvm/test/TableGen/CPtrWildcard.td
+1-1llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+22-224 files

LLVM/project 55a9855llvm/lib/Target/RISCV RISCVInstrInfoXqci.td

[RISCV] Merge multiple QC_EXTU patterns using ImmLeaf and SDNodeXForm. (#175119)

Instead of matching 6 different masks, use an ImmLeaf to detect any of
the 6 masks.

This isn't NFC because using an immediate directly will call
computeKnownBits to fill in bits that are expected to be 1, but have
been cleared because they are known 0 in the LHS of the and. We don't
have tests for this, if it's important we can switch to a ComplexPattern
to restore that behavior.
DeltaFile
+16-7llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+16-71 files

LLVM/project dcef308llvm/include/llvm/DWARFCFIChecker DWARFCFIAnalysis.h, llvm/lib/DWARFCFIChecker DWARFCFIAnalysis.cpp

[DWARF][NFC] Remove unused 'Reads' param from checkCFADiff and checkRegDiff (#174941)

DeltaFile
+3-11llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp
+0-2llvm/include/llvm/DWARFCFIChecker/DWARFCFIAnalysis.h
+3-132 files

LLVM/project a4efe12llvm/lib/Transforms/Scalar NaryReassociate.cpp

make use of uniformity in legacypass if available
DeltaFile
+7-1llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+7-11 files

LLVM/project b3d25f5llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.ldexp.ll fmul-to-ldexp.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FLDEXP (#175072)

DeltaFile
+133-10llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
+33-18llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+8-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+174-283 files

LLVM/project 7df0826llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-ptrmask.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_PTRMASK (#174889)

Add support for G_PTRMASK but we are missing p8 (buffer resource) due to
a legalizer issue in GlobalISel which does not occur on SelectionDAG:
`LLVM ERROR: unable to legalize instruction: %17:_(p8) = G_PTRMASK %0:_,
%22:_(s128) (in function: v_ptrmask_buffer_resource_variable_i48)`

Added a FIXME to indicate this issue.
DeltaFile
+8-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
+9-22 files