LLVM/project 3c67dcbllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU][SIInsertWaitcnts][NFC] Replace Wait.combined() with simple assignment (#179142)

Wait is initialized with all ~0s and by the time it reaches the updated
line it still holds the same value. So Wait.combined(AllZeroWait) is
effectively combining all ~0s with AllZeroWait and given that combined()
returns the min() of the two it should always return AllZeroWait.

So this patch replaces the assignment with `= AllZeroWait` to make it
easier to read.
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+1-11 files

LLVM/project 955fd59clang/lib/Sema HLSLExternalSemaSource.cpp, clang/test/CodeGenHLSL resources-declared-only-once.hlsl

[HLSL] Stop redeclaration of resources types in HLSLExternalSemaSource (#178808)

During the declaration of HLSL resource types, we add a delay to the
completion of such declarations to happen during
`HLSLExternalSemaSource::CompleteType`. Such might cause the parser to
declare the resources twice, like here
https://hlsl.godbolt.org/z/aT4b1Goeb, triggering an assert.

This patch fixes this issue by removing the resources out of the
completions declaration list once they are declared.

Fix: #153619
DeltaFile
+6-0clang/test/CodeGenHLSL/resources-declared-only-once.hlsl
+1-0clang/lib/Sema/HLSLExternalSemaSource.cpp
+7-02 files

LLVM/project ecac6b2llvm/lib/Transforms/Scalar SeparateConstOffsetFromGEP.cpp, llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU xor-decompose.ll

Revert "[SeparateConstOffsetFromGEP] Decompose constant xor operand if possib…"

This reverts commit 77044f944ccdf5f580e8dbacfad65b784c4734fe.
DeltaFile
+0-435llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll
+4-81llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+4-5162 files

LLVM/project 5a4754dllvm/lib/Analysis IVDescriptors.cpp InlineCost.cpp

[perf] Replace copy-assign by move-assign in llvm/lib/Analysis/* (#178169)

DeltaFile
+4-5llvm/lib/Analysis/IVDescriptors.cpp
+1-1llvm/lib/Analysis/InlineCost.cpp
+1-1llvm/lib/Analysis/LoopUnrollAnalyzer.cpp
+6-73 files

LLVM/project e8eb57allvm/lib/IR AutoUpgrade.cpp, llvm/test/Verifier issue176674.ll issue176674_1.ll

Revert "[AutoUpgrade] Prevent deletion of call if uses still exist (#177606)"

This reverts commit 3007e2f050bd36e5e8dab68a5c9abbfbf4561314.
DeltaFile
+25-40llvm/lib/IR/AutoUpgrade.cpp
+0-9llvm/test/Verifier/issue176674.ll
+0-9llvm/test/Verifier/issue176674_1.ll
+25-583 files

LLVM/project 627ea6bllvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine add-shl-mul-umax.ll

Fix profile metadata propagation for umax in InstCombine

Synthesize branch weights for select instructions created from umax intrinsics to satisfy profile verification requirements.
DeltaFile
+15-12llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll
+19-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+0-1llvm/utils/profcheck-xfail.txt
+34-133 files

LLVM/project 84ef35bclang/lib/CodeGen CGHLSLBuiltins.cpp CGHLSLRuntime.h

[HLSL][Codegen][NFC] Simplify intrinsic picking (#179300)

A pattern developed to do WaveActive intrinsics in their own helpers
because some wave intrinsics on spirv lack a signed\unsigned variant.

In the case of Min and Max the variants exist on both DirectX and SPIRV.
That means we can do away with a specialized helper.
DeltaFile
+12-44clang/lib/CodeGen/CGHLSLBuiltins.cpp
+4-0clang/lib/CodeGen/CGHLSLRuntime.h
+16-442 files

LLVM/project 7b6f123libcxx/include/__iterator capacity_aware_iterator.h, libcxx/test/libcxx/iterators/capacity_aware_iter arithmetic.pass.cpp comparison.pass.cpp

[libc++] Implement a type-safe iterator for optional (#154239)

Create a new `__capacity_aware_iterator` iterator type which wraps an
existing iterator, takes its container as a template parameter, and
encodes the maximum amount of elements the container can hold. The main
objective is to prevent iterator mixups between different containers
(e.g. `vector`).
DeltaFile
+186-0libcxx/include/__iterator/capacity_aware_iterator.h
+165-0libcxx/test/libcxx/iterators/capacity_aware_iter/arithmetic.pass.cpp
+116-0libcxx/test/libcxx/iterators/capacity_aware_iter/comparison.pass.cpp
+100-0libcxx/test/std/utilities/optional/optional.iterator/compare.pass.cpp
+80-0libcxx/test/libcxx/iterators/capacity_aware_iter/dereference.pass.cpp
+63-0libcxx/test/libcxx/iterators/capacity_aware_iter/assert.pass.cpp
+710-09 files not shown
+913-715 files

LLVM/project 2a2dd17lld/MachO InputSection.cpp, lld/test/MachO arm64-branch-addend-stubs.s

[lld-macho] Fix branch relocations with addends to target actual function (#177430)

When a branch relocation has a non-zero addend (e.g., `bl _func+16`),
the linker was incorrectly computing `stub_address + addend` instead of
`function_address + addend`. This caused the branch to land in the wrong
location (past the stub section) rather than at the intended interior
point of the function.

The fix checks for non-zero addends on branch relocations and uses the
actual symbol VA in those cases. This makes sense semantically—branching
to an interior offset implies reliance on the original function's
layout, which an interposed replacement wouldn't preserve anyway.

Added test `arm64-branch-addend-stubs.s` that verifies the correct
behavior using `-flat_namespace` (which makes local symbols interposable
and thus routed through stubs).

[Assisted-by](https://t.ly/Dkjjk): Cursor IDE + claude-opus-4.5-high
DeltaFile
+80-0lld/test/MachO/arm64-branch-addend-stubs.s
+19-9lld/MachO/InputSection.cpp
+99-92 files

LLVM/project 55a5232llvm/include/llvm/CodeGen TargetLowering.h

[CodeGen] Remove legacy getTgtMemIntrinsic overload

It is now fully unused.

commit-id:028dd72d
DeltaFile
+1-19llvm/include/llvm/CodeGen/TargetLowering.h
+1-191 files

LLVM/project 8a444c4llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU waitcnt-unscoped.ll memory-legalizer-lds-dma-volatile-and-nontemporal.ll

[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics

Accurately represent both the load and the store part of those
intrinsics.

The test changes seem to be mostly fairly insignificant changes caused by
subtly different scheduler behavior.

commit-id:0269189c
DeltaFile
+61-51llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-4llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll
+2-4llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
+2-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
+68-634 files

LLVM/project 940398allvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/lib/Target/AMDGPU SIISelLowering.cpp

[CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (NFC)

This is a fairly mechanical change. Instead of returning true/false,
we either keep the Infos vector empty or push one entry.

commit-id:c7770af6
DeltaFile
+113-60llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+78-59llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+40-21llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+36-22llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+36-22llvm/lib/Target/ARM/ARMISelLowering.cpp
+26-18llvm/lib/Target/X86/X86ISelLowering.cpp
+329-20216 files not shown
+411-27522 files

LLVM/project 55d1a79llvm/include/llvm/CodeGen SelectionDAGNodes.h TargetLowering.h, llvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[CodeGen] Add getTgtMemIntrinsic overload for multiple memory operands (NFC)

There are target intrinsics that logically require two MMOs, such as
llvm.amdgcn.global.load.lds, which is a copy from global memory to LDS,
so there's both a load and a store to different addresses.

Add an overload of getTgtMemIntrinsic that produces intrinsic info in a
vector, and implement it in terms of the existing (now protected)
overload.

GlobalISel and SelectionDAG paths are updated to support multiple MMOs.
The main part of this change is supporting multiple MMOs in
MemIntrinsicNodes.

Converting the backends to using the new overload is a fairly mechanical step
that is done in a separate change in the hope that that allows reducing merging
pains during review and for downstreams. A later change will then enable
using multiple MMOs in AMDGPU.

commit-id:b4a924aa
DeltaFile
+86-32llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+64-25llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+38-29llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+19-28llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+20-3llvm/include/llvm/CodeGen/TargetLowering.h
+17-3llvm/include/llvm/CodeGen/SelectionDAG.h
+244-1204 files not shown
+250-12410 files

LLVM/project 3007e2fllvm/lib/IR AutoUpgrade.cpp, llvm/test/Verifier issue176674.ll issue176674_1.ll

[AutoUpgrade] Prevent deletion of call if uses still exist (#177606)

The calls to the llvm.x86.sse2.pshuflw are being deleted due to invalid
vector type, even though uses still exist. Adding checks to prevent
deletion of call when uses still exist or even if eraseFromParent() is
called ensuring it is called after replaceAllUsesWith().

Fixes: #176674
DeltaFile
+40-25llvm/lib/IR/AutoUpgrade.cpp
+9-0llvm/test/Verifier/issue176674.ll
+9-0llvm/test/Verifier/issue176674_1.ll
+58-253 files

LLVM/project e0a9be9lldb/source/Expression IRInterpreter.cpp, lldb/test/API/commands/expression/ir-interpreter TestIRInterpreter.py

Reapply "[lldb] Add FP conversion instructions to IR interpreter" (#179022)

This reapplies #175292 with the fixed test. The original test used
integer types with different bit widths on different platforms.

----- Original message:

This allows expressions that use these conversions to be executed when
JIT is not available.
DeltaFile
+109-0lldb/test/API/commands/expression/ir-interpreter/TestIRInterpreter.py
+86-0lldb/source/Expression/IRInterpreter.cpp
+195-02 files

LLVM/project 911acc8utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fix Bazel build for 4f9843b (#179321)

Co-authored-by: Pranav Kant <prka at google.com>
DeltaFile
+0-31utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+0-311 files

LLVM/project 603dc53llvm/include/llvm/CodeGen SelectionDAGNodes.h, llvm/lib/CodeGen/SelectionDAG InstrEmitter.cpp

Add SDNodeFlag::NoConvergent
DeltaFile
+8-2llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+3-0llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+11-22 files

LLVM/project dd5f6d7llvm/lib/Target/RISCV RISCVInstrFormatsV.td

[RISCV] Split RISCVLSUMOP tablegen class for type safety. NFC

Since loads and stores have overlapping encodings we should have
different classes to make sure they stay separate.
DeltaFile
+14-10llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+14-101 files

LLVM/project c8d233fllvm/include/llvm-c Core.h, llvm/lib/IR Core.cpp

Add C API to set this
DeltaFile
+34-0llvm/include/llvm-c/Core.h
+30-0llvm/unittests/IR/AttributesTest.cpp
+16-0llvm/lib/IR/Core.cpp
+80-03 files

LLVM/project 6bde5f4llvm/lib/AsmParser LLParser.cpp, llvm/lib/Support FloatingPointMode.cpp

Revert "XXX - syntax change"

This reverts commit 1336cd4e7d2754ea5eddf2a43c1f66c615ea40ff.
DeltaFile
+4-14llvm/lib/AsmParser/LLParser.cpp
+5-5llvm/test/Assembler/denormal_fpenv.ll
+1-1llvm/lib/Support/FloatingPointMode.cpp
+10-203 files

LLVM/project f01249dllvm/test/Assembler denormal_fpenv.ll, llvm/test/Bitcode compatibility.ll auto_upgrade_denormal_fp_math.ll

bar syntax and only print input if different from output.

Breaks update_test_checks Function Attrs comment check in the rare
case where the modes mismatch.
DeltaFile
+72-72llvm/test/Bitcode/compatibility.ll
+70-72llvm/test/Assembler/denormal_fpenv.ll
+57-57llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+48-48llvm/test/Transforms/InstSimplify/canonicalize.ll
+42-42llvm/test/Bitcode/auto_upgrade_denormal_fp_math.ll
+40-44llvm/test/Transforms/Attributor/denormal-fp-math.ll
+329-335156 files not shown
+861-848162 files

LLVM/project 5cf576bllvm/lib/AsmParser LLParser.cpp, llvm/lib/Support FloatingPointMode.cpp

XXX - syntax change
DeltaFile
+14-4llvm/lib/AsmParser/LLParser.cpp
+5-5llvm/test/Assembler/denormal_fpenv.ll
+1-1llvm/lib/Support/FloatingPointMode.cpp
+20-103 files

LLVM/project 353620fllvm/docs LangRef.rst

Documentation examples
DeltaFile
+6-0llvm/docs/LangRef.rst
+6-01 files

LLVM/project b6c7a77llvm/docs LangRef.rst

Fix links in documentation
DeltaFile
+7-6llvm/docs/LangRef.rst
+7-61 files

LLVM/project e600784llvm/include/llvm/IR Attributes.h, llvm/lib/IR Attributes.cpp

remove raw
DeltaFile
+0-8llvm/lib/IR/Attributes.cpp
+0-6llvm/include/llvm/IR/Attributes.h
+0-142 files

LLVM/project 74d83f9llvm/lib/AsmParser LLParser.cpp, llvm/test/Assembler denormal_fpenv.ll invalid_denormal_fpenv.ll

IR: Promote "denormal-fp-math" to a first class attribute

Convert "denormal-fp-math" and "denormal-fp-math-f32" into a first
class denormal_fpenv attribute. Previously the query for the effective
deormal mode involved two string attribute queries with parsing. I'm
introducing more uses of this, so it makes sense to convert this
to a more efficient encoding. The old representation was also awkward
since it was split across two separate attributes. The new encoding
just stores the default and float modes as bitfields, largely avoiding
the need to consider if the other mode is set.

The syntax in the common cases looks like this:
  `denormal_fpenv(preservesign,preservesign)`
  `denormal_fpenv(float: preservesign,preservesign)`
  `denormal_fpenv(dynamic,dynamic float: preservesign,preservesign)`

I wasn't sure about reusing the float type name instead of adding a
new keyword. It's parsed as a type but only accepts float. I'm also
debating switching the name to subnormal to match the current

    [18 lines not shown]
DeltaFile
+374-0llvm/test/Bitcode/auto_upgrade_denormal_fp_math.ll
+297-0llvm/test/Assembler/denormal_fpenv.ll
+228-2llvm/test/Bitcode/compatibility.ll
+187-0llvm/test/Assembler/invalid_denormal_fpenv.ll
+57-57llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+101-0llvm/lib/AsmParser/LLParser.cpp
+1,244-59227 files not shown
+2,406-973233 files

LLVM/project 2c712feclang/include/clang/Basic DiagnosticGroups.td DiagnosticSemaKinds.td

Reorganise permissive and strict diagnostic groups
DeltaFile
+59-12clang/include/clang/Basic/DiagnosticGroups.td
+7-10clang/include/clang/Basic/DiagnosticSemaKinds.td
+66-222 files

LLVM/project 297ae8eclang/include/clang/Analysis/Analyses/LifetimeSafety Facts.h, clang/lib/Analysis/LifetimeSafety Checker.cpp LifetimeAnnotations.cpp

use-after-invalidation
DeltaFile
+280-0clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+70-5clang/lib/Analysis/LifetimeSafety/Checker.cpp
+29-0clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+25-0clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
+16-1clang/test/Sema/Inputs/lifetime-analysis.h
+13-0clang/lib/Sema/AnalysisBasedWarnings.cpp
+433-69 files not shown
+486-815 files

LLVM/project 7baf1e6llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-minnum.ll simplify-demanded-fpclass-maxnum.ll

InstCombine: Handle minnum/maxnum in SimplifyDemandedFPClass
DeltaFile
+111-180llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
+109-169llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
+11-3llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+2-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+233-3544 files

LLVM/project a86202eclang/docs ReleaseNotes.rst, clang/include/clang/Basic Builtins.td

[clang] __builtin_os_log_format has incorrect PrintfFormat Attribute argument (#178320)

The format string is the 2nd argument of __builtin_os_log_format, thus
has index 1 instead of 0 in 0-based indexing.
The incorrect format attribute argument causes false positive
-Wunsafe-buffer-usage-in-format-attr-call warnings.

rdar://169043228
DeltaFile
+31-0clang/test/SemaCXX/warn-unsafe-buffer-usage-format-attr-builtins.cpp
+1-2clang/include/clang/Basic/Builtins.td
+1-0clang/docs/ReleaseNotes.rst
+33-23 files