LLVM/project 3d7eedcllvm/lib/Target/RISCV RISCVAsmPrinter.cpp, llvm/test/CodeGen/RISCV rv64-stackmap-nops.ll

[RISCV] Fix stackmap shadow trimming NOP size for compressed targets (#189774)

The shadow trimming loop in LowerSTACKMAP hardcoded a 4-byte decrement
per instruction, but when Zca is enabled NOPs are 2 bytes. Use NOPBytes
instead of the hardcoded 4 so the shadow is correctly trimmed on
compressed targets.

Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+14-2llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
+1-1llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+15-32 files

LLVM/project b9e01c2llvm/lib/Target/RISCV RISCVVectorPeephole.cpp, llvm/test/CodeGen/RISCV/rvv rvv-peephole-vmerge-to-vmv.mir

[RISCV] Relax VL constraint in convertSameMaskVMergeToVMv (#189797)

When converting a PseudoVMERGE_VVM to PseudoVMV_V_V, we previously
required MIVL <= TrueVL to avoid losing False elements in the tail.

Relax this constraint when the vmerge's False operand equals its
Passthru operand and the True instruction's tail policy is TU
(tail undisturbed). In this case, True's tail lanes preserve its
passthru value (which equals False and Passthru), so the conversion
is safe even when MIVL > TrueVL.

---------

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
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+72-0llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
+14-4llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+86-42 files

LLVM/project 7c260d3compiler-rt/lib/scudo/standalone combined.h

[scudo] Fix reallocate for MTE. (#190086)

For MTE, we can't use the whole size or we might trigger a segfault.
Therefore, use the exact size when MTE is enabled or the exact usable
size parameter is true.

Also, optimize out the call to getUsableSize and use a simpler
calculation.
DeltaFile
+10-1compiler-rt/lib/scudo/standalone/combined.h
+10-11 files

LLVM/project 54e480eclang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageTest.h UnsafeBufferUsage.h, clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.cpp

address comments
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+27-0clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.h
+1-7clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+4-3clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.cpp
+4-1clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.h
+36-114 files

LLVM/project 2939132llvm/lib/Target/WebAssembly/GISel WebAssemblyCallLowering.cpp, llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator args.ll args-simd.ll

[WebAssembly][GlobalISel] CallLowering `lowerFormalArguments` (#180263)

Implements `WebAssemblyCallLowering::lowerFormalArguments`

Split from #157161
DeltaFile
+233-3llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp
+209-0llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
+171-0llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
+73-0llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
+686-34 files

LLVM/project 4d8f738llvm/test/CodeGen/AMDGPU memory-legalizer-private-wavefront.ll memory-legalizer-private-workgroup.ll

Merge branch 'main' into users/ziqingluo/eng/PR-171920065
DeltaFile
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+8,449-1,355llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+8,449-1,355llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
+8,069-1,315llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+50,599-8,1233,260 files not shown
+337,211-92,5133,266 files

LLVM/project 52fb23elibc/src/__support/math log1pf.h

[libc][math] Remove static from log1pf implementation (#190042)

Reflecting changes according to
https://github.com/llvm/llvm-project/commit/823e3e001724ca2e93ce410a675f3b538f8a74b3
DeltaFile
+3-3libc/src/__support/math/log1pf.h
+3-31 files

LLVM/project e87ea84libc/config config.json, libc/src/__support CMakeLists.txt

Reapply "[libc] Finetune libc.src.__support.OSUtil.osutil dependency." (#190033) (#190065)

This reverts commit 84f23eb3113f2e75d1a2e45db1b5c570a5d2f4c5 and fix GPU
builds.
DeltaFile
+17-9libc/src/__support/CMakeLists.txt
+19-5libc/test/UnitTest/CMakeLists.txt
+21-2libc/test/UnitTest/TestLogger.cpp
+6-0libc/src/unistd/CMakeLists.txt
+6-0libc/src/time/linux/CMakeLists.txt
+6-0libc/config/config.json
+75-163 files not shown
+83-179 files

LLVM/project e5a7a9aclang/cmake/caches Fuchsia-stage2.cmake

[Fuchsia] Cortex-m33 runtime libraries hard float ABI (#190023)

Make cortex-m33 runtime libraries build to use hard float ABI instead of
softfp.
DeltaFile
+2-2clang/cmake/caches/Fuchsia-stage2.cmake
+2-21 files

LLVM/project b3ca423mlir/lib/Dialect/Vector/Transforms VectorUnroll.cpp, mlir/test/Dialect/Vector vector-unroll-options.mlir

[MLIR][Vector] Enhance vector.multi_reduction unrolling to handle scalar result (#188633)

Previously, UnrollMultiReductionPattern bailed out when all the
dimensions were reduced to a scalar. This PR adds support for this case
by tiling the source vector and chaining partial reductions through the
accumulator operand.
DeltaFile
+25-6mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
+8-6mlir/test/Dialect/Vector/vector-unroll-options.mlir
+33-122 files

LLVM/project 1a1fbf9mlir/lib/Dialect/XeGPU/Transforms XeGPUWgToSgDistribute.cpp, mlir/test/Dialect/XeGPU xegpu-wg-to-sg-unify-ops-rr.mlir xegpu-wg-to-sg-rr.mlir

[MLIR][XeGPU] Support round-robin layout for constant and broadcast in wg-to-sg distribution (#189798)

As title.
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+26-0mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
+17-7mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+1-1mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
+44-83 files

LLVM/project 7d24b17llvm/lib/Target/RISCV RISCVOptWInstrs.cpp, llvm/test/CodeGen/RISCV opt-w-instrs-p-ext.mir

[RISCV] Add SATI_RV64/USATI_RV64 to RISCVOptWInstrs. (#190030)

Note the immediates for these 2 instructions in their MachineInstr
representations both use the type width. The SATI_RV64 binary encoding
and the RISCVISD::SATI encoding uses the type width minus one.

Assisted-by: Claude Sonnet 4.5
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+128-0llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
+8-0llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+136-02 files

LLVM/project a9df7c7llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU bf16-math.ll

[AMDGPU] True16 support for bf16 clamp pattern on gfx1250 (#190036)
DeltaFile
+174-55llvm/test/CodeGen/AMDGPU/bf16-math.ll
+9-1llvm/lib/Target/AMDGPU/SIInstructions.td
+183-562 files

LLVM/project c6669c4llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 fma-conversion-multi-use-guard.ll

[SLP] Guard FMulAdd conversion to require single-use/non-reordered FMul operands

The FMulAdd (CombinedVectorize) transformation in transformNodes() marks
an FMul child entry with zero cost, assuming it is fully absorbed into
the fmuladd intrinsic. However, when any FMul scalar has multiple uses
(e.g., also stored separately), the FMul must survive as a separate
node.

Reviewers: hiraditya, RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/189692
DeltaFile
+6-14llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
+16-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+22-142 files

LLVM/project 6c92374llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor/AMDGPU nofpclass-amdgcn-fract.ll

ValueTracking: llvm.amdgcn.fract cannot introduce overflow (#189002)

This returns a value with an absolute value less than 1.
DeltaFile
+26-0llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll
+2-1llvm/lib/Analysis/ValueTracking.cpp
+28-12 files

LLVM/project 478a6ablldb/packages/Python/lldbsuite/test/make Makefile.rules

[lldb/test] Codesign executables built with custom Makefile rules (#189902)

Tests with custom a.out targets in their Makefile (i.e.
`TestBSDArchives.py`) bypass the standard Makefile.rules linking step
where `CODESIGN` is applied. This leaves the binary unsigned, causing
the process to get kill it on remote darwin devices.

This adds a codesigning step to the all target in Makefile.rules that
signs both $(EXE) and a.out if they exist. This ensures all test
binaries are signed regardless of how they were built.

rdar://173840592

Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
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+7-0lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+7-01 files

LLVM/project b75bf1eclang/docs ReleaseNotes.rst, clang/lib/Analysis ThreadSafety.cpp

Revert "Thread Safety Analysis: Drop call-based alias invalidation (#187691)" (#190041)

This reverts commit 873d6bc3b415f1c2d942bbf4e4219c4bdcd4f2f8.

This causes Linux kernel build to fail because it relied on
alias-invalidation in kernel/core/sched.c.
DeltaFile
+52-0clang/lib/Analysis/ThreadSafety.cpp
+11-26clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+0-5clang/docs/ReleaseNotes.rst
+63-313 files

LLVM/project 9f50004mlir/lib/Dialect/XeGPU/Transforms XeGPUPeepHoleOptimizer.cpp, mlir/test/Dialect/XeGPU peephole-optimize.mlir

[MLIR][XeGPU] Enhance the peephole optimization to remove the convert_layout after multi-reduction rewrite (#188849)
DeltaFile
+57-28mlir/test/Dialect/XeGPU/peephole-optimize.mlir
+25-0mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
+82-282 files

LLVM/project 09264aeoffload CMakeLists.txt

Merge commit '61a43720f3e31357ff3842a02d5460e71e4062a6' into HEAD
DeltaFile
+0-114offload/CMakeLists.txt
+0-1141 files

LLVM/project 61a4372offload CMakeLists.txt

Merge commit '1e19b4364dd3f827e4110b0bc14ec31bf5bbaf59' into HEAD
DeltaFile
+0-115offload/CMakeLists.txt
+0-1151 files

LLVM/project 1e19b43offload CMakeLists.txt

Fix incomplete merge
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+0-115offload/CMakeLists.txt
+0-1151 files

LLVM/project d6d0876llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[NFC][SelectionDAG] Refactor out common default `DemandedElts` calculation (#190031)

Deduplicating the repeated pattern
```cpp
APInt DemandedElts = VT.isFixedLengthVector()
                         ? APInt::getAllOnes(VT.getVectorNumElements())
                         : APInt(1, 1);
```
in SelectionDAG.
DeltaFile
+26-85llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+26-851 files

LLVM/project d0fdb9cllvm/test/Transforms/Attributor/AMDGPU nofpclass-amdgcn-fract.ll

Update llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll

Co-authored-by: Yingwei Zheng <dtcxzyw2333 at gmail.com>
DeltaFile
+1-1llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll
+1-11 files

LLVM/project 0045d79llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU bf16-math.ll

[AMDGPU] True16 support for bf16 clamp pattern on gfx1250
DeltaFile
+174-55llvm/test/CodeGen/AMDGPU/bf16-math.ll
+9-1llvm/lib/Target/AMDGPU/SIInstructions.td
+183-562 files

LLVM/project 2b87d02clang-tools-extra/clang-tidy/tool run-clang-tidy.py

[clang-tidy] Properly escape printed clang-tidy command in `run-clang-tidy.py` (#189974)

The `run-clang-tidy.py` script now uses `shlex.join()` to construct the
command string for printing.

This ensures that arguments containing shell metacharacters, such as the
asterisk in `--warnings-as-errors=*`, are correctly quoted. This allows
the command to be safely copied and pasted into any shell for manual
execution, fixing errors previously seen with shells like `fish` that
are strict about wildcard expansion.

Before:
```
[ 1/15][0.2s] /usr/bin/clang-tidy -p=/home/user/work/project/build --warnings-as-errors=* /home/user/work/project/src/main.cpp
```

Note: When running this command in fish shell you get some error like
`fish: No matches for wildcard '--warnings-as-errors=*'. See `help
wildcards-globbing``

    [4 lines not shown]
DeltaFile
+2-1clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
+2-11 files

LLVM/project 7757006clang-tools-extra/clang-doc Representation.cpp Representation.h, clang-tools-extra/clang-doc/tool ClangDocMain.cpp

[clang-doc] Merge data into persistent memory

We have a need for persistent memory for the final info. Since each
group processes a single USR at a time, every USR is only ever processed by
a single thread from the thread pool. This means that we can keep per
thread persistent storage for all the info. There is significant
duplicated data between all the serialized records, so we can just merge
the final/unique items into the persistent arena, and clear out the
scratch/transient arena as we process each record in the bitcode.

The patch adds some APIs to help with managing the data, merging, and
allocation of data in the correct arena. It also safely merges and deep
copies data from the transient arenas into persistent storage that is
never reset until the program completes.

This patch reduces memory by another % over the previous patches,
bringing the total savings over the baseline to 57%. Runtime performance
and benchmarks stay mostly flat with modest improvements.


    [31 lines not shown]
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+134-10clang-tools-extra/clang-doc/Representation.cpp
+25-25clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
+7-0clang-tools-extra/clang-doc/Representation.h
+166-353 files

LLVM/project 93bdfe2clang-tools-extra/clang-doc Representation.cpp Representation.h

[clang-doc] Support deep copy between arenas for merging

Upcoming changes to the merge step will necessitate that we clear the
transient arenas and merge new items into the persistent arena. However
there are some challenges with that, as the existing types typically
don't want to be copied. We introduce some new APIs to simplify that
task and ensure we don't accidentally leak memory.

On the performance front, we reclaim about 2% of the overhead, bringing
the cumulative overhead from the series of patches down to about 7% over
the baseline.

| Metric | Baseline | Prev | This | Culm% | Seq% |
| :--- | :--- | :--- | :--- | :--- | :--- |
| Time | 920.5s | 1014.5s | 991.5s | +7.7% | -2.3% |
| Memory | 86.0G | 39.9G | 40.0G | -53.4% | +0.3% |

| Benchmark | Baseline | Prev | This | Culm% | Seq% |
| :--- | :--- | :--- | :--- | :--- | :--- |

    [28 lines not shown]
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+140-21clang-tools-extra/clang-doc/Representation.cpp
+30-0clang-tools-extra/clang-doc/Representation.h
+170-212 files

LLVM/project 707229cclang-tools-extra/clang-doc BitcodeReader.cpp Serialize.cpp, clang-tools-extra/unittests/clang-doc SerializeTest.cpp MergeTest.cpp

[clang-doc] Move Info types into arenas

Info types used to own significant chunks of data. As we move these into
local arenas, these types must be trivially destructible, to avoid
leaking resources when the arena is reset. Unfortunaly, there isn't a
good way to transition all the data types one at a time, since most of
them are tied together in some way. Further, as they're now allocated in
the arenas, they often cannot be treated the same way, and even the
aliases and interfaces put in pLace to simplify the transition cannot
cover the full range of changes required.

We also use some SFINAE tricks to avoid adding boilerplate for helper
APIs, we'd otherwise ahve to support

Though it introduces some additional churn, we also try to keep tests
from using arena allocation as much as possible, since this is not
required to test the implementation of the library. As much of the test
code needed to be rewritten anyway, we take the opportunity to
transition now.

    [41 lines not shown]
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+419-187clang-tools-extra/clang-doc/BitcodeReader.cpp
+246-189clang-tools-extra/unittests/clang-doc/SerializeTest.cpp
+196-129clang-tools-extra/unittests/clang-doc/MergeTest.cpp
+176-80clang-tools-extra/unittests/clang-doc/ClangDocTest.cpp
+137-75clang-tools-extra/clang-doc/Serialize.cpp
+71-41clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
+1,245-70114 files not shown
+1,661-95220 files

LLVM/project 759fba7clang-tools-extra/clang-doc BitcodeReader.cpp BitcodeReader.h

[clang-doc] Simplify parsing and reading bitcode blocks

Much of the logic int he readBlock implementation is boilerplate, and is
repeated for each implementation/specialization. This will become much
worse as we introduce new custom block reading logic as we migrate
towards arena allocation. In preparation for that, we're introducing the
change in logic now, which should make later refactoring much more
straightforward.
DeltaFile
+103-120clang-tools-extra/clang-doc/BitcodeReader.cpp
+5-0clang-tools-extra/clang-doc/BitcodeReader.h
+1-1clang-tools-extra/clang-doc/Representation.h
+109-1213 files

LLVM/project 4e76a79clang/lib/Format ContinuationIndenter.cpp, clang/unittests/Format FormatTest.cpp

[clang-format] fix aligning inheritance lists  and binary operator operands with UT_AlignWithSpaces (#189218)

fix aligning inheritance lists with UT_AlignWithSpaces
fix aligning binary operator operands

---------

Co-authored-by: Eugene Shalygin <e.shalygin at abberior-instruments.com>
DeltaFile
+59-0clang/unittests/Format/FormatTest.cpp
+22-1clang/lib/Format/ContinuationIndenter.cpp
+81-12 files