LLVM/project 9b645aellvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/MC/AArch64 armv9.7a-gcie.s

[AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0,1}_EL2 system registers

Add GICv5 `ICH_PPI_HVIR{0,1}_EL2` system registers (Interrupt
Controller PPI Hide Virtual Interrupt Registers). These registers
are added because a hypervisor may want to only expose a subset of the
PPIs to the virtual machine and hide the remaining PPIs.

The only way the hypervisor can do this is by trapping all the PPI ICV
registers which leads to additional code complexity and adds performance
overhead especially for nested virtualization.

These are documented here:
  https://developer.arm.com/documentation/111107/latest/AArch64-Registers/ICH-PPI-HVIR-n--EL2--Interrupt-Controller-PPI-Hide-Virtual-Interrupt-Registers
DeltaFile
+20-0llvm/test/MC/AArch64/armv9.7a-gcie.s
+1-0llvm/lib/Target/AArch64/AArch64SystemOperands.td
+21-02 files

LLVM/project f1e92beclang/test/OpenMP split_codegen.cpp, llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

Merge branch 'main' into users/usx95/04-12-annotation_inference_on_constructor
DeltaFile
+2,253-17llvm/test/CodeGen/AMDGPU/freeze.ll
+1,986-0clang/test/OpenMP/split_codegen.cpp
+875-148mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
+432-381llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+301-373llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
+309-364llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
+6,156-1,283705 files not shown
+24,757-13,778711 files

LLVM/project a2bf43dllvm/include/llvm/ExecutionEngine/Orc MachOBuilder.h, llvm/unittests/ExecutionEngine/Orc MachOBuilderTest.cpp CMakeLists.txt

[ORC] Add MachOBuilder support for LC_UUID load commands. (#191807)

Enables LC_UUID load commands to be added with the addLoadCommand
method.

This will be used in future MachOPlatform changes to add support for
adding UUIDs to MachO JITDylibs.
DeltaFile
+43-0llvm/unittests/ExecutionEngine/Orc/MachOBuilderTest.cpp
+9-0llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
+1-0llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
+53-03 files

LLVM/project b6ff43fbolt/lib/Core AddressMap.cpp, llvm/include/llvm/DebugInfo/DWARF/LowLevel DWARFDataExtractorSimple.h

[Support] Remove address-extraction methods from DataExtractor (NFC) (#190519)

Most clients don't have a notion of "address" and pass arbitrary values
(including `0` and `sizeof(void *)`) to `DataExtractor` constructors.
This makes address-extraction methods dangerous to use.

Those clients that do have a notion of address can use other methods
like `getUnsigned()` to extract an address, or they can derive from
`DataExtractor` and add convenience methods if extracting an address is
routine. `DWARFDataExtractor` is an example, where the removed methods
were actually moved.

This does not remove `AddressSize` argument of `DataExtractor`
constructors yet, but makes it unused and overloads constructors in
preparation for their deletion. I'll be removing uses of the
to-be-deleted constructors in follow-up patches.
DeltaFile
+14-47llvm/include/llvm/Support/DataExtractor.h
+50-4llvm/include/llvm/DebugInfo/DWARF/LowLevel/DWARFDataExtractorSimple.h
+26-24llvm/tools/llvm-readobj/ELFDumper.cpp
+9-7llvm/tools/obj2yaml/elf2yaml.cpp
+5-5llvm/lib/Object/ELF.cpp
+5-5bolt/lib/Core/AddressMap.cpp
+109-929 files not shown
+135-11915 files

LLVM/project d012e03llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp Utils.cpp, llvm/test/CodeGen/AArch64 known-never-nan.ll

[GISel] Use GISelValueTracking in isKnownNeverNaN (#190542)

Pass GISelValueTracking* through isKnownNeverNaN and isKnownNeverSNaN so
that the implementation can call computeKnownFPClass to derive NaN
information from value tracking, rather than only looking at flags and
direct constant definitions. Update all callers.

Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+432-381llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+408-22llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
+69-226llvm/test/CodeGen/AMDGPU/fmed3.ll
+148-0llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
+0-83llvm/lib/CodeGen/GlobalISel/Utils.cpp
+24-15llvm/test/CodeGen/AArch64/known-never-nan.ll
+1,081-72713 files not shown
+1,162-85919 files

LLVM/project 28e237allvm/test/Transforms/LoopVectorize/AArch64 reverse-load-scatter.ll, llvm/test/Transforms/LoopVectorize/RISCV reverse-load-scatter.ll

[LV] Add test for reverse load with scatter store. nfc (#189928)
DeltaFile
+53-0llvm/test/Transforms/LoopVectorize/AArch64/reverse-load-scatter.ll
+49-0llvm/test/Transforms/LoopVectorize/RISCV/reverse-load-scatter.ll
+102-02 files

LLVM/project 67f4c2dmlir/include/mlir/Dialect/Transform/IR TransformDialect.td, mlir/include/mlir/Dialect/Transform/Interfaces TransformInterfaces.td

[mlir] transform dialect; add pre/post-condition type

Add a transform dialect type denoting additional invariants on payload
IR usable for pre/post-conditions of a transformation. The invariants
are defined as a list of attributes in the type parameter, where the
attribute implements the interface for invariant-checking. This allows
clients to factor out, explicify and deduplicate precondition
verification logic.

This required adding support for Transform dialect extensions injecting
attributes into the dialects similarly to how they already do this for
operations and types.

Co-authored-by: Tim Gymnich <tim at gymni.ch>
Co-authored-by: Martin Lücke <martin.luecke at amd.com>
Assisted-by: Claude Opus 4.3 / Cursor
DeltaFile
+80-0mlir/test/Dialect/Transform/normal-forms.mlir
+46-3mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
+48-0mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
+33-7mlir/lib/Dialect/Transform/IR/TransformDialect.cpp
+40-0mlir/lib/Dialect/Transform/IR/TransformTypes.cpp
+34-0mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.td
+281-1010 files not shown
+405-1016 files

LLVM/project 3c2a9c9llvm/lib/Target/SPIRV SPIRVBuiltins.cpp, llvm/test/CodeGen/SPIRV/transcoding pown.ll rootn.ll

[SPIR-V] Fix type mismatch in scalar-to-vector promotion for mixed-type builtins (#190969)

When promoting scalar arguments to vectors for builtins like `ldexp`,
`pown`, and `rootn`, use the correct vector type matching the argument
element type instead of always using the return type: these builtins
take an integer argument but at the same time have floating point return
type

Fix `ldexp` test that does not pass spirv-val and add similar tests for
`pown` and `rootn`

related to https://github.com/llvm/llvm-project/issues/190736
DeltaFile
+40-0llvm/test/CodeGen/SPIRV/transcoding/pown.ll
+40-0llvm/test/CodeGen/SPIRV/transcoding/rootn.ll
+10-3llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+3-2llvm/test/CodeGen/SPIRV/transcoding/ldexp.ll
+93-54 files

LLVM/project a042785clang/lib/CIR/CodeGen CIRGenStmtOpenMP.cpp CIRGenStmt.cpp

[CIR][NFC] Add NYI for OMPSplitDirective stmt (#191791)

As requested by @erichkeane here:
https://github.com/llvm/llvm-project/pull/190329#issuecomment-4183615635
DeltaFile
+5-0clang/lib/CIR/CodeGen/CIRGenStmtOpenMP.cpp
+2-0clang/lib/CIR/CodeGen/CIRGenStmt.cpp
+1-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+8-03 files

LLVM/project b33c301llvm/test/Transforms/LoopVectorize epilog-vectorization-fmaxnum-reductions.ll epilog-vectorization-fixed-order-recurrences.ll, llvm/test/Transforms/LoopVectorize/AArch64 loop-vectorization-factors.ll

[LV] Extend epilogue vectorization test coverage with dead FORs/FMinMax. (#191799)

Extend test coverage with dedicated epilogue vectorization tests for
dead first-order recurrences and FMinMaxNum reductions.

Add users to FORs in existing tests where the dead FORs appeared
unintentional.
DeltaFile
+287-277llvm/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
+254-283llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
+199-0llvm/test/Transforms/LoopVectorize/epilog-vectorization-fmaxnum-reductions.ll
+188-0llvm/test/Transforms/LoopVectorize/epilog-vectorization-fixed-order-recurrences.ll
+928-5604 files

LLVM/project 883142bclang/test/Analysis cxx-uninitialized-object-union-field.cpp

Implement tests for union field initialization warnings

Add tests for uninitialized union fields in structs/classes.
DeltaFile
+57-0clang/test/Analysis/cxx-uninitialized-object-union-field.cpp
+57-01 files

LLVM/project 7083e9dcompiler-rt/test/sanitizer_common/TestCases print-stack-trace.cpp, compiler-rt/test/sanitizer_common/TestCases/Linux internal_symbolizer.cpp

XFAIL symbolizer test for TySan (#191810)
DeltaFile
+3-0compiler-rt/test/sanitizer_common/TestCases/Linux/internal_symbolizer.cpp
+2-0compiler-rt/test/sanitizer_common/TestCases/print-stack-trace.cpp
+5-02 files

LLVM/project 14f2556clang/lib/AST/ByteCode Interp.h, clang/test/AST/ByteCode cxx11.cpp

[clang][bytecode] Don't check anonymous union in memcpy op (#191783)

It's fine if they are uninitialized.
DeltaFile
+11-1clang/test/AST/ByteCode/cxx11.cpp
+4-2clang/lib/AST/ByteCode/Interp.h
+15-32 files

LLVM/project d5b8d88clang/lib/AST/ByteCode Pointer.cpp Interp.cpp, clang/test/AST/ByteCode placement-new.cpp

[clang][bytecode] Fix activating primitive array elements (#191772)

For primitive array elements, we would accidentally activate the element
and then immediate de-activate the array root, which is wrong. Ignore
the element from the beginning to the later check never even compares
with the element.
DeltaFile
+26-0clang/test/AST/ByteCode/placement-new.cpp
+5-0clang/lib/AST/ByteCode/Pointer.cpp
+2-0clang/lib/AST/ByteCode/Interp.cpp
+33-03 files

LLVM/project 628a2b5clang/lib/StaticAnalyzer/Checkers/UninitializedObject UninitializedObjectChecker.cpp

Add support for uninitialized union fields check

Implement support for checking uninitialized union fields in FindUninitializedFields.
DeltaFile
+24-2clang/lib/StaticAnalyzer/Checkers/UninitializedObject/UninitializedObjectChecker.cpp
+24-21 files

LLVM/project 4042968llvm/include/llvm/IR IntrinsicsAArch64.td, llvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp

fixup! Fix PR comments
DeltaFile
+24-70llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
+19-55llvm/test/Verifier/AArch64/luti6-intrinsics.ll
+17-36llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+15-33llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
+0-1llvm/include/llvm/IR/IntrinsicsAArch64.td
+75-1955 files

LLVM/project 45d7c0aclang/include/clang/Basic arm_sve.td, clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_luti6.c

fixup! Fix final PR comments for now
DeltaFile
+118-8clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
+5-0llvm/lib/Target/AArch64/SVEInstrFormats.td
+1-1clang/include/clang/Basic/arm_sve.td
+1-0llvm/test/Verifier/AArch64/luti6-intrinsics.ll
+125-94 files

LLVM/project dcf6276clang/lib/Sema SemaARM.cpp, clang/test/CodeGen/AArch64/sme2p3-intrinsics acle_sme2p3_luti6.c

fixup! Address more PR comments
DeltaFile
+21-3clang/lib/Sema/SemaARM.cpp
+4-12llvm/include/llvm/IR/IntrinsicsAArch64.td
+12-4clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
+6-6clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
+9-0clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_target_lane.c
+2-3llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+54-284 files not shown
+59-3410 files

LLVM/project 2e36a94llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64SVEInstrInfo.td

fixup! Address PR comments
DeltaFile
+1-10llvm/lib/Target/AArch64/AArch64InstrInfo.td
+2-2llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+3-122 files

LLVM/project ff5d3f9llvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp

fixup! Add overloaded AArch64DAGToDAGISel::EmitMultiVectorLutiLane() for reuse
DeltaFile
+39-50llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+39-501 files

LLVM/project cf6a480clang/include/clang/Basic arm_sve.td arm_sme.td, clang/test/CodeGen/AArch64/sme2p3-intrinsics acle_sme2p3_luti6.c

fixup! Adjust `def`s and split out tests
DeltaFile
+0-158clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
+138-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
+5-5clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
+0-4clang/include/clang/Basic/arm_sve.td
+1-0clang/include/clang/Basic/arm_sme.td
+144-1675 files

LLVM/project 4fa8ad0clang/lib/Sema SemaARM.cpp, clang/test/Sema/aarch64-sve2p3-intrinsics acle_sve2p3_target_lane.c

fixup! More small PR fixes
DeltaFile
+0-44llvm/test/Verifier/AArch64/luti6-intrinsics.ll
+6-9llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+5-8llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
+8-1clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_target_lane.c
+1-4llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
+1-2clang/lib/Sema/SemaARM.cpp
+21-682 files not shown
+23-698 files

LLVM/project a452e68clang/include/clang/Basic arm_sve.td, clang/lib/Sema SemaARM.cpp

fixup! Address more PR comments
DeltaFile
+3-20clang/lib/Sema/SemaARM.cpp
+0-9clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_target_lane.c
+4-1clang/include/clang/Basic/arm_sve.td
+1-1clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_target_lane.c
+8-314 files

LLVM/project 5cc9caallvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp

fixup! Reuse SelectMultiVectorLuti()
DeltaFile
+6-36llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+6-361 files

LLVM/project d10c0e2clang/test/Sema/aarch64-sve2p3-intrinsics acle_sve2p3_target_lane.c acle_sve2p3_imm.cpp, llvm/test/CodeGen/AArch64 sve2p3-intrinsics-luti6.ll

fixup! Add some more _bf16 tests
DeltaFile
+27-0clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_target_lane.c
+11-0llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
+3-0clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
+41-03 files

LLVM/project 7ece3e1clang/include/clang/Basic arm_sme.td arm_sve.td, clang/test/CodeGen/AArch64/sme2p3-intrinsics acle_sme2p3_luti6.c

fixup! Fix more PR comments
DeltaFile
+10-13llvm/include/llvm/IR/IntrinsicsAArch64.td
+4-4clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
+2-2clang/include/clang/Basic/arm_sme.td
+1-1clang/include/clang/Basic/arm_sve.td
+17-204 files

LLVM/project 6aa59faclang/lib/Basic/Targets AArch64.cpp, clang/test/Preprocessor aarch64-target-features.c

fixup! Address PR comments
DeltaFile
+18-12llvm/lib/Target/AArch64/SVEInstrFormats.td
+0-29clang/lib/Basic/Targets/AArch64.cpp
+0-23clang/test/Preprocessor/aarch64-target-features.c
+13-9llvm/lib/Target/AArch64/SMEInstrFormats.td
+1-6llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+1-4llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+33-831 files not shown
+33-857 files

LLVM/project c4c0de2clang/test/CodeGen/AArch64/sme2p3-intrinsics acle_sme2p3_luti6.c, clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_luti6.c

[AArch64][clang][llvm] Add support for Armv9.7-A lookup table intrinsics

Add support for the following Armv9.7-A Lookup Table (lut)
instruction intrinsics:

SVE2.3
```c
  // Variant is  also available for: _u8 _mf8
  svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);
```

SVE2.3 and SME2.3
``` c
  // Variants are also available for _u16_x2 and _f16_x2.
  svint16_t svluti6_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx);
```

SME2.3
```c

    [9 lines not shown]
DeltaFile
+175-0clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
+112-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
+105-0llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
+102-0llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+79-0llvm/test/Verifier/AArch64/luti6-intrinsics.ll
+55-0llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
+628-016 files not shown
+876-322 files

LLVM/project 80d72aelldb/include/lldb/Target ExecutionContext.h

[lldb] Remove declarations of two non-existent constructors (NFC) (#191622)

They have never existed since the initial public checkin.
DeltaFile
+0-23lldb/include/lldb/Target/ExecutionContext.h
+0-231 files

LLVM/project f4da0callvm/include/llvm/ExecutionEngine/Orc SimpleRemoteEPC.h, llvm/lib/ExecutionEngine/Orc SimpleRemoteEPC.cpp

[ORC] Sink a #include in SimpleRemoteEPC.h, and remove another. (#191797)

These #includes are only needed in the SimpleRemoteEPC.cpp
implementation.
DeltaFile
+0-2llvm/include/llvm/ExecutionEngine/Orc/SimpleRemoteEPC.h
+1-0llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
+1-22 files