LLVM/project dc2f9fellvm/lib/Transforms/InstCombine InstCombineLoadStoreAlloca.cpp, llvm/test/Transforms/InstCombine store.ll

[InstCombine] Fold constant byte stores to integer stores (#196740)

Byte constants are equivalent to integer constants when stored to
memory. Replacing them in store instructions reduces IR differences and
enables existing optimizations over integer constants.
DeltaFile
+111-0llvm/test/Transforms/InstCombine/store.ll
+7-0llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+118-02 files

LLVM/project 7504f6aflang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics openmp-utils.cpp check-omp-loop.cpp

[flang][OpenMP] Optionally get final symbol in Get(Argument|Object)Symbol

Originally these functions returned the ultimate symbol for the one
obtained from the argument or object. However, this may be somewhat
unintuitive/unexpected, so instead return the original symbol, and
add a flag to optionally return the ultimate one.
DeltaFile
+15-6flang/lib/Semantics/openmp-utils.cpp
+2-10flang/lib/Semantics/check-omp-loop.cpp
+6-6flang/lib/Semantics/check-omp-structure.cpp
+4-2flang/include/flang/Semantics/openmp-utils.h
+27-244 files

LLVM/project ea4e329llvm/lib/CodeGen/SelectionDAG LegalizeVectorOps.cpp, llvm/test/CodeGen/NVPTX f16x2-instructions.ll

[llvm][RISCV] Optimize fcopysign for fixed vectors (#193802)

vfsgnj is not available on zvfhmin or zvfbfmin, it's expected to expand
to integer operations instead of unrolling to scalar operations.
General expandFCOPYSIGN already handles that in most of cases except for
fixed vector types that are not promotable, we need to find a better
heuristic to gate this.
DeltaFile
+61-144llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+169-30llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
+38-128llvm/test/CodeGen/Thumb2/mve-fmath.ll
+20-4llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+288-3064 files

LLVM/project 7cc1f32llvm/lib/CodeGen/SelectionDAG LegalizeVectorOps.cpp, llvm/test/CodeGen/ARM vfloatintrinsics.ll

[llvm][RISCV] Optimize fabs for fixed vectors (#194554)

vfabs is not available on zvfhmin or zvfbfmin, it's expected to expand
to integer operations instead of unrolling to scalar operations.
General expandFABS already handles that in most of cases except for
fixed vector types that are not promotable, we need to find a better
heuristic to gate this.
DeltaFile
+174-35llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
+29-43llvm/test/CodeGen/Thumb2/mve-vabd.ll
+10-32llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
+9-27llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+20-4llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+2-2llvm/test/CodeGen/ARM/vfloatintrinsics.ll
+244-1436 files

LLVM/project 8730fb7llvm/lib/CodeGen/SelectionDAG LegalizeVectorOps.cpp, llvm/test/CodeGen/NVPTX f16-instructions.ll

[llvm][RISCV] Optimize fneg for fixed vectors (#194555)

vfneg is not available on zvfhmin or zvfbfmin, it's expected to expand
to integer operations instead of unrolling to scalar operations.
General expandFNEG already handles that in most of cases except for
fixed vector types that are not promotable, we need to find a better
heuristic to gate this.
DeltaFile
+162-35llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll
+14-33llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
+20-4llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+1-2llvm/test/CodeGen/NVPTX/f16-instructions.ll
+197-744 files

LLVM/project 9c95f37clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-perm.c

[CIR][AArch64] Lower NEON vuzp intrinsics (#195591)

### Summary

part of : https://github.com/llvm/llvm-project/issues/185382

lower `vuzp` intrinsics in:
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#unzip-elements

this is a follow up : https://github.com/llvm/llvm-project/pull/195527

Lower `NEON::BI__builtin_neon_vuzp_v` and
`NEON::BI__builtin_neon_vuzpq_v`in CIRGenBuiltinAArch64.cpp by porting
by porting the existing incubator
logic(clangir/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp) : two
bitcasts on the input vectors,two rounds of cir.vec.shuffle generating
the deinterleave (even/odd) shuffle patterns with indices 2*i+vi, each
stored via ptr_stride on the sret base pointer.
DeltaFile
+382-0clang/test/CodeGen/AArch64/neon/perm.c
+0-376clang/test/CodeGen/AArch64/neon-perm.c
+0-36clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
+20-2clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+402-4144 files

LLVM/project 02f78d0clang/lib/Interpreter IncrementalParser.h, clang/tools/libclang CIndexDiagnostic.h

[NFC] Fix C++23 build failures caused by incomplete types in `unique_ptr`
DeltaFile
+6-0llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+6-0llvm/lib/Target/BPF/BPFAsmPrinter.cpp
+1-4clang/lib/Interpreter/IncrementalParser.h
+2-2llvm/lib/Target/BPF/BPFAsmPrinter.h
+1-2clang/tools/libclang/CIndexDiagnostic.h
+2-1llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+18-92 files not shown
+24-98 files

LLVM/project d0d40cfclang-tools-extra/clang-tidy/modernize UseStringViewCheck.cpp UseStringViewCheck.h, clang-tools-extra/docs/clang-tidy/checks/modernize use-string-view.rst

[clang-tidy] Reland "An option for conditional skipping overloaded functions in modernize-use-string-view" (#196387)
DeltaFile
+185-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-overloaded.cpp
+0-91clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
+10-0clang-tools-extra/docs/clang-tidy/checks/modernize/use-string-view.rst
+5-1clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
+3-2clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.h
+203-945 files

LLVM/project c74ecc9clang/lib/CodeGen CGBuiltin.cpp, llvm/include/llvm/IR IRBuilder.h

[IRBuilder] Split CreateAssumption to one with bundle and one with condition [NFC] (#196795)

as it is not possible to combine bundles and conditions from
https://github.com/llvm/llvm-project/pull/160460 reflect that in
CreateAssumption
DeltaFile
+14-15llvm/lib/IR/IRBuilder.cpp
+7-6llvm/include/llvm/IR/IRBuilder.h
+2-4llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+1-1clang/lib/CodeGen/CGBuiltin.cpp
+24-264 files

LLVM/project 2162c16clang-tools-extra/clang-tidy/bugprone UnhandledCodePathsCheck.cpp, clang-tools-extra/clang-tidy/hicpp MultiwayPathsCoveredCheck.cpp

[clang-tidy] Rename hicpp-multiway-paths-covered to bugprone-unhandled-code-paths (#191625)

Part of the work in https://github.com/llvm/llvm-project/issues/183462.

Closes https://github.com/llvm/llvm-project/issues/183464.

Splitting the check into two more focused checks was considered during
discussion, but since clang-tidy does not support one-to-many aliases, a
single name covering both behaviors was chosen instead that is more
clear than `multiway-paths-covered`.

---------

Co-authored-by: Zeyi Xu <mitchell.xu2 at gmail.com>
DeltaFile
+468-0clang-tools-extra/test/clang-tidy/checkers/bugprone/unhandled-code-paths.cpp
+0-468clang-tools-extra/test/clang-tidy/checkers/hicpp/multiway-paths-covered.cpp
+0-175clang-tools-extra/clang-tidy/hicpp/MultiwayPathsCoveredCheck.cpp
+174-0clang-tools-extra/clang-tidy/bugprone/UnhandledCodePathsCheck.cpp
+3-93clang-tools-extra/docs/clang-tidy/checks/hicpp/multiway-paths-covered.rst
+95-0clang-tools-extra/docs/clang-tidy/checks/bugprone/unhandled-code-paths.rst
+740-73610 files not shown
+855-84116 files

LLVM/project 6983aa7llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values (#151372)

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32). This
avoids transferring the value through a GPR when storing.

Also remove the pre-legaliztion early-exit in `combineStoreValueFPToInt`
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 8272f19flang/lib/Semantics rewrite-parse-tree.cpp

[flang] Format rewrite-parse-tree.cpp, NFC

It's a 4-line change that makes the file invariant under clang-format.
DeltaFile
+4-4flang/lib/Semantics/rewrite-parse-tree.cpp
+4-41 files

LLVM/project 7456636flang/include/flang/Parser parse-tree.h, flang/lib/Lower/OpenMP OpenMP.cpp

[flang][OpenMP] Consistent names for non-executable directives, NFC (#196803)

Change
  OpenMPGroupprivate      -> OmpGroupprivateDirective
  OpenMPThreadprivate     -> OmpThreadprivateDirective
  OpenMPRequiresConstruct -> OmpRequiresDirective
  OpenMPUtilityConstruct  -> OmpUtilityDirective
DeltaFile
+13-11flang/include/flang/Parser/parse-tree.h
+10-10flang/lib/Parser/openmp-parsers.cpp
+10-10flang/lib/Semantics/resolve-directives.cpp
+7-7flang/lib/Semantics/check-omp-structure.cpp
+9-4flang/lib/Semantics/unparse-with-symbols.cpp
+6-6flang/lib/Lower/OpenMP/OpenMP.cpp
+55-4814 files not shown
+97-8820 files

LLVM/project 0b98750llvm/utils/gn/secondary/clang/unittests/DependencyScanning BUILD.gn

[gn] Make ClangDependencyScanningTests depend on Testing/Support (#196809)

Needed after ebb9a79cd370c.
DeltaFile
+1-0llvm/utils/gn/secondary/clang/unittests/DependencyScanning/BUILD.gn
+1-01 files

LLVM/project b2f37f4clang/lib/Format ContinuationIndenter.cpp, clang/unittests/Format AlignmentTest.cpp

clang-format: ensure ternary operands are aligned (#196697)

Set ParentState::AlignedTo for ternary operands.
DeltaFile
+16-0clang/lib/Format/ContinuationIndenter.cpp
+10-0clang/unittests/Format/AlignmentTest.cpp
+26-02 files

LLVM/project e7ea212libc/src/__support freetrie.h

[libc] Fix -Wshadow warnings in freetrie.h (#196529)
DeltaFile
+2-2libc/src/__support/freetrie.h
+2-21 files

LLVM/project 2491cc2clang/docs ReleaseNotes.rst, clang/include/clang/Basic Builtins.td

[clang] constexpr `__builtin_elementwise_{max,min}num`
DeltaFile
+42-80clang/lib/AST/ByteCode/InterpBuiltin.cpp
+52-0clang/test/Sema/constant-builtins-vector.cpp
+18-30clang/lib/AST/ExprConstant.cpp
+2-2clang/include/clang/Basic/Builtins.td
+3-0clang/docs/ReleaseNotes.rst
+117-1125 files

LLVM/project ad92988llvm/lib/Target/X86 X86InstrCompiler.td X86ISelLowering.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Cast atomic vectors in IR to support floats

This commit casts floats to ints in an atomic load during AtomicExpand to support
floating point types. It also is required to support 128 bit vectors in SSE/AVX.
DeltaFile
+98-288llvm/test/CodeGen/X86/atomic-load-store.ll
+15-0llvm/lib/Target/X86/X86InstrCompiler.td
+7-0llvm/lib/Target/X86/X86ISelLowering.cpp
+2-0llvm/lib/Target/X86/X86ISelLowering.h
+122-2884 files

LLVM/project a6344c0flang/include/flang/Parser parse-tree.h, flang/lib/Parser openmp-parsers.cpp

[flang][OpenMP] Consistent names for non-executable directives, NFC

Change
  OpenMPGroupprivate      -> OmpGroupprivateDirective
  OpenMPThreadprivate     -> OmpThreadprivateDirective
  OpenMPRequiresConstruct -> OmpRequiresDirective
  OpenMPUtilityConstruct  -> OmpUtilityDirective
DeltaFile
+13-11flang/include/flang/Parser/parse-tree.h
+10-10flang/lib/Parser/openmp-parsers.cpp
+10-10flang/lib/Semantics/resolve-directives.cpp
+7-7flang/lib/Semantics/check-omp-structure.cpp
+9-4flang/lib/Semantics/unparse-with-symbols.cpp
+6-6flang/lib/Semantics/check-omp-structure.h
+55-4814 files not shown
+97-8820 files

LLVM/project 3de25f5clang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeSafety.h, clang/include/clang/Basic DiagnosticGroups.td DiagnosticSemaKinds.td

[LifetimeSafety] Warn on incorrectly placed `[[clang::lifetimebound]]` attributes (#196144)

Adds new warning that is emitted when parameter is marked as
`[[clang::lifetimebound]]` but is not returned in one way or another
(tracked via `OriginEscapeFact`).

Closes #182935
DeltaFile
+89-0clang/test/Sema/warn-lifetime-safety-lifetimebound.cpp
+27-12clang/lib/Sema/SemaLifetimeSafety.h
+24-3clang/lib/Analysis/LifetimeSafety/Checker.cpp
+10-2clang/include/clang/Basic/DiagnosticGroups.td
+5-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+4-0clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
+159-171 files not shown
+160-177 files

LLVM/project 2b26355llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 horizontal-reduce-smax.ll horizontal-reduce-smin.ll

Revert "[VectorCombine] foldShuffleChainsToReduce - add support for partial vector reductions" (#196796)

Reverts llvm/llvm-project#195119 while reported assertions are investigated.
DeltaFile
+0-50llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+6-33llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+134-1156 files

LLVM/project c7ad740clang/docs ReleaseNotes.rst, clang/lib/AST ExprConstant.cpp

[clang] constexpr `__builtin_elementwise_{max,min}num`
DeltaFile
+42-80clang/lib/AST/ByteCode/InterpBuiltin.cpp
+52-0clang/test/Sema/constant-builtins-vector.cpp
+18-30clang/lib/AST/ExprConstant.cpp
+3-0clang/docs/ReleaseNotes.rst
+115-1104 files

LLVM/project 79fa36flldb/source/Plugins/Process/Linux NativeRegisterContextLinux.h, lldb/source/Plugins/Process/Utility NativeRegisterContextRegisterInfo.h

[lldb][Windows] Invalidate cached register values on thread stop (#192430)

Invalidate cached values in register context data structures on every
thread stop.

NativeRegisterContextRegisterInfo::InvalidateAllRegisters performs no
operation by default. Subclasses may override it to clear cached values
within their register context data structures whenever a thread stops.

This change intends to set up the necessary infrastructure to support
caching of the thread context in NativeRegisterContextWindows_arm64,
which will improve read performance. Currently, the thread context is
retrieved for every read or write operation.
DeltaFile
+3-0lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
+0-3lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
+3-0lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h
+6-33 files

LLVM/project af1d9cdllvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 horizontal-reduce-smax.ll horizontal-reduce-smin.ll

Revert "[VectorCombine] foldShuffleChainsToReduce - add support for partial v…"

This reverts commit a2942d472aac907af6f47f8c7658288609b6e1de.
DeltaFile
+0-50llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+6-33llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+134-1156 files

LLVM/project 43ef21fllvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32).
This avoids transferring the value through a GPR when storing.

Also remove the pre-legalization early-exit in combineStoreValueFPToInt
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 53ce9fbllvm/lib/CodeGen/SelectionDAG ExpandMulByConstant.cpp, llvm/test/CodeGen/Lanai constant_multiply.ll

[TargetLowering] Add target-independent mul-by-constant expansion algorithm
DeltaFile
+176-379llvm/test/CodeGen/RISCV/mul-expand.ll
+307-0llvm/lib/CodeGen/SelectionDAG/ExpandMulByConstant.cpp
+130-164llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+88-152llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+73-128llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+82-78llvm/test/CodeGen/Lanai/constant_multiply.ll
+856-90119 files not shown
+1,356-1,40825 files

LLVM/project 9a1da2elibcxx/include algorithm

address review comments
DeltaFile
+4-4libcxx/include/algorithm
+4-41 files

LLVM/project fd89940llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32).
This avoids transferring the value through a GPR when storing.

Also remove the pre-legalization early-exit in combineStoreValueFPToInt
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 6b9b1c2llvm/lib/Transforms/Utils LoopPeel.cpp, llvm/test/Transforms/LoopUnroll peel-last-iteration-load-widening.ll peel-last-iteration-load-widening-be.ll

Address comments 1
DeltaFile
+1,694-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening.ll
+0-616llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+117-79llvm/lib/Transforms/Utils/LoopPeel.cpp
+0-104llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+67-0llvm/test/Transforms/LoopUnroll/PowerPC/peel-last-iteration-load-widening-be.ll
+56-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-disabled.ll
+1,934-7994 files not shown
+1,948-80910 files

LLVM/project 719b58cllvm/include/llvm/Transforms/Utils LoopPeel.h UnrollLoop.h, llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopPeel] Peel last iteration to enable load widening

In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., i32) for
all other N-1 iterations.

Patterns such as:
```
  %a = load i8, ptr %p
  %b = load i8, ptr %p+1
  %c = load i8, ptr %p+2
  ...
  %p.next = getelementptr i8, ptr %p, 3
```

Can be transformed to:
```
  %wide = load i32, ptr %p  ; Read 4 bytes

    [9 lines not shown]
DeltaFile
+616-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+230-1llvm/lib/Transforms/Utils/LoopPeel.cpp
+104-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+19-13llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+7-1llvm/include/llvm/Transforms/Utils/LoopPeel.h
+2-1llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+978-166 files