[Clang][AMDGPU] Add ``amdgpu_av("none")`` attribute for atomic expressions (#199622)
Add a statement attribute that suppresses MakeAvailable/MakeVisible
cache operations on AMDGPU atomic instructions while preserving memory
ordering (waits). The attribute takes a string argument specifying the
mode. Currently "none" is the only supported mode. The resulting atomic
or fence instruction carries !mmra !{!"amdgcn-av", !"none"} metadata.
This only works with builtins that get lowered to intrinsics or
instructions. The attribute does not survive inlining. For example, a
C++ std atomic is typically a wrapper around a Clang builtin, and
applying this attribute on the std atomic does not remove the
MakeAvailableMakeVisible semantics built into it.
Part of a stack:
- #199486
- #199621
- #199489
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[flang][driver] Support Makefile dependency generation (#209379)
Implement the GCC/Clang dependency-file flags for flang, which it
previously rejected as unknown arguments: -M, -MM, -MD, -MMD, -MF,
-MT and -MQ.
Feature:
- -MD/-MMD : write a .d file alongside a normal compile
- -M/-MM : run through semantics; emit deps to stdout by default
- -MF : dependency-file path
- -MT/-MQ : target name (verbatim / Make-quoted)
(-M==-MM and -MD==-MMD; Fortran has no system/user header split.)
Design:
- `-M`/`-MM`: driver passes `-fsyntax-only -dependency-file - -MT
<target>` to `-fc1`. Running through semantics resolves USE
statements so module file dependencies are captured in the output.
This deviates from clang's prescan-only behaviour for -M, but is
intentional: unlike C/C++ #include, Fortran's USE statement is
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[libclc] Add initial support for libclc execution conformance tests (#214072)
Summary:
This uses the `llvm-gpu-loader` tool to invoke OpenCL test kernels. This
routes OpenCL through the standard compute runtimes, which aren't
exactly 1-to-1 with OpenCL, but it's close enough. Obviously, the best
solution would be to have a real OpenCL host library that can launch
these, but this is the best we can get in-tree and is very sipmle, write
kernel, test kernel.
The goal is to have a lot more tests run here, but this just gets the
basic infrastructure in place. We won't be able to do full conformance
like external suites, like exhaustive math, but I think its' a step in
the right direction. It looks like this on my side:
```console
$ ninja check-libclc-amdgpu-amd-amdhsa-llvm
```
This requires building with the LLVM `offload/` runtime enabled for the
source compiler.
[RISCV][MC] Add experimental Smijt, Ssijt, Smehv, and Ssehv support (#213431)
Add support for version 0.19 of the Smijt, Ssijt, Smehv, and Ssehv
extensions from the RISC-V fast interrupt specification.
[ExpandVariadics] Don't lower unmangled C printf on SPIR-V (#206998)
An unmangled C `printf` declaration demangles to bare `printf` (no
argument list), so `SPIRV::ignoreFunction`'s `printf(` prefix check
missed it and ExpandVariadics packed its arguments into a vararg buffer;
the SPIR-V backend then passed the buffer pointer as printf's first
variadic operand, so device printf printed pointer values instead of the
actual arguments. Match the bare name too so OpenCL/HIP printf (emitted
unmangled) is left as a variadic call for the backend's OpenCL.std
printf lowering.
(cherry picked from commit b1d21c6d3121898dc13c0df8cf9e4410bee75cfb)
Reapply "Skipping host target exports during cross-compilation" (#210… (#210496)
This reverts commit 42eb7db188f23625872b6f1d722979a3100d170e. This
reland 3fbb037d03e7ff1ef1cd9156363e895af7caaf98 (#209922).
Under CMake 4+, calling add_library(... SHARED IMPORTED) on a target
platform that lacks dynamic linking support triggers a fatal error. This
becomes an issue when building LLVM and runtimes for baremetal targets
like armv6m-none-eabi. This patch adds the option
"LLVM_OMIT_EXPORTS_FROM_CONFIG" in LLVM. When used in sub builds like
LLVM runtimes, it makes CMake to skip including the LLVM and Clang
exports. This mitigates the CMake 4 errors on baremetal runtimes.
42eb7db188f23625872b6f1d722979a3100d170e originally
apply this flag on all runtimes build and causing issues on runtimes
like intel-sycl-gpu, amdgpu-offload-ubuntu-22-cmake-build-only.
This PR only set this flag when the target platform lacks shared library
support.
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[LoongArch] Use unsigned vector extract for zero extension
Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
[mlir][func] Fix a crash in DuplicateFunctionEliminationPass (#209667)
Previously, we used `SymbolUserMap::replaceAllUsesWith` to replace
symbols, but this could not update the symbol table cached by
`SymbolUserMap` during traversal, leading to a crash. This PR switches
to `SymbolTable::replaceAllSymbolUses`, which always operates on the
latest symbol table and avoids the crash. Fixes #209648.
[libc][cmake] Enable assertions and Werror for baremetal builds (#214093)
Enable LLVM_ENABLE_ASSERTIONS and LLVM_ENABLE_WERROR in
baremetal_common.cmake
to ensure pre-merge checks catch assertion failures and compiler
warnings for
baremetal targets.
Assisted-by: Gemini
Add PISA register file, instruction set, and MC layer
Add the PISA register file and register-bank descriptions, the instruction
formats and definitions, and the MC/assembly layer (instruction printer,
register and code encoders, target streamer, MC target description and the
supporting enums), replacing the stub descriptions from
the initial target skeleton.
This provides the instruction-set description and assembly-emission
foundation. The GlobalISel lowering and instruction selection that consume it
are added in the following changes.
[Clang][AMDGPU] Add amdgpu_av("none") attribute for atomic expressions
Add a statement attribute that suppresses MakeAvailable/MakeVisible
cache operations on AMDGPU atomic instructions while preserving memory
ordering (waits).
The attribute takes a string argument specifying the mode. Currently "none" is
the only supported mode. The resulting atomic or fence instruction carries !mmra
!{!"amdgcn-av", !"none"} metadata.
Assisted-By: Claude Opus 4.6
[clang][StaticAnalyzer] Add support for variables and fields in GetEnclosingDeclContextSignature
Function `getIssueHash` relies on the name of the enclosing
declaration of the issue Decl for hashing. But the underlying
function `GetEnclosingDeclContextSignature` does not compute the
enclosing declaration for variables or fields, causing missing HTML
reports despite text warnings being printed.
The added
`clang/test/Analysis/Checkers/WebKit/html-diag-dedup-members.cpp`
example is a reproducer of this kind of issue we observed in WebKit.
Also, `RawPtrRefLocalVarsChecker` and `RawPtrRefMemberChecker` never
called `Report->setDeclWithIssue()`. This commit fixes it.
rdar://183700416
Assisted-by: Claude sonnet
[CIR] Change previous coroutine builtins to have their own coro intrinsic ops (#211699)
This PR introduces dedicated CIR operations for the coroutine intrinsics
(`coro.intrinsic.id`, `coro.intrinsic.alloc`, `coro.intrinsic.begin`,
`coro.intrinsic.free`, `coro.intrinsic.end`, `coro.intrinsic.size`)
instead of emitting them as calls to hand-created builtin functions.
LLVM IR already has its own dedicated ops for these cases, so this
follows the same pattern at CIR.
Along the way this also changes how coroutine builtins are handled in
`CIRGenBuiltin`: previously the intrinsics emitted automatically as part
of lowering `EmitCoroutineBody` and the ones triggered by an explicit
`__builtin_coro_*` call written in user source code were going through
the same path. This PR separates the two, since they're conceptually
different emission points.
New tests covering these builtins are included as well.
Also added explicit `errorNYI` messages for the remaining
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[AMDGPU][GlobalISel] Use single B32 rule for permlane16
B32 already covers s32, <2 x s16> and 32-bit pointers, so one StandardB
fast rule replaces the separate S32, V2S16 and DivPtr32 rules. This
matches permlane_bcast/up/down/xor and permlane64, which have the same
overloaded intrinsic shape.
Change-Id: I770a93d5e75e68df704e84d7ad165fdd2cf2fc53
Add PISA target registration and backend stub
Register the Intel GPU portable ISA (PISA) target. Add the pisa Triple
arch, data layout, and a minimal MC/TargetMachine skeleton.
