LLVM/project aca0639llvm/include/llvm/ExecutionEngine/Orc WaitingOnGraphOpReplay.h

[ORC] Flush streams in WaitingOnGraphOpStreamRecorder record ops.

Allows us to get useful recordings out of JIT sessions that crash, or are kept
alive indefinitely. (Note that an 'end' operation will have to be appended to
the output in these cases).
DeltaFile
+3-0llvm/include/llvm/ExecutionEngine/Orc/WaitingOnGraphOpReplay.h
+3-01 files

LLVM/project aab3dfamlir/include/mlir/Interfaces FunctionInterfaces.td, mlir/test/Conversion/FuncToLLVM convert-funcs.mlir

[MLIR][Func] Return nullptr for empty ResultAttrs (#185219)

Fixes #185156

When an empty res_attrs is passed manually, we should still return
nullptr to indicate that no results have attributes.
DeltaFile
+5-2mlir/include/mlir/Interfaces/FunctionInterfaces.td
+7-0mlir/test/Conversion/FuncToLLVM/convert-funcs.mlir
+12-22 files

LLVM/project 8b790f8llvm/include/llvm/Frontend/OpenMP OMP.td

[OpenMP] Add definitions of FLATTEN and SPLIT to OMP.td

Add the definitions of the "flatten" and the "split" constructs
to the OMP.td file. This will allow the implementation efforts
in clang and flang to proceed independently.

There is no other functionality added in this patch.
DeltaFile
+20-0llvm/include/llvm/Frontend/OpenMP/OMP.td
+20-01 files

LLVM/project 309b7d0clang-tools-extra/clang-tidy/readability SimplifySubscriptExprCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix false negative in `readability-simplify-subscript-expr` when subscripting substituted types (#185570)

This check's bespoke method of avoiding matching
in template instantations is overeager. This commit
changes it to just rely on IgnoreUnlessSpelledInSource
traversal instead.  This is the same problem 
as in #185559.
DeltaFile
+9-12clang-tools-extra/clang-tidy/readability/SimplifySubscriptExprCheck.cpp
+19-0clang-tools-extra/test/clang-tidy/checkers/readability/simplify-subscript-expr.cpp
+6-0clang-tools-extra/docs/ReleaseNotes.rst
+34-123 files

LLVM/project cd3cab7mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp, mlir/test/Dialect/OpenMP cli-tile.mlir invalid-tile.mlir

[mlir][OpenMP] Allow tile composition (#185380)

The verifier of the TileOp did not allow composition of multiple
transformations out of precaution. However, composition works, therefore
remove the "currently only supports omp.canonical_loop as applyee" check
and add regression tests.
DeltaFile
+193-0mlir/test/Target/LLVMIR/openmp-cli-tile03.mlir
+52-34mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+70-0mlir/test/Dialect/OpenMP/cli-tile.mlir
+22-4mlir/test/Dialect/OpenMP/invalid-tile.mlir
+337-384 files

LLVM/project 2826924clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/lib/CodeGen/TargetBuiltins ARM.cpp

[CIR][AArch64] Add support for the remaining `vceqz` builtins (#185440)

Implement the remaining CIR lowerings for the AdvSIMD (Neon)
`vceqz` intrinsic group (bitwise equal to zero).

Most variants of `vceqz` variant were already supported; this patch
completes the rest of the group [1] that was left as a TODO.

Tests for these intrinsics are moved from:
  * test/CodeGen/AArch64/neon_intrinsics.c
  * test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c

to:
  * test/CodeGen/AArch64/neon/intrinsics.c
  * test/CodeGen/AArch64/neon/fullfp16,

respectively.

The implementation largely mirrors the existing lowering in

    [3 lines not shown]
DeltaFile
+60-16clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-33clang/test/CodeGen/AArch64/neon-intrinsics.c
+20-0clang/test/CodeGen/AArch64/neon/fullfp16.c
+8-4clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+0-8clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
+3-4clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+91-656 files

LLVM/project 14feef8llvm/utils/TableGen/Common CodeGenRegisters.cpp CodeGenRegisters.h

[TableGen] Do not order register classes based on heap addresses

Compare registers using their enum values instead, which I
suspect was the intention in the first place, since we already
have lexicographical ordering defined for CodeGenRegisters.

This does not cause any changes in .inc files and is likely
NFC, but it's still best to have it be deterministic.
DeltaFile
+5-8llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+4-0llvm/utils/TableGen/Common/CodeGenRegisters.h
+9-82 files

LLVM/project 90e5a1elibclc/cmake/modules AddLibclc.cmake

[libclc][CMake] Append target_name to external-funcs test target name (#185639)

Avoid name conflicts when multiple libararies use the same target
triple.
DeltaFile
+1-1libclc/cmake/modules/AddLibclc.cmake
+1-11 files

LLVM/project 35aa3d1clang/include/clang/Analysis/Scalable SSAFBuiltinForceLinker.h SSAFForceLinker.h, clang/include/clang/Analysis/Scalable/Frontend TUSummaryExtractorFrontendAction.h

Reapply "Reapply "[clang][ssaf] Add --ssaf-extract-summaries= and --ssaf-tu-summary-file= options"" (#185616)

This reverts commit 9a1c63230b8ad3f19cb624f0d283f7df10957ab7.

1st attempt: #184421
2nd attempt: #185414
Third time the charm!

rdar://172173836
DeltaFile
+362-0clang/unittests/Analysis/Scalable/Frontend/TUSummaryExtractorFrontendActionTest.cpp
+181-0clang/lib/Analysis/Scalable/Frontend/TUSummaryExtractorFrontendAction.cpp
+51-0clang/unittests/Analysis/Scalable/SSAFBuiltinTestForceLinker.h
+33-0clang/include/clang/Analysis/Scalable/Frontend/TUSummaryExtractorFrontendAction.h
+28-0clang/include/clang/Analysis/Scalable/SSAFBuiltinForceLinker.h
+25-0clang/include/clang/Analysis/Scalable/SSAFForceLinker.h
+680-023 files not shown
+855-1929 files

LLVM/project 32e7bc9llvm/test/CodeGen/SPIRV/debug-info debug-function.ll

[review] fix comment.
DeltaFile
+1-1llvm/test/CodeGen/SPIRV/debug-info/debug-function.ll
+1-11 files

LLVM/project 3e15e61llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp

[review] improve comments.
DeltaFile
+11-11llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+11-111 files

LLVM/project be5d7e3llvm/test/CodeGen/SPIRV/debug-info debug-function.ll

[reviews] Update comment.
DeltaFile
+1-1llvm/test/CodeGen/SPIRV/debug-info/debug-function.ll
+1-11 files

LLVM/project ffe1380llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp

[reviews] minor edit.
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+1-11 files

LLVM/project 734ec21llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp

[reviews] simplify code.
DeltaFile
+8-16llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+8-161 files

LLVM/project 3181206llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-function.ll

[SPIRV] Add support for emitting DebugFunction debug info instructions

This commit adds support for emitting SPIRV DebugFunction and
DebugFunctionDefinition instructions for function definitions.
DeltaFile
+218-0llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+40-0llvm/test/CodeGen/SPIRV/debug-info/debug-function.ll
+258-02 files

LLVM/project b21719fllvm/utils/TableGen/Common CodeGenRegisters.cpp

[TableGen] Fix inferring missing sub-classes for various subreg indices

We should not imply artificial registers have sub-registers for a given
index even if the class is known to 'fully support' that index.

Fixes crashes reported in
https://github.com/llvm/llvm-project/pull/183371#discussion_r2905495313
DeltaFile
+1-1llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+1-11 files

LLVM/project 1d03260llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp

Fix format.
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+1-11 files

LLVM/project fdcb884llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp

[NFC][SPIRV] Extract helper functions in SPIRVEmitNonSemanticDI

This commit extracts reusable helper functions to improve code
organization and reduce duplication. This is a pure refactoring
that does not change behavior.

These helpers will be used in subsequent commits to refactor
emitGlobalDI and add function-level debug info emission.
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+1-11 files

LLVM/project becf44bllvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp

[review] Simplify code.
DeltaFile
+2-3llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+2-31 files

LLVM/project 1927d24llvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp

[review] Improve comment.
DeltaFile
+2-0llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+2-01 files

LLVM/project cf4bd77llvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp

[SPIRV] Refactor NonSemantic debug info placement logic.

Refactor the logic for determining which NonSemantic.Shader.DebugInfo.100
instructions should be placed in the global section from a whitelist
to a blacklist approach.
DeltaFile
+14-7llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+14-71 files

LLVM/project 3bc1de1llvm/lib/Target/PowerPC PPCRegisterInfo.td PPCOperands.td

[PowerPC][NFC] Clean up code in RegisterInfo.td (#185520)

Just some cleanup work. Moving non register related operands to
PPCOperands.td and PatLeaf def to PPCInstrInfo.td.
DeltaFile
+23-193llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+166-0llvm/lib/Target/PowerPC/PPCOperands.td
+3-0llvm/lib/Target/PowerPC/PPCInstrInfo.td
+192-1933 files

LLVM/project 0a6e6dflibclc/clc/lib/amdgpu CMakeLists.txt, libclc/clc/lib/amdgpu/math clc_frexp.cl

libclc: Use frexp builtins to implement frexp for amdgpu

This should really be the default implementation.
DeltaFile
+47-0libclc/clc/lib/generic/math/clc_frexp_builtin.inc
+43-0libclc/clc/lib/amdgpu/math/clc_frexp.cl
+1-0libclc/clc/lib/amdgpu/CMakeLists.txt
+91-03 files

LLVM/project c79a058llvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/AArch64 transform-narrow-interleave-to-widen-memory-cost.ll

[VPlan] Materialize VectorTripCount in narrowInterleaveGroups. (#182146)

When narrowInterleaveGroups transforms a plan, VF and VFxUF are
materialized (replaced with concrete values). This patch also
materializes the VectorTripCount in the same transform.

This ensures that VectorTripCount is properly computed when the narrow
interleave transform is applied, instead of using the original VF
+ UF to compute the vector trip count. The previous behavior generated
correct code, but executed fewer iterations in the vector loop.

The change also enables stricter verification prevent accesses of UF,
VF, VFxUF etc after materialization as follow-up.

Note that in some cases we no miss branch folding, but that should be
addressed separately, https://github.com/llvm/llvm-project/pull/181252

Fixes one of the violations accessing a VectorTripCount after UF and VF
being materialized

PR: https://github.com/llvm/llvm-project/pull/182146
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
+128-8llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
+121-7llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll
+31-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+20-3llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+6-10llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
+469-365 files not shown
+482-5011 files

LLVM/project 57c1fe9lldb/unittests/Platform PlatformDarwinTest.cpp

[lldb][test] PlatformDarwinTest.cpp: add more test-cases for script name sanitization

Adds more test-cases since I'm making changes around this area (see https://github.com/llvm/llvm-project/pull/185627).
DeltaFile
+95-1lldb/unittests/Platform/PlatformDarwinTest.cpp
+95-11 files

LLVM/project b4861b7llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp

[review] Add missing case for source language conversion
DeltaFile
+5-1llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+5-11 files

LLVM/project 2e5e38cllvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR always-uniform-gmir.mir, llvm/test/MachineVerifier/AMDGPU verifier-ec-subreg-liveness.mir

[AMDGPU] Update register class numbers in some tests (#185623)
DeltaFile
+2-2llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
+2-2llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
+4-42 files

LLVM/project c08372allvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge remote-tracking branch 'official/main' into users/meinersbur/mlir_tile-composition
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,112-16,445llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+241,003-187,9487,234 files not shown
+768,715-431,2087,240 files

LLVM/project cc47ba9mlir/test/Dialect/OpenMP invalid-tile.mlir, mlir/test/Target/LLVMIR openmp-cli-tile03.mlir

Address review
DeltaFile
+0-4mlir/test/Target/LLVMIR/openmp-cli-tile03.mlir
+0-1mlir/test/Dialect/OpenMP/invalid-tile.mlir
+0-52 files

LLVM/project d5ed2cclibclc/clc/lib/amdgpu CMakeLists.txt, libclc/clc/lib/amdgpu/math clc_exp.cl clc_exp10.cl

libclc: Use elementwise exp for exp functions (#185626)

For amdgpu use the exp intrinisc. Really, this should be
the default generic implementation. But we're stuck in a
mess where essentially nothing works. All of the exp
intrinsics work for AMDGPU, but aren't really implemented
for spirv or nvptx. Ideally the intrinsic and/or libm call
would be the default implementation.
DeltaFile
+15-0libclc/clc/lib/amdgpu/math/clc_exp.cl
+15-0libclc/clc/lib/amdgpu/math/clc_exp10.cl
+15-0libclc/clc/lib/amdgpu/math/clc_exp2.cl
+3-0libclc/clc/lib/amdgpu/CMakeLists.txt
+48-04 files