LLVM/project f5e5688llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/RISCV samesign.ll

[SelectionDAGBuilder] Pass SDNodeFlags to getSetCC instead of using FlagInserter. (#190878)

getSetCC hasn't always had a SDNodeFlags argument. When it was added, it
stopped looking at FlagInserter.

Also remove unnecessary FlagInserter from visitFCmp.
DeltaFile
+16-0llvm/test/CodeGen/RISCV/samesign.ll
+2-3llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+18-32 files

LLVM/project 290ddb9llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize pseudoprobe.ll

[VPlan][PseudoProbe] Fix `pseudoprobe` duplication when `VF=1` (#185238)

Fix assertion in `loop-vectorize` on loops that contains
`llvm.pseudoprobe` at VF=1, UF=2. Minimal Reproducer:
https://godbolt.org/z/nrcMWWqMx

Originally in https://reviews.llvm.org/D144066, Pseudoprobes were marked
non-uniform in `isUniformAfterVectorization` even for VF=1 that allows
the `REPLICATE call @llvm.pseudoprobe` to survive until the plan is
executed when VF=1, UF=2, causing the crash.

Instead, `isUniformAfterVectorization` as true even for pseudoprobe when
`VF.isScalar()`.
DeltaFile
+41-12llvm/test/Transforms/LoopVectorize/pseudoprobe.ll
+6-5llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+47-172 files

LLVM/project eb06b47clang/include/clang/Basic DiagnosticSemaKinds.td, clang/include/clang/Sema SemaHLSL.h

[HLSL] Diagnose dynamic indexing of struct arrays for resource access (#187132)

Dynamic indexing of structs arrays for resource access is not supported. This change implements the diagnostic for this.

Fixes #187131
DeltaFile
+44-0clang/lib/Sema/SemaHLSL.cpp
+27-0clang/test/SemaHLSL/Resources/resources-in-struct-array-error.hlsl
+12-2clang/lib/Sema/SemaExprMember.cpp
+3-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-0clang/include/clang/Sema/SemaHLSL.h
+87-25 files

LLVM/project 430e1beclang-tools-extra/clang-tidy/llvm RedundantCastingCheck.cpp RedundantCastingCheck.h, clang-tools-extra/docs/clang-tidy/checks/llvm redundant-casting.rst

[clang-tidy] detect redundant uses of LLVM's cast, dyn_cast (#189274)

Warns when casting to the same pointee type, or when the target pointee
type is a super type of the argument's pointee type. Supported
functions:
 - cast
 - cast_if_present
 - cast_or_null
 - dyn_cast
 - dyn_cast_if_present
 - dyn_cast_or_null

---------

Co-authored-by: Victor Chernyakin <chernyakin.victor.j at outlook.com>
DeltaFile
+286-0clang-tools-extra/test/clang-tidy/checkers/llvm/redundant-casting.cpp
+183-0clang-tools-extra/clang-tidy/llvm/RedundantCastingCheck.cpp
+33-7clang/include/clang/ASTMatchers/ASTMatchers.h
+40-0clang/include/clang/ASTMatchers/ASTMatchersInternal.h
+39-0clang-tools-extra/clang-tidy/llvm/RedundantCastingCheck.h
+32-0clang-tools-extra/docs/clang-tidy/checks/llvm/redundant-casting.rst
+613-74 files not shown
+625-710 files

LLVM/project 815edc3llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/AArch64 vselect-widen-mask-tree.ll arm64-zip.ll

[SelectionDAG] Recurse through mask expression trees in WidenVSELECTMask (#188085)

WidenVSELECTMask currently handles only two mask shapes: a bare SETCC
or a single AND/OR/XOR of exactly two SETCCs. Anything deeper bails out
to the generic condition widening path, which often introduces
unnecessary narrow/widen roundtrips (xtn+sshll on AArch64,
packssdw+vpmovsxwd on X86).

Replace the hand-coded cases with a recursive widenMaskTree that walks
through SETCC, AND/OR/XOR, FREEZE, VECTOR_SHUFFLE, SELECT/VSELECT, and
all-ones/all-zeros BUILD_VECTORs.
DeltaFile
+203-0llvm/test/CodeGen/AArch64/vselect-widen-mask-tree.ll
+130-51llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+31-34llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
+9-18llvm/test/CodeGen/AArch64/arm64-zip.ll
+14-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+387-1035 files

LLVM/project 8c88faellvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 scalable-strict-fadd.ll sve-tail-folding-unroll.ll

[VPlan] Lower CanIVIncrementForPart in convertToConcreteRecipes. (#190844)

Move the lowering of CanonicalIVIncrementForPart from generate() to
convertToConcreteRecipes, converting it to an Add VPInstruction at the
VPlan level. This enables VPlan-level simplifications (e.g., folding add
0, x) and prepares for adding a 3-operand form.

PR: https://github.com/llvm/llvm-project/pull/190844
DeltaFile
+9-18llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+6-12llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
+13-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-8llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+28-384 files

LLVM/project 3af4275llvm/include/llvm/Transforms/Utils Cloning.h, llvm/lib/Transforms/IPO Inliner.cpp

[Inliner] Put inline history into IR as !inline_history metadata (#190876)

(Reland of #190700 with checks for RefSCCs with one function with a
self-reference, plus determinism fix)

(Reland of #190092 with verifier change to look through GlobalAliases)

So that it's preserved across all inline invocations rather than just
one inliner pass run.

This prevents cases where devirtualization in the simplification
pipeline uncovers inlining opportunities that should be discarded due to
inline history, but we dropped the inline history between inliner pass
runs, causing code size to blow up, sometimes exponentially.

For compile time reasons, we want to limit this to only call sites that
have the potential to inline through SCCs, potentially with the help of
devirtualization. This means that the callee is in a non-trivial
(Ref)SCC, or the call site was previously an indirect call, which can

    [8 lines not shown]
DeltaFile
+102-0llvm/test/Transforms/Inline/inline-history.ll
+57-28llvm/lib/Transforms/Utils/InlineFunction.cpp
+26-36llvm/lib/Transforms/IPO/Inliner.cpp
+61-0llvm/test/Verifier/inline-history-metadata.ll
+25-26llvm/lib/Transforms/Utils/CloneFunction.cpp
+19-17llvm/include/llvm/Transforms/Utils/Cloning.h
+290-10714 files not shown
+425-21320 files

LLVM/project cf8e6b9llvm/lib/Target/Hexagon HexagonTargetMachine.cpp HexagonMachineFunctionInfo.h, llvm/test/CodeGen/Hexagon aligna-prologue-expansion.mir

Revert "[Hexagon][MIR] Serialize HexagonMachineFunctionInfo::StackAlignBaseRe…"

This reverts commit cd66d79be19b6db00500ba4508b3946ef1caec88.
DeltaFile
+0-36llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+0-29llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
+0-24llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
+9-6llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
+10-0llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+0-8llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+19-1036 files

LLVM/project 802c5cbflang/include/flang/Evaluate expression.h, flang/lib/Parser expr-parsers.cpp

[flang] Implement conditional expressions parser/semantics (F2023) (#186489)

## Implement Fortran 2023 Conditional Expressions (R1002)

***This PR contains the implementation for parsing and semantic
analysis. Lowering is implemented in a separate PR (#186490)***

Implements Fortran 2023 conditional expressions with syntax: `result =
(condition ? value1 : condition2 ? value2 : ... : elseValue)`

Issue: #176999
Discourse:
https://discourse.llvm.org/t/rfc-adding-conditional-expressions-in-flang-f2023/89869/1
-- note that some of the details provided in the RFC post are no longer
accurate

### Implementation Details
**Parser:**
- Added ConditionalExpr as primary expression (F2023 R1002)  

    [36 lines not shown]
DeltaFile
+429-0flang/test/Semantics/conditional-expr.f90
+286-0flang/test/Parser/conditional-expr.f90
+111-0flang/lib/Semantics/expression.cpp
+47-1flang/lib/Parser/expr-parsers.cpp
+39-8flang/include/flang/Evaluate/expression.h
+42-0flang/test/Evaluate/fold-conditional-expr.f90
+954-922 files not shown
+1,178-1428 files

LLVM/project 46dc97cllvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV split-gep.ll

[NFC][SeparateConstOffsetFromGEP] Add pre-commit test (#191006)
DeltaFile
+46-0llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll
+46-01 files

LLVM/project 5fdc35fllvm/test/tools/llvm-mca/RISCV/SiFiveX390 vector-fp.s, llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv arithmetic.test fp.test

[RISCV][MCA] Update `sifive-x390`'s tests to consume input files instead (#190883)

In the same spirit as #189785 , use the new input file system for
sifive-x390's llvm-mca tests.
DeltaFile
+0-4,851llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
+4,526-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/arithmetic.test
+3,706-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/fp.test
+3,126-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/vlseg-vsseg.test
+2,878-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/bitwise.test
+2,334-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/permutation.test
+16,570-4,85129 files not shown
+28,366-9,99035 files

LLVM/project 179a6ballvm/lib/Target/BPF BPFISelLowering.cpp BPFISelLowering.h, llvm/test/CodeGen/BPF i128_return.ll sret.ll

bpf: Support aggregate returns (#190894)

i128 and 16 byte structs are now returned in R0:R2 which matches x86
that returns { i64, i32 } in RAX:RDX.
Both skip one register in between (RCX / R1).

Signed-off-by: Alexei Starovoitov <ast at kernel.org>
Co-authored-by: Alexei Starovoitov <ast at kernel.org>
DeltaFile
+30-24llvm/lib/Target/BPF/BPFISelLowering.cpp
+44-0llvm/test/CodeGen/BPF/i128_return.ll
+43-0llvm/test/CodeGen/BPF/sret.ll
+17-5llvm/test/CodeGen/BPF/struct_ret1.ll
+8-3llvm/test/CodeGen/BPF/struct_ret2.ll
+6-0llvm/lib/Target/BPF/BPFISelLowering.h
+148-322 files not shown
+151-378 files

LLVM/project fd09e8fclang/test/ExtractAPI availability.c objc_property.m

[ExtractAPI] fix filecheck annotation (#92231)

moved fix for ExtractAPI from
https://github.com/llvm/llvm-project/pull/91854,
https://github.com/llvm/llvm-project/pull/91854#pullrequestreview-2052128349

Also noticed typo here, prefix `E` but check for `C`, fixed too:

https://github.com/llvm/llvm-project/blob/ca4a405232cf170f20a2f111bf72beab82095935/clang/test/ExtractAPI/availability.c#L43-L65

Co-authored-by: klensy <nightouser at gmail.com>
Co-authored-by: Prajwal Nadig <pnadig at apple.com>
DeltaFile
+1-1clang/test/ExtractAPI/availability.c
+1-1clang/test/ExtractAPI/objc_property.m
+2-22 files

LLVM/project 0f3e448llvm/include/llvm/IR Instructions.h, llvm/test/Transforms/SimplifyCFG profile-update-unreachable.ll

[SimplifyCFG] Update profile metadata regardless of weight count (#190982)

Otherwise we miss updating in cases where we should be updating which
causes assertion failures later due to the fact that the number of cases
no longer matches the number of branch weights.

It looks like this was last touched in #160629, but it doesn't seem like
there is anything there specifically motivating this diff hunk.

Fixes #190901.
DeltaFile
+39-0llvm/test/Transforms/SimplifyCFG/profile-update-unreachable.ll
+11-2llvm/include/llvm/IR/Instructions.h
+50-22 files

LLVM/project 350d672flang/include/flang/Optimizer/Dialect/Support FIRContext.h, flang/lib/Optimizer/CodeGen CodeGen.cpp

[Flang] mark safe external globals as dso_local (#189709)

Globals inside a Fortran module are not marked as dso_local,
which results in their alignment not being promoted.
This fix mimics some of the functionality found in
shouldAssumeDSOLocal in /clang/lib/CIR/CodeGen/CIRGenModule.cpp

Fixes #189069
DeltaFile
+84-0flang/test/Fir/dso-local.fir
+34-0flang/lib/Optimizer/Dialect/Support/FIRContext.cpp
+17-0flang/test/Fir/dso-local-macho.fir
+13-0flang/include/flang/Optimizer/Dialect/Support/FIRContext.h
+12-0flang/lib/Optimizer/CodeGen/CodeGen.cpp
+2-2flang/test/Lower/common-block.f90
+162-21 files not shown
+164-27 files

LLVM/project c135522

Merge branch 'fix-blockfreq-unroll-unconditional-latches--tests' into fix-blockfreq-unroll-unconditional-latches
DeltaFile
+0-00 files

LLVM/project dd57f60flang/lib/Optimizer/HLFIR/Transforms SimplifyHLFIRIntrinsics.cpp, flang/test/HLFIR simplify-hlfir-intrinsics-count.fir

[flang] Use reduction recognition friendly pattern for hlfir.count. (#190856)

The change is to select between `0` and `1` based on the condition
and then add the result to the current reduction value.
DeltaFile
+8-8flang/test/HLFIR/simplify-hlfir-intrinsics-count.fir
+5-4flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+13-122 files

LLVM/project 1415b28llvm/test/Transforms/LoopUnroll loop-probability-one.ll, llvm/test/Transforms/LoopUnroll/branch-weights-freq unroll-complete.ll unroll-partial-unconditional-latch.ll

[LoopUnroll] Fix freqs for unconditional latches: introduce tests

This patch introduces all tests for PR #179520 but with current
results so that it is easier to see which results PR #179520 improves.
This patch should not land without PR #179520.
DeltaFile
+530-0llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-complete.ll
+280-0llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial-unconditional-latch.ll
+211-53llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-epilog.ll
+122-85llvm/test/Transforms/LoopUnroll/loop-probability-one.ll
+2-1llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial.ll
+1,145-1395 files

LLVM/project 0030f59llvm/lib/Target/AArch64 AArch64RedundantCopyElimination.cpp AArch64.h, llvm/test/CodeGen/AArch64 machine-copy-remove.mir machine-zero-copy-remove.mir

[NewPM] Port AArch64RedundantCopyElimination (#190582)

Adds a newPM pass for AArch64RedundantCopyElimination
- Refactors base logic into an Impl class
- Renames old pass with the "Legacy" suffix
- Adds the new pass manager pass using refactored logic
- Updated existing .mir tests to also test with the New Pass Manager.

Context and motivation in
https://llvm.org/docs/NewPassManager.html#status-of-the-new-and-legacy-pass-managers
DeltaFile
+39-15llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+8-1llvm/lib/Target/AArch64/AArch64.h
+1-1llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/test/CodeGen/AArch64/machine-copy-remove.mir
+1-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+1-0llvm/test/CodeGen/AArch64/machine-zero-copy-remove.mir
+51-176 files

LLVM/project 7b16d10llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp

Added braces.
DeltaFile
+4-3llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+4-31 files

LLVM/project 7056d00llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/InstCombine clamp-to-minmax.ll

[InstCombine][ValueTracking] Add m_FMinNum and m_FMaxNum to matchFastFloatClamp. (#188149)

This allows us to recognize clamp patterns if the first part of the
clamp has been turned into minnum/maxnum.
DeltaFile
+89-0llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
+6-0llvm/lib/Analysis/ValueTracking.cpp
+95-02 files

LLVM/project cd66d79llvm/lib/Target/Hexagon HexagonTargetMachine.cpp HexagonMachineFunctionInfo.h, llvm/test/CodeGen/Hexagon aligna-prologue-expansion.mir

[Hexagon][MIR] Serialize HexagonMachineFunctionInfo::StackAlignBaseReg to MIR (#190003)

This patch adds serialization of HexagonMachineFunctionInfo::StackAlignBaseReg
into MIR. This field stores the physical register used as the aligned-stack base pointer
when a function has both variable-sized stack objects and requires stack
alignment greater than the default.

This replaces the workaround from commit 2e10b6299591 ("[Hexagon] Add AP
register to liveins when used for frame index access") which manually added
AP to liveins. That approach was incorrect because it only updated one
block without updating predecessors, breaking liveness invariants.
DeltaFile
+36-0llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+29-0llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
+24-0llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
+6-9llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
+0-10llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+8-0llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+103-196 files

LLVM/project f3155f0clang/include/clang/Basic HLSLIntrinsics.td, clang/lib/Headers/hlsl hlsl_alias_intrinsics.h

[HLSL] Add missing Shader Model 6.0 availability for wave intrinsics (#189445)

Depends on PR #188814 to be merged first.

This PR fixes Shader Model availability for HLSL wave intrinsics so that
they all require at least SM 6.0.

Furthermore, there wasn't an easy way to specify Shader Model 6.0
availability while maintaining the requirement for Shader Model 6.2 when
16-bit types is enabled and the overload uses half types.
To fix the issue, this PR extends `_HLSL_16BIT_AVAILABILITY` to accept a
3rd optional argument that specifies the Shader Model availability when
16-bit types is disabled.

Example:
```hlsl
// If 16-bit types is enabled, require SM 6.2. Else, require SM 6.0 otherwise.
_HLSL_16BIT_AVAILABILITY(shadermodel, 6.2, 6.0)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_all_equal)

    [6 lines not shown]
DeltaFile
+42-3clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
+11-29clang/utils/TableGen/HLSLEmitter.cpp
+8-12clang/include/clang/Basic/HLSLIntrinsics.td
+11-9clang/test/TableGen/hlsl-intrinsics.td
+3-2clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+75-555 files

LLVM/project 5c8c4d8llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel wmma-gfx12-w64-imm.ll llvm.amdgcn.wmma_32.ll

[AMDGPU][GISel] RegBankLegalize support for WMMA intrinsics (#190724)
DeltaFile
+30-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+5-2llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
+39-65 files

LLVM/project ecbba86llvm/test/CodeGen/AMDGPU llvm.amdgcn.ds.gws.init.ll

[AMDGPU][NFC] Auto-generate ds.gws.init test checks (#190811)

Update ds.gws.init to use auto-generated checks. Missed this test in the
previous pre-commit.
DeltaFile
+404-93llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
+404-931 files

LLVM/project 5f39699flang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics openmp-utils.cpp resolve-directives.cpp

[flang][OpenMP] Improve checks for DO CONCURRENT in loop constructs

In OpenMP 6.0+ DO CONCURRENT is allowed as an alternative to a Canonical
Loop Nest. In other words, DO CONCURRENT is allowed inside loop constructs
as long as it's the only loop.

Add checks to detect DO CONCURRENT as the root of the associated loop
nest. Remove related checks from resolve-directives.cpp.
DeltaFile
+54-0flang/test/Semantics/OpenMP/do-concurrent-collapse-60.f90
+20-1flang/lib/Semantics/openmp-utils.cpp
+0-17flang/lib/Semantics/resolve-directives.cpp
+10-0flang/include/flang/Semantics/openmp-utils.h
+10-0flang/lib/Semantics/check-omp-loop.cpp
+0-2flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
+94-206 files

LLVM/project 82fa0a0clang/lib/Basic/Targets AArch64TargetInfoFeatures.inc AArch64.cpp, llvm/utils/TableGen/Basic ARMTargetDefEmitter.cpp

fixup! Don't checkin AArch64TargetInfoFeatures.inc but generate from tablegen
DeltaFile
+0-69clang/lib/Basic/Targets/AArch64TargetInfoFeatures.inc
+16-8clang/lib/Basic/Targets/AArch64.cpp
+23-0llvm/utils/TableGen/Basic/ARMTargetDefEmitter.cpp
+39-773 files

LLVM/project abd502allvm/lib/Target/X86 X86ISelLoweringCall.cpp, llvm/test/CodeGen/X86 musttail-struct.ll

[X86] Fix missing ByValTemporaries update in CopyViaTemp path for musttail calls (#190540)

This fixes a miscompilation in musttail calls with byval arguments on
X86.

In the CopyViaTemp path, a temporary stack object is created and the
argument is copied into it.
However, the temporary is not recorded in ByValTemporaries, 
so the final lowering phase does not emit the copy to the real outgoing
argument slot.

As a result, the callee may read incorrect values from the stack.

Fix this by recording the temporary in ByValTemporaries so that the
final lowering step correctly copies the argument to the expected stack
location.

Reproducer: https://github.com/llvm/llvm-project/issues/190429
DeltaFile
+45-13llvm/test/CodeGen/X86/musttail-struct.ll
+1-0llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+46-132 files

LLVM/project 9a81d39clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c

[CIR][AArch64] Upstream NEON Minimum (#187935)

Part of https://github.com/llvm/llvm-project/issues/185382
Added intrinsics for
vmin_*
vminq_*
vminnm_*
vminnmq_*
DeltaFile
+304-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-284clang/test/CodeGen/AArch64/neon-intrinsics.c
+14-0clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+318-2843 files

LLVM/project b6b7f31clang/lib/Driver/ToolChains Hexagon.cpp, clang/test/Driver hexagon-toolchain-linux.c

[Hexagon] Add sanitizer-aware library paths for Linux/musl targets (#190267)

When compiling with -fsanitize=memory or -fsanitize=address on
hexagon-unknown-linux-musl, the driver now prepends sanitizer-specific
library paths (e.g. $SYSROOT/usr/lib/msan/) before the normal
$SYSROOT/usr/lib/ so that instrumented libraries (libc, libc++, etc.)
are found first by the linker.
DeltaFile
+36-0clang/lib/Driver/ToolChains/Hexagon.cpp
+33-0clang/test/Driver/hexagon-toolchain-linux.c
+69-02 files