[IR] Update `PHINode::removeIncomingValueIf()` to use the swap strategy like `PHINode::removeIncomingValue()` (#172639)
As suggested in https://github.com/llvm/llvm-project/pull/171963, update
`PHINode::removeIncomingValueIf()` to use the swap strategy too.
[clang][deps] Extract `CompilerInvocation` creation (#172744)
This PR extracts the modifications we make to the scanner's
`CompilerInvocation` from multiple spots into a single function.
[BOLT][AArch64] Use minimal code alignment for cold functions (#172598)
On AArch64, a larger cold code size can result in more veneers,
increasing potential overhead for hot code. This change minimizes cold
code size when the `--use-compact-aligner` option (default) is enabled.
[lldb/test] Fix libcxx configuration handling for remote platforms (#172761)
When using --platform remote-* options, explicitly clear the libcxx
configuration variables instead of just warning and continuing with
potentially set values. This prevents the test suite from attempting to
use custom libcxx paths on remote platforms where they're not
applicable.
Also initialize libcxx variables to None when not specified, ensuring a
clean state regardless of how the arguments are parsed.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
[MLIR] Fix AsmPrinter alias uniqueness check (#172734)
A sneaky operator precedence bug caused this resize operation to always
truncate to size 0 or 1:
```
probeAlias.resize(alias.size() + isdigit(alias.back()) ? 1 : 0);
```
Because `+` is associated more strongly than the ternary operator. This
eventually led to the asm printer repeating an alias name, generating
illegal IR.
It wasn't a problem in most cases because it required two things to
trigger:
- Two naturally generated aliases, one "xxx" the other "xxx1" (note the
trailing "1").
- A unique processing order such that we process "xxx", then "xxx1",
then "xxx" again. This can only happen if they happen to be at different
"alias depths", since otherwise the pre-sorting will make sure this
ordering never happens. See the added test case for how this works in
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[MLIR][Transform] Fix transform.smt.constrain_params's verifier (#172753)
Verifier was insisting on `!transform.param<...>` too early and hence
crashed on `!transform.any_param`.
[VPlan] Add VPBlockUtils::transferSuccessors (NFCI).
Add a new helper to transfer successors to a new, unconnected VPBB.
Helps to simplify existing code, and prepare for upcoming changes.
Use the Propeller CFG profile in the PGO analysis map if it is available. (#163252)
This PR implements the emitting of the post-link CFG information in PGO
analysis map, as explained in the
[RFC](https://discourse.llvm.org/t/rfc-extending-the-pgo-analysis-map-with-propeller-cfg-frequencies/88617).
This is enabled by a flag `pgo-analysis-map-emit-bb-sections-cfg`.
This PR bumps the SHT_LLVM_BB_ADDR_MAP version to 5.
Also includes some refactoring changes related to storing the CFG in the
Basic block sections profile reader.
[scudo] Add an option to zero memory on deallocation. (#142394)
When all the blocks of a page are unused, the page will be full of zero
and decommitted on operating systems that scan the memory.
Change-Id: I278055d82057090b0a04d812b49cf93fdf467478
Co-authored-by: Christopher Ferris <cferris1000 at users.noreply.github.com>
[HLSL][Matrix] Add support for single subscript accessor (#170779)
fixes #166206
- Add swizzle support if row index is constant
- Add test cases
- Add new AST type
- Add new LValue for Matrix Row Type
- TODO: Make the new LValue a dynamic index version of ExtVectorElt
[lldb] Fix TestIvarProtocols to use +new instead of +alloc (NFC) (#172740)
A test failure on green dragon shows the ivars with unexpected values.
This makes the test us an explicit `+new` instead of `+alloc` (which is
missing an `-init` call).
