LLVM/project 996ce0d — llvm/test/CodeGen/LoongArch/lasx xvldrepl-frame-index.ll, llvm/test/CodeGen/LoongArch/lsx vldrepl-frame-index.ll

[LoongArch] Pre-commit tests for misaligned frame-index offset on vldrepl (#239515)

Assisted-by: LLM
(cherry picked from commit edcf6269a0da3f25c4445c0cc9fc0d182707b5ff)
DeltaFile
+76-0llvm/test/CodeGen/LoongArch/lsx/vldrepl-frame-index.ll
+76-0llvm/test/CodeGen/LoongArch/lasx/xvldrepl-frame-index.ll
+152-02 files

LLVM/project c47d782 — llvm/lib/Target/LoongArch LoongArchRegisterInfo.cpp, llvm/test/CodeGen/LoongArch/lasx xvldrepl-frame-index.ll

[LoongArch] Fix misaligned frame-index offset for vldrepl.{h,w,d} (#239516)

eliminateFrameIndex did not check that the final offset is a multiple of
the access size for [X]VLDREPL_{H,W,D}, so a byte-aligned stack object
could produce an unencodable immediate. Materialize the address in a
scratch register in that case, as is already done for [X]VSTELM_*.

Assisted-by: LLM

Fixes #239508

(cherry picked from commit 3ade2bcaa2f31acdf4011e965d5ae39c39796671)
DeltaFile
+12-0llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
+6-3llvm/test/CodeGen/LoongArch/lsx/vldrepl-frame-index.ll
+6-3llvm/test/CodeGen/LoongArch/lasx/xvldrepl-frame-index.ll
+24-63 files

LLVM/project fa5a27d — llvm/test/Transforms/LoopVectorize find-last.ll

[LV] Add tests for FindLast reductions with nested phis (NFC). (#230640)

Add tests where the data value of a FindLast reduction is itself a phi
that yields the reduction phi on some paths, e.g. via a nested if. Both
are currently miscompiled, as the outer condition is used as the
condition for updating the reduction.

Also enable masked memory ops and regenerate checks with the latest UTC
version to make checks more compact without loss of generality.

(cherry picked from commit 2f272fc322cdc1fe1fbb667cd2cb6abddeb0eb9b)
DeltaFile
+299-161llvm/test/Transforms/LoopVectorize/find-last.ll
+299-1611 files

LLVM/project b2307d2 — llvm/lib/Transforms/Vectorize VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize find-last.ll

[VPlan] Bail out on FindLast reductions with extra phi users. (#230676)

handleFindLastReductions uses the mask of the single non-phi incoming
value of the find-last blend as the condition for updating the
reduction. If the data value itself is the reduction phi on some paths,
e.g. via a nested blend for an inner if, the mask is also true for lanes
that keep the old value, and extract-last-active may then pick a stale
lane.

Conservatively bail out if the reduction phi has users other than the
find-last select/blend and the header mask select.

(cherry picked from commit 79caa03343df4da7b8ae0338d932125ef4bcf20b)
DeltaFile
+2-67llvm/test/Transforms/LoopVectorize/find-last.ll
+8-0llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+10-672 files

LLVM/project aa7ff64 — flang/test/Semantics/OpenMP linear-clause01.f90

[flang][OpenMP] Fix DECLARE_SIMD warning annotations in linear-clause01.f90

release/23.x picked 2cc5b8ca (warn on ignored DECLARE_SIMD) before
94467edd (REF modifier verification), the reverse of their order on main.
2cc5b8ca therefore annotated only Case 1-4, and 94467edd later appended
Case 5-7 without the warning annotation, failing check-flang at lines
76/83/90.

Assisted-by: Claude
DeltaFile
+3-0flang/test/Semantics/OpenMP/linear-clause01.f90
+3-01 files

LLVM/project ee2b7a2 — llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp, llvm/test/CodeGen/X86 null-pointer-vector-object.ll

[AsmPrinter] Emit null pointer vector splats as zero bytes (#235980)

Emitting a global such as `@x = global <2 x ptr> zeroinitializer` with
`llc -data-sections -filetype=obj` asserts on 64-bit targets.
`ConstantPointerNull` can represent a vector splat since #195486, but
AsmPrinter passes the entire allocation size to
`MCStreamer::emitIntValue`, which accepts at most eight bytes.

Route pointer-vector splats through `emitGlobalConstantVector`, matching
the existing handling of integer and floating-point splats. Its
zero-value path emits the full allocation with `emitZeros`. Keep scalar
pointers on the existing `emitIntValue` path.

Fixes #235977

Assisted-by: OpenAI Codex
(cherry picked from commit fed20e0e68323be32cb0fe8af679b8cb34e72112)
DeltaFile
+20-0llvm/test/CodeGen/X86/null-pointer-vector-object.ll
+2-0llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+22-02 files

LLVM/project 6ce52ac — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 pr235663.ll

[DAG] LowerShiftByScalarImmediate - early out for shift-by-zero cases (#237365)

Also, add assertions to getGFNICtrlImm that we don't try to shift by
zero

Fixes #235663

(cherry picked from commit 4eff20caf9ca079c6c779f1a0029e7a8f86f4790)
DeltaFile
+6-23llvm/test/CodeGen/X86/pr235663.ll
+13-3llvm/lib/Target/X86/X86ISelLowering.cpp
+19-262 files

LLVM/project 5bc6d89 — llvm/test/CodeGen/X86 pr235663.ll

[DAG] Add test coverage for #235663 (#237334)

(cherry picked from commit 3f311dec0d286a053802198a2e061f1b65f8cd3d)
DeltaFile
+63-0llvm/test/CodeGen/X86/pr235663.ll
+63-01 files

LLVM/project a4ae88b — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 pr236021.ll

[X86] incDecVectorConstant - use ++/-- prefix operator to increment/decrement (#237176)

Don't just add immediate as it might not promote correctly to types
greater than 64-bits

Fixes #236021

(cherry picked from commit f64f3ea8f0f456790399fb50c7df368eafd26686)
DeltaFile
+4-4llvm/test/CodeGen/X86/pr236021.ll
+2-2llvm/lib/Target/X86/X86ISelLowering.cpp
+6-62 files

LLVM/project abce5cb — llvm/test/CodeGen/X86 pr236021.ll

[X86] Add baseline test for #236021 (#237155)

(cherry picked from commit 6fa91d905f12193ddb624e2374aea1be259d8fb6)
DeltaFile
+40-0llvm/test/CodeGen/X86/pr236021.ll
+40-01 files

LLVM/project dcf3540 — llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 abds.ll

[DAG] foldSelectToABD - ensure -Constant negation doesn't overflow (#235279)

The (setcc (add nsw A, Const), 0, sets??) --> (setcc A, -Const, sets??)
fold is only valid if Const isn't MIN_SIGNED_INT

Fixes #235263
DeltaFile
+65-0llvm/test/CodeGen/X86/abds-vector-128.ll
+15-0llvm/test/CodeGen/AArch64/abds.ll
+4-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+84-13 files

LLVM/project 52039e3 — llvm/test/CodeGen/AArch64 stack-coloring-alignment.ll

Update llvm/test/CodeGen/AArch64/stack-coloring-alignment.ll

Fix test failure due to release/23.x not containing @tomershafir's change that prints labels in the ScheduleDAG output.

Co-authored-by: Nathan Corbyn <me at nathancorbyn.com>
DeltaFile
+0-1llvm/test/CodeGen/AArch64/stack-coloring-alignment.ll
+0-11 files

LLVM/project 13b0ce2 — llvm/lib/CodeGen StackColoring.cpp, llvm/test/CodeGen/AArch64 stack-coloring-alignment.ll

[StackColoring] Update IR when merging stack slots of differing alignment (#237412)

(cherry picked from commit 7c3ae84d7f3a14bea27de8eac22cf8f7964ac711)
DeltaFile
+33-0llvm/test/CodeGen/AArch64/stack-coloring-alignment.ll
+4-0llvm/lib/CodeGen/StackColoring.cpp
+37-02 files

LLVM/project 62f97ed — llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize interleaved-accesses.ll

[LV] Invalidate interleave-groups with gaps if for early-exit loops. (#237409)

If the loop exits from a block other than the latch, the scalar
iteration reserved for the exit may leave the loop before reaching the
grouped accesses.

Invalidate interleave groups in the case, to avoid mis-compile.

Fixes https://github.com/llvm/llvm-project/issues/237192.

(cherry picked from commit ccce555818cd682aff8ae4b9d72eb8ed0044331c)
DeltaFile
+169-0llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
+8-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+177-12 files

LLVM/project 032c6b6 — lld/ELF/Arch LoongArch.cpp, lld/test/ELF loongarch-tls-ie64.s loongarch-tlsdesc64.s

[lld][LoongArch] Fix crash with TLS IE relocations in extreme code model (#234508)

Restore TLS IE and DESC relocation expressions needed by the extreme
code model fallback in relocateAlloc().

Fixes: #234507
(cherry picked from commit c98ead286790d9ed6d02a10b02129e63c66c965c)
DeltaFile
+120-0lld/test/ELF/loongarch-tlsdesc64.s
+71-0lld/test/ELF/loongarch-tls-ie64.s
+15-0lld/ELF/Arch/LoongArch.cpp
+206-03 files

LLVM/project feca64d — clang/test/OpenMP declare_variant_construct_match_kind.c, flang/test/Lower/OpenMP metadirective-implementation.f90

[OpenMP] Fix context selector matching and scoring

OMPContext computes some context selector scores differently from the
OpenMP 5.2 rules in "Matching and Scoring Context Selectors", and
crashes on some selectors. Fix the following; each can change which
variant is selected:

- Device weights. kind, arch, and isa are worth 2^l, 2^(l+1), and
  2^(l+2), where l is the depth of the construct context. OMPContext
  used the candidate's own construct selector count, so inside two
  nested parallel regions kind(cpu) was worth 1 instead of 4 and lost
  to vendor(score(2): llvm).
- Scores per selector. A score belongs to a trait selector, but it was
  added once per property, so vendor(score(10): llvm, amd) counted 20.
  Scores now add once, using arbitrary-width arithmetic instead of
  wrapping 64-bit sums.
- Repeated constructs. When a construct selector can match several
  enclosing constructs, the highest-valued complete match counts.
  construct={parallel} inside three nested parallel regions now adds 2^2

    [29 lines not shown]
DeltaFile
+248-17llvm/unittests/Frontend/OpenMPContextTest.cpp
+108-96llvm/lib/Frontend/OpenMP/OMPContext.cpp
+30-0clang/test/OpenMP/declare_variant_construct_match_kind.c
+12-0flang/test/Lower/OpenMP/metadirective-implementation.f90
+398-1134 files

LLVM/project 6d78cd4 — clang/test/OpenMP declare_variant_construct_target.c, flang/test/Lower/OpenMP metadirective-construct.f90

Test device weights at the TARGET boundary

KIND's weight depends on the depth of the construct context, which
starts at the innermost enclosing TARGET. A PARALLEL outside the TARGET
must not raise it, and a PARALLEL inside must.
DeltaFile
+38-0clang/test/OpenMP/declare_variant_construct_target.c
+35-0flang/test/Lower/OpenMP/metadirective-construct.f90
+73-02 files

LLVM/project 60a9817 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 alternate-cmp-minbitwidth-mixed-extends.ll

[SLP]Fix narrowing of alternate icmp with mismatched extensions

Extend the operands of alternate compares back to the original type
unless both predicates match the operand signedness, as done for
non-alternate compares.

Fixes #240119

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240141
DeltaFile
+36-31llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-2llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-minbitwidth-mixed-extends.ll
+40-332 files

LLVM/project 3350d84 — llvm/test/Transforms/SLPVectorizer/X86 alternate-cmp-minbitwidth-mixed-extends.ll

[SLP][NFC]Add a test with incorrect alt cmp compare, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240140
DeltaFile
+32-0llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-minbitwidth-mixed-extends.ll
+32-01 files

LLVM/project 3c5198c — llvm/test/Transforms/SLPVectorizer/X86 alternate-cmp-minbitwidth-mixed-extends.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+32-0llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-minbitwidth-mixed-extends.ll
+32-01 files

LLVM/project d1823a0 — libc/src/math/generic sin.cpp CMakeLists.txt, utils/bazel/llvm-project-overlay/libc BUILD.bazel

[libc][math] Fix LIBC_MATH_HAS_SMALL_TABLES check in sin.cpp and cos.cpp (#240076)
DeltaFile
+3-1libc/src/math/generic/cos.cpp
+1-1libc/src/math/generic/sin.cpp
+2-0libc/src/math/generic/CMakeLists.txt
+1-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+7-24 files

LLVM/project e26b6cf — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 minmax-reduction-leaf-after-cmp.ll

[SLP] Emit min/max reduction at the root select, not its compare

The min/max matcher accepts select (cmp X, Y), X, Y' with Y' identical
to Y but defined after the compare. Emitting the reduction before the
compare used Y' before its definition. The compare position was needed
only while the reduction replaced the compare uses, removed in D99753.
The root compare now has a single use, so emit at the select, which
all reduced values dominate.

Fixes #240006.

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240133
DeltaFile
+61-0llvm/test/Transforms/SLPVectorizer/X86/minmax-reduction-leaf-after-cmp.ll
+1-17llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+62-172 files

LLVM/project c324fc9 — llvm/test/CodeGen/AArch64 red_mla_f16_f32.ll peephole-insert-subreg.mir

[AArch64] Add tests for inserting 8/16/32 bit register values into 0. NFC (#240132)

peephole-insert-subreg.mir is cleaned up a bit at the same time.
DeltaFile
+352-51llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
+209-0llvm/test/CodeGen/AArch64/red_mla_f16_f32.ll
+561-512 files

LLVM/project 6e0b2a4 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV revec-strided-store.ll basic-strided-stores.ll

[SLP]Fix stride of reversed strided stores

Keep the store stride in scalar order and apply the reverse in cost and
codegen, matching strided loads. Do not overwrite stride info of
already strided stores when they become reversed after reordering.

Fixes #240004.

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240131
DeltaFile
+8-7llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-1llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll
+1-1llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-stores.ll
+10-93 files

LLVM/project ddd7529 — llvm/lib/Target/AArch64/GISel AArch64GlobalISelUtils.cpp, llvm/test/CodeGen/AArch64 shift.ll overflow-vec.ll

[GlobalISel][AArch64] Lower vector shift right by register in post-legalizer combiner (#231508)

GlobalISel emitted an extra `neg` for vector right shifts by a non-splat
constant. The negation is now folded into the constant, matching
SelectionDAG.

```llvm
define <16 x i8> @test(<16 x i8> %a) {
  %r = ashr <16 x i8> %a, <i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6>
  ret <16 x i8> %r
}
```

Before:
```
adrp x8, .LCPI0_0
ldr  q1, [x8, :lo12:.LCPI0_0]
neg  v1.16b, v1.16b
sshl v0.16b, v0.16b, v1.16b

    [9 lines not shown]
DeltaFile
+242-308llvm/test/CodeGen/AArch64/combine-sdiv.ll
+81-92llvm/test/CodeGen/AArch64/overflow-vec.ll
+108-0llvm/test/CodeGen/AArch64/shift.ll
+98-0llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-vshr-to-sshl.mir
+23-30llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
+23-0llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+575-4304 files not shown
+620-45010 files

LLVM/project bdbe428 — llvm/test/Transforms/SLPVectorizer/RISCV revec-strided-store.ll

[SLP][NFC]Add incorrect strided store in revec mode, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240130
DeltaFile
+17-0llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll
+17-01 files

LLVM/project 2001575 — llvm/test/Transforms/SLPVectorizer/RISCV basic-strided-stores.ll

[SLP][NFC]Add a test with incorrect stride stores, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240129
DeltaFile
+25-0llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-stores.ll
+25-01 files

LLVM/project 5ef6400 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 loads-from-single-predecessor.ll

[SLP]Fix external uses of the pointers of the jumbled copyable loads

The wide load of the copyable loads uses the pointer of the first load,
which may differ from the main op after reordering. Use it as the root
instruction to correctly detect the pointers, which need extracts.

Fixes https://github.com/llvm/llvm-project/pull/233297#issuecomment-6720659110

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240127
DeltaFile
+58-0llvm/test/Transforms/SLPVectorizer/X86/loads-from-single-predecessor.ll
+3-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+61-02 files

LLVM/project 4706770 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer gathered-swapped-vectorized-lanes.ll extract-many-users-buildvector.ll

[SLP] Price gathered lanes of vectorized entries as a shuffle

A gathered lane already vectorized in another entry is moved out of
that vector with a shuffle, which a zero insert price misses. Add the
shuffle cost of these lanes when their insert price is zero.
DeltaFile
+35-32llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-operand-deps-direct-use.ll
+21-22llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
+34-0llvm/test/Transforms/SLPVectorizer/RISCV/gathered-lane-of-vectorized-entry-zve32.ll
+14-15llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-subtree-schedule-operands.ll
+14-12llvm/test/Transforms/SLPVectorizer/gathered-swapped-vectorized-lanes.ll
+20-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+138-817 files not shown
+166-10713 files

LLVM/project 31b1858 — llvm/test/Transforms/SLPVectorizer gathered-swapped-vectorized-lanes.ll, llvm/test/Transforms/SLPVectorizer/AArch64 gathered-lane-of-vectorized-loads.ll

[NFC][SLP] Add tests for gathers of lanes from vectorized entries
DeltaFile
+92-0llvm/test/Transforms/SLPVectorizer/AMDGPU/gathered-load-strided-picks.ll
+58-0llvm/test/Transforms/SLPVectorizer/gathered-swapped-vectorized-lanes.ll
+25-0llvm/test/Transforms/SLPVectorizer/AArch64/gathered-lane-of-vectorized-loads.ll
+175-03 files