LLVM/project f615c5allvm/include/llvm/IR RuntimeLibcalls.td

ARM: Avoid adding default libcalls overridden by AEABI functions

Avoids adding alternative libcall impls for the same libcall.

I'm not sure if the default names exist or not, or are just not
preferred. compiler-rt appears to define aliases for all of these,
so I'm not sure why we bother distinguishing these in the first place.
DeltaFile
+42-1llvm/include/llvm/IR/RuntimeLibcalls.td
+42-11 files

LLVM/project a84fbd5llvm/include/llvm/IR RuntimeLibcalls.td

X86: Make sure compiler-rt div calls are not added for msvc

The current predicate system is primitive, we ought to have
a way to list a chain of alternatives.
DeltaFile
+12-2llvm/include/llvm/IR/RuntimeLibcalls.td
+12-21 files

LLVM/project 66d3765llvm/include/llvm/IR RuntimeLibcalls.td

RuntimeLibcalls: Make sure _Unwind_Resume entries are mutually exclusive
DeltaFile
+11-2llvm/include/llvm/IR/RuntimeLibcalls.td
+11-21 files

LLVM/project 26450dbllvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64TargetTransformInfo.cpp

AArch64: Use RuntimeLibcallsInfo in SMEAttributes (NFC) (#164968)

Eventually this should be program state, and not part of TargetLowering
so avoid direct references to the libcall functions in it.

The usage of RuntimeLibcallsInfo here is not good though, particularly
the use through TargetTransformInfo. It would be better if the IR
attributes were directly encoded in the libcall definition (or at least made
consistent elsewhere). The parsing of the attributes should not also be 
responsible for doing the libcall recognition, which is the only part pulling in 
the dependency.
DeltaFile
+10-9llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
+8-6llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-4llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
+3-2llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+4-0llvm/include/llvm/CodeGen/TargetLowering.h
+30-215 files

LLVM/project ab9bdb7llvm/test/CodeGen/AArch64 aarch64-matrix-umull-smull.ll

[AArch64] Add an extra long-multiple test case. NFC
DeltaFile
+453-36llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+453-361 files

LLVM/project 426d1feoffload/include OffloadPolicy.h, offload/include/OpenMP InternalTypes.h omp.h

[OFFLOAD] Remove weak from __kmpc_* calls and gather them in one header (#164613)

Follow-up from #162652

---------

Co-authored-by: Michael Klemm <michael.klemm at amd.com>
DeltaFile
+0-23offload/libomptarget/OpenMP/API.cpp
+17-4offload/include/OpenMP/InternalTypes.h
+0-8offload/libomptarget/OpenMP/InteropAPI.cpp
+0-2offload/include/OffloadPolicy.h
+1-1offload/include/OpenMP/omp.h
+18-385 files

LLVM/project f6d8f55clang/lib/Parse ParseHLSL.cpp

[NFC][clang] cleanup dead code (#164977)

Dead code probably left-over of some PR refactoring.
DeltaFile
+0-6clang/lib/Parse/ParseHLSL.cpp
+0-61 files

LLVM/project c0b27cfutils/bazel/llvm-project-overlay/lldb BUILD.bazel

Revert "[bazel][lldb] Port #162730: tablegen for lldb-server platform ops" (#164981)

Reverts llvm/llvm-project#164832. The corresponding
[#162730](https://github.com/llvm/llvm-project/pull/162730) was reverted
in
https://github.com/llvm/llvm-project/commit/aac036a7f6730118f0d832150243d66b603c3af3.
DeltaFile
+2-12utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
+2-121 files

LLVM/project 025add6utils/bazel/llvm-project-overlay/lldb BUILD.bazel

Revert "[bazel][lldb] Port #162730: tablegen for lldb-server platform ops (#1…"

This reverts commit 0ac4a715f55ed860268740ad5f5535161b6cb552.
DeltaFile
+2-12utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
+2-121 files

LLVM/project 8e6abdcllvm/test/MC/AMDGPU literals.s

[AMDGPU][MC][NFC] Fix True16 instructions in the literals test.
DeltaFile
+24-28llvm/test/MC/AMDGPU/literals.s
+24-281 files

LLVM/project 548424cllvm/utils update_mc_test_checks.py

[Utils][NFC] Clean up update_mc_test_checks.py.

Refine the code a bit to make it easier to comprehend the logic.
DeltaFile
+21-37llvm/utils/update_mc_test_checks.py
+21-371 files

LLVM/project 61a3a85llvm/test/MC/AMDGPU literals.s, llvm/utils update_mc_test_checks.py

[Utils][update_mc_test_checks] Support updating round-trip tests.
DeltaFile
+88-57llvm/test/MC/AMDGPU/literals.s
+7-5llvm/utils/update_mc_test_checks.py
+95-622 files

LLVM/project 76b6399llvm/include/llvm/CodeGen TargetLowering.h

DAG: Remove unused TargetLowering field (#164969)

This has been dead since 97bfb936af4077e8cb6c75664231f27a9989d563
DeltaFile
+0-4llvm/include/llvm/CodeGen/TargetLowering.h
+0-41 files

LLVM/project ee36414llvm/lib/Target/AArch64/Utils AArch64SMEAttributes.h

Remove forward decl
DeltaFile
+0-2llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
+0-21 files

LLVM/project 32c0cd3llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64TargetTransformInfo.cpp

AArch64: Use RuntimeLibcallsInfo in SMEAttributes (NFC)

Eventually this should be program state, and not part of TargetLowering
so avoid direct references to the libcall functions in it.

The usage of RuntimeLibcallsInfo here is not good though, particularly
the use through TargetTransformInfo. It would be better if the IR attributes
were directly encoded in the libcall definition (or at least made consistent
elsewhere). The parsing of the attributes should not also be responsible for
doing the libcall recognition, which is the only part pulling in the
dependency.
DeltaFile
+10-7llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
+8-6llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-4llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
+3-2llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+4-0llvm/include/llvm/CodeGen/TargetLowering.h
+30-195 files

LLVM/project fe5f499llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp

[AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122)

Add GlobalISel lowering of G_FMINIMUM and G_FMAXIMUM following the same
logic as in SDag's expandFMINIMUM_FMAXIMUM.
Update AMDGPU legalization rules: Pre GFX12 now uses new lowering method
and make G_FMINNUM_IEEE and G_FMAXNUM_IEEE legal to match SDag.
DeltaFile
+790-131llvm/test/CodeGen/AMDGPU/fmaximum.ll
+790-131llvm/test/CodeGen/AMDGPU/fminimum.ll
+275-0llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
+275-0llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
+74-0llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+30-23llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+2,234-2851 files not shown
+2,235-2857 files

LLVM/project a9638ecllvm/unittests/ExecutionEngine/Orc CMakeLists.txt

Merge branch 'main' into users/arsenm/aarch64/use-runtime-libcalls-info-sme-attrs
DeltaFile
+1-0llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
+1-01 files

LLVM/project c6cc7b1llvm/include/llvm/CodeGen TargetLowering.h

DAG: Remove unused TargetLowering field

This has been dead since 97bfb936af4077e8cb6c75664231f27a9989d563
DeltaFile
+0-4llvm/include/llvm/CodeGen/TargetLowering.h
+0-41 files

LLVM/project e717d00llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64TargetTransformInfo.cpp

AArch64: Use RuntimeLibcallsInfo in SMEAttributes

Eventually this should be program state, and not part of TargetLowering
so avoid direct references to the libcall functions in it.

The usage of RuntimeLibcallsInfo here is not good though, particularly
the use through TargetTransformInfo. It would be better if the IR attributes
were directly encoded in the libcall definition (or at least made consistent
elsewhere). The parsing of the attributes should not also be responsible for
doing the libcall recognition, which is the only part pulling in the
dependency.
DeltaFile
+10-7llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
+8-6llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-4llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
+3-2llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+4-0llvm/include/llvm/CodeGen/TargetLowering.h
+30-195 files

LLVM/project 26db214llvm/unittests/ExecutionEngine/Orc CMakeLists.txt

Fix link error with shared libraries

/usr/bin/ld: unittests/ExecutionEngine/Orc/CMakeFiles/OrcJITTests.dir/L
ibraryResolverTest.cpp.o: undefined reference to symbol '_ZN4llvm4yaml1
1convertYAMLERNS0_5InputERNS_11raw_ostreamENS_12function_refIFvRKNS_5Tw
ineEEEEjm'
/usr/bin/ld: lib/libLLVMObjectYAML.so.22.0git: error adding symbols: DS
O missing from command line
DeltaFile
+1-0llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
+1-01 files

LLVM/project 6c5770dllvm/include/llvm/IR RuntimeLibcalls.td

RuntimeLibcalls: Avoid reporting __stack_chk_guard as available for msvc (#164133)

The predicate system is currently primitive and alternative call
predicates
should be mutually exclusive.
DeltaFile
+15-6llvm/include/llvm/IR/RuntimeLibcalls.td
+15-61 files

LLVM/project f5a2e6bllvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen TargetLoweringBase.cpp

CodeGen: Remove overrides of getSSPStackGuardCheck (NFC) (#164044)

All 3 implementations are just checking if this has the
windows check function, so merge that as the only implementation.
DeltaFile
+0-9llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+0-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+0-9llvm/lib/Target/ARM/ARMISelLowering.cpp
+5-0llvm/lib/CodeGen/TargetLoweringBase.cpp
+1-1llvm/include/llvm/CodeGen/TargetLowering.h
+0-1llvm/lib/Target/AArch64/AArch64ISelLowering.h
+6-292 files not shown
+6-318 files

LLVM/project 7d4430bmlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc TosaOps.td, mlir/test/Dialect/Tosa tosa-validation-version-1p1-valid.mlir invalid_extension.mlir

[mlir][tosa] Add ext-mxfp support for const and cast ops (#163641)

This commit allows const and cast ops with MXFP datatypes through the
validation pass when specification version 1.1.draft is selected.

Note: it doesn't include support for the mxint8 datatype. This will be
added in a separate commit.

Note: this commit adds support as defined in the spec in
https://github.com/arm/tosa-specification/commit/063846a75b9687ab01e58cb3538472bffb3a03b0.
EXT_MXFP extension is considered experimental and subject to breaking
change.
DeltaFile
+15-2mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+16-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+14-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+2-2mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+2-2mlir/test/Dialect/Tosa/availability.mlir
+49-65 files

LLVM/project c087b80llvm/lib/Target/Xtensa XtensaInstrInfo.td, llvm/test/MC/Disassembler/Xtensa debug.txt

[Xtensa] Fix encoding of `break.n` (#155159)

According to the manual, bits 3...0 should be 1101. (1100 is `movi.n`.)
DeltaFile
+1-1llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+1-1llvm/test/MC/Disassembler/Xtensa/debug.txt
+1-1llvm/test/MC/Xtensa/debug.s
+3-33 files

LLVM/project 9e16046llvm/lib/Transforms/Scalar LoopIdiomRecognize.cpp

Test
DeltaFile
+209-0llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
+209-01 files

LLVM/project 9e7a3eelld/test riscv-vendor-relocations.s, lld/test/ELF riscv-vendor-relocations.s

[lld] Fix RISCV vendor relocation testcase to require RISCV

Fixes test issue introduced in 357b030f5e62a5891fd6120c02aa28d0874f0a06
DeltaFile
+19-0lld/test/ELF/riscv-vendor-relocations.s
+0-18lld/test/riscv-vendor-relocations.s
+19-182 files

LLVM/project d34ead1clang/lib/Basic/Targets AArch64.h AArch64.cpp, clang/lib/Driver/ToolChains Linux.cpp Clang.cpp

[PAC][clang] Handle pauthtest environment and ABI in Linux-specific code (#113151)

Since pauthtest is a Linux-specific ABI, it should not be handled in
common driver code.
DeltaFile
+96-0clang/lib/Driver/ToolChains/Linux.cpp
+3-56clang/lib/Driver/ToolChains/Clang.cpp
+25-9clang/test/Driver/aarch64-ptrauth.c
+0-21clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+11-0clang/lib/Basic/Targets/AArch64.h
+1-8clang/lib/Basic/Targets/AArch64.cpp
+136-947 files not shown
+150-10013 files

LLVM/project a2f3811utils/bazel/llvm-project-overlay/llvm/unittests BUILD.bazel

[bazel] Add dependency for 4f53413ff0a5e33cf6e39f538d4103fe0e310bf4
DeltaFile
+1-0utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
+1-01 files

LLVM/project 6a5d2d6llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 dup-ext-load-combine.ll load-zext-bitcast.ll

[AArch64] Optimize splat of extending loads to avoid GPR->FPR transfer

Loads the data into the SIMD register, thus sparing a physical register
and a potentially costly movement of data.

Consolidated into a template which also handles a similar bitconvert
pattern.
DeltaFile
+178-0llvm/test/CodeGen/AArch64/dup-ext-load-combine.ll
+58-16llvm/lib/Target/AArch64/AArch64InstrInfo.td
+19-26llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
+24-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+6-8llvm/test/CodeGen/AArch64/aarch64-smull.ll
+6-6llvm/test/CodeGen/AArch64/dup.ll
+291-576 files

LLVM/project cf0eed5clang/test/Sema/AArch64 arm_sve_feature_dependent_sve___sme.c, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

Merge branch 'main' into users/kovdan01/pauthtest-linux-specific
DeltaFile
+57,934-50,246llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+13,963-13,220llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+19,255-3,889llvm/test/CodeGen/RISCV/atomic-rmw.ll
+19,470-0clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme.c
+6,798-4,602llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+6,646-4,528llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+124,066-76,48512,569 files not shown
+1,018,062-393,57712,575 files