[SPIR-V] Fix removeCapabilityIf not pruning MinimalCaps (#206478)
removeCapabilityIf erased from AllCaps but not MinimalCaps, which is
what the AsmPrinter iterates to emit OpCapability, so pruned
capabilities were still emitted
[ORC] Support new ORC runtime in UnwindInfoRegistrationPlugin. (#206680)
Reworks UnwindInfoRegistrationPlugin::Create(ES) to look up the
register/deregister implementation addresses by symbol name, with
default names matching the SPS-CI alloc actions provided by
orc_rt::StandaloneMachOUnwindInfoRegistrar. In OrcTargetProcess,
UnwindInfoManager::addBootstrapSymbols now also vends its register and
deregister actions under those same names, so the new Create overloads
work against either backend.
Also removes a declared but unused (and undefined) Create overload.
[AArch64] SME definitions for C1-Ultra scheduling model (#194850)
This patch extends the C1-Ultra scheduling model to add support for SME
instructions. These instructions differ from legacy scheduling model
instruction definitions in that they are sent to the CME co-processor
when in streaming mode. Modelling these instructions requires several
changes to the scheduling model
- implementations of instructions added by SME but don't require the
processor to be in streaming mode
- definitions of CME processor resources. Instructions sent to this
co-processor are modelled as having latency derived from the SME
software optimization guide (SWOG),
- predicating the process resource groups for instructions sent to the
CME coprocessor when in streaming mode,
- tests for all SME instructions in the software optimization guide
C1-Ultra SWOG: https://developer.arm.com/documentation/111079/3-0
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[Object][COFF] Introduce the .obj.arm64ec section (#205156)
Introduce a new extension section allowing the embedding of ARM64EC
object files inside native ARM64 object files. Its content consists of
an entire, valid ARM64EC COFF object file.
[X86] Add AVX512F-only test coverage to vector-reduce-add tests (#206686)
Many of the lowerings use AVX512BW instructions - make sure we don't try to use them without it
[CodeGen] Add widening support for ISD::CTTZ_ELTS (#205841)
WidenVectorOperand had no handler forCTTZ_ELTS/
CTTZ_ELTS_ZERO_POISON, causing a fatal error when the input vector type
needed widening.
Add WidenVecOp_CttzElements which widens the input vector and pads the
extra lanes with all-ones, ensuring they do not contribute spurious
trailing zeros to the count. This follows the same pattern as the
existing
WidenVecOp_VP_CttzElements.
Assisted-by: Claude (Anthropic)
[LFI][AArch64] Add guard elimination optimization (#204693)
This adds support for the guard elimination optimization to the AArch64
LFI rewriter. Redundant guards (`add x28, x27, wN, uxtw` instructions)
will be skipped when possible. See the LFI.rst documentation for an
example of the optimization.
[GVN] Support critical-edge splitting in loop-load PRE
When the only in-loop blocker of a loop-load PRE candidate has multiple successors, the reload was placed at the end of that block, so it also ran on the loop-exit edge. Split the critical edge to the unique in-loop successor and insert the reload there, so it runs only on the path back to the header. Bail out on indirectbr or multiple in-loop successors, and keep backedge splitting gated behind the existing flag. Also refresh the stale TODO comments on the freeable-pointer tests, which stay un-PRE'd because the pointer may be freed.
[GVN] Add tests for loop-load PRE into a multi-successor block
Precommit tests for loop-load PRE when the loaded pointer cannot be freed (a gc-managed address-space pointer and a nofree function). PRE currently fires but sinks the reload into a cold block with multiple successors, so it also runs on the loop-exit edge.
[lit] Add stream-injectable run() core to builtin cat (#204711)
Pull cat's logic out into run(argv, stdin, stdout, stderr, cwd) so it
takes explicit streams instead of touching sys.std* directly. main()
just calls run() with the real process streams, so nothing changes for
the spawned-script path.
Needed before cat can run in-process inside the lit worker
Also switched file reads to raw bytes throughout, since the old
text-mode read + win32 msvcrt.setmode was only there for sys.stdout's
encoding, which doesn't apply once we pass in a binary stream directly.
Error messages still report the original filename, not the cwd-joined
path.
Signed-off-by: Prasoon Kumar <prasoonkumar054 at gmail.com>
[lit] Use provided streams in builtin diff (#204869)
We want to move the diff builtin to run in-process inside the lit
worker, instead of spawning a subprocess. The current implementation
talks to sys.stdin / stdout / stderr directly, so it can't be called
with different streams.
To fix this, pull diff's logic into run(argv, stdin, stdout, stderr,
cwd), which takes streams as arguments instead of reaching for sys.std*.
main() now just calls run() with the real process streams, so the
spawned-script path is unchanged.
This also makes the 'import util' dual-mode: lit.util when diff is
imported as part of the lit package, falling back to flat util for the
spawned script.
[AMDGPU] Fix regclass for a true16 pattern. NFCI. (#206513)
Add an EXTRACT_SUBREG to make it clear that the result of the pattern is
only the low 16 bits of the result of the V_BFI_B32. This does not seem
to affect codegen, presumably because we are lax about allowing COPY
between VGPR_16 and VGPR_32.
[libc] Implement CPU_{AND,OR,XOR,EQUAL}(_S)? macros (#205412)
This patch implements CPU_AND, CPU_OR, CPU_XOR, and CPU_EQUAL macros
(along with their _S variants) from sched.h.
The implementation follows existing patterns by adding internal entry
points (__sched_andcpuset, __sched_orcpuset, __sched_xorcpuset, and
__sched_cpuequal) that perform bitwise operations on cpu_set_t. For
__sched_cpuequal, I use inline_memcmp instead of a manual loop.
Assisted by Gemini.
[mlir] Fix StridedMemRefRankOf to check isStrided() (#201415)
StridedMemRefRankOf was equivalent to MemRefRankOf: it only applied
HasAnyRankOfPred and never HasStridesPred, so non-strided memref layouts
(e.g. multi-result affine maps) incorrectly passed ODS verification on
ops using this constraint (e.g. sparse_tensor.push_back).
The inBuffer of push_back uses StridedMemRefRankOf, which requires a
strided memref layout (HasStridesPred). A non-strided layout must be
rejected.
[LoopIdiom] Form memset on runtime-trip multi-store loops. (#206354)
For runtime trip counts, mayLoopAccessLocation cannot bound the size of
the access, which prevents forming memsets for loops with multiple
stores of the same value.
If all may-aliasing stores write the same value, we can still form
potentially overlapping memsets, as the order of the memsets or writing
the same location multiple times should not matter.
On a large C/C++ based corpus (32k modules), we form ~2% more memsets.
```
base patch
memsets formed 90,063 91,853 +1.99%
```
PR: https://github.com/llvm/llvm-project/pull/206354
[mlir][bufferization] Add static memory planner pass for compile-time buffer allocation (#205125)
This PR introduces a new bufferization-related pass that performs static memory
planning at compile time. The pass is part of my GSoC 2026 project on
improving MLIR's buffer allocation strategies:
https://summerofcode.withgoogle.com/programs/2026/projects/XsjxBQ9o
### What this does
The static memory planner analyzes buffer lifetimes within a function
and consolidates multiple small `memref.alloc`/`memref.dealloc` pairs
into a single arena allocation. Instead of making separate heap
allocations for each memref, we compute offsets ahead of time and carve
out slices from one large buffer using `memref.view`.
This is useful for embedded systems and other memory-constrained
environments where you want predictable memory usage without runtime
allocation overhead.
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