[InstSimplify] Add support for llvm.structured.gep (#182874)
Similar to GEP, the SGEP instruction with no indices can be simplified
by directly using the base pointer.
[WebAssembly] optimize ext + shuffle + add into addext (#182849)
cc https://github.com/llvm/llvm-project/issues/179143
This adds a second pattern: we already recognize "shuffle + extend +
add" as `addext`, this adds another pattern for "extend + shuffle +
add", which can come up when programs are optimized.
[SPIRV][AMD] Reenable `SPV_KHR_float_control2` for AMD flavored SPIRV (#182873)
`SPV_KHR_float_controls2` is enabled in the translator after
https://github.com/khronosgroup/spirv-llvm-translator/pull/3475.
This extension was disabled since we were not able to translate it back.
This patch reverts #169659.
Unify expandPow2Division/expandPow2Remainder into expandPow2DivRem.
Merge the two functions into one to share the common signed-path logic (freeze, bias, ashr) and reduce code duplication, as suggested.
[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts.
Previously, power-of-2 div/rem operations wider than
MaxLegalDivRemBitWidth were excluded from IR expansion and left for
backend peephole optimizations. Some backends can fail to process such
instructions in case we switch off DAGCombiner.
Now ExpandIRInsts expands them into shift/mask sequences:
- udiv X, 2^C -> lshr X, C
- urem X, 2^C -> and X, (2^C - 1)
- sdiv X, 2^C -> bias adjustment + ashr X, C
- srem X, 2^C -> X - (((X + Bias) >> C) << C)
Special cases handled:
- Division/remainder by 1 or -1 (identity, negation, or zero)
- Exact division (sdiv exact skips bias, produces ashr exact)
- Negative power-of-2 divisors (result is negated)
- INT_MIN divisor (correct via countr_zero on bit pattern)
Addressed review comments:
- Added proofs for power-of-2 div/rem expansion in ExpandIRInsts at
https://alive2.llvm.org/ce/z/Y-iWm-
- Tests updated as requested.
Also added CreateFreeze() where needed.
[NFC] Add comments for PR “[LLVM][CLANG] Update signal‑handling behavior to comply with POSIX” (#183206)
This PR adds comments to address post‑commit review feedback on commit
15488a7f78ce7b9ae3c06b031134e5cb339b335c.
[analyzer][tests][z3] Fixing the test case bug for testing converting boolean expression to integer (#183034)
* Fixing incorrect "REQUIRES" condition for Z3 introduced by #108900
* Fixing the test failure introduced by #168034
* Adding more comments about the fixes in #168034 for the tests
introduced in #158276
[SelectionDAG] Fix fptoui.sat expansion using minnum/maxnum (#180178)
fptoui.sat can currently use a minnum/maxnum based expansion, which
relies on NaNs not being propagated. Specifically, it relies on
minnum(maxnum(NaN, 0), MAX) to return 0. However, if the input is sNaN,
then maxnum(sNaN, 0) is allowed to return qNaN, in which case the final
result will be MAX rather than 0.
This PR does the following changes:
* Support the fold for minimumnum/maximumnum, which guarantees that NaN
is not propagated even for sNaN, so it can use the old lowering. Test
this using Hexagon which has legal minimumnum but illegal minnum.
* For the minnum/maxnum case, remove the special unsigned case and
instead always insert the explicit NaN check. In that case the NaN
propagation semantics don't matter.
* This also means that we can support this expansion for
minimum/maximum.
[SPIRV] Add support for emitting DebugFunction debug info instructions
This commit adds support for emitting SPIRV DebugFunction and
DebugFunctionDefinition instructions for function definitions.
[orc-rt] Rename ResourceManager detach/shutdown. NFCI. (#183285)
These methods are called by the session in the event of a detach or
shutdown. The new names reflect their roles as event handlers.
[OpenMP] Only generate call to __kmpc_global_thread_num when needed (#182669)
This patch is a small optimization to only generate a call to
__kmpc_global_thread_num if the result is actually used.
[CGOpenCLRuntime] Remove dead code (#183093)
This drops one getPointerType() overload which accepted a name, which is
no longer used since the opaque pointers migration. The fallback code
path always returns a plain pointer now.
Also drop all the virtual qualifiers. Nothing inherits from this class.
Any customization is implemented via TargetCodeGenInfo hooks in the
implementation.
[llvm][release] Note that some packages have 2 signature files (#183266)
For example in the latest release, there is:
LLVM-22.1.0-Linux-ARM64.tar.xz
Which has 2 signature files:
LLVM-22.1.0-Linux-ARM64.tar.xz.jsonl
LLVM-22.1.0-Linux-ARM64.tar.xz.sig
jsonl comes from the GitHub build and the sig is uploaded by the release
manager.
[ORC] WaitingOnGraph perf: faster dependence propagation. (#183272)
This commit replaces the core dependence propagation algorithm in
WaitingOnGraph to avoid worst-case behavior in the common case where
dependence graphs are sparse. This algorithm showed up as the underlying
cause of the bug in https://github.com/llvm/llvm-project/issues/179611.
For each call to MaterializationResponsibility::notifyEmitted,
WaitingOnGraph would build the transitive closure of all SuperNodes
whose "waiting on" relationships were affected by the newly emitted
symbols, then propagate any remaining unemitted dependencies through
this transitive closure graph. This approach is simple, but pushes the
algorithm towards n^2 complexity even for sparse dependence graphs.
The new propagation algorithm:
1. Inverts the edge direction in the SymbolDependenceMap data structure:
SymbolDepMap[SN] now contains the set of SuperNodes that depend on SN,
rather than the set that SN depends upon.
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[SPIRV] Add support for emitting DebugFunction debug info instructions
This commit adds support for emitting SPIRV DebugFunction and
DebugFunctionDefinition instructions for function definitions.
[NFC][CodeGen] Add Register guard to ARMMaterializeFP. (#182559)
This does not directly fix any issue because the implementation
indirectly ensures the correct behaviour. However, all the other
"<Tgt>Materialize" functions (Int and FP across all targets, including
ARMMaterializeInt) have explicit Register guards so for peace of mind I
figured it's worth added them.
[LoopInterchange] Fix test phi-ordering.ll (NFC) (#181989)
I found that the test phi-ordering.ll is a bit fragile and can fail with
any irrelevant changes. Also this test is not consistent with the
following comment, which is at the top of the file:
```
;; Checks the order of the inner phi nodes does not cause havoc.
;; The inner loop has a reduction into c. The IV is not the first phi.
```
After examining the change history, I found that the original intent of
this test was effectively lost in
https://github.com/llvm/llvm-project/commit/c8bd6ea35e459169cbd401372e81168ed8482536.
A workaround was introduced later in
https://github.com/llvm/llvm-project/commit/eac34875109898ac01985f4afa937eec30c1c387
to preserve the test output, but this seems to have made the test more
complicated.
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