[RISCV] Use decodeVMaskReg for VMaskCarryInOp. NFC (#177742)
After #177678 we don't need DecodeVMV0RegisterClass to reject vm=1
cases. All instructions that use VMaskCarryInOp have set vm=0 in their
tablegen classes.
[AArch64][SME] Use LibcallLoweringInfo in the MachineSMEABIPass (#177762)
This adds a new helper to add calls to SME routines (addSMELibCall) and
check they are using the expected CC.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
[clang-tidy] Add llvm-use-vector-utils (#177722)
This new check suggests the following replacements:
* `llvm::to_vector(llvm::map_range(X, Fn))` -> `llvm::map_to_vector(X,
Fn)`
* `llvm::to_vector(llvm::make_filter_range(X, Fn))` ->
`llvm::filter_to_vector(X, Fn)`
and add the `SmallVectorExtras.h` include when necessary.
The check is called `vector-utils` because we may want to handle more
cases in the future, like turning explicit calls to SmallVector
constructor to `llvm::to_vector` (which lives in `SmallVector.h`, not
`SmallVectorExtras.h`).
Assisted-by: claude
SystemZ: Use correctly offset MachinePointerInfo in CC lowering (#177793)
Previously this was just using the original base address as
the pointer info.
[lldb] improve Doxygen rendering of an existing comment (#177785)
This commit improves the way how the example code attached to
`SBDebugger::GetSetting` method is rendered by Doxygen.
Co-authored-by: Matej Košík <matej.kosik at codasip.com>
[VPlan] Share and re-use logic to find FindIVResult (NFC).
Move logic to look for FindIVResult pattern out of LoopVectorize to
allow for re-use in current code and follow-up patches.
[MLIR][XeGPU] Preserve Leading dimension when blocking rank-sensitive operations (#177489)
This PR preserves leading dimensions for
xegpu.load_matrix/store_matrix/atomic_rmw/convert_layout, and vector
operations which have impact on shapes:
broadcast/multi-reduction/shape_cast/transpose.
Rank-sensitive operations are operations whose semantics depend on the
tensor rank (and consequently its shape), and therefore must not alter
the input tile rank or shape, such as by dropping leading dimensions.
[RISCV] Remove decodeRTZArg. NFC (#177744)
We can set the frm field in tablegen class which makes the disassembler
only accept that fixed value without needing to reject it with
decodeRTZArg.
DAG: Replace legal type check in EmitCopyFromReg
It doesn't make sense that an illegal type would get here; a
CopyFromReg cannot be illegally typed. The only exception that
was hit here is in a handful of SystemZ inline assembly tests
for i128, which use untyped. They shouldn't; it should treat
v2i64 as legal instead. Just leave the untyped check for now.
[IR2Vec] Changes to support programmatic creation of Vocabulary (#177348)
These changes would help create `ir2vec::Vocabulary` in Python bindings
(or any other *tool*) without having to run `IR2VecVocabAnalysis` which
reads the Vocab path via command line.
[Polly] Update isl to isl-0.27 (#177776)
Fixes: #177527
Updated test cases:
* CodeGen/OpenMP/matmul-parallel.ll, ScheduleOptimizer/pattern-matching-based-opts.ll
Before the update, ISL bailed out the dependency computation due to
hitting the max operation limit. The commit
https://repo.or.cz/isl.git/commit/4bdfe2567715c5d1a8287c07d8685eb3db281e32
seems to have reduced the complexity needed of the dependency
computation, thus now being able to recognize some loops as parallel.
The tests were checking that the outer loop is not parallel, but some
inner loops can be parallized, particularly the array packing loops.
* DeLICM/reduction_looprotate_hoisted.ll
changes in how isl generates expressions
* ScheduleOptimizer/pattern-matching-based-opts_5.ll
changes in how isl generates expressions, and AST node changes
bar syntax and only print input if different from output.
Breaks update_test_checks Function Attrs comment check in the rare
case where the modes mismatch.