LLVM/project 8e23b6dllvm/lib/Target/AMDGPU GCNCreateVOPD.cpp GCNVOPDUtils.cpp

[NFC][AMDGPU] Fix clang-tidy warnings in VOPD related files (#223261)
DeltaFile
+7-7llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+5-3llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
+12-102 files

LLVM/project cba24d6llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Generalize folding IV increment into phi start value (NFC). (#223260)

simplifyRecipe folds

  X    = phi(0, IVInc)
  IVInc = X + Step
  Def   = IVInc + Y

into a phi starting at Y, but only if Y is a live-in. Also allow values
defined in the block the phi's start value is coming from, which is
where the value conservatively has to be available.

NFC today, but preparation for modeling the full epilogue skeleton in
VPlan.
DeltaFile
+20-13llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+20-131 files

LLVM/project d44791dllvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.sched.barrier.ll

[AMDGPU] IGLP: Sanitize user schedule hints (#221256)

Fixes the following ICE:
```cpp
extern __shared__ int lds[];

__global__
void kern_ice() {
    auto _ = lds[threadIdx.x];
    __builtin_amdgcn_sched_barrier(~0x380); // Allow all except DS instructions
}
```

See: https://godbolt.org/z/oGfT1TTa4
DeltaFile
+0-22llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+22-0llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
+6-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+32-225 files

LLVM/project 914e15cllvm/include/llvm/IR DebugInfoMetadata.h Metadata.h, llvm/lib/IR DebugInfoMetadata.cpp Metadata.cpp

[IR] Move the LLVMContext out of ReplaceableMetadataImpl. NFC (#222085)

No ReplaceableMetadataImpl method reads its LLVMContext reference, and
ValueAsMetadata reaches the context through the wrapped Value. Keep the
reference in a derived ReplaceableUsesWithContext, used by the two
owners with no other route to it: MDNode's on-demand RAUW support and
DIArgList.

Rename the base to ReplaceableUses: it is the use map behind RAUW for
the metadata kinds that support it, not a pimpl, and the name matches
ContextAndReplaceableUses and getReplaceableUses().

Make the base destructor protected, since getOrCreate() hands out
ReplaceableUses pointers that must never be deleted. Delete copy
assignment explicitly; the LLVMContext reference suppresses it
implicitly.

sizeof(ValueAsMetadata) 152 -> 144.
Aided by Opus 5
DeltaFile
+42-32llvm/include/llvm/IR/Metadata.h
+15-16llvm/lib/IR/Metadata.cpp
+4-4llvm/include/llvm/IR/DebugInfoMetadata.h
+4-3llvm/unittests/IR/MetadataTest.cpp
+1-1llvm/lib/Transforms/IPO/GlobalOpt.cpp
+1-1llvm/lib/IR/DebugInfoMetadata.cpp
+67-571 files not shown
+68-587 files

LLVM/project b7877e0llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination induction-relational-predicate-latch.ll

[ConstraintElim] Derive an unsigned IV bound from a signed relational latch. (#222762)

For a known non-negative backedge (either via isKnownNonNegative or
because the increment is increasing), 0 <=s PN <= B holds and implies
that B is non-negative as well.

Use that to translate a signed condition to the equivalent unsigned one.

Note that the general signed->unsigned rewrite cannot catch this,
because the precondition also needs rewriting to unsigned.

No llvm-opt-benchmark-nightly impact, but it can help remove runtime
checks generated by sanitizers or Swift code. An end-to-end C example is
https://clang.godbolt.org/z/vbd91MjaM.

Alive2 Proof:  https://alive2.llvm.org/ce/z/G3Mv7t

PR: https://github.com/llvm/llvm-project/pull/222762
DeltaFile
+243-0llvm/test/Transforms/ConstraintElimination/induction-relational-predicate-latch.ll
+15-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+258-02 files

LLVM/project 4098f56mlir/lib/Dialect/Vector/IR VectorOps.cpp, mlir/test/Dialect/Vector canonicalize.mlir

[mlir][vector] Don't fold in_bounds for negative constant indices (#219681)

`isInBounds` checked only that the transfer *ends* inside the source:

    return cstOp.value() + vectorSize <= sourceSize;

The `in_bounds` attribute promises more than that. Its definition in
VectorOps.td says accesses "(including the starting point)" may run
out-of-bounds when it is "false", so setting it to "true" is a claim
about the start of the transfer as well as its end.

With a negative constant index the two disagree. For

    vector.transfer_read %m[-1] : memref<8xf32>, vector<4xf32>

`-1 + 4 <= 8` holds, so the fold set `in_bounds = [true]`, even though
element -1 is read from outside `%m`.

The same expression also overflows for a large enough index: at `index =

    [13 lines not shown]
DeltaFile
+39-0mlir/test/Dialect/Vector/canonicalize.mlir
+9-1mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+48-12 files

LLVM/project 053b3dbllvm/lib/Target/AMDGPU GCNCreateVOPD.cpp GCNVOPDUtils.cpp

[NFC][AMDGPU] Fix clang-tidy warnings in VOPD related files
DeltaFile
+7-7llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+5-3llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
+12-102 files

LLVM/project 85f694bllvm/lib/Transforms/Instrumentation AddressSanitizer.cpp, llvm/test/Instrumentation/AddressSanitizer asan-detect-invalid-pointer-pair.ll

[ASan] Convert pointer-pair operands based on type (#218494)

`CreatePointerCast` was being called on everything without checking what
it actually is, so if the operand came from ptrtoint ... to i32 it just
crashes (its not a pointer).

now it check the type first - pointers get pointer-cast, ints get
zext/trunc'd to intptr width.

Fixes #217544

also edited regression tests for this
DeltaFile
+27-0llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
+13-1llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+40-12 files

LLVM/project 8864a4bllvm/lib/Target/Mips MipsInstrInfo.td MipsISelLowering.cpp, llvm/test/CodeGen/Mips/llvm-ir udiv.ll srem.ll

[Mips] Handle division by zero trap on MIPS1 (#201133)

LLVM currently emits the `teq` instruction for every arch version, but
`teq` is unsupported on MIPS1.
This special cases MIPS1 so that `bne(z)` and `break` are emitted
instead.
Compared to https://github.com/llvm/llvm-project/pull/81311, this should
also handle liveness as far as I can tell.

I didn't want to add another bool to the argument list so I combined
`IsMicroMips` and what was supposed to be `IsMips1` into an enum, which
feels much nicer in this case.
Besides that and the main change, I also changed the `hasSideEffects`
bit for `PseudoSDIV` and `PseudoUDIV`,
which allows the delay slot to be usefully filled - well, at least with
`-O1`+. This seems to be in line with what GCC does:
https://godbolt.org/z/zqcG5ha35

Tested using clang directly and through Zig's LLVM backend.

    [2 lines not shown]
DeltaFile
+92-0llvm/test/CodeGen/Mips/llvm-ir/urem.ll
+88-0llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
+86-0llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
+86-0llvm/test/CodeGen/Mips/llvm-ir/srem.ll
+65-10llvm/lib/Target/Mips/MipsISelLowering.cpp
+2-2llvm/lib/Target/Mips/MipsInstrInfo.td
+419-126 files

LLVM/project d91624cllvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU mai-hazards-gfx942.mir

[AMDGPU] Fix MAI hazard scan missing 19-instruction-old hazards (#222040)

The scan only looked back 19 instructions, but gfx950 can need a gap of
20 after some MFMAs

A hazard exactly 19 instructions back was missed, so no wait was
inserted
DeltaFile
+45-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
+14-3llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+59-32 files

LLVM/project 3776151llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Fix formatting

Created using spr 1.3.7
DeltaFile
+10-0llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
+4-3llvm/lib/CodeGen/MIRParser/MIParser.cpp
+2-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+16-53 files

LLVM/project ce73dbaclang/lib/CodeGen/Targets SPIR.cpp, clang/test/CodeGenHIP amdgcnspirv-uses-amdgpu-abi.cpp

[clang][SPIR-V][AMDGPU] Fix variadic aggregate ABI classification for AMDGCN (#216326)

Mirror AMDGPUABIInfo fixed/variadic split

AMDGCNSPIRVABIInfo::classifyArgumentType did not distinguish fixed from
variadic arguments, so aggregates passed through `...` were
misclassified as indirect byref instead of direct
DeltaFile
+115-0clang/test/CodeGenHIP/amdgcnspirv-uses-amdgpu-abi.cpp
+18-6clang/lib/CodeGen/Targets/SPIR.cpp
+133-62 files

LLVM/project 80968f0llvm/test/CodeGen/AArch64 overflow-vec.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.832bit.ll amdgcn.bitcast.896bit.ll

Rebase

Created using spr 1.3.7
DeltaFile
+57,327-55,762llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,634-6,608llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,576-5,657llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+4,486-4,550llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+6,589-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+2,884-2,534llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+83,496-75,1114,286 files not shown
+274,206-169,4704,292 files

LLVM/project d36b94allvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/AArch64 parse-low-level-type-invalid11.mir

[MIRParser] Reject a one-element fixed-length vector type (#213290)

MIParser accepts `<1 x sN>` and then asserts while building the LLT, so
llc aborts during parsing instead of reporting a parse error:

```
Assertion `!EC.isScalar() && "invalid number of vector elements"' failed.
```

LLT has no one-element fixed-length vector. `getLLTForType`,
`getLLTForMVT` and
`LLT::changeElementCount` all map a one-element `ElementCount` to the
element
type through `LLT::scalarOrVector`, nothing calls `LLT::fixed_vector(1,
...)`,
and no in-tree .mir test uses the syntax. `verifyVectorElementCount`
already rejects 0 and anything above 2^16, so 1 was the remaining hole; it now
gets the same diagnostic instead of aborting the parser.


    [3 lines not shown]
DeltaFile
+10-0llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
+4-3llvm/lib/CodeGen/MIRParser/MIParser.cpp
+14-32 files

LLVM/project 48cc2ballvm/test/CodeGen/AArch64 overflow-vec.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.832bit.ll amdgcn.bitcast.896bit.ll

Rebase

Created using spr 1.3.7
DeltaFile
+57,327-55,762llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,634-6,608llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,576-5,657llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+4,486-4,550llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+6,589-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+2,884-2,534llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+83,496-75,1114,288 files not shown
+274,226-169,4814,294 files

LLVM/project 1d8a75fllvm/test/CodeGen/AArch64 overflow-vec.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.832bit.ll amdgcn.bitcast.896bit.ll

Rebase

Created using spr 1.3.7
DeltaFile
+57,327-55,762llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,634-6,608llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,576-5,657llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+4,486-4,550llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+6,589-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+2,884-2,534llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+83,496-75,1114,290 files not shown
+274,286-169,4994,296 files

LLVM/project 979b374llvm/lib/Transforms/AggressiveInstCombine TruncInstCombine.cpp AggressiveInstCombineInternal.h

[AggressiveInstCombine] Fix terminology in a few comments (NFC) (#222327)

Fix the comments (and a debug print) that say "dominated by trunc"
rather than "post-dominated".

Also fixes a Doxygen syntax (use \p instead of /p) and fix
capitalization in the middle of a sentence.
DeltaFile
+5-5llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h
+1-1llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
+6-62 files

LLVM/project c95a2f6llvm/test/CodeGen/AArch64 overflow-vec.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.832bit.ll amdgcn.bitcast.896bit.ll

Rebase

Created using spr 1.3.7
DeltaFile
+57,327-55,762llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,634-6,608llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,576-5,657llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+4,486-4,550llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+6,589-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+2,884-2,534llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+83,496-75,1114,317 files not shown
+275,190-169,6284,323 files

LLVM/project cff226allvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination sadd-with-overflow.ll

[ConstraintElim] Fold sadd.with.overflow with a constant op. (#223239)

Generalize the overflow-math simplification to also allow simplifying
sadd.with.overflow if the second operand is constant, using
makeGuaranteedNoWrapRegion.

Note that this partially overlaps with the flag strengthening logic.
I'll share a patch soon to try to unify the code more.

No improvements in llvm-opt-benchmarks-nightly. It improves end-to-end
optimizations for Swift (which emits a lot of checked arithmetic) and
also Clang + UBsan.

An end-to-end improvement with overflow intrinsics is
https://llvm.godbolt.org/z/6nrj7aodd.

PR: https://github.com/llvm/llvm-project/pull/223239
DeltaFile
+223-8llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+32-11llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+255-192 files

LLVM/project 0eac970llvm/lib/CodeGen RegisterCoalescer.cpp, llvm/test/CodeGen/AArch64 coalescer-empty-subrange-early-lis.ll

RegisterCoalescer: Remove empty subranges after merging subranges (#222050)

Merging subranges in joinVirtRegs didn't try to clear empty ranges after
refineSubRanges, manifesting in an assert in overlaps checks later.

Exposed with subregister liveness once LiveIntervals runs before
TwoAddress.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+30-0llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
+4-0llvm/lib/CodeGen/RegisterCoalescer.cpp
+34-02 files

LLVM/project 6fdabf6llvm/test/CodeGen/NVPTX cmpxchg.ll, llvm/test/CodeGen/RISCV condops.ll

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+0-1,202llvm/test/CodeGen/RISCV/condops.ll
+541-522llvm/test/CodeGen/NVPTX/cmpxchg.ll
+0-906llvm/tools/llc/llcdriver.cpp
+906-0llvm/tools/llc/lib/llcdriver.cpp
+589-0llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
+361-205llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
+2,397-2,835518 files not shown
+19,566-9,229524 files

LLVM/project c1f1a28clang/include/clang/Basic AArch64CodeGenUtils.h, clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp

[CIR][AArch64] Complete upstream vector saturating shift left NEON builtins (#221507)

Related to https://github.com/llvm/llvm-project/issues/185382

CIR lowering for the vector saturating shift left intrinsics

(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-left).
This completes the family.

Port tests from `clang/test/CodeGen/AArch64/neon-intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`.
DeltaFile
+793-3clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-704clang/test/CodeGen/AArch64/neon-intrinsics.c
+44-7clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+16-10clang/include/clang/Basic/AArch64CodeGenUtils.h
+853-7244 files

LLVM/project f4ecba3llvm/lib/Analysis ValueTracking.cpp, llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

[KnownFPClass] Unify and refine interested classes for `KnownFPClass::log` (#219751)

Previously, `ValueTracking` and `GISelValueTracking` only called
`KnownFPClass::log` when the requested classes included NaN or infinity.
As a result, narrowly interested queries could miss unconditional
deductions, for example, `log(x)` is never subnormal or negative zero
(With the exception of `PPCDoubleDouble`
https://github.com/llvm/llvm-project/issues/217658).

This change makes the interested-class handling consistent between
`ValueTracking` and `GISelValueTracking`. The source is queried only
when its classes are needed, but `KnownFPClass::log` is always called so
its unconditional deductions are preserved.

Future work:
- Fixing `KnownFPClass::log` for `PPCDoubleDouble`.

AI disclosure:
I used OpenAI Codex (sol 5.6) to help write the unit tests, which I
reviewed and ran locally.
DeltaFile
+28-19llvm/lib/Analysis/ValueTracking.cpp
+21-10llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+24-0llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
+12-0llvm/unittests/Analysis/ValueTrackingTest.cpp
+85-294 files

LLVM/project 588304bllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 and-neg-pow2-copyable.ll

[SLP]Model copyable lanes of idempotent binops as op(V, V) when the operand column has a constant lane

The op(V, identity) form lets the reorder move the lane out of the
joined column, breaking the opcode-peer node; the symmetric form is
reorder-proof.

Reviewers: RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/220252
DeltaFile
+94-28llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+12-21llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
+106-492 files

LLVM/project 860fb77llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/lib/Transforms/Vectorize/SLPVectorizer SLPCostAnalysis.h SLPReductionUtils.h

[SLP]Reduce logical and/or reductions in the wide leaf type

Logical and/or reductions on i1 with booleanized wide leaves (truncs
of same-op chains, zero-tests of values from [0, 1]) are performed in
the wide type, exposing the underlying consecutive values to the tree;
bit 0 of the result is the final value. Fixes the fragmented reduction
and the gather-of-scalars regression for compile-time-expanded Boolean
reductions.

Fixes #221167

Reviewers: RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/221321
DeltaFile
+18-127llvm/test/Transforms/SLPVectorizer/X86/logical-reduction-booleanized-leaves.ll
+122-4llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+65-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
+59-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
+23-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
+21-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
+308-1316 files

LLVM/project 859cf4fllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 logical-binops-booleanized-leaves.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+161-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+24-22llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
+185-242 files

LLVM/project 240670dllvm/include/llvm/Transforms/Utils SplitModuleCommon.h, llvm/lib/Target/AMDGPU AMDGPUSplitModule.cpp

[NFC][ModuleUtils] Move externalize() from module splitting utilities (#221181)

`SplitModule.cpp` and `AMDGPUSplitModule.cpp` each carry an identical
static `externalize()` helper that promotes local-linkage globals to
external + hidden visibility and assigns a stable name to unnamed
entities, so they are named consistently across module partitions.

This patch removes the duplication by moving the helper into
`ModuleUtils` as `llvm::externalize`, and updates both users to call the
shared implementation. No functional changes are intended.

This also prepares for upcoming module splitting utilities to reuse a
single, canonical implementation.

Development of this patch was assisted by AI and reviewed by me.
DeltaFile
+33-0llvm/include/llvm/Transforms/Utils/SplitModuleCommon.h
+33-0llvm/lib/Transforms/Utils/SplitModuleCommon.cpp
+6-18llvm/lib/Transforms/Utils/SplitModule.cpp
+4-16llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+9-9llvm/test/tools/llvm-split/unnamed.ll
+1-0llvm/lib/Transforms/Utils/CMakeLists.txt
+86-436 files

LLVM/project 483af6cflang/include/flang/Lower/OpenMP Clauses.h, flang/lib/Lower/OpenMP Clauses.cpp

[OpenMP] Add definitions for REDUCTION_KIND and SHIFT clauses (#222745)

This is a barebones change to introduce the enum identifiers for these
clauses.
DeltaFile
+15-2llvm/include/llvm/Frontend/OpenMP/ClauseT.h
+4-0llvm/include/llvm/Frontend/OpenMP/OMP.td
+2-0flang/lib/Lower/OpenMP/Clauses.cpp
+2-0flang/include/flang/Lower/OpenMP/Clauses.h
+23-24 files

LLVM/project c67808cllvm/include/llvm/Frontend/Directive DirectiveBase.td, llvm/include/llvm/Frontend/OpenMP OMP.td

[OpenMP] Change association of some directives from "none" to "explicit" (#222703)

Certain declarative directives are associated with base language
declarations by having the declared entities explicitly listed as
arguments.

Previously these had "none" in OMP.td. Change them to "explicit" to be
consistent with the spec. The existing code does not require any
changes, since the only potentially affected code would be that which
checked the assocation for "none", and the only such cases were applied
to executable directives.
DeltaFile
+4-4llvm/include/llvm/Frontend/OpenMP/OMP.td
+2-1llvm/test/TableGen/directive2.td
+2-1llvm/test/TableGen/directive1.td
+2-0llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
+1-0llvm/include/llvm/Frontend/Directive/DirectiveBase.td
+11-65 files

LLVM/project 23f2e44llvm/lib/CodeGen/SelectionDAG LegalizeTypes.h LegalizeTypes.cpp

[SelectionDAG] Remove unused float promotion in DAGTypeLegalizer (NFC) (#223219)

This patch removes PromotedFloats along with GetPromotedFloat and
SetPromotedFloat.  The Mapped bitmask in PerformExpensiveChecks is
adjusted accordingly, shifting the bit for SoftPromotedHalfs.

The last uses of DAGTypeLegalizer::GetPromotedFloat and
DAGTypeLegalizer::SetPromotedFloat were removed on January 26, 2026 in
commit a7d48bd305ef3aa4bd543da6f4cd8682a3d35c32 when TypePromoteFloat
and its associated DAG machinery were removed.

With these accessors gone, DAGTypeLegalizer::PromotedFloats is no longer
populated.

Assisted-by: Antigravity
DeltaFile
+0-17llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+1-16llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+1-332 files