[AArch64] Add a Cortex-A53 multiply-accumulate forwarding test (NFC) (#237522)
Add an llvm-mca test for the Cortex-A53 scheduling model, ahead of the
changes
that follow. Cortex/A53-mac-forwarding.s runs dependent
multiply-accumulate
chains through the accumulator and through a multiplicand. This shows
the
accumulator forwarding, which the instruction tables in
Cortex/A53-neon-instructions.s and Cortex/A53-basic-instructions.s
cannot.
The checks reflect the current model, so the forwarding changes that
follow
show up as a diff to this test.
Part 1 of 4 of the split of #219478, to be merged in order.
AI tool use: prepared with the help of Claude (Anthropic), see the
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[libc] Fix maybe unused warnings in Arm 32-bit no-FP baremetal builds (#237257)
In configurations without floating-point, some variables end up not
used, hence warnings are shown because of this.
This patch adds `[[maybe_unused]]` to the definitions affected by this.
The ultimate goal is to re-enable `-Werror` in no-FP builds.
[mlir][tblgen] Finish checked formatting migration through PDLL
Register parsed TableGen source buffers before processing imported
records. Format the predicate before wrapping it in the generated
success return, and propagate failure without appending an invalid
declaration.
Adapt shared formatting messages to PDLL diagnostics. Anchor the primary
at the import in the main document so LSP publishes it, and retain the
constraint definition, multiclass instantiations, and nested PDLL import
locations as notes. Formatting errors return through the parser and
leave the language server alive for subsequent edits.
Deprecate pointer-taking factories, lazy object types, PHKind shims, and
the unchecked summary helper while retaining compatibility behavior.
Migrate successful format tests and suppress warnings locally around
intentional legacy tests. Complete migration and diagnostic
documentation.
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[CostModel][X86] Add AVX512BW cost for in-lane v64i8 2 src shuffles (#236618)
Without VBMI, two-source v64i8 shuffles always got the cross-lane cost
of 19,
even when the mask stays inside 128-bit lanes (e.g.
vpunpcklbw/vpunpckhbw).
Add an in-lane entry for AVX512BW that matches the AVX2 v32i8 one
(2*vpshufb + vpor) and check it before the cross-lane table.
This lets the Stockfish NNUE loop from #236617 get fully unrolled on
AVX512BW. The new LoopUnroll test covers the unroll decision, and the
first
commit adds the tests with the current costs.
Fixes #236617
[mlir][tblgen] Check substitutions throughout code generation
Migrate generator and shared-verifier emission to eager fatal formatting
with template-definition origins and operation use notes. Synthesized
properties without a record fall back to the operation location.
Speculative attribute and property uniquing now consumes checked errors
and falls back to inline verification. Keep value-specific bindings
local to their verifier.
Add checked summary-expression formatting that retains the escaped
segment and propagates its owned error to the source diagnostic
boundary. Expose reference-taking tgfmt and tgfmtv overloads returning
Expected, retain transition aliases, and document migration and parsing
corrections.
Escape literal dollars in a test builder comment, and keep the nested
matcher error test focused on its intended invalid DAG. Add regression
coverage for shared and inline constraints, summaries, attribute
templates, interface templates, and the reference-taking API.
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[docs] Fence more LangRef IR examples as `llvm`
Change the instruction examples that use a `<result>` placeholder, and
a few other IR examples, from `text` to `llvm`. The new lexer handles
the placeholder, which renders as plain text.
Also drop `llvm/utils/pygments/README.md` and the `pygmentize` fallback
in the lexer. The docs only load it through Sphinx.
[mlir][tblgen] Diagnose substitution failures at their source
Render owned formatting errors as source-aware messages, preserving
inner definition origins, use sites, and multiclass location arrays.
Consume every error payload before printing and terminating so joined
errors and their notes are not lost.
Add eager fatal wrappers for generator boundaries and use them for trait
predicates. Missing substitutions now fail in TableGen with the
template, failed occurrences, and available bindings instead of
generating bad C++. Snapshot the trait context before value verifiers
add temporary bindings, so an inline attribute check cannot accidentally
bind $_self for a trait.
Share message construction between generic logging and source
diagnostics. Use portable death-test expressions and handle invalid
success payloads defensively at the fatal-reporting boundary.
Validation: 74 TableGen unit tests and all 69 mlir-tblgen lit tests
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[mlir][tblgen] Add checked formatting with owned substitution errors
Add tgfmtChecked and tgfmtvChecked, validating all placeholders before
rendering and returning owned FmtError payloads on failure. Retain
failed occurrences, available substitutions, and provenance for
diagnostic users.
Unify builtin and custom binding storage: addSubst("_self", ...) now
aliases withSelf(), including consistent last-registration-wins
behavior. Parse positional indices as decimal, so $010 means 10 instead
of 8 and $08 means 8 instead of reaching an unreachable path.
Unrepresentable indices become checked errors or legacy markers instead
of assertions.
Keep the legacy API lazy, including observing later context mutations.
The compatibility PHKind entry points remain until caller migration.
Validation: 66 TableGen unit tests; unchecked Expected arguments
rejected by the compiler. Include snapshot logging and typed error
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[docs] Register an LLVM IR lexer for Sphinx docs
The Pygments LLVM IR lexer has a fixed keyword list that lags behind the
IR. It doesn't know `ptrtoaddr`, `bitextract`, `samesign`, `captures`,
byte types and others. When it meets one, it emits error tokens and
Sphinx renders the whole block as plain text.
Add `llvm/utils/pygments/llvm_lexer.py`, which extends the stock lexer
with the keywords from `LLLexer.cpp` and the attribute names from
`Attributes.td`, read when the lexer is loaded. It also handles byte
types, comdat names, summary entries, debug records, DI constants, `|`,
sign-prefixed hex integers, hex FP literals and numbered calling
conventions. Any other word is lexed as a name, so a placeholder in an
example doesn't drop highlighting for the whole block.
Register it for every project in `common_conf()`, like the MLIR lexer.
Also change the LangRef examples that are IR but were fenced as `text`
to `llvm`, and fix two typos in them.
[CodeGen] Ignore debug instructions in the VLIW block-size heuristic (#224497)
The converging VLIW scheduler derived `CriticalPathLength` from the raw
size of
the `MachineBasicBlock`. This counted debug instructions. On Hexagon,
one
`DBG_VALUE` could cross an issue-width boundary, change candidate costs,
and
produce a different ordinary schedule.
Count the block's non-debug instructions with
`instructionsWithoutDebug`, while
passing `SkipPseudoOp=false` to preserve the existing pseudo-probe and
block-wide semantics. Add a reduced Hexagon MIR regression test at the
integer
threshold.
Fixes #224483
AI disclosure: This patch was developed with OpenAI Codex 5.6 Sol and
co-reviewed by Claude and Yongqiang Tian.
[SLP]Reduce loop accumulators before seeds
Store/PHI seeds of per-stream reductions transposed the loop
accumulators. Try the seed reductions first when each reduces its
own accumulators with uniform updates over consecutive loads in the
same block. Cost the selects, whose conditions are the lanes
extracted from a vectorized compare, with the predicate of this
compare.
Assisted-by: Cursor
Reviewers: bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/234766
Regenerate callbr tests for label-must-be-emitted
Main now prints label-must-be-emitted on INLINEASM_BR indirect targets
(#234850).
Assisted-by: Claude Opus 5.5
[MLIR] Pack vector state with SmallVectorWithFlags
Store PresburgerSpace's identifier state, WalkContinuation's action, and
UseListOrderStorage's encoding flag in the capacity fields of their
vectors. Preserve inline capacities and move-based bytecode buffer
transfers; the temporaries in the bytecode reader that only shuffle the
indices stay plain SmallVectors, moved out of the flagged storage.
On x86-64, this reduces PresburgerSpace from 40 to 32 bytes,
WalkContinuation from 72 to 64, and UseListOrderStorage from 40 to 32.
Test flags across empty and heap-backed copies and moves. Cover inline
and heap-backed index pairs and full-shuffle bytecode encoding.
Assisted-by: Codex
Assisted-by: Claude Code
[ADT] Add SmallVectorWithFlags with packed user flags
Structures that hold a SmallVector followed by a bool or a couple of
flag bits pay up to eight bytes of padding for those bits, and there is
no padding inside the vector to reuse: the header is exactly a pointer
and two 32-bit fields, and the inline storage of pointer-sized elements
is a multiple of eight bytes. SmallVectorWithFlags stores one to four
user flag bits in the high bits of the capacity field, so it has the
same size and inline capacity as SmallVector.
The capacity field is the one header field not read on the hot path:
the buffer pointer's free low bits depend on the element alignment and
are read on every element access, and the size is read by size() and
end(). Only capacity() masks the flags out, which costs one extra `and`
in the growth check of push_back; begin(), end(), and size() are
untouched. The cost is a maximum capacity divided by 2^FlagBits, which
with the 32-bit size type and four flag bits is 268 million elements.
The SmallVector implementation layers take a FlagBits template
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[mlir] Support thread-safe context access without parallel execution (#236551)
Add enableThreadSafeLocking() and isThreadSafeLockingEnabled() so
clients using external threads can unique context-owned entities without
enabling MLIR parallel execution or creating a thread pool. Use the
locking mode for operation-name uniquing as well as the type, attribute,
and affine uniquers. Enabling multithreading also enables locking.
Follow-up to #235294.
Assisted-by: Codex
[AST] Optimize isWeakImported() for decl without attributes (NFC) (#237619)
This method can only return true if there is a WeakImportAttr or
AvailabilityAttr, so we can skip cases that don't have any attributes.
This avoids the call to canBeWeakImported(), which is fairly expensive
due to the use of isThisDeclarationADefinition().
This improves compile-time for C++ code, by -0.25% for the clang build.
Suggested by LLM. Original motivation was to reduce ASLR noise on
beman-execution.
