LLVM/project 2877672libcxx/docs index.rst, libcxx/docs/DesignDocs WindowsSupport.rst

[libc++] Add a design document for Windows support (#202668)

This adds a design document that sets the expectations for libc++
support on Windows.
DeltaFile
+20-0libcxx/docs/DesignDocs/WindowsSupport.rst
+1-0libcxx/docs/index.rst
+21-02 files

LLVM/project ab40e2bclang/lib/CodeGen CGCoroutine.cpp, clang/test/CodeGenCoroutines coro-gro.cpp coro-gro5.cpp

[clang][CodeGen] Never collect return value alloca into coroutine frame (#213580)

The coroutine return value must not reside within the coroutine frame;
otherwise, a heap-use-after-free error will occur, as the frame is
destroyed before the return is completed.

In the front end, emit `coro_outside_frame` metadata for the
return-value alloca so that it does not accidentally enter the frame.

Close #49843
DeltaFile
+35-0clang/test/CodeGenCoroutines/coro-gro5.cpp
+2-2clang/test/CodeGenCoroutines/coro-gro.cpp
+3-0clang/lib/CodeGen/CGCoroutine.cpp
+40-23 files

LLVM/project 5b750bcllvm/test/MC/Disassembler/AMDGPU gfx950_dasm_err.txt gfx9_dasm_err.txt

[NFC][AMDGPU] Reorganize dasm error tests
DeltaFile
+0-135llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+48-0llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_err.txt
+43-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_err.txt
+38-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_err.txt
+10-0llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_err.txt
+10-0llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
+149-1356 files

LLVM/project d2e6940clang/include/clang/CIR/Dialect/IR CIRTypesDetails.h, clang/lib/CIR/CodeGen CIRGenBuilder.h

[CIR] Derive record padding from the member marks

Now that every record member carries a kind, the record-level `padded`
bool is redundant: a record is padded exactly when some member is marked
pad.  Drop the parameter and answer `getPadded()` from the marks.

That also fixes `computeStructDataSize`, which had read the bool as "the
last member is tail padding" and so dropped a real member when padding
sat between two data members.  It now drops the trailing run of pad
members instead.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+136-0clang/test/CIR/Lowering/copy-skip-tail-padding.cir
+44-48clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+47-14clang/unittests/CIR/RecordMemberKindTest.cpp
+11-26clang/lib/CIR/CodeGen/CIRGenBuilder.h
+16-16clang/test/CIR/IR/invalid-array-structor.cir
+13-18clang/include/clang/CIR/Dialect/IR/CIRTypesDetails.h
+267-12254 files not shown
+429-29460 files

LLVM/project fd89b52llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.h AMDGPUDisassembler.cpp, llvm/test/MC/Disassembler/AMDGPU decode-err.txt gfx950_dasm_err.txt

[AMDGPU][MC] Fix crash caused by unsupported non-VGPR widths

Fixes #215001.
DeltaFile
+42-0llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_err.txt
+27-14llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+5-2llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+5-0llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+79-164 files

LLVM/project 58dffdellvm/lib/Target/AMDGPU AMDGPUWaitSGPRHazards.cpp, llvm/test/CodeGen/AMDGPU valu-mask-write-hazard.mir

[AMDGPU] Prevent GFX11 VALU Hazard Wait merging into terminators (#214935)

Fix an issue where a pending wait would be moved into the block
terminators causing a validation error.
Flush all pending waits and exit optimization loop when reaching first
terminator within a block.
DeltaFile
+51-0llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
+10-5llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
+61-52 files

LLVM/project 2b44692utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] Fixes 0ec3860 (#215163)

This fixes 0ec3860fe6d0b347e8e76b8353d0d71bd0684a0a (#215160).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0ec3860fe6d0b347e8e76b8353d0d71bd0684a0a

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-1utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+1-11 files

LLVM/project 6c4c03bllvm/test/MC/Disassembler/AMDGPU decode-err.txt

[NFC][AMDGPU] Use brackets in decode-err.txt
DeltaFile
+65-61llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+65-611 files

LLVM/project e337de1llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.h AMDGPUDisassembler.cpp, llvm/test/MC/Disassembler/AMDGPU decode-err.txt

[AMDGPU][MC] Fix out-of-range MFMA tuple register-name assertion (#215147)

Fixes #215007.
DeltaFile
+51-34llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+16-0llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+2-2llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+69-363 files

LLVM/project 0ec3860llvm/include/llvm/ExecutionEngine/Orc EPCGenericMemoryAccess.h, llvm/include/llvm/ExecutionEngine/Orc/RTBridge Proxy.h

[ORC] Reimplement EPCGenericMemoryAccess on RTBridge proxies (#215160)

Move EPCGenericMemoryAccess off ExecutionSession::callSPSWrapperAsync
and onto rt::Proxy objects. The FuncAddrs struct (13 ExecutorAddrs)
becomes Funcs (13 rt::Proxy members), and each access method collapses
to a single proxy call: the ProxySpec's dispatch now handles argument
serialization and the (Error, Result) -> Expected result plumbing that
was previously open-coded in each method.

Funcs members are protocol-agnostic rt::Proxy values, so a client can
populate a Funcs for a different protocol and pass it to the (public)
constructor. A new static Create(ES) provides the SPS convenience path,
resolving the proxies from the bootstrap JITDylib. The proxy types are
named once as rt::Mem*Proxy aliases in Proxy.h (beside the existing
Call*Proxy aliases) and reused by both the Funcs struct and the
memory-access ProxySpecs added to RTBridge/SPS/ProxySpecs.h.
InProcessEPC and SimpleRemoteEPC now just call
EPCGenericMemoryAccess::Create.


    [4 lines not shown]
DeltaFile
+63-121llvm/include/llvm/ExecutionEngine/Orc/EPCGenericMemoryAccess.h
+103-0llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/ProxySpecs.h
+43-19llvm/unittests/ExecutionEngine/Orc/EPCGenericMemoryAccessTest.cpp
+0-28llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
+13-15llvm/lib/ExecutionEngine/Orc/TargetProcess/OrcRTBootstrap.cpp
+26-0llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Proxy.h
+248-1833 files not shown
+250-2329 files

LLVM/project 29d7baellvm/lib/Target/LoongArch LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction fptosi.ll fptoui.ll

[LoongArch][LASX] Fix fptosi/fptoui from <4 x float> to <4 x i64> (#214621)

These were lowered through a 128-bit f32 to i32/u32 conversion followed
by a sign/zero extension, which silently clamps any finite input that
does not fit in i32/u32 instead of producing the correct 64-bit integer.

Convert directly with xvftintrzl.l.s for the signed case. For the
unsigned case there is no f32 -> u64 lane conversion in LASX, so widen
to f64 first (which is exact) and convert with xvftintrz.lu.d. Both
forms use xvpermi.d to move the inputs into the low 64 bits of each
128-bit lane, as required by these lane-wise conversions.

Built and verified on Arch Linux for Loong64:
https://github.com/lcpu-club/loongarch-packages/pull/974. Both the LLVM
side and the Highway test suite that discovered the bug have passed
verification.
Assisted by Kimi K3 AI agent.

Fixes https://github.com/llvm/llvm-project/issues/214605
DeltaFile
+7-6llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+3-2llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll
+2-2llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll
+12-103 files

LLVM/project 64fc330llvm/lib/Target/NVPTX NVPTXISelDAGToDAG.cpp NVPTXPassRegistry.def

[NVPTX] Add NewPM boilerplate to NVPTXISelDAGToDAG (#215132)
DeltaFile
+7-0llvm/lib/Target/NVPTX/NVPTX.h
+6-0llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
+4-0llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+17-03 files

LLVM/project 3f6b3a3llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer Legality.h

[SandboxVec][Legality] Fix a warning when build with GCC (NFC) (#214907)

Remove `maybe_unused` attribute from ResultReason member, beacuse it
used in `getReason` method. This PR fixes:


llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h:186:33:
error: ‘maybe_unused’ attribute ignored [-Werror=attributes]
  186 |   [[maybe_unused]] ResultReason Reason;
      |                                 ^~~~~~
DeltaFile
+1-1llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
+1-11 files

LLVM/project f7edf57llvm/include/llvm/ExecutionEngine/Orc EPCGenericMemoryAccess.h, llvm/lib/ExecutionEngine/Orc SimpleRemoteEPC.cpp InProcessEPC.cpp

[ORC] Construct EPCGenericMemoryAccess from ExecutionSession. (#215097)

Construct EPCGenericMemoryAccess objects from ExecutionSessions, rather
than ExecutorProcessControl objects. This is a step towards migrating
EPCGenericMemoryAccess off of raw callSPSWrapper* calls and on to the
new Proxy objects (d99bd3ed157).
DeltaFile
+16-19llvm/include/llvm/ExecutionEngine/Orc/EPCGenericMemoryAccess.h
+5-4llvm/unittests/ExecutionEngine/Orc/EPCGenericMemoryAccessTest.cpp
+1-1llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
+1-1llvm/lib/ExecutionEngine/Orc/InProcessEPC.cpp
+23-254 files

LLVM/project 941a04ellvm/lib/Target/AMDGPU GCNHazardRecognizer.h AMDGPU.td, llvm/test/CodeGen/AMDGPU fence-barrier-latency.ll llvm.amdgcn.tensor.load.store.ll

[AMDGPU] Keep TDM counter low (#214885)

Fixes: LCOMPILER-2572
DeltaFile
+153-0llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
+27-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPU.td
+3-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
+1-0llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
+1-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+193-06 files

LLVM/project 8f69580llvm/lib/MC MCXCOFFStreamer.cpp, llvm/test/MC/PowerPC aix-weak-definition.s

[PowerPC][AIX] Reject .weak_definition like ELF (#156072)

weak_definition is a Mach-O-specific directive and is not supported on
XCOFF. Previously it crashed the XCOFF streamer via report_fatal_error
in emitSymbolAttribute. Return false for MCSA_WeakDefinition like
MCELFStreamer does, so the parser rejects it with the same diagnostic as
ELF.
DeltaFile
+13-0llvm/test/MC/PowerPC/aix-weak-definition.s
+4-0llvm/lib/MC/MCXCOFFStreamer.cpp
+17-02 files

LLVM/project efe96c5libc/config/linux/aarch64 entrypoints.txt, libc/config/linux/riscv entrypoints.txt

Revert "[libc] Add realpath to linux entrypoints" (#215156)

Reverts llvm/llvm-project#212925, the tests assume that `/tmp` is a
real, valid directory on the system, which is not true for all
buildbots. `libc-riscv32-qemu-yocto-fullbuild-dbg` in particular seems
to have a symlink or similar from `/tmp` to `/var/volatile/tmp`. See
https://github.com/llvm/llvm-project/pull/212925#issuecomment-5234167255.
DeltaFile
+4-1libc/config/linux/x86_64/entrypoints.txt
+4-1libc/config/linux/riscv/entrypoints.txt
+0-1libc/config/linux/aarch64/entrypoints.txt
+8-33 files

LLVM/project 7941265clang/lib/StaticAnalyzer/Checkers DanglingPtrDeref.cpp

[analyzer] Add aggregate lifetime source binding to DanglingPtrDeref
DeltaFile
+8-0clang/lib/StaticAnalyzer/Checkers/DanglingPtrDeref.cpp
+8-01 files

LLVM/project fbda2f3clang/lib/StaticAnalyzer/Checkers LifetimeModeling.cpp, clang/test/Analysis lifetime-bound.cpp

Handle by-value struct cases and remove test case comment.
DeltaFile
+9-15clang/test/Analysis/lifetime-bound.cpp
+9-3clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
+18-182 files

LLVM/project 8fd9018llvm/test/CodeGen/DirectX WaveGetLaneCount.ll

[DXIL,test] Fix WaveGetLaneCount.ll after #156338 (#215155)
DeltaFile
+3-3llvm/test/CodeGen/DirectX/WaveGetLaneCount.ll
+3-31 files

LLVM/project bc0b122llvm/lib/Target/AMDGPU GCNHazardRecognizer.h AMDGPU.td, llvm/test/CodeGen/AMDGPU fence-barrier-latency.ll llvm.amdgcn.tensor.load.store.ll

[AMDGPU] Keep TDM counter low

Fixes: LCOMPILER-2572
DeltaFile
+153-0llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
+27-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPU.td
+3-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
+1-0llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
+1-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+193-06 files

LLVM/project 3c13d11utils/bazel/llvm-project-overlay/libc BUILD.bazel, utils/bazel/llvm-project-overlay/libc/test/src/stdlib BUILD.bazel

[bazel][libc] Add targets for realpath (#215127)
DeltaFile
+142-12utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+27-0utils/bazel/llvm-project-overlay/libc/test/src/stdlib/BUILD.bazel
+169-122 files

LLVM/project cc563cblibc/config/linux/aarch64 entrypoints.txt, libc/config/linux/riscv entrypoints.txt

[libc] Add realpath to linux entrypoints (#212925)
DeltaFile
+1-4libc/config/linux/x86_64/entrypoints.txt
+1-4libc/config/linux/riscv/entrypoints.txt
+1-0libc/config/linux/aarch64/entrypoints.txt
+3-83 files

LLVM/project 9d4d0bdclang/lib/CIR/CodeGen TargetInfo.h TargetInfo.cpp, clang/test/CIR/CodeGen record-member-kinds.c record-member-kinds.cpp

[CIR] Mark record members as data, pad, or empty in CIRGen

The per-member marks landed with no producer, so every record still reads as
though all of its members held data.  A record type still can't say whether it
carries anything for argument passing.  The x86_64 classifier has to know that
before it can drop an empty class from a signature.

CIRGen fills the marks in now.  Every member goes through one `addField` that
takes its kind, so a new push site can't quietly inherit a default.

A field's mark comes from `isEmptyFieldForABI`, ported from `isEmptyField` in
`ABIInfoImpl.cpp`.  Taking the ABI predicate rather than the layout one is
what gets C right.  Given `struct E {}`, a struct holding one `E` is empty for
the ABI in C but not in C++.

An assert on every record checks the marks against `isEmptyRecordForABI`, so
the existing `-fclangir` tests exercise them.

One case is now NYI.  A `[[no_unique_address]]` field that

    [9 lines not shown]
DeltaFile
+169-38clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+141-0clang/test/CIR/CodeGen/record-member-kinds.cpp
+97-0clang/test/CIR/CodeGen/record-member-kinds.c
+56-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+23-0clang/lib/CIR/CodeGen/TargetInfo.h
+9-9clang/test/CIR/CodeGenCoroutines/coro-task.cpp
+495-4721 files not shown
+554-9527 files

LLVM/project fc008d0llvm/test/Transforms/SLPVectorizer insert-element-build-vector.ll insert-element-build-vector-inseltpoison.ll, llvm/test/Transforms/SLPVectorizer/X86 entries-shuffled-diff-sizes.ll pr47629.ll

Rebase, fix regressions

Created using spr 1.3.7
DeltaFile
+94-2llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
+94-2llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
+30-23llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
+36-16llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
+36-16llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
+14-8llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll
+304-672 files not shown
+320-698 files

LLVM/project 3f4f519llvm/test/Transforms/ConstraintElimination monotonic-int-phis-decrement.ll induction-condition-in-loop-exit-postinc.ll

[ConstraintElim] Add tests for facts with decrementing IVs. (NFC) (#215143)

Extend test coverage with loops with decrementing inductions.
DeltaFile
+383-2llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit-postinc.ll
+163-0llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-decrement.ll
+546-22 files

LLVM/project c1119e9llvm/test/MC/Disassembler/AMDGPU decode-err.txt

[NFC][AMDGPU] Use brackets in decode-err.txt
DeltaFile
+65-61llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+65-611 files

LLVM/project 5c8f5b6llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize outer_loop_contiguous.ll

[VPlan] Don't classify irregular element types as contiguous. (#215121)

Before classifying an access as continuous, check if it has an irregular
type. If so, do not widen incorrectly. This matches the logic of the
inner loop code path.
DeltaFile
+5-13llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
+12-6llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+17-192 files

LLVM/project f531029llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.h AMDGPUDisassembler.cpp, llvm/test/MC/Disassembler/AMDGPU decode-err.txt

[AMDGPU][MC] Fix out-of-range MFMA tuple register-name assertion

Fixes #215007.
DeltaFile
+51-34llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+16-0llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+2-2llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+69-363 files

LLVM/project 00e6263llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h

[BFI] Extract computeMassInIrreducibleLoop. NFC (#215137)

This is a load-bearing irreducible loop extension of the Wu-larus
algorithm.
Give it its own function.
DeltaFile
+71-58llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+71-581 files