Fix lldb-dap non-leaf frame source resolution issue (#165944)
Summary
-------
While dogfooding lldb-dap, I observed that VSCode frequently displays
certain stack frames as greyed out. Although these frames have valid
debug information, double-clicking them shows disassembly instead of
source code. However, running `bt` from the LLDB command line correctly
displays source file and line information for these same frames,
indicating this is an lldb-dap specific issue.
Root Cause
----------
Investigation revealed that `DAP::ResolveSource()` incorrectly uses a
frame's PC address directly to determine whether valid source line
information exists. This approach works for leaf frames, but fails for
non-leaf (caller) frames where the PC points to the return address
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[AMDGPU] Insert `s_wait_xcnt(0)` before atomics to work around write-combining miss hazard
This patch adds a workaround for a hazzard on GFX1250, which inserts an `s_wait_xcnt(0)` instruction before any atomic operation that might write to memory.
Fixes SWDEV-543703.
AMDGPU: Remove override of TargetInstrInfo::getRegClass (#159886)
This should not be overridable and the special case hacks
have been replaced with RegClassByHwMode
tools: Remove unused PluginLoader includes
As far as I can tell there are 2 parallel plugin mechanisms.
opt -load=plugin does not work, and is ignored. opt -load-pass-plugin
does work. The only user of PluginLoader appears to be bugpoint.
[MLIR][Python] Add wrappers for scf.index_switch (#167458)
The C++ index switch op has utilities for `getCaseBlock(int i)` and
`getDefaultBlock()`, so these have been added.
Optional body builder args have been added: one for the default case and
one for the switch cases.
[JITLINK] Fix large offset issue (#167600)
Removed large offset test. It caused issue with ARM 32-bit because of
large offset.
Co-authored-by: anoopkg6 <anoopkg6 at github.com>
[mlir][tensor] Fix runtime verification for tensor.extract_slice for empty tensor slices (#166569)
I hit another runtime verification issue (similar to
https://github.com/llvm/llvm-project/pull/164878) while working with
TFLite models. The verifier is incorrectly rejecting
`tensor.extract_slice` operations when extracting an empty slice
(size=0) that starts exactly at the tensor boundary.
The current runtime verification unconditionally enforces `offset <
dim_size`. This makes sense for non-empty slices, but it's too strict
for empty slices, causing false positives that lead to spurious runtime
assertions.
**Simple example that demonstrates the issue:**
```mlir
func.func @extract_empty_slice(%tensor: tensor<?xf32>, %offset: index, %size: index) {
// When called with: tensor size=10, offset=10, size=0
// Runtime verification fails: "offset 0 is out-of-bounds"
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[mlir][memref] Fix runtime verification for memref.subview for empty memref subviews (#166581)
This PR applies the same fix from #166569 to `memref.subview`. That PR
fixed the issue for `tensor.extract_slice`, and this one addresses the
identical problem for `memref.subview`.
The runtime verification for `memref.subview` incorrectly rejects valid
empty subviews (size=0) starting at the memref boundary.
**Example that demonstrates the issue:**
```mlir
func.func @subview_with_empty_slice(%memref: memref<10x4x1xf32, strided<[?, ?, ?], offset: ?>>,
%dim_0: index,
%dim_1: index,
%dim_2: index,
%offset: index) {
// When called with: offset=10, dim_0=0, dim_1=4, dim_2=1
// Runtime verification fails: "offset 0 is out-of-bounds"
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AMDGPU: Remove override of TargetInstrInfo::getRegClass
This should not be overridable and the special case hacks
have been replaced with RegClassByHwMode
AMDGPU: Remove wrapper around TRI::getRegClass (#159885)
This shadows the member in the base class, but differs slightly
in behavior. The base method doesn't check for the invalid case.
AMDGPU: Remove override of TargetInstrInfo::getRegClass
This should not be overridable and the special case hacks
have been replaced with RegClassByHwMode
AMDGPU: Remove wrapper around TRI::getRegClass
This shadows the member in the base class, but differs slightly
in behavior. The base method doesn't check for the invalid case.
AMDGPU: Start using RegClassByHwMode for wavesize operands
(#159884)
This eliminates the pseudo registerclasses used to hack the
wave register class, which are now replaced with RegClassByHwMode,
so most of the diff is from register class ID renumbering.
