[Bazel] Add Support dependency to amdgpu_tests (#229597)
Fixes amdgpu_tests bazel layering failure introduced in commit
45ebdb6a55db, where AMDGPUUtilsTest.cpp includes
llvm/Support/Compiler.h.
[Bazel][libc] Update platform_file to depend on dup3 (#229595)
Fixes bazel build failure introduced in commit 64d83dcba1cb, where
file.cpp switched from using dup2 to dup3.
AMDGPU/GlobalISel: Use integer types when narrowing loads and stores
The narrowScalar mutation for loads and stores produced untyped scalars.
For FP-typed values this resulted in an untyped G_OR in the lowerLoad
expansion for unaligned private accesses, which failed to select.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Fix true16 losing 16-bit subreg operands
Folding a true16 v2s copy such as %2:sreg_32 = COPY %1.lo16 rewrites
its users to read %1.lo16 and relies on legalizeOperandsVALUt16 to
legalize the narrower operand. PHI and REG_SEQUENCE operands have no
register class, so it skipped them, leaving a 16-bit input in a VGPR_32
PHI or a 32-bit REG_SEQUENCE slot. DetectDeadLanes then marked the PHI
input undef and the defining load was deleted.
Widen such operands with a REG_SEQUENCE in legalizeOperandsVALUt16,
which runs both when the copy is folded and when the user is moved to
the VALU. This miscompiled uniform i16 loads feeding PHIs on gfx1250.
Change-Id: I9ddee5b11ff8503f4b2b1d1c4c776a12b270d968
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[RISCV] Fold (sub 0, (srl (and X, (1 << ShAmt)), ShAmt)) -> (sra (shl X, ShAmt2), bits-1) (#229509)
Improves codegen of is.fpclass+select. The AND to test bits of
is.fpclass may get turned into and+srl while the select emits a
neg. Isel will turn the and+srl into shl+srl but it's too late to
fold the neg.
Assisted-by: Claude
AMDGPU/GlobalISel: Use integer types when narrowing loads and stores
The narrowScalar mutation for loads and stores produced untyped scalars.
For FP-typed values this resulted in an untyped G_OR in the lowerLoad
expansion for unaligned private accesses, which failed to select.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
GlobalISel: Use integer types when splitting loads in lowerLoad
lowerLoad built the split pieces using the destination type with the
element size changed, which preserved floating-point types. An
unaligned f64 load was decomposed into G_ZEXTLOAD, G_SHL and G_OR on
f32 and f64, which then crashed in AMDGPU RegBankLegalize. Build the
pieces as integers and bitcast to a non-integer result type, as
lowerStore already does.
The pieces are now consistently integer typed, which allows more
constants to be CSEd in the existing tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[LV] Use frozen start values from the main plan directly (NFC). (#229571)
Only freeze possibly-poison start values of FindIV reductions in the
main plan. When preparing the epilogue plan, set the start operand of
its FindIV reduction results directly to the value frozen for the main
plan, instead of creating Freeze recipes in the epilogue plan and
replacing them later via a map. This leaves only VPExpandSCEVRecipes to
replace in the epilogue plan's entry.
[CIR] Fix use-after-free in BrOp::canonicalize (#229191)
BrOp::canonicalize took the branch's destination operands as an
OperandRange, erased the branch, and then passed the range to
mergeBlocks. The range points into the branch's operand storage, which
eraseOp frees, so mergeBlocks read freed memory whenever the merged
block had arguments. Valgrind reports it on the new test:
```
Invalid read of size 8
at mlir::ValueRange::dereference_iterator
by mlir::RewriterBase::inlineBlockBefore
by cir::BrOp::canonicalize
Address ... is 136 bytes inside a block of size 144 free'd
by mlir::RewriterBase::eraseOp
by cir::BrOp::canonicalize
```
It goes unnoticed with glibc malloc, which usually leaves the freed
operands intact. Copy the operands before erasing the branch.
[msan][test] Add MSan case to clang/test/CodeGen/fake-use-sanitizer.cpp (#229564)
Regression test for https://github.com/llvm/llvm-project/issues/225425,
showing that MSan incorrectly strictly handles fake_use.
[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions (#223563)
**migration tl;dr:** Replace usages of `amdgpu::Chipset` with
`ROCDL::TargetInfo`, ideally move from `chipset=` to `arch=`. If you
don't use upstream pipelines, call
'TargetInfo::migrateArchFeaturesToModuleFlags` at the appropriate
location.
Further note: if you've got a build pipeline that's getting a `gfxXXX`
name from something like `rocm_agent_enumerator`, using a full triple
name like the ones you get from `rocminfo` is preferred.
`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).
This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
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[Bazel] Add FlowSensitive/Models headers to clang:analysis (#229578)
Fixes bazel build failure introduced in commits e03123a63162 and
f0d6540d5307, where GtestModelHelpers.h was added to
lib/Analysis/FlowSensitive/Models and included in Models/*.cpp.
Take a different approach
HLASM derives the AMODE from the RMODE if no AMODE is explicitly
given. The same can be done in the GOFF writer, simplifying the
coding a lot.
[CodeGen] Drop dead SlotIndexes before allocation
SlotIndexes keeps the index list entry of an erased instruction and only
clears its instruction pointer. Live range sizes are measured in slot
indexes and greedy ranks ranges by size, so the leftovers inflate some
ranges more than others and reorder allocation, spilling heavily on
register-starved functions.
Add SlotIndexes::compactIndexes() to erase them. Erased entries are
unlinked, so LiveIntervals first reports the indexes it holds via
appendReferencedIndexes().
Off by default behind -greedy-compact-slot-indexes, since it changes
allocation across much of the test suite.
[libc] Add 'x' and 'e' mode support to fopen() (#224207)
Add exclusive creation (x) and close-on-exec (e) support to the fopen.
Also extended the related close-on-exec handling to fdopen() and to
freopen()
Fixes #223070
Assisted-by: Codex
[libc][locale] Fix nullptr argument handling in setlocale. (#229569)
`setlocale` function should accept `nullptr` as a possible value for the
second argument - in this case the
locale is not modified but queried. Make sure to return `C` locale in
this case (the only one supported by LLVM-libc).
Expand the unit test to verify `setlocale` behavior.
[CIR] Classify reference-to-pointer catch parameters in CIRGen
When a handler catches a reference to a pointer, __cxa_begin_catch returns
the caught pointer by value instead of the address of the exception object,
and how the reference is bound depends on whether the pointer points to a
class. The CIR type of the catch parameter cannot always tell whether it is
a reference to a pointer, or whether the pointee is a class.
CIRGen now records both facts from the AST in two new InitCatchKind values,
reference_to_pointer and reference_to_record_pointer. The Itanium EH
lowering switches on the kind alone, the way classic codegen does.
Assisted-by: Claude Code / Claude Opus 5.5
[AMDGPU] Account for gfx950 permlane hazards during scheduling (#229517)
The [CDNA4 ISA Reference Guide, §4.5, Table 11, p.
21](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf#page=29)
requires 2 wait states between a VALU writing a VGPR and a permlane
reading it, and 4 between a `VCMPX` writing EXEC and a permlane. As far
as I know, this is GFX950 specific.
Right now the gfx950 scheduler does not query this existing hazard
check, so final hazard processing can insert avoidable `nop`s despite
available independent instructions.
This patch expose the existing permlane hazard check in
`getHazardType()`.
Also add MIR coverage for source dependencies, unrelated writes,
available fillers, and VCMPX scheduling boundaries.
Partially addresses: #228816
RuntimeLibcallsEmitter: Handle calling conv in per-library functions (#223760)
Pull handling of the default calling convention into the
setAvailableLibFuncs_<name> functions, so the library logic will be
fully contained.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[libc] Use sighandler_t typedef in public headers for all platforms. (#229508)
`signal` function from ANSI C takes an argument and returns value of
type `typeof(void(int))`.
While not strictly necessary, some libc implementations provide their
own convenience typedef for the signal handler type. LLVM-libc used
`sighandler_t` previously, but only on Linux systems. This change makes
this typedef used on other systems as well, the reasons being:
* convenience for the user code, which can rely on this typedef in the
signal-handling code;
* ability to fix a gross hdrgen workaround (YAML configs and
hdrgen-based generation doesn't really support a C-style syntax for
functions-returning-function-pointers)
* ability to fix a **bug** in the generated header - `__NOEXCEPT` suffix
is translated into `noexcept` in the C++ mode, with this qualifier
applied to the _returned function pointer type_ instead of the `signal`
function itself. The "proper" way to use noexcept would be to move it
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[X86] Mark .lrodata for non-mergeable constants with SHF_X86_64_LARGE (#229279)
Under the large code model, a constant pool entry that is not mergeable
(a size other than 4, 8, 16 or 32 bytes, such as a 64-byte AVX-512
vector) is placed in .lrodata without SHF_X86_64_LARGE. Sections are
uniqued by name, so a large global emitted into .lrodata later in the
same module ends up in that unflagged section.
Assisted-By: Claude Opus 5.5
