[flang][AllocationPlacement] prevent promotion of mock result to allocmem (#212825)
Under the new experimental pass that can move automatic arrays to the
heap, "mock" result storage may be promoted to allocmem before
AbstractResult removes them and replace them by a hidden result.
Add a fir.must_be_stack attribute to these mock alloca so they are never
promoted. So that passes dealing with array function results ABI can
expect to find an fir.alloca and remove it.
AMDGPU: Export the TargetParser feature bitset
Previously this bitset was only used to populate the feature
name string map used by clang. Eventually this will replace
the current bitmask integer. AArch64 already has a similar
interface.
Co-authored-by: Claude (Claude-Opus-4.8)
AMDGPU: Tablegenerate TargetParser feature sets
Traditionally we maintained 2 parallel feature mechanisms,
one in clang (later moved to TargetParser), with largely
mirrored subtarget features defined in the backend. Start
directly taking feature information from the backend and putting
it into TargetParser. This is still in a compromise mid-migration
state. We still have both the legacy "ArchAttr" bitfield integer,
plus a new AMDGPUFeatureBitset field stored in the table, which
isn't yet exported.
For the moment, the new bitset is only used to populate the
feature string name map, which is the big maintainability win.
This also lists an explicit subset of exported features to
avoid churn.
Co-authored-by: Claude (Claude-Opus-4.8)
[flang][OpenMP] Lower allocate align modifier on parallel
Lower the align modifier on OpenMP allocate clauses for parallel constructs.
Carry per-item alignments through the OpenMP dialect and select
__kmpc_aligned_alloc for aligned private storage while retaining the existing
allocation and cleanup behavior for unaligned items.
Add source, verifier, preservation, LLVM IR, i386 ABI, and overflow coverage.
Keep unsupported construct kinds and device lowering unchanged.
Assisted-by: GitHub Copilot
[libc++][NFC] Rename the streambuf members (#212277)
This refactors `streambuf` to contain a `_GetArea` and a `_PutArea`.
This makes the code significantly easier to read, since the pointers
belonging together are bundled in a struct.
[VPlan] Make simplifyRecipe more like InstCombine
Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.
Similarly to InstCombine, combines that modify a recipe should return the same recipe.
[libc++] Remove SFINAE checks in tuple which are always true (#212765)
We have a specialization for `tuple` with no arguments, so checking
`sizeof...(_Tp) >= 1` in the primary template will never be false.
[lldb] Fix stale L1 memory cache read after memory write (#208347)
A `memory write` can leave stale bytes in the L1 memory cache, so a later
`memory read` of the address that was just written returns the old value.
The L1 cache (`m_L1_cache`) is a map keyed by each chunk's start address, and
chunks can overlap: a read larger than an L2 cache line
(`target.memory-cache-line-size`, 512 by default) bypasses L2 and is stored
whole in L1, so two large reads can produce two chunks that both cover the same
address.
`Flush()` invalidates the L1 cache on a write. It started at the chunk at or
below the flushed address and walked forward, stopping at the first chunk that
did not intersect. It therefore never inspected a chunk that starts below the
flushed address but is long enough to reach into it, leaving that chunk behind
with the stale byte. A later read fully contained in that chunk is served from
the cache and returns the old value.
Fix `Flush()` to walk the whole L1 cache and erase every chunk that intersects
[7 lines not shown]
[SPARC] Support the .seg directive (#209001)
Support the legacy .seg directive used by SunOS SPARC assembly. Map
"text", "data", "data1", and "bss" to their corresponding MC sections,
using subsection 1 for "data1".
[WebAssembly][TTI] Avoid crash when costing scalable vector shifts (#212759)
I see the following
```
anutosh491 at Anutoshs-MacBook-Air llvm-project % cat /private/tmp/wasm-scalable-shift-cost.ll
define <vscale x 4 x i32> @shift(<vscale x 4 x i32> %x,
<vscale x 4 x i32> %amount) {
%result = shl <vscale x 4 x i32> %x, %amount
ret <vscale x 4 x i32> %result
}
anutosh491 at Anutoshs-MacBook-Air llvm-project % build-assert/bin/opt \
-mtriple=wasm32-unknown-unknown \
-mattr=+simd128 \
-passes='print<cost-model>' \
-disable-output \
/private/tmp/wasm-scalable-shift-cost.ll
[27 lines not shown]
IR: Introduce "float-abi" module flag (#210821)
This is intended to eliminate the FloatABIType TargetOptions field.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[RISCV] Fix crash in convertToVLMAX when AVL is an ADDI of a frame index (#212923)
`getConstant()` recognizes an AVL that is an immediate by checking
the opcode is `ADDI`, then reading the second operand and checking
if it is `X0`. However the second operand may be a frame index and
`getReg()` asserts with "This is not a register operand!".
We should guard the register access with `isReg()` before comparing
against `X0`.
Fixes #212797.
[Docs][AMDGPU] Explain completion of async operations (#212756)
This improves the somewhat hand-wavey "memory model" currently described
for async operations. While this version is also not complete, it
prepares for the more complete memory model being written down.
[RISCV] Split and rename WriteVSlideI/WriteVISlide1X/WriteVFSlide1F (#212184)
Split each of these SchedWrites into separate slide-up and slide-down
variants:
- WriteVSlideI -> WriteVSlideUpI, WriteVSlideDownI
- WriteVISlide1X -> WriteVISlide1Up, WriteVISlide1Down
- WriteVFSlide1F -> WriteVFSlide1Up, WriteVFSlide1Down
SpacemiT X100 and A100 have different latencies and/or throughput for
slide up vs. slide down operations, so they need separate SchedWrites to
model that difference.
clang/AMDGPU: Forward xnack/sramecc mode to the assembler
When assembling a .s file with no target ID directive, the requested
xnack/sramecc mode has no module flag to carry it. Forward the mode
requested via -mxnack/-msramecc (or the -mcpu target ID modifiers) to the
assembler as a target feature so it is recorded in the object's e_flags.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
CSKY: Avoid constructing a temporary CSKYSubtarget in AsmPrinter (#212944)
This was reconstructing a subtarget equivalent to the global
subtarget instead of just using the available one.
ARM: Mark more generic libgcc functions as available (#210961)
Generic libgcc/compiler-rt functions coexist with aeabi variants
(e.g., __divsi3 and __aeabi_idiv) according to my reading of the
build. At least in compiler-rt, some are aliases.
They were previously removed from the available set on AEABI+AAPCS
targets to force selection of the preferred __aeabi_* variants, back when
only one implementation per libcall could be recorded.
Now that multiple implementations can be available per libcall, stop
hiding the generics and select the __aeabi_* variant explicitly as the
preferred implementation. This reduces the number of special cases to
consider for future libcalls info improvements.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[Docs][AMDGPU] availability/visibility in addrspace(3) and other cleanups
addrspace(3) on AMDGPU corresponds to LDS, which is a fast memory directly
accessed by all threads in a workgroup (there is no intervening cache). Thus,
any accesses to this addrspace have built-in availability and visibility at
"workgroup" scope.
Other cleanups:
- Update the intrinsic names to match the implementation.
- Explain store-available and load-visible.
- Rename to "make-available" and "make-visible" for consistent spelling.
[AArch64] Remove assembler-only register classes (#211527)
ZPRMul2, ZPRMul4 and PPRMul2 register classes are used solely by the asm
parser to validate other register classes (ZPR2Mul2, ZPR4Mul4,
PPR2Mul2). Since they're real register classes TableGen synthesizes
numerous intersection classes and pressure sets from them.
Removing them and validating the constraint directly in the assembly
parser reduces:
- generated register classes: 521 -> 403 (~22%)
- generated pressure sets: 188 -> 60 (68%)
- generated register-info size: 11.9 MB -> 9.1 MB (23%)
Also improves CTMark geomean -0.23% on stage1-aarch64-O3.
https://llvm-compile-time-tracker.com/compare.php?from=a90dbb43cd67856f681feba82d51a0d5fbcae3c2&to=5565d4907cdf960cc142a7507f16e551f51919b0&stat=instructions%3Au
Assisted-by: codex
AMDGPU: Export the TargetParser feature bitset
Previously this bitset was only used to populate the feature
name string map used by clang. Eventually this will replace
the current bitmask integer. AArch64 already has a similar
interface.
Co-authored-by: Claude (Claude-Opus-4.8)
