[mlir][spirv] Fix crash in FuncOpVectorUnroll for dynamic-shaped tensor args (#184626)
FuncOpVectorUnroll::matchAndRewrite iterates over all function arguments
and creates a zero-constant placeholder for any non-vector argument via
rewriter.getZeroAttr(type). For dynamically-shaped tensor types such as
tensor<?x2xi8>, getZeroAttr ultimately calls
DenseIntOrFPElementsAttr::getRaw which asserts that the type has a
static shape.
Add an early pre-check that returns failure() for any non-vector
argument with a dynamically-shaped type. This must be done before any IR
modifications are made, since returning failure() after inlining the
function body would leave the IR in an inconsistent state.
Fixes #148369
[mlir] Add cross-context checks to the IR verifier (#184627)
Detect IR where result types, operand types, or discardable attribute
values come from a different MLIRContext than the operation itself.
Mixing contexts is a latent use-after-free hazard when one context is
destroyed before the other; the verifier now reports a clear error
instead of silently allowing the invalid IR through.
Three new unit tests in MLIRIRTests cover each scenario.
Fix #61569
[MLIR][Vector] Fix crash in operatesOnSuperVectorsOf on rank-mismatched shaped (#183967)
The `operatesOnSuperVectorsOf` function in VectorUtils.cpp contained an
assertion that fired when a `vector.transfer` operation's vector type
had a different rank (or non-divisible shape) from the sub-vector type
supplied by the caller:
assert((ratio || \!mustDivide) &&
"vector.transfer operation in which super-vector size is not an"
" integer multiple of sub-vector size");
This assertion was incorrect because the function's callers (e.g., the
affine super-vectorizer) legitimately pass transfer ops whose vector
type doesn't match the requested sub-vector shape. In those cases the
correct answer is simply that the op does not operate on a super-vector
of that sub-vector type, so `operatesOnSuperVectorsOf` should return
`false`.
Remove the assert return `false` when `computeShapeRatio` produces no
[3 lines not shown]
[clang-tidy] Teach `performance-faster-string-find` about `operator+=` (#182697)
This is a followup to #182633. Like in that PR, `operator+=` doesn't fit
with the check name, but the same optimization is applicable to it:
https://en.cppreference.com/w/cpp/string/basic_string/operator+=.html
[AMDGPU] Optimize S_SETREG_IMM32_B32 piggybacking by treating it as a mode scope boundary (#184703)
When `handleSetregMode` encounters an `S_SETREG_IMM32_B32` with `Size <=
12`, the instruction's `imm32[12:19]` bits are "free" for VGPR MSB
piggybacking. Previously, the old mode was eagerly written into these
bits, but the `Rewritten` guard in `setMode` would then block subsequent
piggybacking when the next VGPR instruction needed a different mode,
causing an unnecessary `S_SET_VGPR_MSB` to be emitted.
Model the `S_SETREG_IMM32_B32` as the boundary of the old mode's control
range: reset `CurrentMode` and clear `bits[12:19]` to zero. This lets
the next `setMode` call freely piggyback the required mode without
triggering `Rewritten`.
Add a test for handling a crashing breakpoint condition (#184247)
I was working on something and broke the handling of breakpoint
conditions that crash. In fixing that I noticed that there wasn't a test
for this scenario, so this PR adds one.
---------
Co-authored-by: Med Ismail Bennani <ismail at bennani.ma>
[SafeStack] Fix crashing with scalable TypeSizes (#180547)
On e.g. aarch64 the TypeSize of scalar types can have a size that is not
known at compile time.
Currently when safestack occurs those it simply crashes as described in
https://github.com/llvm/llvm-project/issues/175868.
Since we cannot verify the size at compile time we simply consider the
access to be unsafe (in regards to safestack).
Reproducer:
```
#include <arm_sve.h>
int main() {
svint32_t vec = svindex_s32(0, 1);
svint32_t res = svadd_s32_z(svptrue_b32(), vec, vec);
int32_t buffer[1024];
svst1_s32(svptrue_b32(), buffer, res);
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[lldb] Fix the AArch64 CPSR reg defn to list generic reg
My change to remove an incorrect DWARF register number for
CPSR unintentionally dropped the LLDB_REGNUM_GENERIC_FLAGS
generic reg type in the definitions of cpsr.
We need to have a macro (DEFINE_MISC_REGS) for status/control
registers that have no DWARF/eh_frame and no generic reg num.
I added a new macro, DEFINE_GPR_CPSR, for cpsr which is unique
in having no DWARF/eh_frame numbers but does have a generic
flags reg number.
[llvm][Support] Make createUniquePath require at least one wildcard marker (#184688)
The API was a bit easy to accidentally mis-use, as it silently accepted
Model strings without any randomness marker characters (`%`), which
results in a unique path that's not at all unique. To avoid this
foot-gun, we now assert that the model contains at least one, and update
all the broken usages accordingly.
rdar://170349565
[CIR][NFCI] Fixup some test regressions due to OGCG changes (#184699)
Discovered during CI in a different patch, 3 tests started failing for
unknown reasons due to some very mild changes to the IR, but only in
'classic' codgen parts of the tests. These tests were overly specific
for no good reason, so this patch just fixes that.
[AMDGPU] Optimize S_SETREG_IMM32_B32 piggybacking by treating it as a mode scope boundary
When `handleSetregMode` encounters an `S_SETREG_IMM32_B32` with `Size <= 12`,
the instruction's `imm32[12:19]` bits are "free" for VGPR MSB piggybacking.
Previously, the old mode was eagerly written into these bits, but the
`Rewritten` guard in `setMode` would then block subsequent piggybacking when the
next VGPR instruction needed a different mode, causing an unnecessary
`S_SET_VGPR_MSB` to be emitted.
Model the `S_SETREG_IMM32_B32` as the boundary of the old mode's control range:
reset `CurrentMode` and clear `bits[12:19]` to zero. This lets the next
`setMode` call freely piggyback the required mode without triggering
`Rewritten`.
[DebugInfo] Don't match wrong NULL in CHECK lines of dwarf5-debug-info-static-member.ll (#184694)
Fixes failure on clang-ppc64le-rhel buildbot
(https://lab.llvm.org/buildbot/#/builders/145/builds/13080) after
#184219.
On ppc64le, children are not produced for DW_TAG_subprogram "main" in
this test. Therefore, dwarfdump doesn't print NULL after this tag. On
other platforms (AArch64/X86), DW_TAG_subprogram has DW_TAG_variable
"instance_C", which should not be matched by the check lines.
Loosened the check lines (turned CHECK-NEXT into CHECK) to make them
work for all mentioned platforms.
[Clang] Only define `wchar_size` module flag if non-standard (#184668)
Summary:
This PR simply changes the behavior of the `wchar_size` flag. Currently,
we emit this in all cases for all targets. This causes problems during
LLVM-IR linking, specifically because this would vary between Linux and
Windows in unintuitive ways. Now we have an llvm::Triple helper to
determine the size from the known values. The module flag will only be
emitted if these do not match (indicating a non-standard environment).
In addition to fixing AMDGCN bitcode linking, this also means we don't
need to bloat *every* IR module compiled by clang with this flag. The
changed tests reflects this, one less unnecessary piece of metadata.
[SLP]Do not consider split vectorize nodes as vector phi nodes
Split vectorize nodes should not be considered as vector PHI nodes, when
trying to find the insertion point for the postpotned nodes.
Fixes #184585
[clang-doc] Sort index and avoid non-determinism (#184675)
Consolidate logic to get sorted children from StringMap.
Using the new API makes it more natural to not miss cases
where we missed sorting the children directly.
This also allows us to remove -DAG checks from tests and have
deterministic ordering.
[CIR] Upstream global variable replacement (#184686)
This change upstreams the CIR implementation of global variable
replacement. When we get a call to get or create a global variable using
a type that does not match the previous type for a variable of the same
name, we need to replace the old definition with the new one. In classic
codegen that was as simple as replaceAllUses+eraseFromParent, but in CIR
because we have typed pointers, we need to visit the uses and update
them with bitcasts to reflect the new type.
[lld][WebAssembly] Convert weak-alias tests to assembly. NFC (#184667)
This actually both improves and simplifies the `Inputs/weak_alias`. With
the `.ll` version we ended up using memory and `__stack_pointer` and
locals, but LLVM ended up generated `call` rather than `call_indirect`
for the `call_alias_ptr` and `call_direct_ptr`. With the assembly tests
we can ensure the usage of `call_indirect` while avoiding all the other
stuff.
