[libcxx] Add user to linux-builder docker image (#228933)
Accidentally didn't move this over when copying from the builder-base
image in 84812cba90fe0a0f95544a3ff01da1e61346a68d. Without these we run
as root by default which results in not throwing permission denied
errors when running the test suite.
[CIR] Parse .cir cc1 input and support -emit-cir from it (#228288)
Fill in the Language::CIR path of CIRGenAction::ExecuteAction: register
the ClangIR dialects, parse and verify the main file into a ModuleOp
with MLIR diagnostics routed through CIRDiagnosticHandler, and require
the module's cir.triple to match the target triple. A mismatch is an
error rather than an override, because CIR emitted by -emit-cir has
already been lowered for the target ABI of its own triple.
It is still unclear whether we should disallow any overrides of module
CIRGen attribues. At this point in time, I opt to go with a conservative
approach.
The CIR-to-CIR pipeline is not run, because -emit-cir output has already
been through it and its lowering passes are not idempotent; recording
the pipeline stage on the module is left for a follow-up. Other outputs
still report that ClangIR input is not yet supported.
`registerAllDialects` now registers the LLVM dialect. The data layout
[14 lines not shown]
[MC][ELF] Preserve bits 7:4 of st_other (#228882)
The ELF gABI defines visibility in the low bits of st_other and leaves
the upper bits without a generic meaning [1]. Architecture-specific ELF
extensions use these upper bits. MIPS uses bits 7:4 to identify MIPS16
code symbols with STO_MIPS_MIPS16 (0xf0).
MCSymbolELF currently accepts only bits 7:5, so setting STO_MIPS_MIPS16
triggers an assertion. Expand the storage to preserve bits 7:4 and shift
the adjacent internal flags accordingly.
[1] ELF gABI, Section 5.1, Symbol Table Entry:
https://gabi.xinuos.com/elf/05-symtab.html#symbol-table-entry
Assisted-by: OpenAI Codex
[LoongArch] Use [X]VSETNEZ.V/[X]VSETEQZ.V for whole-vector zero check (#226814)
Introduce `loongarch_vanynonzero` and `loongarch_vallzero` for checking
wether a vector has any non zero or all of them are zero, which could
simply some vector comparison such as the one below.
Before
```
xvseq.d $xr0, $xr0, $xr1
xvmskltz.d $xr0, $xr0
xvpickve2gr.wu $a0, $xr0, 0
xvpickve2gr.wu $a1, $xr0, 4
bstrins.d $a0, $a1, 3, 2
beqz $a0, .LBB2_2
```
After
```
xvseq.d $xr0, $xr0, $xr1
xvseteqz.v $fcc0, $xr0
[4 lines not shown]
[LoongArch] Use [X]VSETNEZ.V/[X]VSETEQZ.V for whole-vector zero check (#226814)
Introduce `loongarch_vanynonzero` and `loongarch_vallzero` for checking
wether a vector has any non zero or all of them are zero, which could
simply some vector comparison such as the one below.
Before
```
xvseq.d $xr0, $xr0, $xr1
xvmskltz.d $xr0, $xr0
xvpickve2gr.wu $a0, $xr0, 0
xvpickve2gr.wu $a1, $xr0, 4
bstrins.d $a0, $a1, 3, 2
beqz $a0, .LBB2_2
```
After
```
xvseq.d $xr0, $xr0, $xr1
xvseteqz.v $fcc0, $xr0
[4 lines not shown]
[CodeGenPrepare] Prefix option names with cgp-
Rename the CodeGenPrepare options so that they start with cgp-, and turn
the -disable-* options into positive options that default to true:
```
-addr-sink-* -cgp-addr-sink-*
-cgpp-huge-func -cgp-huge-func
-disable-cgp-X -cgp-X=0
-disable-complex-addr-modes -cgp-complex-addr-modes=0
-disable-preheader-prot -cgp-preheader-prot=0
-enable-andcmp-sinking -cgp-andcmp-sinking
-force-split-store -cgp-force-split-store
-stress-cgp-X -cgp-stress-X
```
The section prefix options (-profile-guided-section-prefix, etc.) are
kept, as they are not specific to CodeGenPrepare.
Aided by Opus 5.5
[CodeGen] Declare command line options in TableGen (#228911)
Move the cl::opts of TargetPassConfig.cpp and CodeGenPrepare.cpp into
CodeGenOptions.td, private to lib/CodeGen; other files will follow.
-enable-machine-outliner (cl::ValueOptional) and -regalloc
(RegisterPassParser) stay cl::opt.
CodeGenPrepare and its addressing-mode helpers hold
`const CodeGenOptions &Opts`; TargetPassConfig functions read
CodeGenOptions::Global. getCGPassBuilderOption() converts BoolOrDefault
members to the cl::boolOrDefault and std::optional<bool> fields of the
public CGPassBuilderOption. -basic-block-section-match-infer, which was
not cl::Hidden, is now listed by -help-hidden only.
Aided by Opus 5.5
[Mips] Add microMIPS CP0 move encodings (#228884)
Define the microMIPS MFC0 and MTC0 formats and instruction records for
pre-R6 targets, including the select field. Accept the two-operand forms
with an implicit select value of zero and add generic scheduling
entries.
Extend the control-instruction tests with explicit and implicit select
operands, checking both byte orders.
Assisted-by: OpenAI Codex # Testcases
[CodeGenPrepare] Prefix option names with cgp-
Rename the CodeGenPrepare options so that they start with cgp-, and turn
the -disable-* options into positive options that default to true:
```
-addr-sink-* -cgp-addr-sink-*
-cgpp-huge-func -cgp-huge-func
-disable-cgp-X -cgp-X=0
-disable-complex-addr-modes -cgp-complex-addr-modes=0
-disable-preheader-prot -cgp-preheader-prot=0
-enable-andcmp-sinking -cgp-andcmp-sinking
-force-split-store -cgp-force-split-store
-stress-cgp-X -cgp-stress-X
```
The section prefix options (-profile-guided-section-prefix, etc.) are
kept, as they are not specific to CodeGenPrepare.
Aided by Opus 5.5
[CodeGen] Declare command line options in TableGen
Move the cl::opts of TargetPassConfig.cpp and CodeGenPrepare.cpp into
CodeGenOptions.td, private to lib/CodeGen; other files will follow.
-enable-machine-outliner (cl::ValueOptional) and -regalloc
(RegisterPassParser) stay cl::opt.
CodeGenPrepare and its addressing-mode helpers hold
`const CodeGenOptions &Opts`; TargetPassConfig functions read
CodeGenOptions::Global. getCGPassBuilderOption() converts BoolOrDefault
members to the cl::boolOrDefault and std::optional<bool> fields of the
public CGPassBuilderOption. -basic-block-section-match-infer, which was
not cl::Hidden, is now listed by -help-hidden only.
Aided by Opus 5.5
[VPlan] Support pointer min/max bounds in VPlan memory runtime checks. (#225828)
Expand pointer-typed SCEV min/max expressions in VPSCEVExpander as
icmp + select (including profile metadata), matching SCEVExpander.
This allows modeling memory runtime checks with pointer min/max bounds
in VPlan, e.g. for accesses with a runtime stride of unknown sign.
Depends on https://github.com/llvm/llvm-project/pull/221483
PR: https://github.com/llvm/llvm-project/pull/225828
[Mips] Add microMIPS hazard-barrier jump encodings (#228885)
Add microMIPS encodings for jr.hb and jalr.hb. Use BaseOpcode and MMRel
to map the standard opcodes to their microMIPS encodings.
Assisted-by: OpenAI Codex # Testcases
[mlir][acc] Declare the memory effects of acc.atomic.read
The operation read `x` and wrote `v` but declared no memory effects at
all, so every memory analysis had to treat both locations as unknown and
stay maximally conservative. In particular it could not be seen to
overwrite `v`.
Declare the effects per operand so the read on `x` and the write on `v`
are visible.
[OCaml] Use DataLayout instead of string in (set_)data_layout (#228445)
Now that DataLayout is part of llvm rather than llvm_target, make use of
it in the `data_layout` and `set_data_layout` APIs.
[Mips] Restrict microMIPS GP load folding to word loads (#228881)
Only LW has a GP-relative variant, so restrict the folding to LW_MM and
LW_MMR6.
Assisted-by: OpenAI Codex # Testcases
[lld][Mips] Remove signed range check for R_MICROMIPS_26_S1 (#228880)
R_MICROMIPS_26_S1 encodes a shifted index within the current PC region,
not a signed absolute address. Applying the PC-relative relocation's
signed 27-bit check rejects valid destinations in higher address
regions.
Write the jump index without that check, as for R_MIPS_26, while
retaining
the signed range check for R_MICROMIPS_PC26_S1. Cover both jumps and
calls
at a high address in little- and big-endian objects.
Assisted-by: OpenAI Codex # Testcases
[Mips] Emit 16-bit microMIPS NOPs for alignment (#228879)
Zero-filled halfword padding is not a complete microMIPS NOP. Emit
move $zero, $zero when alignment requires a two-byte instruction, then
use zero-encoded 32-bit NOPs for the remaining padding.
Handle an odd leading byte as data padding and preserve zero filling in
standard MIPS mode. Extend the unaligned-NOP test to cover both byte
orders, odd-sized data, and mode changes.
Assisted-by: OpenAI Codex # Testcases
