[SPIR-V] Decompose bool vector bitcasts element-wise (#231150)
`preprocessBoolVectorBitcasts` (#187960) lowers bitcasts to or from `<N
x i1>` through an `iN`, which fails with `Unsupported Integer width!`
once N exceeds the maximum SPIR-V integer width. InstCombine creates
such bitcasts from `trunc (extractelement <16 x i32> %v, 0) to i1`,
which becomes an extract from a `<512 x i1>` bitcast. We hit this in
Julia's KernelAbstractions.jl, which shuffles a struct with a `Bool`
field as a `<16 x i32>`.
When the other side is a vector, convert it per element instead: lane
`I` is bit `I % K` of element `I / K`. Scalars and single-element
vectors keep the `iN` path. Since no InstCombine runs afterwards,
constant-index extracts are computed directly rather than materializing
every lane.
AArch64: Use minimal tablegen inputs for TargetParser
Generate AArch64TargetParserDef.inc from a minimal file instead of all
of AArch64.td
llvm-min-tblgen -gen-arm-target-def
Gigainstructions Peak RSS .td deps
AArch64.td 3.36 169 MB 100
AArch64TargetParserDef.td 0.05 7 MB 10
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AArch64: Move scheduling model definitions to separate file
Move the SchedMachineModel definitions, and the unsupported feature
lists they use, out of the scheduling files. The processor definitions
can then be parsed without the instruction and scheduling information.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AArch64: Move predicate definitions to separate file
Split the subtarget predicate definitions out of AArch64InstrInfo.td
so they can be used without parsing the instruction definitions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CIR][HIP] Support managed variables (#230910)
Lower HIP __managed__ variables in CIR as classic codegen does
- Rename variable x to `x.managed` and add a pointer x that the runtime
fills in
- Access the variable through that pointer
- Register it with __hipRegisterManagedVar
[LoongArch] Add support for vector add/sub on vNi128 types
Make v1i128 and v2i128 legal types in the LSX/LASX register classes and
lower ADD/SUB on them to VADD.Q/XVADD.Q and VSUB.Q/XVSUB.Q.
The vNi128 types are intentionally kept out of LSXVTs/LASXVTs so that
only a minimal set of operations is legal on them: LOAD, STORE, BITCAST,
UNDEF, ADD, SUB and VSELECT (via [X]VBITSEL.V). VECTOR_SHUFFLE is custom
lowered by performing the shuffle on the equivalent i64 vector type.
Everything else keeps the default Expand action.
Since the widening extend combine can now produce VEXTH/VEXTH_U on
vNi128, also add the [X]VEXTH.Q.D and [X]VEXTH.QU.DU patterns.
[LoongArch][NFC] Add tests for vector add/sub on vNi128
Also add tests for load/store, select and shuffle on vNi128 types to
make sure operations without dedicated support are still legalized
correctly.
[libc] Use a syscall wrapper for `sched_setscheduler` (#231865)
Follow up of https://github.com/llvm/llvm-project/pull/231512.
This PR move `sched_setscheduler` behind the centralized syscall
wrappers, following `libc/docs/dev/syscall_wrapper_refactor.md`.
[mlir][vector] Expose vector linearize as transforms (#231412)
Adds vector linearize patterns as a transform op.
The transforms design follows existings tests which are also converted
to use transform schedules instead of dedicated test passes.
Assisted-by: Claude
[SCEV] Prove monotonic predicates from loop entry in isKnownViaInduction
Prove "IV pred Inv" on every iteration of a loop when Inv is
loop-invariant, the predicate holds on loop entry, and it can only change
from false to true as the loop iterates.
Before, the predicate also had to be proven on the backedge, which
usually fails when the loop exit only bounds the IV from above. E.g.
i >=s 0 for an nsw IV starting at s was not proven even when s >=s 0 was
known on entry. As a result, in a loop guarded by "start <u len",
IndVars could not compute a[i - 32] in i64.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[flang] simplify ieee_logb.f90 (NFC) (#229644)
This patch is to simplify the test to focus on lowering of the ieee_logb
intrinsic so that it can be tested with other targets. The test is also
enabled for the PPC target.
[SCEV][NFC] Factor getMonotonicPredicate out of getLoopInvariantPredicate
The next change needs the same setup as getLoopInvariantPredicate.
Move it into a private helper: put the loop-invariant operand on the
RHS, check that the other side is a recurrence of the loop, and compute
the predicate's monotonicity.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][NFC] Use isKnownOnEveryIteration in isKnownViaInduction
isKnownViaInduction and isKnownOnEveryIteration both prove a predicate
on every iteration from loop entry and the backedge, so the next change
can extend one place.
Add a private isKnownOnEveryIteration overload that takes any LHS and
RHS and the loop, and move the entry/backedge check from
isKnownViaInduction into it. The public overload is unchanged.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[flang][acc] Do not hoist loops into gang-redundant code of a parallel region
In a compute region from an acc.parallel construct, code outside of the
loops with gang-level worksharing is executed redundantly by all gangs.
A loop that LICM moved there from inside an scf.parallel could later be
distributed across gangs. When its result is used in the same kernel,
each gang then only computed part of it, giving wrong results.
Attach an OpenACC-aware fir::OperationMoveOpInterface model to
scf.parallel that does not allow moving loops out of it in a compute
region from an acc.parallel construct.
[lldb][NFC] Split up TestMultithreaded.py (#231856)
This splits the big and slow TestMultithreaded test into several smaller
tests. This allows running subtests in parallel.
It also makes it more obvious which of the subtests is flakey as the
test sometimes hangs on the bots without any output.
