[M68k] Finish implementation of `MOVX` (move and extend) pseudo-instructions and fix related errors (#218938)
This patch adds remaining addressing modes to the "move and extend"
pseudo-instructions, and fixes a few errors and inconsistencies in the
logic that caused inefficient code generation.
- Remaining addressing modes were implemented to match non-pseudo `MOVE`
instructions.
- Names of the pseudos now correctly reflect the register classes they
operate on, e.g. `MOVZXd32r16` for XR16 -> DR32.
- Fixed an issue where `MOVZX` could be allocated to an address
register, which has no way to zero-extend the result. (There were even
some of these in the test `register-spills.ll`, emitted as illegal
instructions, but the test doesn't have instruction verification
enabled, so it wasn't caught.)
- Fixed some `extload` patterns where the register was unnecessarily
extended to 32 bits before being truncated to its final size, causing
redundant instructions to be omitted.
- Fixed `anyext` patterns lowering to `MOVZX` instead of `MOVX`, causing
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[SCEV] Remove unused classof(const SCEVUse *) overloads (NFC) (#226734)
isa/cast/dyn_cast on SCEVUse go through simplify_type or CastInfo.
classof(SCEVUse) is unused.
[LAA] Remove unused functions (NFC) (#226733)
Remove RuntimePointerChecking::empty and LoopAccessInfo::getNumLoads /
getNumStores, which have no callers, together with the NumLoads and
NumStores counters that were only read by the latter.
[LV] Skip low-trip count logic there is no scalar tail. (#225633)
https://github.com/llvm/llvm-project/pull/195823 added logic consider
vectorization of low trip count loops if there was no or a single
iteration remaining.
This causes loops to be vectorized with a VF where no scalar tail
remains, even if it is required for legality (loop with multiple
countable exits require scalar epilogue to pick the exit).
For now, limit to cases where there's a scalar iteration remaining.
PR: https://github.com/llvm/llvm-project/pull/225633
[VPlan] Take wide induction wrap flags from the increment of the phi. (#226726)
The binary operator of an integer InductionDescriptor is the incoming
value from the latch, which is not required to have the phi as operand.
E.g. for
%x = add i32 %iv, 5
%iv.next = add nuw nsw i32 %x, 1
the flags only apply to %x + 1, while the induction step is 6, and %iv +
6 may wrap even though %iv.next does not. Determine the wrap flags from
the increment of the header phi instead, and only if it adds to or
subtracts from the phi directly.
[LLVM][Docs] Define IR in the lexicon (#221388)
Define IR in the LLVM lexicon using terminology from the LLVM Language
Reference Manual, including its SSA-based structure and three equivalent
representations.
Fixes #139867
AI Usage: ChatGPT
FastISel: Assert the emitted instruction defines the result
The fallback path copied the result out of implicit_defs()[0], assuming
the first implicit physical register def is the result. That is an X86
assumption about MUL/IMUL, and it is unreachable for all but
fastEmitInst_r: FastISelEmitter skips any instruction whose first
operand is not an output register, so every opcode reaching these
helpers from generated code has an explicit def.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
ARM: Remove cached TargetABI from ARMBaseTargetMachine (#226482)
This cannot account for the "target-abi" module flag, so
let the uses query that. ARMElfTargetObjectFile was the one user of
this value, so this failed to respect the module flag.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Mips: Properly account for target-abi in subtarget construction
Store the used ABI from the target-abi module flag and add it to the
subtarget map key, so the module flag is properly respected.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
[libc++][pstl] Add more benchmarks of the parallel algorithms (#225908)
This PR adds benchmarks of these 3 parallel algorithms:
- `std::find(policy, ...)`
- `std::sort(policy, ...)`
- `std::transform_reduce(policy, ...)`
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
[AArch64] Reorganise perfect shuffle generation. NFC (#224526)
This adds a generatePerfectShuffle implementation for parsing through
the perfect shuffle tables, generating a list of ShuffleEntry's that
represent the sequence of shuffles that need to be performed. This is
intended to be a NFC as-is, allowing it to be reused in global isel and
extended in the future to handle shuffles that are not part of the
shuffle table. The number of instructions generated can also be used for
costing shuffles, as we do for immediate generation.
[LV] Add tests for wide induction wrap flags (NFC). (#226715)
Add tests for:
* inductions where the lane offsets may signed-overflow, even if the
scalar induction values do not,
* inductions whose increment does not directly update the phi, where the
increment's wrap flags do not apply to the induction,
* narrow inductions where the VF may exceed the signed maximum of the
induction type.
[CostModel][X86] arith-fp.ll - test AVX512DQ instead of AVX512BW (#226519)
AVX512DQ has instructions relevant to fp arithmetic (vXi64 fp2int in particular)
[WebKit Checkers] Add built-in recognition for standard view types (#226350)
libc++ doesn't fully annotate `[[clang::lifetimebound]]` for all view
types. This results in false negatives in borrow checking.
Ultimately we need to fix this in libc++, but for now we can work around
the most common / most important false negatives. For example, borrow
checking can now check
for (auto& x : vector | std::views::reverse) { ... }
Assisted-by: Claude
[libc++] Add static_assert diagnostics for LWG3133 named requirements (#212360)
Add a static_assert to both std::complex<T> and std::valarray<T>
requiring that T be a cv-unqualified object type that satisfies the
Cpp17DefaultConstructible, Cpp17CopyConstructible, Cpp17CopyAssignable,
and Cpp17Destructible named requirements, per the revised wording in
[numeric.requirements]. This mirrors the existing pattern already used
by std::optional<T>.
Non-_v (class-style) trait forms are used throughout so that the
assertion is well-formed even when <complex>/<valarray> are included in
C++03/11/14 mode.
Test coverage:
- A .verify.cpp for complex<T> and one for valarray<T>, each covering
six failure modes: cv-qualified types, and one type violating each of
the four named requirements individually.
Follows-up e062a29cf865bb7cadea6cb605c9f3515e5b883f.
[Transforms] Remove unused functions (NFC) (#226655)
createAnyOfReduction:
The last caller was removed on January 18, 2026 in commit
ae1bd068db293c494c4c6314da3b9d138706460d.
canHaveUnrollRemainder:
The last caller, in an assert, was removed on May 1, 2026 in commit
316f0d3bfeaf7eee7b6d4ae60d357a8216ec5264.
Assisted-by: Antigravity
[VPlan] Mark default value or ExtractLastActive as only first lane used. (#226153)
The default value (operand 0) of ExtractLastActive is the scalar value
of @llvm.experimental.vector.extract.last.active. Only the first lane is
used, mark accordingly.
PR: https://github.com/llvm/llvm-project/pull/226153
[lld][LoongArch] Prevent relaxation oscillation for PCHi20 and CALL
Relaxation of pcalau12i+addi (relaxPCHi20Lo12, isInt<22>) and
call36/call30 (relaxMediumCall, isInt<28>) can oscillate: shrinking
one section moves a symbol, which flips isInt<N> for other sites and
changes bytesDropped again. In large programs (e.g. Rust) the PC of
a site can stabilize while Dest jitter near the range limit, so
remove keeps alternating between 0 and 4 and relaxOnce never settles.
Follow the same approach as RISCV::relaxCall: after a few passes, do
not allow remove to increase beyond the previous pass's value
(cur - delta). Pass that cap as prevRemove into the two helpers;
range checks may still clear remove (0) when the target goes out of
range.
No reduced in-tree stress test: the failure is layout- and
input-order-sensitive and was validated against a fixed response-file
reproduction in the bug issue.
[CodeGen] Keep wave-profiled spill frequencies positive
SpillPlacement expects positive block weights, but a valid wave profile can
record zero executions for a CFG-reachable block. Giving such a block zero
spill cost can make the allocator choose a very different placement.
Clamp every accepted wave-derived frequency to at least one, as we already
do for nonzero counts that round down to zero. Unmeasured or rejected blocks
still use their existing MBFI frequency. Add a focused MIR test for a valid
zero-wave record.
This pattern arose in a profiled Composable Kernel convolution case. With
the separate spill correctness fixes and partial spilling enabled, the
zero-cost policy failed two CPU-reference checks; the positive floor passed
both. The test checks the cost directly; the application result was checked
separately on gfx950.
[Clang][OpenMP] Optimize `collapse` IV bit-width precision expression (#225612)
`collapse` used to build both a 32-bit and a 64-bit trip-count, then
keep one.
This patch does the same in `checkOpenMPLoop`:
If we know 32-bit is enough, build only 32-bit.
Else build 64-bit first.
Build 32-bit only when the product is a compile-time constant and fits.
Origin: `flatten` already builds only the width it keeps.
[CIR][CUDA] Read fat binary in CIRGen and store its bytes on the module (#225971)
Two problems with the current implementation of GPU CIR:
1. `LoweringPrepare` read the fat binary from disk, via
`astCtx->getSourceManager().getFileManager().getVirtualFileSystem()`. A
transform pass should not do I/O, and this is one of the `ASTContext`
dependencies that keeps the post-CIRGen pipeline from being IR-to-IR.
Some of the related discussion on this has been done
[here](https://discourse.llvm.org/t/rfc-clangir-making-cir-pipeline-boundaries-first-class-driver-artifacts/90998)
and PR: #219048
2. `#cir.cu.binary_handle` stored the *file path*. That's a build input,
not a
property of the program: it bakes one machine's directory layout into a
`.cir`.
The PR removes the file path and adds an attribute
CIRGen now reads the file in and records the contents
as `#cir.cu.device_binary`, a `StringAttr` of raw bytes. The
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[NFC][SLP][AMDGPU] Precommit a cross-block fmul fadd contraction test (#226609)
Two contract fmuls feed contract fadds in different successors. AMDGPU
sinks such an fmul into the block of its user and fuses the pair, so the
scalar form is one fma per path. Record the current behaviour, the pair
is kept scalar when the fmul is operand 0 of the fadd and paired when it
is operand 1.
[SSAF] Close unsafe-buffer reachability over override families
An unsafe pointer reaching one override's parameter is equally unsafe in every
sibling and base override of that method, because the call site picks the
target dynamically. Without closing over the families, reachability depended
on which override the extractor happened to see the flow through, so a fix
suggested for the base could be contradicted by a derived override.
- Mirroring is level-preserving: families relate slot entities, so a reachable
EPL propagates only to the same pointer level on its family members.
- Mirroring happens inside the pointer-flow search, so flows out of a mirrored
EPL are followed too.
- Type-constrained slots are never mirrored onto, so C3 still holds.
§4 of rdar://179151603
Assisted-By: claude
[SSAF] Serialize virtual method summaries and families
Per-TU summaries and whole-program results cross process boundaries, and the
JSON layer refuses to write a summary kind it has no format for. Register both
sides so --ssaf-extract-summaries=VirtualMethod becomes usable and the family
result survives a round trip.
Deserialization tolerates a missing override list, since a root virtual method
legitimately has none.
§3 of rdar://179151603
