[Hexagon] Prevent invalid packets with HLX loads and stores (#241439)
The HLX load and store pseudos are expanded after packetization into a
memory access and a register copy in the same packet. Make the
packetizer account for this:
- A store pseudo packetized with a later definition of the stored
register makes the copy and the definition both write the register. A
load pseudo packetized with an earlier reader of the loaded register
makes the reader see the temporary loaded value. Reject both pairings.
- The expansion takes two packet slots, so adding a constant-extended
instruction to a packet that holds a pseudo and one more instruction
exceeds the four-word packet limit. Reject this case in
shouldAddToPacket, which the global scheduler also uses.
- On V65 and later, a load and a possibly aliasing store may share a
:mem_noshuf packet only for non-vector accesses, but only HVX accesses
were treated as vector. Treat HLX accesses like HVX accesses.
Co-authored-by: Ikhlas Ajbar <iajbar at qti.qualcomm.com>
[3 lines not shown]
[Hexagon] Fix HLX copy, masked load/store and zext-i1 select lowering (#241442)
Fix several issues that made HLX vector code crash or generate worse
code than HVX:
- copyPhysReg did not handle copies between HLX vector registers or
register pairs, and the LX_lo/LX_hi pseudos were not expanded after
register allocation. Lower the copies to LX_assign/LX_assign_w and
expand LX_lo/LX_hi to a copy of the corresponding sub-register, as is
done for V6_lo/V6_hi.
- isLegalMaskedLoad/isLegalMaskedStore only accepted HVX types, so HLX
masked loads and stores were scalarized before instruction selection,
which then crashed. Report them as legal for HLX vector types too.
- ppHoistZextI1 runs after legalization, so a select it creates for an
HLX vector type is never custom-lowered and fails to select. Skip the
transformation for HLX vector types.
- Teach HexagonBitSimplify's getSubregMask and getFinalVRegClass about
the HLX register pair class, as is done for HVX pairs, so copies of HLX
pair halves are replaced with direct sub-register uses.
[14 lines not shown]
[libc] Use new Docker image with qemu-system-arm (#241386)
This will be used to run baremetal Arm tests
---------
Co-authored-by: Aiden Grossman <aidengrossman at google.com>
[lldb] Let language plugins extend the version string (#241057)
LLDB's version string ends with the revisions of the clang and LLVM it
embeds, which lldb_private::GetVersion() reads directly from clangBasic.
This patch moves the Clang and LLVM revisions into a new
Language::GetVersionInfo() method, and adds
Language::GetVersionWithLanguageInfo(), which appends each language
plugin's information to GetVersion(). This removes lldbVersion's
dependency on clangBasic.
The output of the version command doesn't change, and neither does
SBDebugger::GetVersionString() once LLDB is initialized.
Both lldb-server and assertion messages now print the bare GetVersion().
Assisted-by: Claude
[Hexagon] Add llvm-mc -mhlx, HLX register aliases, 64-bit reg check (#241438)
- Add a -mhlx option to llvm-mc that enables the HLX feature.
- Accept "Ld = Lu" and "Ldd = Luu" as aliases of the HLX register
transfers, and "Ld = #0" and "Ldd = #0" as aliases that zero an HLX
register or register pair.
- An HLX instruction that reads a 64-bit scalar register cannot share a
packet with another HLX instruction that uses a scalar register or an
immediate; HLX loads and stores are exempt. The packetizer already
enforces this for generated code. Diagnose it in the MC checker too.
Co-authored-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
Co-authored-by: Rishabh Bali <rbali at qti.qualcomm.com>
Assisted by AI
Co-authored-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
Co-authored-by: Rishabh Bali <rbali at qti.qualcomm.com>
Collect IPO amendable functions in initializeInformationCache
Instead of caching the answer lazily in isFunctionIPOAmendable, compute
whether a function has an exact definition or is inlineable once, when its
information is initialized (review feedback).
Assisted-by: Claude Opus 5.5
RuntimeLibcalls: Add missing attributes to libm libcalls
Add the function and memory attributes inferLibFuncAttributes would
give the scalar libm functions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
RuntimeLibcalls: Add missing attributes to memory and allocator libcalls
Add the attributes inferLibFuncAttributes would give these functions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[MLIR][XeVM] Use findProgramByName to locate tools on PATH (#240622)
SerializeGPUModuleBase::findTool looked up tools on PATH via
llvm::sys::Process::FindInEnvPath, which checks for the exact file name.
On Windows the tool is named e.g. `ocloc.exe`, so the lookup always
failed with "Couldn't find the `ocloc` binary" even when the tool was on
PATH.
Use llvm::sys::findProgramByName instead, which handles executable
extensions on Windows and behaves the same on POSIX.
[ValueTracking] Teach LLVM that rem_euclid is always positive (#236900)
Teach ValueTracking to infer that scalar Euclidean remainder expressions
R + (R < 0 ? A : 0) are non-negative, where R = srem X, Y and A is
either Y (when known non-negative) or abs(Y). Enables folding
comparisons of the result against zero.
Fixes #224449
[ConstraintElim] Split signed min/max across their operands when checking a compare
The existing constraint systems only record the bounds that hold for both
operands of a min/max (smax(a, b) >= a and >= b, smin(a, b) <= a and <= b). The
other direction is a disjunction, which cannot be recorded as a fact. When a
compare of signed decompositions involves a min/max result, split it into its
operands: the decomposition is monotonic in that result, so it is the max or min
of its values on each side, and the relation holds for all or for either side
respectively.
https://alive2.llvm.org/ce/z/zsGkJ-
[ConstraintElim] Prove sadd/ssub.with.overflow cannot overflow from the exact sum
Decompose the operands and show that the sum lies in the range of the type. This
handles patterns like A + (B - A), as well as sums involving signed min/max
results, which are split across their respective operands using monotonicity
(for example start + smax(end - start - 1, 0) <= end).
https://alive2.llvm.org/ce/z/ze8LCk
[SLP][NFC] Pre-commit tests for compare chains feeding heterogeneous sinks (#240778)
Add tests covering compares that feed a uniform single-use chain whose
sinks are heterogeneous. vectorizeCmpInsts() roots the SLP tree at the
compares, so today only the compares are vectorized and the chain they
feed is left scalar, with one extract per lane.
No functional change.
Co-authored-by: Balakrishna Bandlapalli <bbandlap at gmail.com>
[SLP]Fix bit pack lane cost for interchangeable lanes
A lane like add %x, 0 in the shl node is an interchangeable shl, so
check the op it matches instead of its own opcode.
Fixes #241471
Pull-request: https://github.com/llvm/llvm-project/pull/241485
[X86][ACEV1] Address review comments
- Drop the AMX_TILE dependency; under acev1 enable only the AMX
instructions that ACE v1 actually shares.
- Namespace the ACE-invented intrinsics under llvm.x86.acev1.* and leave
the shared AMX-AVX512 ones in the flat llvm.x86.* namespace.
- Sync the public intrinsic and builtin names with GCC, and add the
helper macros from the ACE v1 spec.
- Tighten Sema checking of the outer-product group bits, and add driver,
preprocessor and feature-error test coverage.
- Spell BSR0 literally in the AsmStrings with Defs/Uses instead of
carrying it as a custom operand, which removes the bespoke handling
from X86AsmParser and both instruction printers.
- Drop the unused BSR register class; like TMMCFG, BSR0 needs only its
X86Reg definition and the getReservedRegs entry.
- Adopt the operand-type record naming convention, 't' for a TILE and
'e' for a GR32 index, on both the instructions and their pseudos,
retiring the ad-hoc _REG suffix.
- Use WriteSystem rather than WriteVecLogic for the tile outer products
[3 lines not shown]
[lldb][test] Write the Shell tests' lit-lldb-init files from lit (#236887)
The %lldb substitutions source lit-lldb-init-quiet from the test
execution root, and CMake wrote that file and lit-lldb-init into the
build directory. Write them from the lit config instead, when the
substitutions are set up. The test execution root is where lit already
writes test outputs, so this works for any build system that can run lit
with a writable execution root, including ones that cannot add generated
files to it ahead of time, like Bazel.
[X86] combineBasicSADPattern - incorrect vector element count (#240005)
Ensure we determine the vector element count from the reduction ROOT,
not the first vector in the chain - to correctly handle cases where the
ROOT is split during reduction
Fixes #239204
[mlir][vector] Reject `vector.mask` on Xfer ops that have a mask operand (#240797)
`vector.transfer_{read,write}` already have a _mask operand_, so
wrapping them in `vector.mask` gives two ways to express the same thing
and risks double masking. This PR makes `vector.mask` reject a masked
Xfer op that already has a mask operand.
Changes:
- Add a check to `MaskOp::verify` that fails if the op has a mask
operand.
- Add two _negative_ tests for `vector.transfer_{read,write}`.
Part of #239511.
RFC:
https://discourse.llvm.org/t/rfc-unify-masking-in-the-vector-dialect/92675
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
[GitHub][libc] Bump LLVM to 24 in container image (#241368)
Otherwise we get errors about having an out of date clang (e.g., CMake
error in libc-fullbuild on AMDGPU).
