[Clang] Fix mangling of parenthesized aggregate initialization (#232357)
Clang was not correctly including the arguments used to initialize a
struct with parentheses in the generated symbol name. This could give
different template expressions the same symbol name, and some cast forms
could crash while being mangled.
Used the arguments written in the source when generating the symbol
name, including for C-style casts and static_cast.
Followed the Itanium ABI section 5.1.6 for mangling.
The generated names were compared with GCC 15.2 and GCC trunk:
https://godbolt.org/z/xWPcnr3K6
Fixes #231953
[mlir][Mem2Reg] Standardise memory slot interface implementation file names (nfc) (#232637)
Renames the files implementing the interfaces defined in
`MemorySlotInterfaces.td` to consistently use
`MemorySlotInterfacesImpl.{h,cpp}`.
The previous names (e.g. `MemRefMemorySlot.h` and
`MemorySlotOpInterfaceImpl.h`) were inconsistent with the TableGen
definition, particularly its use of the plural `Interfaces`.
Also:
* Adds and updates comments to clarify that the implementations in
`mlir/lib/Dialect/MemRef/Transforms/` use external models, unlike
those in `mlir/lib/Dialect/MemRef/IR/`.
* Moves all Mem2Reg tests to `mlir/test/Transforms/Mem2Reg/`. As
demonstrated by #217793, these tests depend on multiple dialects,
making `mlir/test/Transforms/` a more appropriate location than
`mlir/test/Dialect/`.
[AMDGPU][NFC] Explicitly narrow conversions in hazard and waitcnt passes (#215197)
Fixes 53 instances of MSVC warning C4244 and 11 of C4267 ("possible loss of data") across 6 files in llvm/lib/Target/AMDGPU.
Assisted-by: Claude <noreply at anthropic.com>
[RISCV] Ignore debug uses when folding offsets into a global address (#231718)
Check for non-debug uses instead. The fold changes the value of the
address register, so make its debug users undef first, and make those of
the erased offset instructions undef too.
Assisted-by: Claude
[mlir][vector] Keep a write mask that does not cover the whole vector (#228668)
`isMaskTriviallyFoldable` decides whether a transfer mask is all-true
and can be left out. For constant sizes and indices it checked that the
masked part stays in bounds, but not that the mask covers the whole
vector.
Since #174810 the write mask size is `dim - index`. With a non-zero
constant index that can be smaller than the vector, and the mask was
still dropped.
For example, vectorizing this with `vector_sizes [4]`:
```mlir
%r = tensor.insert_slice %src into %dest[6] [%size] [1]
: tensor<?xi32> into tensor<8xi32>
```
gave an unmasked 4-element `vector.transfer_write` at index 6, marked
`in_bounds`. It is now masked with size 2.
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[AArch64] Make options per-context (#232584)
Follow-up to #232170: drop `perContext = false` from AArch64Options and
AArch64MCOptions. Their readers use MCTargetOptions::LibraryOptions; the
IR passes use their function's or module's LLVMContext.
LLM-aided
[profcheck][CrossDSOCFI] Label synthesized __cfi_check profile as explicitly unknown (#232634)
The frontend writes a weak stub for `__cfi_check`. The `CrossDSOCFI`
pass deletes the body of this stub. Then the pass writes a new body. The
new body has a `switch` on the CFI type ID. Each case of the `switch`
calls `llvm.type.test`.
Because this function synthesized by compiler so no profile data for
this function can exist. Before this change, the pass did not attach
profile metadata to the function. It also did not attach profile
metadata to the `switch`. Thus, the profile verifier failed with this
error: "function entry count missing".
This PR does these changes:
1. It sets the entry count of `__cfi_check` to "explicitly unknown". It
uses `setExplicitlyUnknownFunctionEntryCount` for this step.
2. It sets the branch weights of the `switch` to "explicitly unknown".
It uses `setExplicitlyUnknownBranchWeights` for this step.
Co-authored-by: Jin Huang <jingold at google.com>
[OpenMP] Fix SPMDszaton pass reordering strict fences (#232481)
Summary:
The SPMDization pass works by moving the explitic single threaded then
fork model into a single parallel region where the previously
single-threaded code is executed under a masked thread which shares a
barrier. In some cases, this was moving a system-scope memory fence past
where it was and broke the happens-before relationship it implied.
The pass already handled things like stores, just extend this handling
to fences of sufficiently strict scope.
Fixes https://amd-hub.atlassian.net/browse/LCOMPILER-2940
[libc][math] Optimize exp2 and refactor shared double-precision exp utilities. (#231041)
Refactor double-precision `exp2` to improve latency, throughput, and
code
sharing across `exp`, `exp2`, `exp10`, and `pow`, while adding support
for
`LIBC_MATH_HAS_SMALL_TABLES` and `LIBC_MATH_HAS_SKIP_ACCURATE_PASS`.
Algorithm & implementation overview:
- Fast path (`exp2_double_eval.h`, `exp_utils.h`):
- Single-step range reduction `x = k * 2^-N + dx` (`N = 7` by default,
or
`N = 4` when `LIBC_MATH_HAS_SMALL_TABLES` is enabled) with
`hi = k >> N`, `idx = k & (2^N - 1)`, and `u = dx * log(2)`.
- Without FMA, use fixed-point splitting (`SPLIT_18` on `dx`,
`LOG_2_HI_12`
on `log(2)`, and `SPLIT_22` on `EXP2_MID[idx]`) so `m_hi * (1 + u_hi)`
is
exact in `double` without needing Veltkamp splitting or `DoubleDouble`
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[AMDGPU] Fix assembler predicates for GFX13 DS barrier arrive atomics. NFCI. (#231977)
DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 and DS_ATOMIC_BARRIER_ARRIVE_RTN_B64
were defined with DS_Real_gfx12_gfx13 inside
"let AssemblerPredicate = HasLdsBarrierArriveAtomic". The outer let
overrode the isGFX12Only/isGFX13Only predicates set by the multiclass, so
the asm matcher could not tell the _gfx12 and _gfx13 reals apart and
always picked the _gfx12 one.
The let was redundant anyway, since the reals already inherit
HasLdsBarrierArriveAtomic from the pseudos via OtherPredicates. Remove
it.
This is NFC for all current processors because no GFX13 processor has
FeatureLdsBarrierArriveAtomic, and the encodings are the same in any
case.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[SLP] Handle REVEC when costing expanded compress mask
With REVEC the scalars are vectors. The masked-load-compress shuffle that is
emitted uses the compress mask expanded to the elements of those vectors
(transformScalarShuffleIndiciesToVector), but the cost was computed with the
unexpanded per-vector mask, so a shuffle such as <24 x i8> -> <16 x i8> was
costed as a <2 x i8> shuffle. This made the compress sequence looked cheaper
than it is.
Assisted-By: Claude Sonnet 5.5
[flang][Evaluate] Fold type-only inquiries of conditional arguments (#227466)
Fold a reference to an intrinsic inquiry function whose result depends
only on the declared type, kind type parameters, or rank of an argument
when that argument is a conditional argument with a non-constant
condition:
integer, parameter :: k = kind((flag ? a : b))
Every consequent-arg of a conditional argument has the same declared
type and kind type parameters (F2023 C1538) and the same rank unless
all of them are assumed-rank (C1539), so such an inquiry has the same
value whichever consequent-arg is chosen at run time.
FoldOperation(FunctionRef) folds the reference by substituting the
first consequent-arg for the conditional argument in a copy of the
reference and keeps the result when it is a constant.
Accepting such a reference in a constant expression, as in the
PARAMETER above, is an extension. F2023 10.1.12 item (6) admits a
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[Clang][Sema] Fix lambdas mistakenly inheriting InImmediateFunctionContext (#232458)
This fixes a regression since Clang 21.
As per [expr.const]/p14.1, only the innermost enclosing function
parameter scope matters for determining whether a function or lambda is
in an immediate function context. It does not matter whether the parent
is an immediate function or not.
However, synthesized functions such as Lambda conversion operators and
constructors do need to inherit immediate function context from the
parent. Fix this by explicitly exempting the lambda call operator.
Fixes #183415.
Fixes #169139.
[TableGen] Declare `MCRegisterClassStorageType` as `inline constexpr` (NFC) (#232403)
This reduces size of binaries generated by MSVC on Windows. After
#207168 was merged some of the binaries that include AMDGPU back-end
grew by around 15% on Windows. Declaring the storage class as
`constexpr` allows MSVC to correctly optimize the code brining the
binary size back to its original size.
This is an alternative to #232010 that was reverted due to not being
compatible with MSVC 2019.
[AArch64] Ignore debug uses when splitting immediates (#231717)
and make the debug users of the erased MOV and SUBREG_TO_REG undef.
Assisted-by: Claude
[clang][ThreadSafety] Do not read a C field's address as a pointer to member (#231604)
The analysis reads `&Class::mu` in an attribute as a wildcard, matching
`mu` of any object, and tested for it with `isCXXInstanceMember()`. That
test is true of a C field too -- probably unexpectedly given the CXX in
the name -- so in:
struct Dev {
struct Mutex mu;
int a GUARDED_BY(&mu);
};
`a` was guarded by the `mu` of any object: locking `other->mu` allowed
writing `dev->a`. C has no pointer-to-member syntax, so there `&mu`
names the field of the same object, as `mu` does. The wildcard is kept
for C++ only, as seems likely to have been intended (despite the test
from #191187 being changed here). This ensures the struct annotation now
has the same meaning on C and C++ parsing.
ProcessImplicitDefs: Mark kept physreg IMPLICIT_DEFs dead
A physreg IMPLICIT_DEF has undef set on all of its readers in the block,
but is only erased if the block has no successors. Otherwise it was left
live even when no successor has the register live-in. Mark it dead in
that case.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
