LLVM/project 797ead5llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.fp8.f16.ll code-size-estimate-gfx1250.ll, llvm/test/MC/AMDGPU gfx13_asm_vop1_dpp16.s gfx1250_asm_vop3-fake16.s

[AMDGPU] Add gfx13 support for v_cvt_pk_{fp8,bf8}_f16 (#211263)

GFX13 supports VOP1 and VOP3 forms of these instructions; GFX1250 keeps
its VOP3-only encoding.

Co-authored-by: Guo Chen <guochen2 at amd.com>
DeltaFile
+272-25llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
+70-28llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
+89-0llvm/test/MC/AMDGPU/gfx13_asm_vop1_dpp16.s
+28-36llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
+18-24llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s
+18-24llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
+495-1379 files not shown
+638-16515 files

LLVM/project 73f2489llvm/lib/Bitcode/Writer BitcodeWriter.cpp

Test
DeltaFile
+1-0llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+1-01 files

LLVM/project b476a59llvm/lib/Transforms/Utils FunctionComparator.cpp, llvm/test/Transforms/MergeFunc atomic-elementwise.ll atomic-load-elementwise.ll

Support atomicrmw
DeltaFile
+42-0llvm/test/Transforms/MergeFunc/atomic-elementwise.ll
+0-22llvm/test/Transforms/MergeFunc/atomic-load-elementwise.ll
+3-0llvm/lib/Transforms/Utils/FunctionComparator.cpp
+45-223 files

LLVM/project 05a2d2c

Test
DeltaFile
+0-00 files

LLVM/project 83530celldb/source/Plugins/Process/Windows/Common ProcessDebugger.cpp NativeProcessWindows.cpp, lldb/test/API/attach TestWindowsAttachBreakpoint.py main.c

[lldb][Windows] ignore loader breakpoints in system modules (#208233)

Currently, when debugging a program with `lldb-dap` on Windows and using
the `integratedTerminal` option, lldb-dap immediatly stops with an
`0x80000003` Exception. This is because `ntdll` executes an `int3`
breakpoint during process initialization when a debugger is attached.

This patch makes `lldb` and `lldb-server` skip the first `int3` after
launch when it originates from a system module (the loader's debugger
notification). Only that first loader breakpoint is skipped. Any later
int3, including `__debugbreak()`, `__builtin_debugtrap()` in the
debuggee's own code, still stops the debugger.

Fixes https://github.com/llvm/llvm-project/issues/198763
DeltaFile
+160-0lldb/test/API/attach/TestWindowsAttachBreakpoint.py
+65-0lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
+15-43lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+27-3lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
+5-0lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
+4-0lldb/test/API/attach/main.c
+276-464 files not shown
+283-4710 files

LLVM/project 58cebeeclang/lib/CodeGen/TargetBuiltins RISCV.cpp, clang/test/CodeGen/RISCV rvp-intrinsics.c

[RISCV][P-ext] Support Packed "Q-format" Multiplication (#211236)
DeltaFile
+136-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+60-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+51-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+44-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+18-1clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+18-0llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+327-24 files not shown
+367-210 files

LLVM/project 55ef878llvm/docs AMDGPUUsage.rst

Comments
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

LLVM/project 2d01da5llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp

[AMDGPU] Add synthetic apertures and use them for barriers

Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
DeltaFile
+72-87llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+44-5llvm/docs/AMDGPUUsage.rst
+21-23llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+18-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-0llvm/lib/Target/AMDGPU/SIDefines.h
+9-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+176-1324 files not shown
+186-13710 files

LLVM/project ff7e77bllvm/docs AMDGPUUsage.rst

Update docs
DeltaFile
+20-13llvm/docs/AMDGPUUsage.rst
+20-131 files

LLVM/project 8e7feb1llvm/lib/Target/AMDGPU SIDefines.h AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll

Comments
DeltaFile
+4-3llvm/lib/Target/AMDGPU/SIDefines.h
+1-3llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+9-106 files

LLVM/project 786c7cdlld/test/ELF/lto amdgpu.ll, llvm/lib/IR AutoUpgrade.cpp

Add DL auto-upgrade
DeltaFile
+19-11llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+4-0llvm/lib/IR/AutoUpgrade.cpp
+1-1lld/test/ELF/lto/amdgpu.ll
+24-123 files

LLVM/project 09ab7a3flang/include/flang/Evaluate tools.h, flang/lib/Evaluate tools.cpp

[flang][Lower] Admit opaque terms to real sum reassociation (#211316)

First part of generalisations requested in #207377.

The split-sum eligibility check rejected any RHS containing explicit
parentheses or subtraction, even though the Add flattener already
preserves every non-Add subtree as one opaque term.

Remove those blanket guards and their unused predicates. Document the
opaque-term invariant and extend the test to cover parenthesized
additions and subtractions, whole-RHS parentheses, and subtraction
terms.

I did not observe any benchmark result changes as a result of this
patch.

Assisted-by: Codex
DeltaFile
+184-21flang/test/Lower/split-sum-expression-tree-lowering.f90
+4-32flang/lib/Evaluate/tools.cpp
+0-6flang/include/flang/Evaluate/tools.h
+188-593 files

LLVM/project a2b42b1llvm/include/llvm/IR Attributes.h, llvm/lib/Analysis InlineCost.cpp

[IR] Reject inlining strictfp alwaysinline callee into non-strictfp caller (#210701)

Commit af0c933eda31 added a verifier check requiring every strictfp call
site to reside in a strictfp function.
It caused verify error `call site marked strictfp without caller
function marked strictfp` since AlwaysInliner force-inlines strictfp
callees into non-strictfp callers, bypassing checkStrictFP.

47b3b76825dc explictly not implemented inlining strictfp function into
non-strictfp function. But the restriction was lost in 8eb6757564cc.
8eb6757564cc was only NFC for the normal inliner pass. It regressed
AlwaysInliner path which bypasses checkStrictFP.

This PR restores the restriction.

---------

Co-authored-by: Jinsong Ji <jinsong.ji at intel.com>
Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
Co-authored-by: Nikita Popov <github at npopov.com>
DeltaFile
+29-0llvm/test/Transforms/Inline/always-inline-strictfp.ll
+5-0llvm/include/llvm/IR/Attributes.h
+5-0llvm/lib/IR/Attributes.cpp
+3-0llvm/lib/Analysis/InlineCost.cpp
+42-04 files

LLVM/project 4138dc4mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[MLIR][OpenMP] Preserve debug location in OpenMPIRBuilder calls. (#211254)

Many `OpenMPIRBuilder` entry points take an
`OpenMPIRBuilder::LocationDescription`. It has two relevant
constructors:

`LocationDescription(const IRBuilderBase &IRB)` // captures IP and debug
loc
`LocationDescription(const InsertPointTy &IP)` // captures IP only; DL
is empty

The OpenMP MLIR-to-LLVM-IR translation constructs the location from
`builder` in almost all places (~45 call sites), which selects the first
constructor and propagates both the insertion point and the current
debug location. A few call sites instead passed `builder.saveIP()`,
which selects the second constructor and silently drops the debug
location.

Change the 9 offending call sites to pass `builder` instead of
`builder.saveIP()`, so the debug location is preserved.
DeltaFile
+13-13mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+13-131 files

LLVM/project 9c5858ellvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp RISCVProcessors.td, llvm/test/Transforms/LoopUnroll/RISCV vector.ll

[RISCV] Add TuneNoDefaultUnroll to generic CPUs (#135318)

Almost all CPUs have added this and experiments have shown
considerable gains.

And, we set a lower runtime unrolling count 4 for in-order models
to avoid potential regressions.

Fixes #134272.
DeltaFile
+740-540llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+4-0llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+2-1llvm/lib/Target/RISCV/RISCVProcessors.td
+746-5413 files

LLVM/project 5bf9d61llvm/test/CodeGen/AArch64 sve-fixed-vector-lrint.ll sve-lrint.ll

[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
DeltaFile
+490-1,132llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+319-1,280llvm/test/CodeGen/AArch64/sve-lrint.ll
+319-1,280llvm/test/CodeGen/AArch64/sve-llrint.ll
+270-586llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+113-333llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
+87-269llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
+1,598-4,8803 files not shown
+1,906-4,8979 files

LLVM/project 1ee1c0ellvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86/apx ccmp-cse.ll

[X86][CCMP] Reorder Comparison Trees to Facilitate CSE (#211476)

This patch ports AArch64's CMP CSE optimization #168064

Assisted-by: Claude Opus 4.8
DeltaFile
+123-0llvm/test/CodeGen/X86/apx/ccmp-cse.ll
+35-17llvm/lib/Target/X86/X86ISelLowering.cpp
+158-172 files

LLVM/project 27ec80fllvm/lib/Target/Hexagon HexagonISelLoweringHVX.cpp, llvm/test/CodeGen/Hexagon/autohvx hvx-half-store-no-spurious-vmem.ll

[Hexagon] Avoid spurious high vmem for contained sub-HVX stores (#204661)

When a sub-HVX store is widened into a masked HVX store, the unaligned
masked store lowering can split it into two vector stores: one at Base
and one at Base+HwLen. For stores whose original memory size fits within
the guaranteed alignment, the high half predicate is known to be all
false, so the Base+HwLen store is unnecessary.

Even an all-false predicated vmem can still probe the TLB. Emitting the
high store can therefore fault when Base+HwLen is on an unmapped page,
even though no bytes should be written there.

Preserve the original memory VT when widening sub-HVX stores, and use
that size during masked-store lowering to elide the empty high vmem.

Relevant links:
https://docs.qualcomm.com/doc/80-N2040-60/topic/conditional-execution.html#consuming-scalar-predicates
and
https://docs.qualcomm.com/doc/80-N2040-61/topic/memory.html#permissions

Co-authored-by: L-roro <rodriguez at roofline.ai>
DeltaFile
+44-0llvm/test/CodeGen/Hexagon/autohvx/hvx-half-store-no-spurious-vmem.ll
+17-3llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+61-32 files

LLVM/project 0e78045llvm/lib/Transforms/Scalar LowerMatrixIntrinsics.cpp, llvm/test/Transforms/LowerMatrixIntrinsics phi.ll

[Matrix] De-duplicate reshaped matrixes used as incoming values for phi. (#211210)

Phis can have multiple incoming entries for the same block. In that
case, all incoming values for the block must be the same.

Update visitPHI to avoid expanding the incoming matrix multiple times
for the some incoming block.

Fixes a verifier error for the newly added test case.

PR: https://github.com/llvm/llvm-project/pull/211210
DeltaFile
+34-0llvm/test/Transforms/LowerMatrixIntrinsics/phi.ll
+7-1llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
+41-12 files

LLVM/project 6975087llvm/docs GettingInvolved.md

[docs] Update BOLT Office Hours Zoom link
DeltaFile
+1-1llvm/docs/GettingInvolved.md
+1-11 files

LLVM/project d3fead5libcxx/test/benchmarks adjacent_view_begin.bench.cpp

[libc++] Remove some adjacent_view::begin() benchmarks (#210265)

Benchmarking a bunch of very similar values has rather little benefit,
since they behave essentially the same.
DeltaFile
+0-17libcxx/test/benchmarks/adjacent_view_begin.bench.cpp
+0-171 files

LLVM/project 64b593cclang/lib/ScalableStaticAnalysis/Core/WholeProgramAnalysis AnalysisDriver.cpp, clang/test/Analysis/Scalable/ssaf-analyzer analyzer.test

[clang][SSAF] Allow no Data for summary analysis (#211342)

Extractors might not always add summaries for all the TUs. If they don't
add any summaries to the TU result, then loading this summary for a
summary analysis would cause a failure.

This patch handles the situation gracefully by accepting such cases.

Split from: #209354

---------

Co-authored-by: Ziqing Luo <ziqing_luo at apple.com>
DeltaFile
+22-12clang/unittests/ScalableStaticAnalysis/WholeProgramAnalysis/AnalysisDriverTest.cpp
+7-21clang/lib/ScalableStaticAnalysis/Core/WholeProgramAnalysis/AnalysisDriver.cpp
+4-4clang/test/Analysis/Scalable/ssaf-analyzer/analyzer.test
+33-373 files

LLVM/project beca2e9llvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 add-to-sub-imm.ll

[AArch64] Prefer (sub x, -c) over (add x, c) if -c is cheaper. (#211020)

The negation of an immediate can be cheaper to materialise than the
original immediate, in which case a subtraction is preferable.
DeltaFile
+82-0llvm/test/CodeGen/AArch64/add-to-sub-imm.ll
+21-0llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+11-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+114-03 files

LLVM/project 14371a7llvm/lib/Target/AMDGPU SIInstrInfo.cpp

[AMDGPU] Simplify check for packed fp32/64 opsel bits. NFCI (#211374)

Call isLegalGFX12PlusPackedMathFP32or64BitOperand directly instead
of the whole isLegalOperand.
DeltaFile
+23-14llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+23-141 files

LLVM/project 355dac7llvm/lib/Target/AMDGPU GCNIterativeScheduler.cpp GCNIterativeScheduler.h, llvm/test/CodeGen/AMDGPU iterative-ilp-restore-undef.mir

[AMDGPU] Preserve liveness flags in ILP scheduler (#211190)

During DAG construction, liveness flags such as `undef` are removed from
the instructions. When the scheduler succeeds, the flags are recomputed
and restored.

However, so far, if the scheduler failed to meet the occupancy target,
it would not restore the liveness flags, leading to verification
failure/assertions later in the pipeline.

This change restores the liveness flags in cases where no schedule
meeting the occupancy target could be found.

---------

Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
DeltaFile
+49-0llvm/test/CodeGen/AMDGPU/iterative-ilp-restore-undef.mir
+24-12llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
+5-0llvm/lib/Target/AMDGPU/GCNIterativeScheduler.h
+78-123 files

LLVM/project 3b7447elibcxx/src iostream.cpp, libcxx/test/libcxx/input.output/iostream.objects sync_with_stdio.buffer_type.pass.cpp

[libc++] Optimize standard streams with sync_with_stdio(false) (#209161)

This updates the standard streams so that the buffers are replaced with
`basic_filebuf`s.

Fixes #21566

---------

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
DeltaFile
+5,000-0libcxx/test/std/input.output/iostream.objects/many-ints.dat
+109-0libcxx/test/std/input.output/iostream.objects/sync_with_stdio.state.pass.cpp
+84-18libcxx/src/iostream.cpp
+72-0libcxx/test/libcxx/input.output/iostream.objects/sync_with_stdio.buffer_type.pass.cpp
+58-0libcxx/test/std/input.output/iostream.objects/wide.stream.objects/wcin.readmany.sh.cpp
+56-0libcxx/test/std/input.output/iostream.objects/narrow.stream.objects/cin.readmany.sh.cpp
+5,379-1821 files not shown
+5,740-3627 files

LLVM/project f59bda2clang/docs UsersManual.md, clang/test/CIR/CodeGen loop-cond-var-cleanup.cpp

Merge main into users/mariusz-sikora-at-amd/gfx13/upstream-v-cvt-f8-f16
DeltaFile
+0-7,750flang/lib/Lower/ConvertExpr.cpp
+2,162-2,303clang/docs/UsersManual.md
+554-688llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+1,095-3mlir/test/CAPI/rewrite.c
+1,036-0clang/test/CIR/CodeGen/loop-cond-var-cleanup.cpp
+370-370llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+5,217-11,1141,060 files not shown
+25,282-22,4711,066 files

LLVM/project b605aa6llvm/test/Transforms/LoopDistribute metadata.ll bounds-expansion-bug.ll

[LoopDistribute][NFC] Autogenerate checks for some tests (#211471)
DeltaFile
+141-12llvm/test/Transforms/LoopDistribute/metadata.ll
+108-10llvm/test/Transforms/LoopDistribute/bounds-expansion-bug.ll
+45-3llvm/test/Transforms/LoopDistribute/crash-in-memcheck-generation.ll
+41-6llvm/test/Transforms/LoopDistribute/uncomputable-backedge-taken-count.ll
+335-314 files

LLVM/project 4469fballvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir, llvm/test/CodeGen/RISCV/GlobalISel atomicrmw-max-min-umax-umin.ll

slightly nicer tablegen

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+9,398-9,218llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+6,993-6,921llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,803-5,808llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+3,842-3,722llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+2,196-5,244llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+41,300-30,9133,079 files not shown
+275,025-167,4103,085 files

LLVM/project 748387ellvm/test/Transforms/MergeFunc atomic-store-elementwise.ll

Add mergeFunc elementwise test.
DeltaFile
+22-0llvm/test/Transforms/MergeFunc/atomic-store-elementwise.ll
+22-01 files