[RISCV] Generate Xqcilsm LWMI/SWMI load/store multiple instructions (#171079)
This patch adds support for generating the Xqcilsm load/store multiple
instructions as a part of the RISCVLoadStoreOptimizer pass. For now we
only combine two load/store instructions into a load/store multiple.
Support for converting more loads/stores will be added in follow-up
patches. These instructions are only applicable for 32-bit loads/stores
with an alignment of 4-bytes.
[LoongArch] Add support for the ud macro instruction (#171583)
This patch adds support for the `ud ui5` macro instruction. The `ui5`
operand must be inthe range `0-31`. The macro expands to:
`amswap.w $rd, $r1, $rj`
where `ui5` specifies the register number used for `$rd` in the expanded
instruction, and `$rd` is the same as `$rj`.
Relevant binutils patch:
https://sourceware.org/pipermail/binutils/2025-December/146042.html
[RISCV] Add Xsfmm vlte and vste intrinsics to getTgtMemIntrinsics. (#171747)
Replace dyn_cast with cast. The dyn_cast can never fail now. Previously
it never succeeded.
[NFC] isOSGlibc: musl is not glibc. (#171734)
Previously, `isOSGlibc()` was returning true for musl triples as well.
This commit changes `isOSGlibc()` to return false for musl triples, and
updates all existing `isOSGlibc()` checks to call `isOSGlibc() ||
isMusl()`, in order to preserve existing behaviour.
[Tooling] Fix misleading progress report when files have multiple compile commands (#169640)
This patch fixes an issue in progress reporting where the processed item
counter could exceed the total item count, leading to confusing outputs
like [22/18].
Closes [#169168](https://github.com/llvm/llvm-project/issues/169168)
[RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)
This enables MachineVerifier and MachineIR printing support for these
operands.
[compiler-rt] follow-up to 166837, rename COMPILER_RT_FORCE_TEST_BUILTINS_DIR to COMPILER_RT_TEST_BUILTINS_DIR (#171741)
Co-authored-by: David Tenty <daltenty at ibm.com>
[RISC-V][MC] Fix tied operand register class mismatch in P-extension
I have a change to validate the operand classes emitted in the AsmParser
and that caused llvm/test/MC/RISCV/rv32p-valid.s to fail due to the rd_wb
register using a different register class from rd:
`PWADDA_H operand 1 register X6 is not a member of register class GPRPair`
This happens because tablegen's AsmMatcherEmitter emits code to literally
copy over the tied registers and does not feed them through the equivalent
of RISCVAsmParser::validateTargetOperandClass() which would allow adjusting
these operand classes.
Ideally we would handle this in tablegen (or at least add an error), but
the tied operand handling logic is rather complex and I don't understand
it yet. For now just update the rd register class to match rd_wb.
Pull Request: https://github.com/llvm/llvm-project/pull/171738
[TableGen] Replace reachable assertion with error in *ByHwMode
Having duplicate mode entries previously asserted (or silently replaced
the last value with a new one in release builds). Report an error with
a helpful message instead.
Pull Request: https://github.com/llvm/llvm-project/pull/171715
Add a _regexp-break-add and some more tests for the b alias. (#171236)
This commit leaves "b" aliased to the old _regexp-break for now. The two
variants are identical except that `_regexp-break` allows you to say:
`(lldb) b <unrecognized_input>
`
which gets translated to:
`break set <unrecognized_input>
`
So switching people to `_regexp-break-add` would be a surprising
behavior change. It would be wrong for `_regexp_break-add` have one
branch that call `break set`, so to avoid surprise, I'll add the command
and let people who are playing with `break add` instead of `break set`
can set the alias to the new one by hand for now.
[AArch64] Restrict TBI to ignore top 4 bits for Darwin targets.
In order to allow arm64 code to run on MTE environments, we need to make the
compiler only assume the top 4 bits can be ignored as MTE occupies the lower 4.
rdar://164645323
