[SLP]Recalculate cleared deps for all cancelled copyable elements
Deps of a cancelled copyable element were recalculated only for
control-dependency nodes; a speculatable one stayed unschedulable and
deadlocked the final scheduling. Recalculate unconditionally.
Fixes #216544
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/216734
NVPTX: Fix using getVRegDef on a physical register
This was calling getVRegDef on the frame register; change to
getOneDef instead. This still seems like a dubious way to deal
with any kind of frame setup optimization though.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[MLIR][NVVM] Spell strict assembly properties directly
Bind every NVVM inherent property in its operation assembly format and
re-enable strict property parsing for the dialect. Use direct named clauses
for declarative formats and custom MMA parsers while retaining dictionaries
for discardable attributes.
Assisted-by: Codex
[MLIR][NVVM] Enable strict property assembly format
Enable strict property assembly format mode for the NVVM dialect and update
custom assembly formats to expose property dictionaries explicitly.
Refresh NVVM tests so inherent operation properties are printed and parsed
through the property dictionary while non-property attributes remain in the
attribute dictionary.
Assisted-by: Codex
[AArch64] Fold vector select with power-of-2 bit-test to CMTST+BSP (#209100)
Fixes: #107088
* A vector select whose condition is (X & Mask) == Mask, where Mask is a
power-of-2 constant splat, was generating suboptimal code: AND + CMEQ +
BIF instead of CMTST + BIF.
* This happens because the condition is canonicalized to (X & Mask) ==
0, and AArch64 was not folding the resulting SETCC(AND(X, Mask), 0,
SETEQ) into a CMTST based mask.
* This patch adds a SelectionDAG fold in AArch64ISelLowering.cpp to
lower vector SETCC(AND(X, Mask), 0, SETEQ) to an inverted
AArch64ISD::CMTST. The existing bitselect lowering can then absorb the
inversion and emit CMTST.
Note: Test cases were derived from those reported by the original
author.
Revert "workflows/release-binaries: Disable flang on Darwin (#164667)" (#216667)
This reverts commit 6d54a5e5b83ce3502b7a3488fea5afe1c8bf9c5c.
Flang Darwin builds were reverted due to #160546. That issue has not
been reproducible (at least on my machine) for several months. There was
a request for MacOS builds on the most recent flang community call.
Flang is not enabled in the MacOS pre-commit CI.
Closes #160546
[lldb][test] Fix skip in TestWriteMemoryWithHWBreakpoint.py (#216723)
In a87b27fd5161ec43527fc3356852046a321ea82c, the opposite
skip was put in. It should skip if hardware breakpoints are
*not* supported.
Also that commit added a stray "skip". I have removed that and
fixed the incorrect variable name.
AMDGPU: Use mi_match for more manual selector patterns
Use mi_match G_SHUFFLE_VECTOR/G_FRAME_INDEX/G_SUB checks. Add new
matchers to check the shufflevector and frame index cases, avoiding
raw getVRegDef uses.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[X86] Fold scalar ABS_MIN_POISON store of a load to PABS (#216697)
Extend the scalar load→abs→store SIMD fold from #210654 to `ISD::ABS_MIN_POISON` (`llvm.abs(..., i1 true)`).
That form was left on `neg`+`cmov` while `llvm.abs(..., i1 false)` already
used `PABS`. Vector `PABS` is `ISD::ABS`; `PABS(INT_MIN)` is `INT_MIN`,
which is a valid refinement of poison.
[SLP] Check the fmul's own flags in canConvertToFMA (#216599)
CheckForContractable ran the operand bundle through the fadd's
InstructionsState, so every fmul in it failed the main/alt op test and
was skipped. The flags stayed set and allowContract was trivially true,
which priced a plain fmul feeding a contract fadd as if it would fuse.
The backend will not do that. Give the lambda the state to assess
against and pass the fmul's own.
Assisted-by: Claude Code Opus 5
[GlobalISel] Add G_EXTRACT_SUBVECTOR to computeKnownBits (#214533)
Port the SDAG EXTRACT_SUBVECTOR computeKnownBits handling to GlobalISel.
Offsets the demanded elements by the subvector index to propagate known
bits from the source vector to the extracted subvector.
Part of #150515.
AMDGPU: Fix machine sink crash on an undef SGPR operand
isSafeToSink dereferenced the defining instruction of an
SGPR use without checking for a null def, which crashes on
an undef operand that has no defining instruction.
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[mlir][SPIR-V] Add ComplexToSPIRV lowering for complex.angle (#214172)
Lower complex.angle to spirv.GL.Atan2/spirv.CL.Atan2 on the real and
imaginary components, following the existing complex.abs pattern
[libc++] Define behaviour for calling target() and target_type() on -fno-rtti std::functions (#209471)
The main aim of this change is to have the same vtable between
`-fno-rtti` and `-frtti`. Since it's very cheap to do, this also asserts
if the `function` object was created in `-fno-rtti` mode.
The vtable can be extended, since the members are either never accessed
in `-fno-rtti` mode, or are already expected to exist in `-frtti` mode.
This means that we either define behaviour that wasn't before, or we add
some extra bytes that are never accessed.
AArch64: Fix csel-fold crash on an undef register
removeCopies and canFoldIntoCSel dereference getVRegDef() while checking
whether a select operand can be folded into a csel during early
if-conversion.
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[CIR][OpenCL] Attach kernel argument metadata to CIR functions (#200581)
Emit the CIR OpenCL kernel argument metadata attribute for kernel
functions. Preserve CIR language address-space kinds until lowering and
include argument names only when `-cl-kernel-arg-info` is enabled.
[IR] Add elementwise modifier to atomic stores (#210672)
Add an elementwise modifier to atomic stores to represent
per-element atomic semantics for fixed-vector stores.
Without the modifier, a vector atomic store remains a whole-value
atomic operation. With elementwise, the store behaves as if it were
expanded into one scalar atomic load per fixed-vector element, without
providing atomicity for the vector value as a whole.
Discussion:
https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomic-loads-and-stores/91100
GlobalISel: Match loads by pointer operand in CombinerHelper (#216672)
Add a load matcher that binds the pointer operand (like IR's m_Load),
with optional outputs for the load instruction and its MachineMemOperand
via m_MMO. Use it to replace the getVRegDef + dyn_cast idiom in the load
combines.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
PowerPC: Fix VSX swap removal crash on an undef register
formWebs walks each vector-register use and unions its equivalence class
with that of its defining instruction, which it requires to be present in
the swap map. A use of an undef register has no defining instruction, so the
web formation crashed. Treat it like a physical-register mention so the web
is conservatively rejected.
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[lldb] Serve MemoryCache::ReadRanges from the L2 cache as well as L1 (#216318)
`MemoryCache::Read` fetches a whole L2 cache line for any read that fits
in one,
so reading a few bytes caches the line around them. `ReadRanges` probed
only L1,
and re-fetched ranges that line already held. Callers hit this whenever
they
read an array's header and then batch the elements that follow it in the
same
line, as `AppleObjCRuntimeV2::SharedCacheImageHeaders` and
`ClassDescriptorV2::method_list_t` both do. #201166 uses MemoryCache in
`Process::ReadRangesFromMemory`, but I didn't see why is L1 used only.
Add `FindL2CacheEntry`, a lookup that never reads from the inferior, and
consult
it after L1. When it serves every range in a batch, `ReadRanges` returns
without
calling `Process::DoReadMemoryRanges`, so no packet is sent. As in the
[15 lines not shown]
[libc][test] Condition out tests that can't work on bare metal (#215830)
In bare-metal builds of libc, the `EXPECT_DEATH` macro may not be
defined. Also, `signal-macros.h` may not define the values needed for
the rest of `<signal.h>` to work. So tests that rely on either of those
things will fail to compile.
I've conditioned out the `EXPECT_DEATH` tests completely if
`EXPECT_DEATH` isn't defined. There's inherently no reliable way to
define it: you can't rely on finding out about segmentation faults by a
signal, because accessing memory outside valid C objects might silently
succeed (valid unused memory), or generate a CPU fault that no kernel
traps for you, or overwrite something important outside your program.
The check for signals in `FPExceptMatcher.cpp` can be more lenient, and
just condition out the signal-handling code, leaving the test of
cumulative FP exception flags in place, so that the checker simply
returns "no signal was caught" unconditionally.
[clang-format] Fix short functions with nested braced-init (#213550)
Fixes #213286.
Keep short functions on one line when their return statement contains
nested braced initializers.
The closing brace now checks the kind of its matching opening brace, so
braced-init lists are allowed while structural
braces still prevent merging.
Tests:
- `FormatTest.CustomShortFunctionOptions`
- `FormatTest.AllowShortRecordOnASingleLine`
- full `FormatTests` suite (1275 passed)
Signed-off-by: Gaurav Chaudhary <chaudharygaurav2004 at gmail.com>
[flang][OpenMP] Do not emit barrier after SECTIONS with LASTPRIVATE and NOWAIT (#216018)
Fixes #192907
Flang inserted an explicit omp.barrier after SECTIONS when both
lastprivate and nowait were present, which serialized all threads at the
end of the construct and prevented nowait from taking effect.
Limit the barrier to lastprivate(conditional:) cases, where reduction
results must be finalized before the post-sections copy-back. Regular
lastprivate + nowait now matches wsloop lowering behavior.
