LLVM/project 3e49a56 — llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

by jofrn on ⎇
[SelectionDAG] Scalarize <1 x T> vector types for atomic store

`store atomic <1 x T>` is not valid. This change legalizes
vector types of atomic store via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
DeltaFile
+57-0llvm/test/CodeGen/X86/atomic-load-store.ll
+12-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+70-03 files

LLVM/project a31aee7 — clang/lib/AST ASTImporter.cpp, clang/unittests/AST ASTImporterTest.cpp

by Balázs Kéri via GitHub on ⎇
[clang][ASTImporter] Add import of node 'TemplateParamObjectDecl' (#193492)
DeltaFile
+34-0clang/unittests/AST/ASTImporterTest.cpp
+17-0clang/lib/AST/ASTImporter.cpp
+51-02 files

LLVM/project 03326f9 — mlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp

by Varad Rahul Kamthe via GitHub on ⎇
[MLIR][NVVM] Add rsqrt Op (#195854)

Adds `nvvm.rsqrt` op for fast approximate reciprocal square root. Supports f32 and f64 with an optional `ftz` attribute.

For more information, see PTX ISA: https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-rsqrt
DeltaFile
+28-0mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+21-0mlir/test/Target/LLVMIR/nvvm/rsqrt/rsqrt.mlir
+20-0mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+69-03 files

LLVM/project f9246ad — llvm/test/Transforms/InstCombine sub.ll

by Iris Shi on ⎇
update tests
DeltaFile
+2-2llvm/test/Transforms/InstCombine/sub.ll
+2-21 files

LLVM/project 245dcd8 — llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp, llvm/test/Transforms/InstCombine sub.ll

by Iris Shi on ⎇
[InstCombine] Drop `(X + Z) - (Y + Z) --> (X - Y)` fold
DeltaFile
+33-0llvm/test/Transforms/InstCombine/sub.ll
+2-9llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+35-92 files

LLVM/project f19c931 — llvm/test/CodeGen/X86 atomic-load-store.ll

by jofrn on ⎇
[X86] Add atomic vector store tests for unaligned >1 sizes.

Unaligned atomic vector stores with size >1 are lowered to calls.
Adding their tests separately here.
DeltaFile
+1,068-0llvm/test/CodeGen/X86/atomic-load-store.ll
+1,068-01 files

LLVM/project ca8d74b — lldb/include/lldb/Interpreter CommandReturnObject.h, lldb/source/Commands CommandObjectProtocolServer.cpp CommandObjectProcess.cpp

by Dmitry Vasilyev via GitHub on ⎇
Revert "[lldb] Assert that CommandObject::DoExecute sets a return status (#19…"

This reverts commit 78d124eb16aa62e02a465b0fd6c3c2cab0a26dd8.
DeltaFile
+0-38lldb/unittests/Interpreter/TestCommandReturnObject.cpp
+1-24lldb/source/Interpreter/CommandObject.cpp
+1-4lldb/include/lldb/Interpreter/CommandReturnObject.h
+2-2lldb/test/API/commands/command/script/TestCommandScript.py
+1-2lldb/source/Commands/CommandObjectProtocolServer.cpp
+0-2lldb/source/Commands/CommandObjectProcess.cpp
+5-722 files not shown
+6-748 files

LLVM/project b88008c — llvm/lib/Transforms/InstCombine InstCombineMulDivRem.cpp, llvm/test/Transforms/InstCombine powi.ll powi-mul-overflow.ll

by Iris Shi on ⎇
address review comments
DeltaFile
+61-5llvm/test/Transforms/InstCombine/powi.ll
+0-45llvm/test/Transforms/InstCombine/powi-mul-overflow.ll
+4-12llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+65-623 files

LLVM/project 45c1414 — llvm/docs AMDGPUUsage.rst

by Sameer Sahasrabuddhe on ⎇
fixed a runaway sed replacement
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

LLVM/project 46e07d3 — llvm/test/CodeGen/RISCV callee-saved-gprs.ll vararg.ll, llvm/test/CodeGen/RISCV/GlobalISel vararg.ll

by Garvit Gupta via GitHub on ⎇
[RISCV] Prefer SP over FP for frame index access when offset fits within compressed immediate range. (#193962)

Before this change, we would use fp/s0/x8 for most stack accesses when
frame pointers were present. This is an over-approximation when a
stack slot is reachable from both SP and FP with no scalable offset.

This patch replaces the unconditional getFrameRegister() call in
getFrameIndexReference with an explicit register selection decision
tree.

When both SP and FP are available (no stack realignment, no RVV objects,
no variable-sized objects), prefer SP if the SP-relative offset fits in
the compressed instruction immediate range (<=252 for RV32, <=504 for RV64).
This enables compression for sp-relative instructions to c.swsp/c.lwsp
(RV32) and c.sdsp/c.ldsp (RV64) thereby reducing code size.
DeltaFile
+316-316llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+295-303llvm/test/CodeGen/RISCV/vararg.ll
+226-230llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+224-224llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+128-128llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
+75-75llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+1,264-1,27618 files not shown
+1,465-1,45824 files

LLVM/project 1a6fa34 — mlir/lib/Conversion/ComplexToLLVM ComplexToLLVM.cpp, mlir/lib/Conversion/ComplexToStandard ComplexToStandard.cpp

by hanbeom via GitHub on ⎇
[mlir][complex] Emit complex.mul multiplications before add/sub lowering (#196231)

[mlir][complex] Emit complex.mul multiplications before add/sub lowering
This changes the lowering of complex.mul in both ComplexToStandard and
ComplexToLLVM to emit the four independent multiplications before
creating the
final add/sub operations.

The lowered computation is unchanged:

  real = lhs.real * rhs.real - lhs.imag * rhs.imag
  imag = lhs.imag * rhs.real + lhs.real * rhs.imag

but the generated operation order changes from:

  mul, mul, sub, mul, mul, add

to:


    [6 lines not shown]
DeltaFile
+13-6mlir/lib/Conversion/ComplexToLLVM/ComplexToLLVM.cpp
+6-7mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
+5-6mlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir
+3-2mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
+1-2mlir/test/Conversion/ComplexToLLVM/full-conversion.mlir
+28-235 files

LLVM/project a1e9d82 — libc/src/__support big_int.h, libc/src/__support/FPUtil bfloat16.h NormalFloat.h

by lntue via GitHub on ⎇
[libc][NFC] Propagate LIBC_CONSTEXPR qualifier for those depending on bitt_cast. (#197355)

This should fix the LLVM APFloat build with gcc pre-11.
DeltaFile
+128-122libc/src/__support/big_int.h
+16-16libc/src/__support/math/atan2f128.h
+15-15libc/src/__support/FPUtil/bfloat16.h
+13-10libc/src/__support/math/sqrtf128.h
+12-10libc/src/__support/FPUtil/NormalFloat.h
+10-7libc/src/__support/macros/attributes.h
+194-180379 files not shown
+710-637385 files

LLVM/project c831bb5 — clang/docs ReleaseNotes.rst, clang/include/clang/Sema Sema.h

by Matheus Izvekov on ⎇
[clang] make concept normalization a SFINAE context

It is incorrect to allow the substitution failures in concept normalization
to make the program ill-formed.

These can happen when comparing the equivalence of constraints for
redeclaration checking, and a failure here only means these declarations
are not equivalent.

For now, these diagnostics are simply discarded. It would be nice
if some day, as part of diagnostics for non-matching out-of-line definitions,
we would explain why matching failed for each candidate, and then add these
as notes explaining why the constraints were not equivalent.
DeltaFile
+27-49clang/lib/Sema/SemaConcept.cpp
+7-30clang/lib/Sema/SemaTemplateInstantiate.cpp
+11-3clang/test/SemaTemplate/concepts-out-of-line-def.cpp
+0-9clang/include/clang/Sema/Sema.h
+0-2clang/lib/Frontend/FrontendActions.cpp
+2-0clang/docs/ReleaseNotes.rst
+47-932 files not shown
+47-968 files

LLVM/project 5c66ef1 — clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip

by Chaitanya via GitHub on ⎇
[CIR][AMDGPU] Add lowering for amdgcn readlane readfirstlane builtins (#197153)

Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/2053

This PR adds support for lowering of "_builtin_amdgcn_readlane" and
"_builtin_amdgcn_readfirstlane" amdgpu builtins to clangIR.
DeltaFile
+16-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+13-2clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+29-22 files

LLVM/project 3d9d8ce — libcxx/docs/Status Cxx2cIssues.csvgb

by Connector Switch via GitHub on ⎇
[libc++] Remove empty csvgb file. (#196939)

This file was introduced in #172905, but it is empty and I could not
find any reference to it.
DeltaFile
+0-0libcxx/docs/Status/Cxx2cIssues.csvgb
+0-01 files

LLVM/project 228fc61 — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/include/clang/Sema Sema.h

by Matheus Izvekov on ⎇
[clang] make concept normalization a SFINAE context

It is incorrect to allow the substitution failures in concept normalization
to make the program ill-formed.

These can happen when comparing the equivalence of constraints for
redeclaration checking, and a failure here only means these declarations
are not equivalent.

For now, these diagnostics are simply discarded. It would be nice
if some day, as part of diagnostics for non-matching out-of-line definitions,
we would explain why matching failed for each candidate, and then add these
as notes explaining why the constraints were not equivalent.
DeltaFile
+27-49clang/lib/Sema/SemaConcept.cpp
+7-30clang/lib/Sema/SemaTemplateInstantiate.cpp
+11-3clang/test/SemaTemplate/concepts-out-of-line-def.cpp
+0-9clang/include/clang/Sema/Sema.h
+0-2clang/lib/Frontend/FrontendActions.cpp
+0-2clang/include/clang/Basic/DiagnosticSemaKinds.td
+45-951 files not shown
+47-957 files

LLVM/project 38cf0f1 — clang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeSafety.h, clang/include/clang/Basic DiagnosticSemaKinds.td

by Zeyi Xu via GitHub on ⎇
[LifetimeSafety] Diagnose invalidated-global (#197220)

Teach lifetime safety invalidation diagnostics to handle origins that
escape through global or static storage before the referenced object is
invalidated. Previously they were skipped.

Follow up of #196680
Closes https://github.com/llvm/llvm-project/issues/195706
DeltaFile
+61-0clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+42-0clang/lib/Sema/SemaLifetimeSafety.h
+14-2clang/lib/Analysis/LifetimeSafety/Checker.cpp
+6-0clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
+4-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+127-25 files

LLVM/project 9413af0 — llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

by Craig Topper via GitHub on ⎇
[RISCV][P-ext] Support pabd(u).db/h. (#197332)
DeltaFile
+6-24llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+10-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+2-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+18-243 files

LLVM/project 98500fc — llvm/lib/Target/RISCV RISCVInsertVSETVLI.cpp RISCVVSETVLIInfoAnalysis.h, llvm/test/CodeGen/RISCV/rvv sifive-xsfmm-vset-insert.mir

by Piyou Chen via GitHub on ⎇
[RISCV] Make SFMM configuration instruction emit like VSETVLI (#196487)

Reuse the PseudoVSETVLI condition instead of its own condition.

---------

Co-authored-by: Luke Lau <luke_lau at icloud.com>
DeltaFile
+12-26llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+2-2llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir
+4-0llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
+18-283 files

LLVM/project f6e26cb — clang/test/Instrumentor StackUsageRT.cpp StackUsageRT.json

by Johannes Doerfert via GitHub on ⎇
[Instrumentor] Remove brittle clang tests for now (#197350)

This should fix https://github.com/llvm/llvm-project/pull/195378
DeltaFile
+0-60clang/test/Instrumentor/StackUsageRT.cpp
+0-54clang/test/Instrumentor/StackUsageRT.json
+0-37clang/test/Instrumentor/InstrumentorStackUsage.cpp
+0-2clang/test/Instrumentor/lit.local.cfg
+0-1534 files

LLVM/project 8edb0d9 — llvm/include/llvm/MC DXContainerInfo.h, llvm/lib/MC DXContainerInfo.cpp

by Vladislav Dzhidzhoev via GitHub on ⎇
Revert "[DirectX][ObjectYAML] Add ILDN part support" (#197348)

Reverts llvm/llvm-project#194508 due to
1. Compilation error on older cl.exe versions due to having a field
"DebugName" as a member of class "DebugName".
2. Layout violation between MC and Object
(see https://github.com/llvm/llvm-project/pull/197343).
DeltaFile
+0-64llvm/test/tools/obj2yaml/DXContainer/ILDNPart.yaml
+2-46llvm/lib/Object/DXContainer.cpp
+0-41llvm/lib/MC/DXContainerInfo.cpp
+0-36llvm/unittests/Object/DXContainerTest.cpp
+0-33llvm/unittests/ObjectYAML/DXContainerYAMLTest.cpp
+0-32llvm/include/llvm/MC/DXContainerInfo.h
+2-25211 files not shown
+2-39317 files

LLVM/project 263b78f — llvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp

by Craig Topper via GitHub on ⎇
[RISCV][GISel] Use getZExtValue() instead of getLimitedValue(). NFC (#196638)

The constants here should be 64 bits or less.
DeltaFile
+7-7llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+7-71 files

LLVM/project 37a9cf4 — libc/src/__support/CPP bit.h, libc/src/__support/macros attributes.h

by Muhammad Bassiouni via GitHub on ⎇
[libc][NFC] Increase minimum GCC version for `LIBC_CONSTEXPR` to 11 (#197333)
DeltaFile
+12-9libc/src/__support/CPP/bit.h
+1-1libc/src/__support/macros/attributes.h
+13-102 files

LLVM/project 9cd33f8 — utils/bazel/llvm-project-overlay/libc BUILD.bazel, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

by Aiden Grossman via GitHub on ⎇
[libc] Port 2b2a63819f9f26d661bad5c269a03077d22ff6b4 (#197337)
DeltaFile
+506-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+507-12 files

LLVM/project 9908f7e — clang/lib/Headers intrin.h, clang/test/Headers ms-intrin.cpp

by GkvJwa via GitHub on ⎇
[clang] Align x86 CR/DR intrinsic declarations with MSVC (#196886)

Align CR/DR and related MSR intrinsic declarations in intrin.h with
MSVC's x86/x64 signatures

Fixes #185457
DeltaFile
+45-0clang/test/Headers/ms-intrin.cpp
+14-10clang/lib/Headers/intrin.h
+59-102 files

LLVM/project 9b6e77d — libclc CMakeLists.txt

by Joseph Huber via GitHub on ⎇
[libclc] Apply hidden visibility to amdgpu / nvptx builds (#197235)

Summary:
    This is not currently used because we force `--internalize` for
llvm-link, but if you ever want to link this normally we'd need hidden
visibility. SPIR-V does not currently handle hidden visibility, as it is
    an extension still under discussion, so it is omitted for now.
DeltaFile
+4-0libclc/CMakeLists.txt
+4-01 files

LLVM/project 4106333 — libclc/cmake/modules AddLibclc.cmake

by Joseph Huber via GitHub on ⎇
[libclc] Create a static `.a` file in addition to the `.bc` file (#197247)

Summary:
This changes the libraries to be object libraries instead of static
libraries. We can then just link these into final static libraries that
contain everything we need.

The desire here is that we'd need static libraries if we wanted to move
away from `-mlink-builtin-bitcode` appraoches.

Effectively we'll have `libclc.a` next to `libclc.bc` and the idea is
that we could alternatively link it and let the target linker handle it.
DeltaFile
+43-53libclc/cmake/modules/AddLibclc.cmake
+43-531 files

LLVM/project 5aa86b7 — llvm/include/llvm/CodeGen MIRYamlMapping.h, llvm/lib/CodeGen MIRPrinter.cpp

by Quentin Colombet on ⎇
[MIR] Save internal VirtRegMap state in MIR

Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:

  registers:
    - { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }

Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.

So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.

Mechanism:
- For serialization:
  - MIRPrinter emits the new fields only when the new -mir-emit-vrm

    [16 lines not shown]
DeltaFile
+48-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+30-8llvm/lib/CodeGen/MIRPrinter.cpp
+32-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
+18-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
+17-1llvm/include/llvm/CodeGen/MIRYamlMapping.h
+17-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
+162-95 files not shown
+221-1311 files

LLVM/project 4baa5aa — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll regalloc-hoist-spill-live-range-upd.mir

by Quentin Colombet on ⎇
[AMDGPU][test] Use mir test for regalloc issue

Use the newly introduced split-from flag to produce a more robust test case
for the hoistSpillInsideBB live-range update issue.

NFC
DeltaFile
+0-2,870llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+71-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
+71-2,8702 files

LLVM/project f5069ff — llvm/test/CodeGen/AMDGPU splitkit-copy-live-lanes.mir ra-inserted-scalar-instructions.mir, llvm/test/CodeGen/X86 statepoint-invoke-ra-inline-spiller.mir

by Quentin Colombet on ⎇
[MIR] Serialize/Deserialize MachineInstr::LRSplit attribute

The LRSplit MachineInstr flag is set by SplitKit on copies inserted for
live-range splitting.
Until now the flag had no MIR-text representation.

This patch fixes that so that it gets easier to reproduce/capture issues
that involves SplitKit.

Round-trip coverage in
llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir.
DeltaFile
+168-168llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
+36-36llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+32-32llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
+27-27llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+22-22llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
+22-22llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
+307-30731 files not shown
+436-40237 files