LLVM/project 89f9ebdllvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-v4-instructions.ll, llvm/test/CodeGen/AArch64/Atomics aarch64-atomicrmw-v8a_fp.ll aarch64-atomicrmw-lsfe.ll

[AArch64][GlobalISel] Enable BF16 legalization for fadd and friends. (#196081)

This enabled bf16 promotion for the following operations in GISel,
promoting them to f32 and truncating the result back:
G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM,
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT, G_FNEARBYINT,
G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN
DeltaFile
+2,062-1,026llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+975-581llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+824-404llvm/test/CodeGen/AArch64/bf16-instructions.ll
+420-240llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
+195-90llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+34-34llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+4,510-2,3751 files not shown
+4,516-2,3767 files

LLVM/project 102ac85llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/Transforms/InstCombine fold-multi-use-select-packed-constants.ll

address review comments

Co-Authored-By: arsenm <arsenm2 at gmail.com>
DeltaFile
+10-10llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
+5-9llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+15-192 files

LLVM/project 0da8649llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/CodeGen/AMDGPU amdgpu-simplify-libcall-pow.ll

[InstCombine] Fold binop into multi-use select when one select arm and the other operand are constant
DeltaFile
+48-48llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+21-2llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+2-7llvm/test/Transforms/InstCombine/pr72433.ll
+2-7llvm/test/Transforms/InstCombine/pr80597.ll
+2-6llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
+1-4llvm/test/Transforms/InstCombine/extractelement.ll
+76-741 files not shown
+77-757 files

LLVM/project a7aebecllvm/test/Transforms/InstCombine fold-multi-use-select-packed-constants.ll

pre-commit tests

1
DeltaFile
+263-0llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
+263-01 files

LLVM/project d1f0d1bclang/lib/Basic TargetID.cpp, clang/test/Driver amdgpu-invalid-target-id.s

[clang][AMDGPU] Reject malformed target IDs with empty components (#196140)

Fixes #196078

An extra colon in `-mcpu` (e.g. `gfx900::xnack+`) produced an empty
feature component and triggered an assertion in `StringRef::back()`.

Return `std::nullopt` for malformed target IDs instead.
DeltaFile
+6-0clang/test/Driver/amdgpu-invalid-target-id.s
+2-0clang/lib/Basic/TargetID.cpp
+8-02 files

LLVM/project 8e36604llvm/test/CodeGen/RISCV/GlobalISel rv64zba.ll

[RISCV][GISel] Add test coverage for the srliw+shXadd patterns. NFC (#196676)

GISel isn't canonicalizing the shift pair to an AND the same way
SelectionDAG does so the patterns weren't firing. Add more directed
tests that use an And explicitly.
DeltaFile
+54-0llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll
+54-01 files

LLVM/project 6da957dllvm/lib/CodeGen/SelectionDAG LegalizeFloatTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/PowerPC soft-promote-half-br-cc.ll

[DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214)

`SoftPromoteHalfOperand` had no case for `ISD::BR_CC`, causing a crash
when a half-typed `fcmp` result fed directly into a conditional branch.
All other comparison-related nodes (`SETCC, SELECT_CC`) were already
handled. Add `SoftPromoteHalfOp_BR_CC` following the same pattern as
`SoftPromoteHalfOp_SELECT_CC`.

Fixes #195562

---------

Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
DeltaFile
+162-0llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll
+27-0llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+190-03 files

LLVM/project 66d4162clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen TargetInfo.cpp

[CIR][CUDA][NVPTX] Set ptx_kernel calling convention on CUDA kernels (#195382)

Related: https://github.com/llvm/llvm-project/issues/179278,
https://github.com/llvm/llvm-project/issues/175871

More target attributes like: NoInline on kernels, CUDALaunchBoundsAttr,
CUDAGridConstantAttr param attrs, nvvm.annotations for surface/texture
VarDecls to be deferred for later patches.
DeltaFile
+42-0clang/test/CIR/CodeGenCUDA/ptx-kernels.cu
+41-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+2-0clang/include/clang/CIR/MissingFeatures.h
+1-1clang/test/CIR/CodeGenCUDA/address-spaces.cu
+86-14 files

LLVM/project c71e991llvm/lib/Transforms/Utils BreakCriticalEdges.cpp, llvm/test/Transforms/CodeGenPrepare/X86 split-indirectbr-duplicate-pred.ll

[Utils] Fix duplicate DomTree updates in SplitIndirectBrCriticalEdges (#196475)

SplitIndirectBrCriticalEdges generates DomTree Insert/Delete pairs for
each predecessor in OtherPreds. However, OtherPreds can contain
duplicate entries when a conditional branch has both targets pointing to
the same block (e.g., `br i1 %c, label %X, label %X`). This produces
duplicate DomTree updates for the same edge, triggering the assertion
`std::abs(NumInsertions) <= 1 && "Unbalanced operations!"` in
LegalizeUpdates.

Fix by tracking which source blocks have already had DomTree updates
emitted, and skipping duplicates.
DeltaFile
+31-0llvm/test/Transforms/CodeGenPrepare/X86/split-indirectbr-duplicate-pred.ll
+5-1llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
+36-12 files

LLVM/project 6f2df1cclang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaOverload.cpp

[Clang] Do not eat SFINAE diagnostics for explicit template arguments (#139066)

Instead of merely suggesting the template arguments are invalid, we now
provide an explanation of why the explicit template argument is invalid.
DeltaFile
+26-18clang/lib/Sema/SemaOverload.cpp
+6-6clang/include/clang/Basic/DiagnosticSemaKinds.td
+4-4clang/test/CXX/drs/cwg2xx.cpp
+4-4clang/test/CXX/dcl.dcl/basic.namespace/namespace.udecl/p12.cpp
+4-3clang/test/SemaCXX/cxx2a-template-lambdas.cpp
+2-2clang/test/SemaTemplate/overload-candidates.cpp
+46-3714 files not shown
+63-5220 files

LLVM/project bb174f4clang/include/clang/Basic DiagnosticLexKinds.td, clang/test/Lexer __counter__-system-include.c

[clang] Don't warn on __COUNTER__ in system macros

The introduction of extension and compatibility warnings means
that __COUNTER__ has started causing warnings (and -Werror= build
failures) due to use of system APIs.

This PR simply ensures that these diagnostics don't get reported
for system macro expansions as well.
DeltaFile
+15-0clang/test/Lexer/__counter__-system-include.c
+7-0clang/test/Lexer/Inputs/__counter__-system-header.h
+2-2clang/include/clang/Basic/DiagnosticLexKinds.td
+24-23 files

LLVM/project c3f14e5llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/CodeGen/AMDGPU amdgpu-simplify-libcall-pow.ll

[InstCombine] Fold binop into multi-use select when one select arm and the other operand are constant
DeltaFile
+48-48llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+21-2llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+7-11llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
+2-7llvm/test/Transforms/InstCombine/pr80597.ll
+2-7llvm/test/Transforms/InstCombine/pr72433.ll
+1-4llvm/test/Transforms/InstCombine/extractelement.ll
+81-791 files not shown
+82-807 files

LLVM/project 3e24255llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/CodeGen/AMDGPU amdgpu-simplify-libcall-pow.ll

[InstCombine] Fold binop into multi-use select when one select arm and the other operand are constant
DeltaFile
+48-48llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+18-2llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+7-11llvm/test/Transforms/InstCombine/fold-multi-use-select-packed-constants.ll
+2-7llvm/test/Transforms/InstCombine/pr80597.ll
+2-7llvm/test/Transforms/InstCombine/pr72433.ll
+1-4llvm/test/Transforms/InstCombine/extractelement.ll
+78-791 files not shown
+79-807 files

LLVM/project 5d1a9belldb/tools/driver Driver.cpp

Revert "Revert "[lldb] Handle SIGINT via the MainLoop signal thread (on POSIX…"

This reverts commit 0ad1bc96429863fe9fa65706df9a86cec649bf60.
DeltaFile
+56-4lldb/tools/driver/Driver.cpp
+56-41 files

LLVM/project 0ad1bc9lldb/tools/driver Driver.cpp

Revert "[lldb] Handle SIGINT via the MainLoop signal thread (on POSIX)" (#196684)

Reverts llvm/llvm-project#195959 because it caused
`TestIOHandlerCompletion.py` to fail in CI (GreenDragon).
DeltaFile
+4-56lldb/tools/driver/Driver.cpp
+4-561 files

LLVM/project fdc9664flang/test/Integration/OpenMP map-types-and-sizes.f90, mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[OpenMP][MLIR] Modify lowering OpenMP Dialect lowering to support attach mapping

This PR adjusts the LLVM-IR lowering to support the new attach map type that the runtime
uses to link data and pointer together, this swaps the mapping from the older
OMP_MAP_PTR_AND_OBJ map type in most cases and allows slightly more complicated ref_ptr/ptee
and attach semantics.
DeltaFile
+379-281mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+273-0mlir/test/Target/LLVMIR/omptarget-host-ref-semantics.mlir
+101-165flang/test/Integration/OpenMP/map-types-and-sizes.f90
+27-58mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir
+70-0offload/test/offloading/fortran/map_attach_always.f90
+55-0offload/test/offloading/fortran/map_attach_never.f90
+905-50415 files not shown
+1,078-59821 files

LLVM/project 0b70f5fflang/lib/Optimizer/OpenMP MapInfoFinalization.cpp, flang/test/Lower/OpenMP use-device-ptr-to-use-device-addr.f90 optional-argument-map-2.f90

[Flang][OpenMP][Offload] Modify MapInfoFinalization to handle attach mapping and 6.1's ref_* and attach map keywords

This PR is one of four required to implement the attach mapping semantics in Flang, alongside the
ref_ptr/ref_ptee/ref_ptr_ptee map modifiers and the attach(always/never/auto) modifiers.

This PR is the MapInfoFinalization changes required to support these features, it mainly deals with
applying the correct attach map type and manipulating the descriptor types maps for base address
and descriptor so that when we specify ref_ptr/ref_ptee we emit one of the two maps and when we
emit ref_ptr_ptee we emit our usual default maps. In all cases we add the "glue" of an new
attach map except in cases where a user has provided attach never. In cases where we are
provided an always, we apply the always map type to our attach maps.

It's important to note the runtime has a toggle for the auto map behaviour, which will flip the
attach behaviour to the newer semantics or the older semantics for backwards compatability (outside
the purview of this PR but good to mention).
DeltaFile
+695-321flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
+43-44flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90
+19-19flang/test/Lower/OpenMP/optional-argument-map-2.f90
+22-11flang/test/Transforms/omp-map-info-finalization.fir
+18-12flang/test/Lower/OpenMP/derived-type-allocatable-map.f90
+18-9flang/test/Lower/OpenMP/map-descriptor-deferral.f90
+815-41613 files not shown
+890-45719 files

LLVM/project 6f595b1lldb/tools/driver Driver.cpp

Revert "[lldb] Handle SIGINT via the MainLoop signal thread (on POSIX) (#195959)"

This reverts commit 38d79280ac57159b92a23d90eb34a2f646b57f71.
DeltaFile
+4-56lldb/tools/driver/Driver.cpp
+4-561 files

LLVM/project e4d5880llvm/test/CodeGen/AMDGPU load-atomic-global.ll load-atomic-local.ll

[AMDGPU] Support atomic load and store for vector float types (v2f16, v2i16, v4i16, v4f16, v2f32) (#192904)

Add support for atomic load and store on <2 x half>, <4 x half>, and
<2 x float> vector types in the AMDGPU backend.

These types are promoted to equivalently sized integer types before
instruction selection:
  <2 x half>  -> i32
  <4 x half>  -> i64
  <2 x i16>  -> i32
  <4 x i16>  -> i64
  <2 x float> -> i64
DeltaFile
+1,246-0llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
+1,204-0llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
+561-0llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
+438-0llvm/test/CodeGen/AMDGPU/store-atomic-global.ll
+429-0llvm/test/CodeGen/AMDGPU/store-atomic-local.ll
+198-0llvm/test/CodeGen/AMDGPU/store-atomic-flat.ll
+4,076-09 files not shown
+4,274-12015 files

LLVM/project 01ffe2eflang/lib/Optimizer/OpenMP MapInfoFinalization.cpp, flang/lib/Utils OpenMP.cpp

[Flang][MLIR][OpenMP] Add distinct var_ptr_ptr_type to omp.map.info operations & remove ref_ptr_ptee

This is a precursor patch to attach and ref_ptr/ptee mapping that I intend to upstream
over the next few weeks. The attach maps require both the type of the descriptor and
the pointed to data to calculate the appropriate offload/base pointers and size. In
the base case of ref_ptr_ptee all of this information can be gathered from the pointer
and pointee maps, but in cases where we have only one (i.e. ref_ptr/ref_ptee) we will
be missing one of the key elements required to create an corresponding attach map.

So, this PR basically adds the ability to ferry around the type of both var_ptr and
var_ptr_ptr as opposed to just var_ptr, then we can emit attach maps as seperate
map.info's that carry all the pre-requisite informaion for lowering to LLVM-IR. But,
otherwise it seems reasonable to have var_ptr_ptr mirror var_ptr in all aspects for
consistency.

It also removes ref_ptr_ptee, instead opting to use the setting of both ref_ptr and
ref_ptee to mean ref_ptr_ptee.
DeltaFile
+25-16flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
+20-10mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+18-11flang/lib/Utils/OpenMP.cpp
+14-14flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
+17-10mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+11-11flang/test/Transforms/omp-map-info-finalization.fir
+105-7241 files not shown
+218-16947 files

LLVM/project f4f27e6flang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP attach-and-ref-modifier.f90

[Flang][OpenMP][MLIR] Add attach and ref map type lowering to MLIR

This doesn't implement the functionality, just the relevant map type
lowering to MLIR's omp.map.info. The more complicated changes to
MapInfoFinalizationPass.cpp and OpenMPTOLLVMIRTranslation.cpp to support
attach map and the various ref/attach semantics will come in a subsequent
set of PRs. This just helps compartmentalize the changeset.
DeltaFile
+107-0flang/test/Lower/OpenMP/attach-and-ref-modifier.f90
+29-2flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+0-9flang/test/Lower/OpenMP/Todo/attach-modifier.f90
+136-113 files

LLVM/project 5f18584lldb/source/API SBCommandInterpreter.cpp, lldb/source/Commands CommandObjectTarget.cpp CommandObjectType.cpp

[lldb] Fix CommandObjects that don't set a return status (#196588)

Several CommandObject subclasses had DoExecute paths that returned
without ever calling SetStatus on the CommandReturnObject. The status
was silently left at its initial eReturnStatusStarted value, which made
Succeeded() report false for what were really successful commands and
left CommandReturnObject in an undefined state.
DeltaFile
+7-1lldb/source/API/SBCommandInterpreter.cpp
+7-0lldb/source/Commands/CommandObjectTarget.cpp
+4-2lldb/source/Commands/CommandObjectType.cpp
+4-0lldb/source/Commands/CommandObjectExpression.cpp
+3-0lldb/source/Commands/CommandObjectSettings.cpp
+3-0lldb/source/Commands/CommandObjectMemory.cpp
+28-311 files not shown
+46-417 files

LLVM/project 74e07e1clang/lib/CIR/CodeGen CIRGenBuiltinRISCV.cpp, clang/test/CIR/CodeGenBuiltins/RISCV riscv-zksh.c

[CIR][RISCV] Support zksh builtin codegen (#196463)
DeltaFile
+26-0clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zksh.c
+8-2clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+34-22 files

LLVM/project d2db5bbclang/lib/CodeGen CGCall.cpp, llvm/include/llvm/ABI FunctionInfo.h

[CodeGen] Use unique_ptr for FunctionInfo to prevent memory leaks (#196603)

Raw pointer return from `FunctionInfo::create` caused leaks in callers
like `computeABIInfoUsingLib`, breaking BPF tests on ASan bots.
Using `std::unique_ptr` enforces automatic cleanup.

Fixes leak from #194460.
Buildbot: https://lab.llvm.org/buildbot/#/builders/52/builds/17090

Assisted-by: Gemini
DeltaFile
+8-5llvm/lib/ABI/FunctionInfo.cpp
+1-1clang/lib/CodeGen/CGCall.cpp
+1-1llvm/include/llvm/ABI/FunctionInfo.h
+10-73 files

LLVM/project c7120bbmlir/lib/Dialect/Tensor/Transforms DropRedundantRankExpansionPatterns.cpp, mlir/test/Dialect/Tensor drop-redundant-insert-slice-rank-expansion.mlir

[mlir][tensor] Enhance pattern to fold extract_slice(insert_slice) (#195045)

Extend the DropRedundantRankExpansionOnExtractSliceOfInsertSlice pattern
to support cases where the expanded dimensions are a subset of the
dropped dimensions, rather than requiring them to be exactly equal.
For example:
```
%inserted_slice = tensor.insert_slice %src into %dest[0, 0, 0, 0] [1, 1, 128, 480] [1, 1, 1, 1] :
        tensor<128x480xf32> into tensor<1x1x128x480xf32>
%extracted_slice = tensor.extract_slice %inserted_slice[0, 0, 0, 0] [1, 1, 123, 1] [1, 1, 1, 1] :
        tensor<1x1x128x480xf32> to tensor<123xf32>
```
can be folded into:
```
%extracted_slice = tensor.extract_slice %src[0, 0] [123, 1] [1, 1] :
        tensor<128x480xf32> to tensor<123xf32>
```
DeltaFile
+17-10mlir/lib/Dialect/Tensor/Transforms/DropRedundantRankExpansionPatterns.cpp
+12-0mlir/test/Dialect/Tensor/drop-redundant-insert-slice-rank-expansion.mlir
+29-102 files

LLVM/project bc654b4bolt/lib/Rewrite RewriteInstance.cpp

Revert "[BOLT] Fix EH data encoding checks in relocateEHFrameSection (#195691)" (#196672)

This reverts commit 7ab26d7c3a160e1dc166f2673644baa396703ee5.

There is test failure in bolt-tests::exceptions-split-strip.test.
DeltaFile
+7-4bolt/lib/Rewrite/RewriteInstance.cpp
+7-41 files

LLVM/project 2daf204clang/lib/Serialization ASTReader.cpp, llvm/lib/DWARFLinker/Parallel DWARFLinkerImpl.cpp

Merge branch 'main' into users/vitalybuka/spr/codegen-use-unique_ptr-for-functioninfo-to-prevent-memory-leaks-2
DeltaFile
+1,608-0llvm/test/MC/AMDGPU/gfx13_asm_vop3p.s
+555-435llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+108-246llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+13-318mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
+140-144clang/lib/Serialization/ASTReader.cpp
+140-61llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
+2,564-1,204225 files not shown
+6,109-2,788231 files

LLVM/project 54ea7c5llvm/lib/Target/RISCV RISCVInstrInfoXAndes.td, llvm/test/CodeGen/RISCV rv64zba.ll

[RISCV] Use the nhs.lea.h/w/d instead of nhs.lea.h/w/d.ze with Sh1AddPat. (#196660)

The srliw already took care of zeroing the upper bits. Using the non-.ze
form is consistent with the Zba version of this pattern.
DeltaFile
+3-3llvm/test/CodeGen/RISCV/rv64zba.ll
+3-3llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+6-62 files

LLVM/project f03da66clang-tools-extra/clangd ProjectModules.cpp, clang/include/clang/DependencyScanning DependencyScanningService.h

[clang][deps] Move `ScanningOutputFormat` out of the library (#196631)

Basing behavior of the dependency scanner on the final output format is
a leaky abstraction. Instead, we should aim to introduce proper feature
flags.
DeltaFile
+20-1clang/tools/clang-scan-deps/ClangScanDeps.cpp
+2-18clang/include/clang/DependencyScanning/DependencyScanningService.h
+2-1clang-tools-extra/clangd/ProjectModules.cpp
+1-1clang/lib/DependencyScanning/DependencyScannerImpl.cpp
+0-2clang/unittests/Tooling/DependencyScannerTest.cpp
+25-235 files

LLVM/project 0366ed2llvm/lib/Target/PowerPC PPCISelLowering.cpp, llvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-v4-instructions.ll

rebase

Created using spr 1.3.4
DeltaFile
+5,938-880llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+4,634-367llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+3,322-504llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+1,608-0llvm/test/MC/AMDGPU/gfx13_asm_vop3p.s
+555-435llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+0-775llvm/utils/Reviewing/find_interesting_reviews.py
+16,057-2,9611,818 files not shown
+52,277-20,1441,824 files