LLVM/project ab810fbllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv-fp16.ll faddv.ll

Address comments 1

Removed:
Flags.setNoSignedZeros(true);

Because technically the produced result can be a signed zero, it just
does not matter.
DeltaFile
+43-25llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+54-0llvm/test/CodeGen/AArch64/faddv-fp16.ll
+45-0llvm/test/CodeGen/AArch64/faddv.ll
+2-3llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+144-284 files

LLVM/project 1ccb026llvm/test/CodeGen/Thumb2 mve-sli-sri.ll

[ARM] Add sli / sri codegen tests. NFC

These ones are taken from the AArch64 equivalent tests.
DeltaFile
+557-0llvm/test/CodeGen/Thumb2/mve-sli-sri.ll
+557-01 files

LLVM/project ab0823cllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/RISCV avgflooru.ll

[TargetLowering][RISCV] Disable the special illegal type expansion of ISD::AVGFLOORU on RV32 (#181073)

RISC-V doesn't have a carry flag which makes the UADDO expansion
expensive to emulate.

I've disabled the code by checking if UADDO is not supported for the
type that will be legalized too. Unfortunatley, we have custom lowering
of UADDO on RV64 so this doesn't disable this code there.
DeltaFile
+22-26llvm/test/CodeGen/RISCV/avgflooru.ll
+3-1llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+25-272 files

LLVM/project c706306llvm/test/CodeGen/AMDGPU load-saddr-offset-imm.ll

[AMDGPU] change to show the benefit in new way
DeltaFile
+10-4llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
+10-41 files

LLVM/project 0a9d7ffllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 fminimumnum-fmaximumnum.ll fminimum-fmaximum.ll

[X86][AVX10] Change MINMAX sign control to select the sign of compare result (#183452)

The imm8[3:2] controls the sign bit behavior. 0b01 represents to select
the sign of compare result, while 0b00 select the sign of Src1.
DeltaFile
+31-31llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+31-31llvm/test/CodeGen/X86/fminimum-fmaximum.ll
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+63-633 files

LLVM/project 07d053fllvm/test/CodeGen/RISCV clmul.ll clmulr.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll clmul-sdnode.ll

Merge remote-tracking branch 'origin/main' into add-test
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+137,295-20,03010,557 files not shown
+809,694-277,52110,563 files

LLVM/project da0c41cllvm/include/llvm/ADT DenseMap.h, mlir/tools/mlir-tblgen OpDocGen.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+10-1llvm/include/llvm/ADT/DenseMap.h
+2-4mlir/tools/mlir-tblgen/OpDocGen.cpp
+12-52 files

LLVM/project 78c9dffllvm/include/llvm/ADT DenseMap.h

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+10-1llvm/include/llvm/ADT/DenseMap.h
+10-11 files

LLVM/project d5feac7llvm/include/llvm/ADT DenseMap.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+10-1llvm/include/llvm/ADT/DenseMap.h
+10-11 files

LLVM/project b7c2ddaclang/test/Driver riscv-cpus.c, clang/test/Driver/print-enabled-extensions riscv-xt-c920v2.c riscv-xt-c910v2.c

[RISCV] Add processor definitions for XuanTie C910V2 and C920V2 (#174056)

XuanTie C910V2 and C920V2 are 64-bit superscalar out-of-order CPUs:
https://www.xrvm.com/community/download?id=4530178488929423360
C910V2 is a C920V2 version without vector, zvfbfmin, zvfbfwma, zvfh and
xtheadvdot extensions.

Scheduling model will be added in a further PR.
DeltaFile
+86-0clang/test/Driver/print-enabled-extensions/riscv-xt-c920v2.c
+73-0clang/test/Driver/print-enabled-extensions/riscv-xt-c910v2.c
+50-0llvm/lib/Target/RISCV/RISCVProcessors.td
+10-0clang/test/Driver/riscv-cpus.c
+4-0clang/test/Misc/target-invalid-cpu-note/riscv.c
+1-0llvm/docs/ReleaseNotes.md
+224-06 files

LLVM/project fb371ceclang/docs ReleaseNotes.rst, clang/lib/Sema TreeTransform.h

[clang][Sema] Guard polymorphic check in TransformCXXTypeidExpr for incomplete record types (#180442)

This ensures that when querying the typeid of a record type, it is fully defined.

Fixes #176397
Fixes #63242
DeltaFile
+48-0clang/test/SemaCXX/typeid-incomplete-local-crash.cpp
+11-4clang/lib/Sema/TreeTransform.h
+1-0clang/docs/ReleaseNotes.rst
+60-43 files

LLVM/project 81c652cclang/lib/CIR/Dialect/IR CIRTypes.cpp

fix matching as check
DeltaFile
+1-0clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+1-01 files

LLVM/project d215427llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp, llvm/test/CodeGen/SystemZ zos-ada-relocations.ll

[SystemZ] Emit external aliases for indirect function descriptors in the ADA section

This is the last of the three patches aimed to support indirect symbol handling for
the SystemZ backend.

An external alias is emitted for indirect function descriptors within the ADA
section, rather than a temporary alias, while also setting all of the appropriate
symbol attributes that are needed for the HLASM streamer to emit the correct XATTR
and ALIAS instructions for the indirect symbols.

Moreover, this patch updates the `CodeGen/SystemZ/zos-ada-relocations.ll` test
as the ADA section is currently the only user of indirect symbols on z/OS.
DeltaFile
+7-4llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+5-1llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
+12-52 files

LLVM/project ac321c2llvm/include/llvm/MC MCSymbolGOFF.h MCSectionGOFF.h, llvm/lib/MC GOFFObjectWriter.cpp MCAsmInfoGOFF.cpp

[SystemZ] Emit external aliases required for indirect symbol handling support

This is the second of three patches aimed to support indirect symbol handling for
the SystemZ backend. An external name is added for both MC sections and symbols
and makes the relevant printers and writers utilize the external name when present.
Furthermore, the ALIAS HLASM instruction is emitted after every XATTR instruction.
DeltaFile
+20-15llvm/lib/MC/GOFFObjectWriter.cpp
+17-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
+9-0llvm/include/llvm/MC/MCSymbolGOFF.h
+8-0llvm/include/llvm/MC/MCSectionGOFF.h
+6-0llvm/lib/MC/MCAsmInfoGOFF.cpp
+4-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+64-156 files

LLVM/project ad410c6llvm/include/llvm/MC MCSymbolGOFF.h MCGOFFAttributes.h, llvm/lib/MC GOFFObjectWriter.cpp MCSymbolGOFF.cpp

[SystemZ] Add indirect reference bit XATTR REFERENCE(INDIRECT) for indirect symbol handling support

This is the first of three patches aimed to support indirect symbol handling for
the SystemZ backend. This PR introduces a `GOFF:ERAttr` to represent indirect
references, handles indirect symbols within `setSymbolAttribute()` by setting
the indirect reference bit, and also updates the HLASM streamer to emit
`XATTR REFERENCE(INDIRECT)` and various other combinations.
DeltaFile
+24-9llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+8-2llvm/include/llvm/MC/MCSymbolGOFF.h
+4-3llvm/lib/MC/GOFFObjectWriter.cpp
+3-1llvm/lib/MC/MCSymbolGOFF.cpp
+1-0llvm/include/llvm/MC/MCGOFFAttributes.h
+40-155 files

LLVM/project 143664fbolt/test merge-fdata-skip-truncated.test merge-fdata-no-lbr-mode.test, bolt/tools/merge-fdata merge-fdata.cpp

[BOLT][merge-fdata] Skip truncated lines in raw profile data (#183187)

Raw profile data file may contain lines truncated due to unexpected
app exit. This change is to have merge_fdata check number of fields
in each line of raw profile data file and ignore a line if the number
is not expected.
DeltaFile
+22-0bolt/tools/merge-fdata/merge-fdata.cpp
+20-0bolt/test/merge-fdata-skip-truncated.test
+3-3bolt/test/merge-fdata-no-lbr-mode.test
+3-3bolt/test/merge-fdata-bat-no-lbr.test
+2-2bolt/test/merge-fdata-mixed-mode.test
+2-2bolt/test/merge-fdata-mixed-bat-no-lbr.test
+52-106 files

LLVM/project b75222cclang/lib/CIR/CodeGen TargetInfo.h, clang/lib/CIR/Dialect/IR CIRTypes.cpp

correct nits
DeltaFile
+3-1clang/lib/CIR/CodeGen/TargetInfo.h
+2-2clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+2-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+7-53 files

LLVM/project d12870ellvm/lib/Target/RISCV RISCVOptWInstrs.cpp, llvm/test/CodeGen/RISCV opt-w-instrs-p-ext.mir

[RISCV] Add MERGE, MVM, and MVMN to isSignExtendedW in RISCVOptWInstrs. (#183433)

These instructions are a combination of AND/OR/XOR which return sign
extended values if all inputs are sign extended.
DeltaFile
+119-0llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir
+13-3llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+132-32 files

LLVM/project 8533889llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV rvp-unaligned-load-store.ll

[RISCV] Partial support for using PPAIRE.B/H to optimize unaligned load sequences. (#183423)

Patterns are based on patterns we use for Zbkb. We can't copy all
patterns because PPAIRE.B/H are a little different than PACKW/PACKH.

PACKW packs the first 16 bits of rs1 and rs2 and sign extends the upper
32 bits of rd. PACKH packs the first 8 bits of rs1 and rs2 and puts
zeros in bits 16 of rd.

PPAIRE.B copies the even bytes of rs1 to the even bytes of rd and copies
the even bytes of rs2 to the odd bytes of rd. PPAIRE.H is similar, but
copys halfwords instead of bytes. We can treat them equivalently to
PACKH/PACKW when we know that we only care about the lower halfword or
word, respectively of the result.
DeltaFile
+124-178llvm/test/CodeGen/RISCV/rvp-unaligned-load-store.ll
+27-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+6-0llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+157-1783 files

LLVM/project 5361c38llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp, llvm/test/CodeGen/SystemZ zos-ada-relocations.ll

[SystemZ] Emit external aliases for indirect function descriptors in the ADA section

This is the last of the three patches aimed to support indirect symbol handling for
the SystemZ backend.

An external alias is emitted for indirect function descriptors within the ADA
section, rather than a temporary alias, while also setting all of the appropriate
symbol attributes that are needed for the HLASM streamer to emit the correct XATTR
and ALIAS instructions for the indirect symbols.

Moreover, this patch updates the `CodeGen/SystemZ/zos-ada-relocations.ll` test
as the ADA section is currently the only user of indirect symbols on z/OS.
DeltaFile
+7-4llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+5-1llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
+12-52 files

LLVM/project dd9d242llvm/lib/Target/RISCV RISCVInstrInfoZb.td RISCVRegisterInfo.cpp, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[RISCV] Treat zext.h as a separate instruction from pack(w) with Zbkb. (#183364)

The Zbb encoding for zext.h is a subset of the encoding for pack(w).

There is a statement in the ISA manual that says "For RV32, the pack
instruction with rs2=x0 is the zext.h instruction. Hence, for RV32, any
extension that contains the pack instruction also contains the zext.h
instruction"

This patch makes the zext.h instruction mnemonic canonical when only
Zbkb is enabled. -Mno-aliases will not disable the printing of zext.h. I
believe this matches binutils.

I've taught the assembler to remap PACK/PACKW to ZEXT_H to make printing
parsed assembly match the disassembler output.
DeltaFile
+6-19llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+20-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+11-0llvm/test/MC/RISCV/rv64zcb-zbkb-valid.s
+11-0llvm/test/MC/RISCV/rv32zcb-zbkb-valid.s
+2-9llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+5-2llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+55-301 files not shown
+57-337 files

LLVM/project 8d3ab19llvm/include/llvm/MC MCSymbolGOFF.h MCSectionGOFF.h, llvm/lib/MC GOFFObjectWriter.cpp MCAsmInfoGOFF.cpp

[SystemZ] Emit external aliases required for indirect symbol handling support

This is the second of three patches aimed to support indirect symbol handling for
the SystemZ backend. An external name is added for both MC sections and symbols
and makes the relevant printers and writers utilize the external name when present.
Furthermore, the ALIAS HLASM instruction is emitted after every XATTR instruction.
DeltaFile
+19-15llvm/lib/MC/GOFFObjectWriter.cpp
+17-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
+9-0llvm/include/llvm/MC/MCSymbolGOFF.h
+8-0llvm/include/llvm/MC/MCSectionGOFF.h
+6-0llvm/lib/MC/MCAsmInfoGOFF.cpp
+4-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+63-156 files

LLVM/project f7be6a8clang/include/clang/CIR/Dialect/Builder CIRBaseBuilder.h, clang/include/clang/CIR/Dialect/IR CIRTypes.h CIRTypes.td

Handle empty AS attr as LangAs::Default and Normalize LangAs::Default a to null in PointerType
DeltaFile
+13-2clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+4-0clang/include/clang/CIR/Dialect/IR/CIRTypes.h
+4-0clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+0-2clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+21-44 files

LLVM/project ad530e8clang/lib/CIR/Dialect/IR CIRTypes.cpp

test work now yo
DeltaFile
+2-0clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+2-01 files

LLVM/project a1a56ffclang/lib/CIR/CodeGen CIRGenBuiltin.cpp

nit: Handle target AS value as unsigned int
DeltaFile
+1-1clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+1-11 files

LLVM/project d8192fdclang/include/clang/CIR/Dialect/Builder CIRBaseBuilder.h, clang/include/clang/CIR/Dialect/IR CIRTypes.h

Address first round of comments
DeltaFile
+5-6clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+2-3clang/include/clang/CIR/Dialect/IR/CIRTypes.h
+2-2clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+1-1clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+1-1clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+11-135 files

LLVM/project e71fcdfclang/include/clang/CIR/Dialect/Builder CIRBaseBuilder.h, clang/include/clang/CIR/Dialect/IR CIRAttrs.td

[CIR] Infrastructure and MemorySpaceAttrInterface for Address Spaces
DeltaFile
+150-39clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+104-4clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
+52-3clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+41-0clang/test/CIR/IR/address-space.cir
+29-3clang/test/CIR/IR/invalid-addrspace.cir
+9-11clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+385-6012 files not shown
+452-7718 files

LLVM/project 8f3dd82libc/shared/math asinpif.h, libc/src/__support/math asinpif.h

[libc][math][c23] implement `asinpif` function (#181511)

Implementing `asinpi` for single-precision. it continues what is done in
#152690 that implemented `asinpif16` with header-only approach that is
followed since #147386
DeltaFile
+152-0libc/src/__support/math/asinpif.h
+44-0libc/test/src/math/smoke/asinpif_test.cpp
+38-0libc/test/src/math/asinpif_test.cpp
+33-0libc/test/src/math/exhaustive/asinpif_test.cpp
+24-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+23-0libc/shared/math/asinpif.h
+314-023 files not shown
+431-129 files

LLVM/project 765c4e6clang/lib/Sema SemaLambda.cpp, clang/test/Modules pr178893.cppm

[clang] Don't use `VarDecl` of local variables as `ManglingContextDecl` for lambdas (#179035)

Currently, in a C++20 modules context, a `VarDecl` of a local variable
can wrongly end up as a `ManglingContextDecl` for a lambda.

Fix this by removing `ContextKind::NonInlineInModulePurview` in
`Sema::getCurrentMangleNumberContext` and add
`IsExternallyVisibleInModulePurview` checks in the appropriate places:

- For externally visible functions defined in a module purview, add a
check to `isInInlineFunction`, renaming it to
`IsInFunctionThatRequiresMangling`
- For externally visible variables defined in a module purview, add a
new `ContextKind::ExternallyVisibleVariableInModulePurview` and an
appropriate check to the `VarDecl` case

Fixes #178893

---------

    [2 lines not shown]
DeltaFile
+46-33clang/lib/Sema/SemaLambda.cpp
+29-0clang/test/Modules/pr178893.cppm
+75-332 files

LLVM/project d7bd36dmlir/lib/Bindings/Python Rewrite.cpp, mlir/test/python rewrite.py

[MLIR][Python] Handle errors in dialect conversion properly (#183320)

Before this, MLIR error capture in `apply_partial_conversion` and
`apply_full_conversion` wasn’t handled, which meant any `emitError`
would crash the entire program. This PR adds the handling.
DeltaFile
+19-0mlir/test/python/rewrite.py
+4-2mlir/lib/Bindings/Python/Rewrite.cpp
+23-22 files