LLVM/project a53bc4fllvm/cmake/modules AddLLVM.cmake, mlir/cmake/modules AddMLIR.cmake

[mlir] Reuse the MLIRIR PCH through dependencies (NFC)

Track whether an MLIR library's link closure reaches MLIRIR and reuse the
MLIRIR PCH for those libraries. Preserve higher-priority local PCHs and add an
explicit opt-out for targets whose sources are incompatible with reuse.

Relative to the core and LLVM dialect PCH parent, clean Release builds of LLVM
and MLIR with Ninja -j16 pinned to CPUs 16-31 improved as follows:

  wall:   398.79s -> 386.47s (-3.09%)
  user:  5789.14s -> 5624.02s (-2.85%)
  system: 455.05s -> 438.45s (-3.65%)

Assisted-by: Codex
DeltaFile
+60-1mlir/cmake/modules/AddMLIR.cmake
+38-0mlir/test/lib/CMake/CMakeLists.txt
+8-1llvm/cmake/modules/AddLLVM.cmake
+1-0mlir/test/lib/CMakeLists.txt
+1-0mlir/test/lib/CMake/Inputs/PCHOptOut.cpp
+1-0mlir/test/lib/CMake/Inputs/PCHOptOut.c
+109-26 files

LLVM/project 707c032mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/test/Dialect/Tosa ops.mlir invalid_extension.mlir

[mlir][tosa] Add support for MXFP SCATTER (#222288)

Tosa specification changes in
https://github.com/arm/tosa-specification/pull/78
DeltaFile
+60-0mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+16-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
+7-0mlir/test/Dialect/Tosa/ops.mlir
+7-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+98-05 files

LLVM/project 81b343fmlir/include/mlir/Dialect/LLVMIR pch.h, mlir/lib CMakeLists.txt

[mlir][LLVM] Reuse a PCH for MLIRLLVMDialect (NFC)

Build a private precompiled header from the LLVM dialect and LLVM IR headers
and use it for MLIRLLVMDialect. Build dialect libraries before conversions so
the PCH is available early and repeated parsing is avoided.

Relative to the MLIRIR PCH parent, clean Release builds of LLVM and MLIR with
Ninja -j16 pinned to CPUs 16-31 improved as follows:

  wall:   420.41s -> 398.79s (-5.14%)
  user:  6125.97s -> 5789.14s (-5.50%)
  system: 481.88s -> 455.05s (-5.57%)

Assisted-by: Codex
DeltaFile
+14-0mlir/include/mlir/Dialect/LLVMIR/pch.h
+3-0mlir/lib/Dialect/LLVMIR/CMakeLists.txt
+1-1mlir/lib/CMakeLists.txt
+18-13 files

LLVM/project 2d70439llvm/utils/gn/secondary/lldb/test BUILD.gn

[gn] port eb5cd179549d68 (#222476)
DeltaFile
+0-1llvm/utils/gn/secondary/lldb/test/BUILD.gn
+0-11 files

LLVM/project cdf702dmlir/include/mlir/IR pch.h, mlir/lib CMakeLists.txt

[mlir] Reuse a precompiled header for MLIRIR (NFC)

Build a private precompiled header from the common MLIR IR headers and use it
for MLIRIR. Build Support and IR first so the PCH is available early, and
qualify the LLVM LSP Location name that the broader header surface exposes.

On current main, clean Release builds of LLVM and MLIR with Ninja -j16 pinned
to CPUs 16-31 improved as follows:

  wall:   535.99s -> 420.41s (-21.56%)
  user:  7550.29s -> 6125.97s (-18.86%)
  system: 569.85s -> 481.88s (-15.44%)

Assisted-by: Codex
DeltaFile
+20-0mlir/include/mlir/IR/pch.h
+8-8mlir/lib/Tools/mlir-lsp-server/LSPServer.cpp
+2-2mlir/lib/CMakeLists.txt
+3-0mlir/lib/IR/CMakeLists.txt
+33-104 files

LLVM/project 265bb9fclang/lib/Basic/Targets AMDGPU.cpp AMDGPU.h, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Migrate R600 onto generated TargetParser bitset (#222461)

Follow the new amdgcn system so we don't have to carry 2 different
forms of this infrastructure.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+80-36llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+12-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+8-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+1-5clang/lib/Basic/Targets/AMDGPU.cpp
+2-4clang/lib/Basic/Targets/AMDGPU.h
+5-0llvm/lib/Target/AMDGPU/R600Processors.td
+108-451 files not shown
+111-457 files

LLVM/project 70e79a0llvm/lib/Target/X86/AsmParser X86AsmParser.cpp, llvm/test/MC/X86 x86_errors.s

[X86] Reject a register where a memory operand displacement belongs (#216068)

Fixes #61438
DeltaFile
+13-0llvm/test/MC/X86/x86_errors.s
+5-1llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+18-12 files

LLVM/project 7c5e5callvm/utils profcheck-xfail.txt

[ProfCheck] Removing passing tests from xfail list (#222473)

These tests appear to be passing/deleted as of 9/9/26.
DeltaFile
+0-4llvm/utils/profcheck-xfail.txt
+0-41 files

LLVM/project f1b62b8clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl

First attempt implementing InterlockedCompareExchangeFloatBitwise
DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-3clang/lib/Sema/SemaHLSL.cpp
+271-35 files not shown
+302-611 files

LLVM/project f861da9clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

First attempt implementing InterlockedCompareStoreFloatBitwise
DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+35-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+20-8clang/lib/Sema/SemaHLSL.cpp
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+251-86 files not shown
+316-1312 files

LLVM/project 31a16a5clang/lib/Sema SemaHLSL.cpp HLSLExternalSemaSource.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl RWByteAddressBuffer-InterlockedCompareExchange.hlsl

First attempt implementing InterlockedCompareExchange
DeltaFile
+113-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchange-errors.hlsl
+70-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchange.hlsl
+43-24clang/lib/Sema/HLSLExternalSemaSource.cpp
+44-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchange.hlsl
+24-12clang/lib/Sema/SemaHLSL.cpp
+35-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl
+329-366 files not shown
+417-5212 files

LLVM/project 92e630bclang/test/AST/HLSL Textures-vector-AST.hlsl Textures-scalar-AST.hlsl, clang/test/CodeGenHLSL/resources Textures-Sample.hlsl Textures-Mips.hlsl

[HLSL] Add Texture3D and RWTexture3D types (#220438)

Fixes https://github.com/llvm/llvm-project/issues/194739 and fixes
https://github.com/llvm/llvm-project/issues/194743

This PR implements Texture3D and RWTexture3D and adds+modifies tests for
the two types.

Assisted by: Claude Opus 5

---------

Co-authored-by: Finn Plummer <mail at inbelic.dev>
DeltaFile
+425-401clang/test/AST/HLSL/Textures-scalar-AST.hlsl
+424-400clang/test/AST/HLSL/Textures-vector-AST.hlsl
+54-20clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
+32-0clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
+16-9clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
+17-0clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
+968-83019 files not shown
+1,145-83325 files

LLVM/project 3cff976clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Sema HLSLExternalSemaSource.cpp

First attempt implementing InterlockedCompareStore
DeltaFile
+88-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStore-errors.hlsl
+54-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStore.hlsl
+45-7clang/lib/Sema/HLSLExternalSemaSource.cpp
+37-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStore.ll
+29-7clang/lib/CodeGen/CGHLSLBuiltins.cpp
+36-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStore.hlsl
+289-147 files not shown
+397-1613 files

LLVM/project ff2b4c2llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Count the intrinsics that really become calls when refusing promotion
DeltaFile
+81-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+30-9llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+111-92 files

LLVM/project d35391ellvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll

Do not add a second lifetime start when allocating VGPRs again
DeltaFile
+21-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+17-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+0-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+38-43 files

LLVM/project 1f7b3e5llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Promote private objects into the VGPR address space via flag
DeltaFile
+279-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+138-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+1-35llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+23-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+19-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+460-395 files

LLVM/project 5bab363llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Carry null operands and intrinsic names across when promoting to VGPRs
DeltaFile
+145-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+42-2llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+187-22 files

LLVM/project f940596llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-private-object-vgprs.mir

Propagate object liveness to every changed successor, not only back edges
DeltaFile
+56-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+14-4llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+70-42 files

LLVM/project ebb7ec3llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-budget.ll

Diagnose an object that does not fit the function's register budget
DeltaFile
+82-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-budget.ll
+36-13llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+118-132 files

LLVM/project cc91d70llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Refuse promotion only when the object is live across a call
DeltaFile
+183-4llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+117-15llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+300-192 files

LLVM/project 929d2a7llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll

Treat a sub-dword VGPR-memory load as divergent too
DeltaFile
+83-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-divergent.ll
+3-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+86-12 files

LLVM/project 3d934ebllvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll

Diagnose inline asm that clobbers a VGPR-memory object's registers
DeltaFile
+93-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-asm-clobber.ll
+31-5llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+124-52 files

LLVM/project 0bc0c41llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-across-call.ll as-vgpr-private-object-vgprs.mir

Allocate and reserve registers for address space 13 objects
DeltaFile
+340-0llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+178-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-object-regalloc.ll
+140-12llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+133-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+106-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+80-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+977-1218 files not shown
+1,280-2324 files

LLVM/project c5170f3llvm/unittests/Target/AMDGPU VGPRAsMemory.cpp

Pin the width guard that keeps sub-dword accesses out of aliasing decisions
DeltaFile
+66-0llvm/unittests/Target/AMDGPU/VGPRAsMemory.cpp
+66-01 files

LLVM/project fe6a59bllvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-index-demanded-bits.ll

Regenerate the demanded-bits expectations for the gfx1250 entry sequence
DeltaFile
+24-16llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-index-demanded-bits.ll
+24-161 files

LLVM/project 8c6abb8llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits-encoding.ll as-vgpr-bits.ll

Regenerate the sub-dword expectations for the M0 setup change
DeltaFile
+38-54llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-control-flow.ll
+30-49llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits.ll
+1-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-encoding.ll
+69-1043 files

LLVM/project f2fb95bllvm/lib/Target/AMDGPU AMDGPULowerIdxOps.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir as-vgpr-verifier.mir

Check the encodings of the sub-dword VGPR-memory accesses
DeltaFile
+71-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-encoding.ll
+0-40llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-verifier-m0.mir
+32-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-verifier.mir
+8-18llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-8llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-lower-idx-ops.mir
+2-10llvm/lib/Target/AMDGPU/AMDGPULowerIdxOps.cpp
+121-761 files not shown
+125-797 files

LLVM/project 9b3c2fcllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp

Document the sub-dword access rules for the VGPR address space
DeltaFile
+14-12llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-0llvm/docs/AMDGPUUsage.rst
+21-122 files

LLVM/project 2a1620dllvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll as-vgpr-index-demanded-bits.ll

Fix tests
DeltaFile
+105-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-index-demanded-bits.ll
+10-5llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits.ll
+115-52 files

LLVM/project 6871e98llvm/lib/Target/AMDGPU SIInstructions.td SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir

Inherit the M0 operand when expanding the sub-dword VGPR-memory pseudos
DeltaFile
+21-4llvm/lib/Target/AMDGPU/AMDGPULowerIdxOps.cpp
+12-11llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-lower-idx-ops.mir
+1-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-2llvm/lib/Target/AMDGPU/SIInstructions.td
+34-194 files