LLVM/project bdd0f4cllvm/lib/Target/AArch64 AArch64InstrInfo.cpp, llvm/test/CodeGen/AArch64 atomic-ops-lse.ll cheap-as-a-move-MOVaddr.ll

[AArch64] Consider MOVaddr* as cheap if fuse-adrp-add
DeltaFile
+88-88llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+55-0llvm/test/CodeGen/AArch64/cheap-as-a-move-MOVaddr.ll
+9-9llvm/test/CodeGen/AArch64/memcmp.ll
+8-8llvm/test/CodeGen/AArch64/atomic-ops.ll
+6-6llvm/test/CodeGen/AArch64/cgdata-outline-gvar.ll
+9-0llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+175-1116 files not shown
+190-12012 files

LLVM/project b0192c3mlir/lib/Target/SPIRV/Deserialization Deserializer.cpp, mlir/lib/Target/SPIRV/Serialization Serializer.cpp

[mlir][spirv] (De)serialize Offset, XfbBuffer and XfbStride decorations (#181835)

Process decorations number 35, 36 and 37 in SPIR-V deserializer and
serializer; add a simple test case.
DeltaFile
+9-0mlir/test/Target/SPIRV/decorations.mlir
+3-0mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
+3-0mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
+15-03 files

LLVM/project d98d625llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 hoist-and-by-const-from-shl-in-eqcmp-zero.ll known-pow2.ll

[X86] combineSETCC - drop unnecessary shift amount bounds check for larger-than-legal ICMP_ZERO(AND(X,SHL(1,IDX))) folds (#182021)

For i128 etc. bittest patterns, we split the pattern into a i32
extraction + i32 bittest.

But we were unnecessarily limiting this to inbounds shift amounts. I
wrote this fold at the same time as narrowBitOpRMW where we needed the
bounds check for safe memory access, which isn't necessary in
combineSETCC.

Fix 2 of 2 for #147216
DeltaFile
+62-167llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+12-17llvm/lib/Target/X86/X86ISelLowering.cpp
+8-13llvm/test/CodeGen/X86/known-pow2.ll
+82-1973 files

LLVM/project a28d89bllvm/lib/CodeGen RDFLiveness.cpp, llvm/test/CodeGen/Hexagon rdf-liveness-phi-invalidation.ll

[RDF] Fix DenseMap reference invalidation in computePhiInfo (#182144)

In Liveness::computePhiInfo, the reference `RefMap &RUM =
RealUseMap[PA.Id]` can be invalidated when the inner loop inserts into
RealUseMap via `RealUseMap[P.first][SS.Id]`. If `P.first` is a new key,
the DenseMap may rehash, invalidating the RUM reference and any
iterators into it.

Fix by making a copy of the map value instead of holding a reference.
This is detected by _GLIBCXX_DEBUG (enabled via EXPENSIVE_CHECKS) which
tracks iterator validity on std::unordered_map (RefMap).
DeltaFile
+87-0llvm/test/CodeGen/Hexagon/rdf-liveness-phi-invalidation.ll
+5-1llvm/lib/CodeGen/RDFLiveness.cpp
+92-12 files

LLVM/project 46bfd69llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[LV] NFCI: Add RecurKind to VPPartialReductionChain (#181705)

This avoids having to pass around the RecurKind or re-figure it out from
the VPReductionPHI node.

This is useful in a follow-up PR, where we need to distinguish between a
`Sub` and `AddWithSub` recurrence, which can't be deduced from the
`ReductionBinOp` field.
DeltaFile
+24-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+24-141 files

LLVM/project 85688fbmlir/include/mlir/IR OpBase.td AttrTypeBase.td, mlir/lib/TableGen AttrOrTypeDef.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+45-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+10-2mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+8-2mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
+10-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+9-0mlir/include/mlir/IR/OpBase.td
+8-0mlir/include/mlir/IR/AttrTypeBase.td
+90-43 files not shown
+110-49 files

LLVM/project 15515efmlir/test/Dialect/Tosa tosa-narrow-f64-to-f32.mlir tosa-narrow-f64-to-f32-aggressive.mlir

[mlir][tosa] Fix dense_resource data alignment in tosa-narrow-* tests (#182253)

The alignment of int64 and float64 dense resource should be 8 and not 4
DeltaFile
+1-1mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32.mlir
+1-1mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32-aggressive.mlir
+1-1mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32-aggressive.mlir
+1-1mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32.mlir
+4-44 files

LLVM/project 72344f5llvm/test/CodeGen/ARM/ParallelDSP multi-use-loads.ll, llvm/test/CodeGen/Thumb2 mve-satmul-loops.ll mve-fpclamptosat_vec.ll

[RegisterCoalescer] Prefer copy over rematerialization when smaller

When the source register has multiple uses, compare instruction sizes
before rematerializing. If the copy is smaller than the rematerialized
instruction, prefer keeping the copy to reduce code size.

Additionally, register-to-register copies are often eliminated by
register renaming on modern out-of-order CPUs, making them effectively
free at runtime.
DeltaFile
+269-258llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+98-98llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
+62-78llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
+61-61llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+52-55llvm/test/CodeGen/Thumb2/mve-scmp.ll
+52-51llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
+594-60149 files not shown
+1,008-1,01155 files

LLVM/project b2c2df6llvm/lib/Target/AMDGPU VOPCInstructions.td, llvm/test/MC/AMDGPU gfx12_asm_vopc.s gfx12_asm_vopcx.s

[AMDGPU] Add VOPC to gfx13
DeltaFile
+1,763-1,747llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+186-181llvm/lib/Target/AMDGPU/VOPCInstructions.td
+78-50llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+68-28llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+56-14llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+4-25llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+2,155-2,04523 files not shown
+2,227-2,06129 files

LLVM/project fb5e2e0mlir/include/mlir/IR OpBase.td, mlir/lib/TableGen AttrOrTypeDef.cpp Operator.cpp

[MLIR] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+45-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+10-2mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+10-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+8-2mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
+9-0mlir/include/mlir/IR/OpBase.td
+8-0mlir/lib/TableGen/Operator.cpp
+90-43 files not shown
+110-49 files

LLVM/project 3cdb2e2flang/lib/Semantics resolve-directives.cpp, flang/test/Semantics/OpenMP common-block_copyin.f90

[Flang][OpenMP] Fix for threadprivate check in copyin clause (#181354)

Use the ultimate symbol in the threadprivate check

Fixes #180094
DeltaFile
+12-0flang/test/Semantics/OpenMP/common-block_copyin.f90
+3-4flang/lib/Semantics/resolve-directives.cpp
+15-42 files

LLVM/project b4386f7flang/lib/Semantics resolve-directives.cpp

[flang][OpenMP] Push context for all directives in resolve-directives.cpp (#181736)

The visitors for loop and simple-standalone constructs had switch
statements that explicitly listed all directives in the category, and
pushed the context for them.

The visitor for OmpBlockConstruct listed a selection of block-associated
directives, but they are the only ones for which OmpBlockConstruct is
created directly without a subclass.
DeltaFile
+8-107flang/lib/Semantics/resolve-directives.cpp
+8-1071 files

LLVM/project 1fdae49llvm/lib/Target/AMDGPU VOPCInstructions.td, llvm/test/MC/AMDGPU gfx12_asm_vopcx.s gfx12_asm_vopc.s

[AMDGPU] Add VOPC to gfx13
DeltaFile
+1,763-1,747llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+1,246-1,232llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+186-181llvm/lib/Target/AMDGPU/VOPCInstructions.td
+89-110llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+78-50llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+68-28llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+3,430-3,34823 files not shown
+3,502-3,36429 files

LLVM/project bca95d1lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional TestDataFormatterGenericOptional.py, lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/shared_ptr TestDataFormatterStdSharedPtr.py

Disable shared builds for tests failing on Windows (#182249)

PR #181720 introduced shared builds for LLDB API tests to improve test
efficiency. But several data formatter tests requiring PDB debug info
are failing on Windows x64 and AArch64 platforms.

This patch disables shared builds for these tests by setting
SHARED_BUILD_TESTCASE = False

The shared build optimization breaks these tests because they reuse
build artifacts between test methods
The test runs may could use multiple methods with different debug
formats or compiler flags. When a test runs first it builds with one set
of flags, but then it runs again but **make** sees the source unchanged
so it skips rebuilding and reuses the same old binary instead of
rebuilding with correct flags.
DeltaFile
+1-0lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
+1-0lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/shared_ptr/TestDataFormatterStdSharedPtr.py
+1-0lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/span/TestDataFormatterStdSpan.py
+1-0lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/string_view/TestDataFormatterStdStringView.py
+1-0lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/TestDataFormatterStdU8String.py
+1-0lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string_view/TestDataFormatterStdU8StringView.py
+6-05 files not shown
+11-011 files

LLVM/project 6a78d37clang/lib/StaticAnalyzer/Core ExprEngine.cpp, clang/test/Analysis uninitialized-branch.c

[analyzer] Add BranchCondition callback to 'switch' (#182058)

Previously the condition of a 'switch' statement did not trigger a
`BranchCondition` callback. This commit resolves this old FIXME and e.g.
lets the checker `core.uninitialzed.Branch` report code where the
condition of a `switch` statement is undefined.

This commit also contains a very small unrelated change that removes a
short fragment of dead code from `processBranch`.
DeltaFile
+64-54clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+61-0clang/test/Analysis/uninitialized-branch.c
+1-0clang/unittests/StaticAnalyzer/BlockEntranceCallbackTest.cpp
+126-543 files

LLVM/project 63492callvm/test/tools/llubi gep.ll alloca.ll, llvm/tools/llubi/lib Interpreter.cpp Value.h

[llubi] Add support for GEP/alloca/inttoptr (#181861)

This patch mainly adds support for GEP. To test GEP functionality,
alloca/inttoptr are also introduced.
DeltaFile
+210-1llvm/tools/llubi/lib/Interpreter.cpp
+146-0llvm/test/tools/llubi/gep.ll
+41-0llvm/test/tools/llubi/alloca.ll
+17-0llvm/test/tools/llubi/inttoptr.ll
+11-5llvm/tools/llubi/lib/Value.h
+10-4llvm/tools/llubi/lib/Value.cpp
+435-106 files not shown
+492-1412 files

LLVM/project 956290cllvm/test/CodeGen/AMDGPU/GlobalISel divergence-divergent-i1-used-outside-loop.mir divergence-structurizer.mir

update failing test checks
DeltaFile
+132-171llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
+101-127llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
+58-85llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
+17-27llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+15-21llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
+2-5llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
+325-4361 files not shown
+327-4417 files

LLVM/project 5ed643cllvm/test/CodeGen/SPIRV/debug-info debug-type-pointer.ll debug-opeation-expression-debugValue.ll

[SPIRV] Simplify tests checks by removing MIR checks. SPIRV checks are enough.
DeltaFile
+0-39llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
+0-39llvm/test/CodeGen/SPIRV/debug-info/debug-opeation-expression-debugValue.ll
+0-38llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll
+0-18llvm/test/CodeGen/SPIRV/debug-info/debug-type-template.ll
+0-17llvm/test/CodeGen/SPIRV/debug-info/debug-type-enum.ll
+0-17llvm/test/CodeGen/SPIRV/debug-info/debug-macro-def.ll
+0-16813 files not shown
+0-30919 files

LLVM/project d0ead09llvm/test/CodeGen/SPIRV/debug-info debug-option-off.ll debug-opeation-expression-debugValue.ll

[SPIRV] Simplify debug info tests by only testing the new option (off) effect only once.
DeltaFile
+13-0llvm/test/CodeGen/SPIRV/debug-info/debug-option-off.ll
+0-6llvm/test/CodeGen/SPIRV/debug-info/debug-opeation-expression-debugValue.ll
+0-4llvm/test/CodeGen/SPIRV/debug-info/debug-macro-def.ll
+0-4llvm/test/CodeGen/SPIRV/debug-info/debug-scope-noscope-localvariable.ll
+0-4llvm/test/CodeGen/SPIRV/debug-info/debug-build-identifier-storagepath.ll
+0-4llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
+13-2215 files not shown
+13-5421 files

LLVM/project 7c7950bllvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp, llvm/test/CodeGen/SPIRV/debug-info crash-000.ll debug-inlinedAt-Declare.ll

[SPIRV] Fix crash due to incorrect state of the SPIRVGlobalRegistry.

Also, simplified checks in test that were not stricly necessary and were failing with this fix.
DeltaFile
+15-0llvm/test/CodeGen/SPIRV/debug-info/crash-000.ll
+0-11llvm/test/CodeGen/SPIRV/debug-info/debug-inlinedAt-Declare.ll
+2-0llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+17-113 files

LLVM/project 1636fb2llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-inlinedAt-Declare.ll debug-type-pointer.ll

--Added support for the extension SPV_KHR_non_semantic_info
--Added support for the extension SPV_KHR_relaxed_extended_instruction
--Added instructions from the documentation of the extension.
--Added supporting tests for the same.
DeltaFile
+2,223-209llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+164-0llvm/test/CodeGen/SPIRV/debug-info/debug-inlinedAt-Declare.ll
+65-67llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
+126-0llvm/test/CodeGen/SPIRV/debug-info/debug-opeation-expression-debugValue.ll
+59-58llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll
+117-0llvm/test/CodeGen/SPIRV/debug-info/debug-line.ll
+2,754-33424 files not shown
+3,837-36330 files

LLVM/project 0ee8f72llvm/include/llvm/ADT GenericUniformityImpl.h GenericSSAContext.h, llvm/lib/CodeGen MachineSSAContext.cpp

review: remove ir header
DeltaFile
+5-9llvm/include/llvm/ADT/GenericUniformityImpl.h
+4-0llvm/lib/IR/SSAContext.cpp
+2-0llvm/lib/CodeGen/MachineSSAContext.cpp
+1-0llvm/include/llvm/ADT/GenericSSAContext.h
+12-94 files

LLVM/project a606feellvm/lib/CodeGen MachineUniformityAnalysis.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel divergence-divergent-i1-used-outside-loop.mir divergence-structurizer.mir

track uniform value for machine uniformity
DeltaFile
+171-132llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
+127-101llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
+85-58llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
+27-17llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+21-15llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
+12-7llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+443-3302 files not shown
+453-3348 files

LLVM/project c17a312llvm/include/llvm/ADT GenericUniformityImpl.h GenericUniformityInfo.h, llvm/lib/Analysis UniformityAnalysis.cpp

track uniform values at SSA level
DeltaFile
+23-2llvm/include/llvm/ADT/GenericUniformityImpl.h
+17-0llvm/lib/Analysis/UniformityAnalysis.cpp
+12-0llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+1-0llvm/include/llvm/ADT/GenericUniformityInfo.h
+53-24 files

LLVM/project 93dc44dllvm/lib/Target/SPIRV SPIRVGlobalRegistry.cpp SPIRVGlobalRegistry.h

rename
DeltaFile
+94-84llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+4-4llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+98-882 files

LLVM/project 5e226b1clang-tools-extra Maintainers.rst

[clang-tidy][NFC] move Cai Congcong to inactive maintainer (#182248)

DeltaFile
+1-3clang-tools-extra/Maintainers.rst
+1-31 files

LLVM/project d1b161cllvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass-powi.ll

Avoid short circuiting call if exponent is zero
DeltaFile
+4-4llvm/test/Transforms/Attributor/nofpclass-powi.ll
+1-1llvm/lib/Analysis/ValueTracking.cpp
+5-52 files

LLVM/project a13442dllvm/lib/Support KnownFPClass.cpp, llvm/test/Transforms/Attributor nofpclass-powi.ll

It was the right way the first time
DeltaFile
+8-8llvm/test/Transforms/Attributor/nofpclass-powi.ll
+6-3llvm/lib/Support/KnownFPClass.cpp
+14-112 files

LLVM/project d98c1a3llvm/lib/Support KnownFPClass.cpp, llvm/test/Transforms/Attributor nofpclass-powi.ll

ValueTracking: Handle tracking nan through powi

Nans should propagate simply, the infinity cases are complicated.
DeltaFile
+161-1llvm/test/Transforms/Attributor/nofpclass-powi.ll
+12-0llvm/lib/Support/KnownFPClass.cpp
+173-12 files

LLVM/project d7b590bllvm/lib/Target/RISCV RISCVVectorPeephole.cpp, llvm/test/CodeGen/RISCV/rvv vmerge-peephole.mir

[RISCV] Ensure false dominates in vmerge peephole (#181664)

When folding vmerge into it's true operand, true will eventually use the
false operand as its passthru, but we don't check that the instruction
defining false dominates true. This can cause a use before def.

Fix this by sinking true past false. We already do this for the mask, so
this does it in the same call to ensureDominates.

We don't seem to run into this with current codegen but upcoming changes
to RISCVVLOptimizer expose it.
DeltaFile
+11-5llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+13-0llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
+24-52 files