[WebAssembly][DAGCombine] Avoid scalarizing v8i8 to v8f16 conversions (#213636)
WebAssembly FP16 can convert `v8i16` to `v8f16`, but direct `v8i8` to
`v8f16` conversions were scalarized during SelectionDAG type
legalization.
This results in lane extractions, scalar conversions, calls to
`__truncsfhf2`, and reconstruction of the result vector.
We should extend `v8i8` to `v8i16` in `performVectorExtendToFPCombine`
before type legalization. This allows the existing WebAssembly combines
to select:
- `i16x8.extend_low_i8x16_{s,u}`
- `f16x8.convert_i16x8_s`
[mlir][NFC] Remove internal linkage from core header function templates (#214756)
These are more of the cases fixed alongside #208001, which enabled
-Wunused-template under -Wall. Each template is `static` in a widely
included header, so clang warns in every TU that includes it without
instantiating it. Dropping `static` gives them vague linkage and
silences the warning.
[mlir][NFC] Remove internal linkage from reshape op helper templates (#214759)
Another case of the cleanup done for #208001, which enabled
-Wunused-template under -Wall. Both helpers are `static` in
ReshapeOpsUtils.h, which reaches many TUs via Linalg.h, Tensor.h and
MemRef.h, so clang warns wherever they are not instantiated. Dropping
`static` gives them vague linkage.
[RISCV][NFC] Move ZacasABIFix Pass Declaration
This change moves them into their own header, as has been done for the
other NewPM passes.
Assisted-by: AI
[RISCV][NFC] Move RISCVCodeGenPrepare Declarations
This change moves them into their own header, as has been done for the
other NewPM passes.
Assisted-by: AI
[Perf2bolt] Support multi-PID filtering for multiple perf inputs (#215541)
#199324 added support for multiple perf inputs in perf2bolt. Building on
that, this patch additionally supports filtering by multiple PIDs via
--pid=pid1,pid2...
[RISCV][NFC] Move ZacasABIFix Pass Declaration
This change moves them into their own header, as has been done for the
other NewPM passes.
Assisted-by: AI
[RISCV][NFC] Move RISCVCodeGenPrepare Declarations
This change moves them into their own header, as has been done for the
other NewPM passes.
Assisted-by: AI
[RISCV] Port Gather/Scatter Lowering to NewPM (#215669)
This change also adds some missing pass dependencies to the legacy
version of the pass, to reflect some analyses that are already being
used.
Assisted-by: AI
[TypePromotion][RISCV][ARM] Ignore the condition operand of selects. (#215685)
We don't need to promote the condition operand in order to promote a
select. It must always be an i1 type so it doesn't matter where it comes
from.
The change to pr148084.ll is a regression, but I don't think it's
directly related to select. TypePromotion is using a zero extend
promotion which makes constants that are harder to materialize and
prevents the use of `not`. This kind of thing can happen independent of
selects being involved.
[LoongArch] Fold shifted vector extract comparisons
Fold comparisons of the form:
(shl (extract_vector_elt X, I), GRLen - EleBits) ==/!= 0
into:
(extract_vector_elt X, I) ==/!= 0
When the shift amount equals `GRLen - EleBits`, the left shift only moves
the extracted element into the most significant bits without affecting
whether the value is zero. This canonicalization exposes
EXTRACT_VECTOR_ELT to later combines and enables selecting
VPICKVE2GR_* instructions directly.
[CIR] Fix a linking problem with a abi_tag deduced lambda (#215702)
This showed up in self build, but only happens when there is a lambda
with a deduced return type inside another lambda, that returns a type
with an abi_tag on it (std::string in this case). The problem was that
we weren't pulling our mangled name out of the cache, and instead were
re-calculating it every time. This takes code effectively-exactly from
classic-codegen an d puts it into CIRGenModule.cpp
Note the teest is a little fragile for the reproducer, so it needs to be
its own file. Also, there are some parts that are not necessary in it to
reproduce (the 'i' in particular) because this avoids us having 'padded'
lambdas, which results in a call-conv NYI. I considered disabling that,
but it is more work to go back and un-do that flag later, than to just
deal with an extra 'i' for the near future.
[AMDGPU] Gate TBUFFER merging on relaxed OOB mode (#212695)
SILoadStoreOptimizer can combine adjacent TBUFFER accesses into a wider
typed buffer instruction. This changes the granularity of hardware OOB
handling and may affect neighboring components when an access is
partially
out of bounds.
Only allow TBUFFER load/store merging when
`amdgpu.tbuffer.oob.mode` is set to relaxed. Keep the accesses separate
when
the flag is absent, any, or strict to preserve strict OOB semantics.
Reference: https://github.com/llvm/llvm-project/pull/160922