LLVM/project 29cd0f5 — llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/hlsl-resources ImageHandleCallArg.ll

[SPIR-V] Define image handles used outside image intrinsics (#238050)

Image intrinsics reload the handle themselves, so other users such as
calls read an undefined vreg
DeltaFile
+28-0llvm/test/CodeGen/SPIRV/hlsl-resources/ImageHandleCallArg.ll
+2-7llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+30-72 files

LLVM/project b3c7948 — llvm/lib/Target/RISCV RISCVLoadStoreOptimizer.cpp

[RISCV] Assert ordering in tryConvertToXqcilsmLdStPair (#238386)

The code to handle the second instruction having the lower offset was
broken: it intended to swap its references to the data operands of the
two instructions, but since they were references it actually swapped
the MachineOperand objects themselves, corrupting parent pointers and
use-def lists.

However this case is unreachable because the only caller, via
mergePairedInsns, always orders the instructions by offset first. So
remove the swap and assert the ordering instead.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+3-7llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+3-71 files

LLVM/project e3b70d1 — llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-ldexp.ll

 [InstCombine] Handle denormal mode for ldexp in SimplifyDemandedUseFPClass (#238189)

Fixes https://github.com/llvm/llvm-project/issues/229985

Demands `fcNegSubnormal` if inputs could flush to positive zero, and
`fcNegNormal | fcNegSubnormal` if outputs could flush to positive zero.
Also adds test coverage to ensure that input/output denormal mode
handling is done correctly in case we refine `SrcDemandedMask` based on
`KnownExpBits` in the future.

AI Disclosure:
I used Claude Opus 5 to help write the tests
DeltaFile
+265-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-ldexp.ll
+15-8llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+280-82 files

LLVM/project 58a4f7c — clang/lib/StaticAnalyzer/Core ExprEngine.cpp, clang/test/Analysis matrix-subscript.c

[analyzer] Fix crash upon encountering `MatrixSubscriptExpr` (#238268)

The analyzer currently does not support expressions of kind
`MatrixSubscriptExpr`, however, previously, the switch cases of these
expressions in `ExprEngine::Visit` were marked as `llvm_unreachable`.

This patch moves `MatrixSubscriptExpr` and `MatrixSingleSubscriptExpr`
into the group of switch cases which are unhandled, so that code with
these expressions can still be analyzed without crashing.

Fixes: #237351
DeltaFile
+2-9clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+9-0clang/test/Analysis/matrix-subscript.c
+11-92 files

LLVM/project 781fab3 — mlir/lib/Dialect/Tosa/Transforms TosaValidation.cpp, mlir/test/Dialect/Tosa tosa-validation-invalid.mlir

[mlir][tosa] Add slice bounds validation (#238385)

Fixes slice validation check after being dropped in
https://github.com/llvm/llvm-project/pull/234584.

Assisted-by: Codex
DeltaFile
+53-0mlir/test/Dialect/Tosa/tosa-validation-invalid.mlir
+22-0mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+75-02 files

LLVM/project bada15c — llvm/test/CodeGen/AMDGPU regalloc-spill-wmma-scale.ll

Apply suggestion from @chinmaydd
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
+3-31 files

LLVM/project c31fe5f — llvm/test/CodeGen/AMDGPU vector-reduce-fmaximum.ll llvm.amdgcn.mfma.ll

[AMDGPU][NFC] Clean up pre-gfx125x test RUN lines

Drop flags that match defaults: -verify-machineinstrs in .ll tests,
-global-isel=0 in tests without a GlobalISel run, and redundant
-global-isel-abort. Use subarch triples instead of amdgcn plus -mcpu.
Error-only MC runs use -filetype=null.

Change-Id: Ic8e2469780e32dbe204a032fcf9d91a1e8b737d2
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+11-11llvm/test/CodeGen/AMDGPU/minimumnum.ll
+11-11llvm/test/CodeGen/AMDGPU/maximumnum.ll
+10-10llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+10-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+10-10llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+10-10llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+62-6280 files not shown
+203-20386 files

LLVM/project c408d80 — llvm/test/CodeGen/AMDGPU trans-bf16-omod.ll s-wakeup-barrier.ll, llvm/test/MC/AMDGPU gfx1251_asm_wmma_w32.s

[AMDGPU][NFC] Clean up gfx125x test RUN lines

Drop flags that match defaults: -verify-machineinstrs in .ll tests,
-global-isel=0 in tests without a GlobalISel run, and redundant
-global-isel-abort. Use subarch triples instead of amdgcn plus -mcpu.
Error-only MC runs use -filetype=null.

Change-Id: I22e9cf71556173486cd9bbed4123ee4644dd1cd8
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
+3-3llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
+2-2llvm/test/Verifier/AMDGPU/llvm.amdgcn.cooperative.atomic.ll
+2-2llvm/test/MC/AMDGPU/gfx1251_asm_wmma_w32.s
+2-2llvm/test/CodeGen/AMDGPU/trans-bf16-omod.ll
+2-2llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
+14-1422 files not shown
+46-4628 files

LLVM/project 873be26 — llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/Attributor nofpclass-canonicalize.ll

[InstCombine] Correctly handle denormal modes for `llvm.canonicalize` (#237096)

Adds proper FTPZ/DAPZ support to `SimplifyDemandedUseFPClass`, so
`fcPosZero` will demand `fcNegSubnormal` under DAPZ and etc.

AI Disclosure:
I used Claude Opus 5 to help write the tests.
DeltaFile
+904-3llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
+20-0llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+5-3llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+929-63 files

LLVM/project 6017a1f — llvm/test/CodeGen/AMDGPU s-wakeup-barrier.ll llvm.amdgcn.sin.bf16.ll, llvm/test/MC/AMDGPU gfx13_asm_vop3_err.s

[AMDGPU][NFC] Clean up gfx13 test RUN lines (#238104)

Drop flags that match defaults: `-verify-machineinstrs` in `.ll` tests,
`-global-isel=0` in tests without a GlobalISel run, and redundant
`-global-isel-abort`.

Use subarch triples instead of amdgcn plus `-mcpu`. 

Error-only MC runs use `-filetype=null`.
DeltaFile
+4-4llvm/test/MC/AMDGPU/gfx13_asm_vop3_err.s
+2-2llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/cachepolicy.cfs.ll
+14-1412 files not shown
+26-2618 files

LLVM/project 331b53d — lld/MachO SyntheticSections.cpp, lld/MachO/Arch ARM64.cpp

[lld][MachO] Support Objective-C class selector stubs (#219744)

Support Objective-C class selector stubs in lld's Mach-O backend.

This consumes the class-stub symbols emitted by Clang in [ObjC] Emit
class msgSend stub calls (#186433), using the form
`_objc_msgSendClass$<selector>$_OBJC_CLASS_$_<class>`.

Class stubs load the class object into `x0`, load the selector into
`x1`, and branch to `_objc_msgSend`. Local class symbols are
materialized directly with `adrp`/`add`; dylib or dynamic class symbols
are loaded indirectly.

The implementation also tracks the resolved class symbol before dead
stripping so live class stubs can retain the needed class definition
without keeping dead dylib references alive.
DeltaFile
+379-0lld/test/MachO/arm64-objc-class-stubs.s
+172-0lld/test/MachO/arm64-objc-class-stubs-weak.s
+115-14lld/MachO/SyntheticSections.cpp
+85-0lld/MachO/Arch/ARM64.cpp
+82-0lld/test/MachO/arm64-objc-class-stubs-dead.s
+46-0lld/test/MachO/objc-class-stubs-unsupported.s
+879-145 files not shown
+949-2111 files

LLVM/project 6949ecb — llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll, llvm/test/Transforms/SLPVectorizer/AMDGPU bitcast-int-fp.ll

[AMDGPU][NFC] Add tests for bitcasts between integer and FP types

Add cost model tests for bitcasts between integer and floating-point
types of the same size, as scalars and as vectors. Add an SLP test that
stores a pair of values bitcast from i32 to float.

Assisted-by: Claude Opus
DeltaFile
+106-0llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+72-0llvm/test/Transforms/SLPVectorizer/AMDGPU/bitcast-int-fp.ll
+178-02 files

LLVM/project f2eb1c8 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll

[AMDGPU] Treat a bitcast between integer and FP types as free

The generic cost model treats a bitcast as free only when both types
are integer types or both are not. AMDGPU keeps integer and
floating-point values in the same registers, so a bitcast between them
is a no-op when the sizes match. A scalar bitcast from i32 to float
cost 1, but the vector bitcast from <2 x i32> to <2 x float> cost 0.
The SLP vectorizer counted this difference as a saving. In a rocFFT
kernel this saving made it vectorize trees that gave no real gain and
added register pressure.

Bitcasts that involve pointers or i1 keep their costs.

Assisted-by: Claude Opus
DeltaFile
+28-28llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+4-3llvm/test/Transforms/SLPVectorizer/AMDGPU/bitcast-int-fp.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+38-313 files

LLVM/project f05a9d1 — llvm/lib/Target/RISCV RISCVISelLowering.cpp

[RISCV] Remove redundant casts in byte vector lowering

Type legalization already makes these RV32 BUILD_VECTOR operands i32.
DeltaFile
+4-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+4-41 files

LLVM/project 53c7d67 — llvm/test/Transforms/SLPVectorizer/RISCV gep-inttoptr-mixed.ll

[SLP][NFC]Add an extra test for strided loads, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/238397
DeltaFile
+35-0llvm/test/Transforms/SLPVectorizer/RISCV/gep-inttoptr-mixed.ll
+35-01 files

LLVM/project 06d9b37 — clang/lib/Sema SemaDecl.cpp SemaDeclCXX.cpp, clang/test/CodeGenCXX mangle-inline-namespace-redeclarations.cpp

[Clang] Preserve namespace identity for inline namespace redeclarations (#233862)

Fixes #95154.

This change is motivated by building libstdc++ with Clang.

This is already done partly within the hermetic-llvm Bazel toolchain
module. But it was reported to crash with a simple usage of
`std::filesystem::directory_iterator`.

libstdc++ [declares `_Dir` inside its C++11 ABI
namespace](https://github.com/gcc-mirror/gcc/blob/releases/gcc-14.2.0/libstdc%2B%2B-v3/include/bits/fs_dir.h#L94-L98),
then [defines it as `fs::_Dir` through the `std::filesystem`
alias](https://github.com/gcc-mirror/gcc/blob/releases/gcc-14.2.0/libstdc%2B%2B-v3/src/c%2B%2B17/fs_dir.cc#L39-L45).
Clang can omit the inline namespace from mangled names, allowing old and
new ABI symbols to collide and the wrong implementation to be selected
at link time.

These declarations need to keep their namespace identity so that valid

    [9 lines not shown]
DeltaFile
+53-0clang/test/PCH/inline-namespace-redeclarations.cpp
+34-0clang/test/SemaCXX/inline-namespace-redeclarations.cpp
+24-0clang/test/CodeGenCXX/mangle-inline-namespace-redeclarations.cpp
+9-1clang/lib/Sema/SemaDeclCXX.cpp
+6-0clang/lib/Sema/SemaDecl.cpp
+126-15 files

LLVM/project d7df85a — llvm/test/CodeGen/SPIRV/passes SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll SPIRVPrepareGlobals-predicate-id-string.ll

[NFC][SPIR-V][NewPM] Use -stop-after instead of -print-after-all in pass tests (#238355)

IR dump banner is specific to the legacy pass manager
DeltaFile
+2-4llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals-predicate-id-string.ll
+2-4llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll
+2-4llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll
+1-3llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll
+7-154 files

LLVM/project f02e6bd — lld/MachO InputFiles.cpp, lld/test/MachO arm64e-input-abi.s

Check arm64e ABI markers in static links too

Static links skipped the check, but ld64 takes only unversioned and
kernel objects there besides version 0, and ignores the other markers.

Assisted-by: Claude Code
DeltaFile
+13-5lld/MachO/InputFiles.cpp
+6-1lld/test/MachO/arm64e-input-abi.s
+19-62 files

LLVM/project b5c6dab — lld/MachO InputFiles.cpp, lld/test/MachO arm64e-input-abi.s

[lld-macho] Reject incompatible arm64e object ABI markers

The CPU subtype of an arm64e object carries a pointer authentication ABI
marker. In a dynamic link, ld64 accepts only objects marked userland ABI
version 0, even on macOS and Mac Catalyst, whose executables are marked
version 1. It names any other marker as another architecture
(arm64e.old, arm64e.v1, arm64e.kernel, arm64e.kernel.v1 or unknown) and,
as with an arm64 object, ignores the file with a warning, or reports an
error with -arch_errors_fatal. This applies to archive members too.

lld linked these objects. Check the marker in the same way. ld64 accepts
unversioned and kernel-ABI objects in static links, so those links are
not checked.

Assisted-by: Claude Code



DeltaFile
+134-0lld/test/MachO/arm64e-input-abi.s
+31-11lld/MachO/InputFiles.cpp
+165-112 files

LLVM/project 85dfe82 — lld/MachO InputSection.h Writer.cpp, lld/test/MachO arm64e-tlv-bootstrap.s

[lld-macho] Sign the arm64e TLV bootstrap pointer as ld64 does

The first word of a thread-local variable descriptor is bound to
__tlv_bootstrap, which dyld replaces with a pointer to tlv_get_addr that
TLV accesses call with blraaz. On arm64e, ld64 writes that bind as an
authenticated bind with the IA key and no diversity, although the object
asks for a plain pointer. Do the same.

Assisted-by: Claude Code



DeltaFile
+30-0lld/test/MachO/arm64e-tlv-bootstrap.s
+16-1lld/MachO/InputSection.cpp
+2-1lld/MachO/Writer.cpp
+2-0lld/MachO/InputSection.h
+50-24 files

LLVM/project e5f682b — lld/test/MachO arm64e-stubs.s

Check which __auth_got slot each stub loads

The ObjC stub's slot was captured but never checked, so a stub loading
the wrong slot would have passed.

Assisted-by: Claude Code
DeltaFile
+2-2lld/test/MachO/arm64e-stubs.s
+2-21 files

LLVM/project 6ca53ad — lld/MachO OutputSegment.cpp

Give __stubs and __auth_stubs distinct section priorities

The other code sections already had -5, so move the header, __text and
the code sections down by one to make room for __stubs. The order of the
sections is unchanged; only the ties are gone.

Assisted-by: Claude Code
DeltaFile
+4-4lld/MachO/OutputSegment.cpp
+4-41 files

LLVM/project 84d4f04 — lld/MachO InputSection.h OutputSegment.cpp, lld/MachO/Arch ARM64.cpp

[lld-macho] Call through authenticated stubs on arm64e

ld64 calls dylib functions from arm64e code through __auth_stubs rather
than __stubs. Each stub is four instructions instead of three:

  adrp x17, slot at page
  add  x17, x17, slot at pageoff
  ldr  x16, [x17]
  braa x16, x17

where the slot is in __auth_got and holds a pointer that dyld signs with
the IA key, blended with the slot's address. The raw target is only ever
held in x16 and x17, so a stub never branches through an unauthenticated
pointer loaded from writable memory. Do the same: on arm64e, name the stubs
section __auth_stubs, make stubs 16 bytes, and put stub targets in
__auth_got. Fast ObjC stubs load _objc_msgSend from __auth_got and braa to
it in the same way, as ld64's do; small ones already branch to its stub.

__auth_stubs gets __stubs' place directly after __text. That is not just

    [11 lines not shown]
DeltaFile
+56-14lld/test/MachO/arm64e-stubs.s
+52-0lld/MachO/Arch/ARM64.cpp
+35-0lld/test/MachO/arm64e-auth-stubs-section-order.s
+21-8lld/MachO/SyntheticSections.cpp
+2-0lld/MachO/OutputSegment.cpp
+1-0lld/MachO/InputSection.h
+167-226 files

LLVM/project 3390d59 — lld/MachO MapFile.cpp, lld/test/MachO arm64e-map.s

[lld-macho] List arm64e __auth_got entries in the map file

The map file printed the entries of __got but not those of arm64e's
__auth_got, which held the targets of the stubs and the personalities.
Print them in the same way.

Assisted-by: Claude Code



DeltaFile
+36-0lld/test/MachO/arm64e-map.s
+11-6lld/MachO/MapFile.cpp
+47-62 files

LLVM/project 698bc9f — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-reduce-or-cmp.ll movmsk-v3i1.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+463-0llvm/test/CodeGen/X86/movmsk-v3i1.ll
+29-197llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+19-0llvm/lib/Target/X86/X86ISelLowering.cpp
+511-1973 files

LLVM/project b1dc6f6 — lld/MachO SyntheticSections.cpp, lld/test/MachO arm64e-auth-reloc-local.s arm64e-auth-pointer.s

[lld-macho] Add arm64e pointer authentication support (#234002)

This adds an arm64e target to lld that links pointer-authenticated
code the way ld64 does: it parses `ARM64_RELOC_AUTHENTICATED_POINTER`
and writes authenticated chained rebases and binds. The behavior was
checked against Xcode 27's ld and tested extensively.

1. Add an arm64e target. `-arch arm64e` selects it. The CPU subtype
carries ptrauth ABI version 1 for macOS/Catalyst executables and version
0 for everything else.
2. Use chained fixups for arm64e. `DYLD_CHAINED_PTR_ARM64E_USERLAND24`
is used from the same deployment targets as in ld64 and
`DYLD_CHAINED_PTR_ARM64E` for those below.
3. Link arm64e authenticated pointers. The extern-only
`ARM64_RELOC_AUTHENTICATED_POINTER` is parsed and its signing schema
kept in `Relocation`, which stays 24 bytes. Auth'd rebases store an
offset of at most 4 GiB from the image base, auth'd binds keep their
addends in the imports table, and auth'd pointers in `__thread_vars`
stay signed pointers.

    [19 lines not shown]
DeltaFile
+208-23lld/MachO/SyntheticSections.cpp
+180-0lld/test/MachO/arm64e-chained-fixups.s
+156-0lld/test/MachO/arm64e-auth-pointer-invalid.yaml
+140-0lld/test/MachO/arm64e-auth-got.s
+137-0lld/test/MachO/arm64e-auth-pointer.s
+117-0lld/test/MachO/arm64e-auth-reloc-local.s
+938-2323 files not shown
+1,685-6629 files

LLVM/project 2dd64b2 — llvm/lib/IR DebugInfo.cpp, llvm/test/Transforms/Util strip-nonlinetable-debuginfo-call-target.ll

[DebugInfo] Avoid invalid IR from retained call targets (#233151)

Clang can attach `!call_target` to indirect virtual calls in optimized DWARF
5 debug builds. For a method of a function-local class, this attachment can
retain the function's `DICompileUnit`.

Both `stripDebugInfo` and `stripNonLineTableDebugInfo` currently leave the
attachment behind after removing or replacing that compile unit. The resulting
IR is invalid, and `llvm-as` and `llc` reject it with `DICompileUnit not listed
in llvm.dbg.cu`. This occurred in 24 LLVM/Clang self-build translation units.

Remove `MD_call_target` in both stripping paths. Line-tables-only Clang output
does not contain this attachment, so dropping it matches the intended stripped
representation. Add a focused regression test for both modes.
DeltaFile
+31-0llvm/test/Transforms/Util/strip-nonlinetable-debuginfo-call-target.ll
+8-2llvm/lib/IR/DebugInfo.cpp
+39-22 files

LLVM/project e170a4a — libc/src/signal CMakeLists.txt killpg.h, libc/src/signal/linux CMakeLists.txt killpg.cpp

[libc] Implement killpg (#237561)

This patch implements the POSIX `killpg` signal function in LLVM libc,
along with unit tests.

Part of #236167.
DeltaFile
+50-0libc/test/src/signal/killpg_test.cpp
+39-0libc/src/signal/linux/killpg.cpp
+26-0libc/src/signal/killpg.h
+15-0libc/test/src/signal/CMakeLists.txt
+15-0libc/src/signal/linux/CMakeLists.txt
+7-0libc/src/signal/CMakeLists.txt
+152-04 files not shown
+162-010 files

LLVM/project 930f2d2 — llvm/include/llvm/Target TargetMachine.h, llvm/lib/CodeGen/GlobalISel CSEInfo.cpp

[SPIR-V][NewPM] Disable GlobalISel CSE to match legacy PM  (#238283)

CSE merges same LLT values with different SPIR-V types

Legacy PM gets no CSE from the TargetPassConfig default, but new PM
always used the standard config
DeltaFile
+19-0llvm/test/CodeGen/SPIRV/instructions/undef-composite.ll
+6-0llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+4-1llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+4-0llvm/include/llvm/Target/TargetMachine.h
+1-0llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
+34-15 files

LLVM/project f8c1231 — mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp, mlir/test/Target/LLVMIR openmp-target-recipe-internal-shared-mem.mlir

[MLIR][OpenMP] Support device shared memory for recipe ops

Some recipe ops (`omp.private` and `omp.declare_reduction`) can hold
stack allocations inside their allocation or initialization regions, and
these regions are inlined in the corresponding blocks of their users when
translating to LLVM IR.

The issue is that, when compiling for a target device, certain stack
allocations must be replaced with device shared memory to account for
the disjoint memory spaces of GPUs when kernels run in Generic mode.
This is sometimes handled by frontends by emitting `omp.alloc_shared_mem` and
`omp.free_shared_mem` operations instead of using stack allocations, and
the `StackToShared` MLIR pass addresses any remaining stack allocations
that need to be replaced.

None of those solutions are well suited for these recipe ops, which
might need to use device shared memory for some instantiations but not
others, based on context and usage of the resulting storage. Instead,
what this patch does is to identify the cases where device shared memory

    [17 lines not shown]
DeltaFile
+439-0mlir/test/Target/LLVMIR/openmp-target-recipe-internal-shared-mem.mlir
+345-0offload/test/offloading/fortran/target-reduction-allocatable-arrays.f90
+308-34mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+305-0offload/test/offloading/fortran/target-privatization-allocatable-arrays.f90
+1,397-344 files