[libc][test][NFC] Fix pthread_setschedparam_test flakiness (#212067)
Synchronised child thread execution in pthread_setschedparam_test using
a mutex lock. This prevents race conditions where the child thread
exited before scheduling parameter assertions ran on multi-core
platforms such as aarch64.
Added missing pthread target dependencies to CMakeLists.txt.
Assisted-by: Automated tooling, human reviewed.
[AMDGPU][GISel] Remove redundant AND on scalar shift amounts
A scalar shift only consumes the low log2(bitwidth) bits of its amount,
so an explicit (and amt, mask) feeding the amount is redundant whenever
mask has all of those low bits set. SelectionDAG already achieves this
via SimplifyDemandedBits on the shift-amount operand; this adds the
equivalent to the post-RegBankSelect combiner for G_SHL/G_LSHR/G_ASHR.
Co-authored-by: Cursor <cursoragent at cursor.com>
[LoopInfo] Identify loops with a single-pass DFS algorithm. NFC (#212000)
analyze() numbers the dominator tree, scans it in reverse preorder for
header candidates, floods backward through the CFG from each header's
latches, then walks the CFG again to order the blocks.
Do all of it in one forward DFS, with the algorithm of Wei et al.,
"A New Algorithm for Identifying Loops in Decompilation", which
GenericCycleInfo already implements.
On an irreducible CFG that algorithm may return an irreducible superset
of the natural loop subset `discoverAndMapSubloop` would return.
(Depending on the successor visiting order, the algorithm may report a
reducible loop nested in an irreducible loop, where the reducible one
exactly matches `discoverAndMapSubloop`.)
To satisfy verifyLoop and LoopSimplify, reduce each such ireducible loop
to the natural loop of its header's backedges instead: the latches the
header dominates, and the blocks reaching them without passing the
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[clang][bytecode] Don't check global variable init size (#212092)
The current interpreter doesn't do this either. If we do, the clang
build fails because AMDGPUGenGlobalISel.inc: contains a global constexpr
array called MatchTable0 with 1'926'005 elements.
[clang][bytecode] Only override constant-context state if we have an EvalEmitter (#211475)
This does not make sense when emitting bytecode, as the bytecode would
just contain a `PushCC`/`PopCC` pair with nothing in between.
[AArch64] Add CAS instructions to NeoverseN2 schedule model (#211195)
CAS instructions (B, H, W, X variants) are not described in the ARM
Neoverse N2 Software Optimization Guide. There used to be no schedule
model for them, so `llvm-mca` was unable to analyze code containing
these instructions:
llvm-mca -mtriple=aarch64 -mcpu=cortex-a78 -mattr=+lse casb.s
error: found an unsupported instruction in the input assembly
sequence, use -skip-unsupported-instructions=lack-sched to ignore
these on the input.
note: instruction: casb w0, w1, [sp]
The patch adds a basic schedule model of 14 cycles (as measured on
Cortex-A78 with llvm-exegesis) and L/S utilized pipelines (this is a
guess, the reality is likely more complicated).
[Github] Add myself and lforg37 as mlir wasmssa codeowners (#212079)
Adding @flemairen6 and @lforg37 as codeowners of WasmSSA
Co-authored-by: Ferdinand Lemaire <flemairen6 at gmail.com>
[MLIR][WasmSSA] Add global_set and select ops (#196613)
Adds two missing ops to the WasmSSA dialect.
- `wasmssa.global_set`
- `wasmssa.select`
---------
Co-authored-by: Ferdinand Lemaire <flscminecraft at gmail.com>
[ELF] Retain .got for revertible no-PIC GOTPCRELX optimization (#212077)
Commit 9d6ec280fc537b55ef8641ea85d3522426bc5766 (2023) sets
GotSection::hasGotOffRel when adjustGotPcExpr returns R_RELAX_GOT_PC,
keeping .got alive for an optimization that X86_64::relaxOnce may
revert.
R_RELAX_GOT_PC_NOPIC (e.g. `addq`) in -no-pie mode has the same issue.
[mlir][tosa] Fix mul/intdiv folds crashing on dynamic-shaped results (#212073)
`tosa.mul` and `tosa.intdiv` fold constant splat operands by building a
`DenseElementsAttr` of the result type, which asserts when that type has
a dynamic shape. When the operands are constants but the result type is
dynamic, folding aborted. Guard `mulBinaryFolder` and the `IntDivOp`
splat path on a static result shape, matching the other fold paths in
these ops.
Signed-off-by: Víctor Pérez Carrasco <victor.pc.upm at gmail.com>
[LV] Extract fixupHeaderPhiBackedges from VPlan::execute (NFC) (#212063)
Hoist the header-phi backedge fixup loop at the end of VPlan::execute
into a helper VPTransformState::fixupHeaderPhiBackedges.
clang/AMDGPU: Rename amdgcn triples to amdgpu in cc1 tests (14)
Replace the legacy amdgcn architecture name with amdgpu in various
test triples. This set of updates covers cases that did not have
a set -target-cpu.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DAG: Use poison in getLoad/getStore for offsets
The painful part of this is due to a few unfortunate things.
1. poison is legalized to undef
2. Non-indexed load/store encode the offset as an undef (which is
not like a TargetConstant, and does get legalized)
3. 2 asserts in DAGCombiner expect identical load/store nodes,
which assumes the offset will be preserved and not converted
between poison and undef
4. The getLoad/getStore overloads are a mess, and a path was missing
to recreate the store case with the original offset.
clang/AMDGPU: Migrate -aux-triple amdgcn in cc1 tests to amdgpu (13) (#212052)
Update to the new architecture name.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang/AMDGPU: Migrate OpenMP cc1 tests to amdgpu triples (12) (#212051)
Migrate the OpenMP offload cc1 tests to the new amdgpu triple scheme:
* -fopenmp-targets=amdgcn-amd-amdhsa ->
-fopenmp-targets=amdgpu-amd-amdhsa
(the offload toolchain triple, the generic amdgpu arch).
* The device -triple amdgcn-amd-amdhsa -> amdgpu-amd-amdhsa, or to the
specific subarch triple (dropping -target-cpu) where a -target-cpu was
present.
Autogenerated CHECK lines are regenerated, and the few -Wopenmp-target-
exception diagnostics that embed the triple string are updated. Tests
that
intentionally assert the "target-cpu" function attribute are left
unchanged.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[VPlan] Add VPRegionBlock::getEntryBranchOnMask helper (NFC) (#212060)
Add an accessor returning the VPBranchOnMaskRecipe guarding a replicate
region, i.e. the sole recipe of the region's entry block.
clang/AMDGPU: Migrate cc1 tests to subarch triples (11) (#211956)
Rewrite the second half of CodeGenOpenCL cc1 test RUN lines to the new
subarch triple form, dropping the redundant -target-cpu.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[libunwind][PPC64] Fix unw_getcontext corrupting callee-saved VSX registers on LE (#198371)
This is the first of two independent fixes for libunwind on ppc64le
(ELFv2 ABI, little-endian), where two separate bugs together cause
SIGSEGV during backtracing. This commit addresses the VSX register
corruption; the TOC-restore fault is handled in a follow-up. Both
were discovered while debugging lang/rust build failures with
RUST_BACKTRACE=1 on FreeBSD/powerpc64le (IBM POWER9).
On ppc64le, `unw_getcontext` saves each VS register with an in-place
`xxswapd n, n` followed by `stxvd2x`. The swap is needed because
`stxvd2x` stores doublewords in the wrong order on LE. However, the
macro never applies a second `xxswapd` to restore the register after
the store, so all 64 VS registers are permanently corrupted on return
from `unw_getcontext`.
This affects every callee-saved VSX register: f14-f31 (VSR14-VSR31)
and VR20-VR31 (VSR52-VSR63). After `_Unwind_Backtrace` returns, any
code that uses these registers sees wrong values. In practice this
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[Clang] Don't build static analyzer if disabled (#212024)
Even if the static analyzer is disabled, it still gets built into the
dylib. Unit tests and tools already get disables, so also stop building
the library. This reduces the time needed to build a dylib clang by
8-9%.
