LLVM/project 9a6ba31llvm/lib/Transforms/Vectorize VPlanConstruction.cpp

[VPlan] Add helper to add incoming values for last predecessor (NFC). (#222149)

Factor logic to helper function, so it can be re-used in follow-up
changes.
DeltaFile
+12-7llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+12-71 files

LLVM/project e94e2bellvm/lib/Transforms/Vectorize VPlanUtils.h

[VPlan] Collect predecessors/successors up front (NFC) (#222145)

Collect predecessors and successors up front in reassociateBlocks.
Currently NFC, but makes it more robust in the future, because it also
correctly handles self-edges.
DeltaFile
+4-2llvm/lib/Transforms/Vectorize/VPlanUtils.h
+4-21 files

LLVM/project 4a6228ellvm/test/CodeGen/AArch64 arm64-big-endian-bitconverts.ll arm64-xaluo.ll, llvm/test/CodeGen/AMDGPU dpp_combine_rev_opcode.ll

Rebase, improvements, address comments

Created using spr 1.3.7
DeltaFile
+5,248-0llvm/test/CodeGen/X86/active_lane_mask.ll
+4,997-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+1,653-1,679llvm/test/CodeGen/AArch64/arm64-xaluo.ll
+1,299-431llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
+1,503-0llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll
+640-640llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
+15,340-2,7501,115 files not shown
+55,501-23,7191,121 files

LLVM/project b91e683clang/docs DataFlowAnalysisIntro.md, clang/docs/_static custom.css

[clang][docs] Give DataFlow figures a light background
DeltaFile
+28-7clang/docs/DataFlowAnalysisIntro.md
+4-0clang/docs/_static/custom.css
+32-72 files

LLVM/project 62eee09clang/docs UsersManual.md

Fix text color in dark mode
DeltaFile
+1-1clang/docs/UsersManual.md
+1-11 files

LLVM/project c6d8062clang/docs/analyzer conf.py, libc/docs/_static copybutton.js

[clang][docs] Prototype Furo theme setup
DeltaFile
+140-0utils/docs/llvm_sphinx/_static/furo-common.css
+0-71llvm/docs/_static/custom.css
+0-56llvm/docs/_static/copybutton.js
+0-56libc/docs/_static/copybutton.js
+56-0utils/docs/llvm_sphinx/_static/copybutton.js
+10-34clang/docs/analyzer/conf.py
+206-2179 files not shown
+335-39215 files

LLVM/project ac6f2f9clang/docs Toolchain.md ReleaseNotes.md, clang/include/clang/Basic BuiltinsAMDGPUDocs.td

[clang][docs] Remove page-local contents directives
DeltaFile
+0-10clang/docs/DriverInternals.md
+0-4clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+0-4clang/docs/Toolchain.md
+0-4clang/docs/ReleaseNotes.md
+0-4clang/docs/LanguageExtensions.md
+0-4clang/docs/FunctionEffectAnalysis.md
+0-3075 files not shown
+0-25481 files

LLVM/project 1f61306clang/docs conf.py, clang/docs/_static custom.css

[docs] Restore project-specific Furo CSS
DeltaFile
+0-140utils/docs/llvm_sphinx/_static/furo-common.css
+71-0llvm/docs/_static/custom.css
+60-0clang/docs/_static/custom.css
+8-0utils/docs/llvm_sphinx/__init__.py
+3-0clang/docs/conf.py
+3-0clang/docs/analyzer/conf.py
+145-1404 files not shown
+147-14210 files

LLVM/project 881aef5clang/docs/_static custom.css

[clang][docs] Widen content on medium viewports
DeltaFile
+21-0clang/docs/_static/custom.css
+21-01 files

LLVM/project 423165allvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Remove unused getBaseArchNameAMDGCN

This ended up unused for gfx1250-strict

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+1-15llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+7-7llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
+0-6llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+0-3llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+8-314 files

LLVM/project fa4d413utils/bazel/llvm-project-overlay/libc BUILD.bazel

[bazel] Port 35fe7e14ec (#222150)
DeltaFile
+1-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+1-11 files

LLVM/project c7eaa57clang/utils/TableGen ClangOptionDocEmitter.cpp

colon fence {program}
DeltaFile
+4-4clang/utils/TableGen/ClangOptionDocEmitter.cpp
+4-41 files

LLVM/project d2d8dccclang/include/clang/Options FlangOptions.td, flang/docs FlangOptionsMan.td FlangOptionsDocs.td

[flang][docs] Support Markdown option documentation
DeltaFile
+42-51clang/include/clang/Options/FlangOptions.td
+15-15flang/docs/CMakeLists.txt
+11-12flang/docs/FlangOptionsDocs.td
+7-5flang/docs/FlangOptionsMan.td
+75-834 files

LLVM/project 15034a7flang/lib/Lower/OpenMP OpenMP.cpp, flang/test/Lower/OpenMP omp-declarative-allocate-save-warning.f90 omp-declarative-allocate-derived-warning.f90

[OpenMP] [MLIR] [Flang] Replace all uses of variables in ALLOCATE directive to use new value which is created. (#212361)

Limitation:
Right now, added a TODO warning about lowering of variable with SAVE
attribute or named COMMON block are not completely supported end to end.
So a warning is emitted.
DeltaFile
+121-0mlir/test/Target/LLVMIR/openmp-allocate-directive.mlir
+77-24mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+63-12flang/lib/Lower/OpenMP/OpenMP.cpp
+46-0flang/test/Lower/OpenMP/omp-declarative-allocate-derived-warning.f90
+44-0flang/test/Lower/OpenMP/omp-declarative-allocate-save-warning.f90
+10-0mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+361-363 files not shown
+375-419 files

LLVM/project dadb909utils/bazel/llvm-project-overlay/libc BUILD.bazel

[bazel] Port 35fe7e14ec
DeltaFile
+1-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+1-11 files

LLVM/project f079886llvm/test/MC/AMDGPU out-of-range-registers.s misaligned-vgpr-tuples-err.s

[AMDGPU] Update no-modifier operand tests for the dropped align diagnostic

The no-modifier reg-or-inline operands routed through the HwMode
predicate now report a misaligned tuple as a plain invalid operand,
matching the diagnostic dropped earlier in the stack.
DeltaFile
+7-7llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
+1-1llvm/test/MC/AMDGPU/out-of-range-registers.s
+8-82 files

LLVM/project 6f51533llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU misaligned-vgpr-tuples-err.s

[AMDGPU] Route no-modifier reg-or-inline AsmParser operands through HwMode predicate

Convert the reg-or-inline operands with no modifiers (MFMA VGPR/AGPR
sources, VCSrc, v_pk_mov_b32, VOP scalar f64) from the fixed-class
isRegOrInlineNoMods to the HwMode-aware isRegOrInlineNoModsByHwMode, so an
odd-aligned tuple is rejected at the offending operand column instead of by
the validateVGPRAlign catch-all.

Co-Authored-By: Claude <noreply at anthropic.com>
DeltaFile
+53-46llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+7-7llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
+60-532 files

LLVM/project cbc1384llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

[AMDGPU] Drop the misaligned VGPR-tuple AsmParser diagnostic

The alignment-aware matchers already reject a misaligned tuple, so a
misaligned operand now fails as a plain invalid operand. Keeping the
dedicated "vgpr tuples must be 64 bit aligned" message only for that
case is not worth the extra match-error ranking, the per-operand
diagnostic, and getUnalignedEquivalentRC, so remove all of it.
DeltaFile
+0-87llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+13-57llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+3-3llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
+0-5llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+1-1llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
+17-1535 files

LLVM/project 5a9861ellvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

[AMDGPU] Make custom AsmParser matchers alignment aware

Currently custom matchers accept registers belonging to unaligned classes,
leaving the alignment check and its diagnostic to validateVGPRAlign. The problem
is that validateVGPRAlign does not account for the operand register class, which
may have a different alignment requirement on mixed-alignment targets.

The fix is to make a custom matcher resolve the operand's _AlignTarget class via
HwMode and use that resolved class to accept a register. However, doing so alone
would reject a misaligned register with a generic "invalid operand for
instruction" diagnostic, so extra infrastructure conveys the alignment diagnostic
instead: on a class miss, diagnoseRegAlign re-checks the register against the same
class with alignment relaxed (getUnalignedEquivalentRC, new in AMDGPUBaseInfo);
if it fits, the only problem is alignment, so it records
OperandMatchError::VGPRAlignMismatch on the operand. matchAndEmitInstruction
selects that reason and prints the alignment error, now at the offending operand
column instead of column 1.

This commit converts the input-mods and DP-ALU DPP matchers. The no-modifier

    [4 lines not shown]
DeltaFile
+87-18llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+87-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+6-6llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
+5-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+1-1llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
+186-255 files

LLVM/project 1936b4allvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp

[AMDGPU] Factor the AsmParser match-specificity comparison into a helper, NFC (#221987)

Extract the "keep the most specific match status" comparison in
matchAndEmitInstruction into an atLeastAsSpecific() lambda ranking
Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature. No
functional change.
DeltaFile
+15-7llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+15-71 files

LLVM/project c0a6b4bllvm/lib/CodeGen MachineInstr.cpp

[CodeGen] Avoid quadratic operand removal in MachineInstr::insert (#220165)

This optimizes MachineInstr::insert by copying trailing operands
first and then removing them from the end. This avoids repeatedly
shifting the remaining operands, reducing the operation from quadratic
to linear time without changing behavior.
DeltaFile
+3-9llvm/lib/CodeGen/MachineInstr.cpp
+3-91 files

LLVM/project cfd9119clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl

First attempt implementing InterlockedCompareExchangeFloatBitwise
DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-3clang/lib/Sema/SemaHLSL.cpp
+271-35 files not shown
+306-611 files

LLVM/project 269da19llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir v_swap_b16.ll

[AMDGPU][SIInstrInfo] Materialise t16 PHI subreg operands
DeltaFile
+1,527-1,045llvm/test/CodeGen/AMDGPU/frem.ll
+20-26llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
+18-7llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-2llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+1,573-1,0804 files

LLVM/project ff9905dclang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

First attempt implementing InterlockedCompareStoreFloatBitwise
DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+35-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+20-8clang/lib/Sema/SemaHLSL.cpp
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+251-86 files not shown
+318-1312 files

LLVM/project 83fd470clang/lib/Sema SemaHLSL.cpp HLSLExternalSemaSource.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl RWByteAddressBuffer-InterlockedCompareExchange.hlsl

First attempt implementing InterlockedCompareExchange
DeltaFile
+114-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchange-errors.hlsl
+70-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchange.hlsl
+43-24clang/lib/Sema/HLSLExternalSemaSource.cpp
+44-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchange.hlsl
+24-12clang/lib/Sema/SemaHLSL.cpp
+35-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl
+330-366 files not shown
+420-5212 files

LLVM/project 8208ec4clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Sema HLSLExternalSemaSource.cpp

First attempt implementing InterlockedCompareStore
DeltaFile
+89-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStore-errors.hlsl
+54-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStore.hlsl
+46-7clang/lib/Sema/HLSLExternalSemaSource.cpp
+37-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStore.ll
+29-7clang/lib/CodeGen/CGHLSLBuiltins.cpp
+36-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStore.hlsl
+291-147 files not shown
+401-1613 files

LLVM/project c888d21clang/test/SemaHLSL/BuiltIns InterlockedExchange-errors.hlsl ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl, llvm/lib/Target/DirectX DXILResourceAccess.cpp DXILLegalizePass.cpp

First attempt implementing float InterlockedExchange
DeltaFile
+40-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl
+39-0llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat.ll
+38-0llvm/test/CodeGen/DirectX/ResourceAtomicExchangeFloat.ll
+21-14clang/test/SemaHLSL/BuiltIns/InterlockedExchange-errors.hlsl
+29-0llvm/lib/Target/DirectX/DXILLegalizePass.cpp
+17-3llvm/lib/Target/DirectX/DXILResourceAccess.cpp
+184-178 files not shown
+246-2814 files

LLVM/project 915c349.github new-prs-labeler.yml

[Github] Match backend:NVPTX files outside llvm/ (#221968)

The backend:NVPTX labeler rules are anchored to the llvm/ subtree (every
glob starts with llvm/**), so NVPTX/NVVM-related files elsewhere in the
tree never get the label. In particular, ClangIR's lowering under clang/
touches NVPTX code but the PR is not tagged backend:NVPTX.

This drops the llvm/ prefix so the patterns match anywhere in the tree.
DeltaFile
+8-8.github/new-prs-labeler.yml
+8-81 files

LLVM/project 8fdbba5libc/include unistd.yaml, libc/include/llvm-libc-macros/linux unistd-macros.h

[libc][unistd] Support _SC_GET(GR|PW)_R_SIZE_MAX in sysconf. (#222135)

* Add support for POSIX-specified `_SC_GETGR_R_SIZE_MAX` and
`_SC_GETPW_R_SIZE_MAX`
  constants used as arguments to `sysconf` function;
* Return -1 for these values - they provide "initial size" for
user-supplied buffers passed to `getgr*` and `getpw*`
functions, but there's no real maximum limit imposed by the LLVM-libc
implementation, and user might provide a
size they can, and rely on `ERANGE` return values if the chosen size
ended up being too small for pwd/group entries.
* Add unit test coverage, and update the unit test to use proxy headers
instead of system-provided `<unistd.h>`.
  Also, properly test errno values returned by `sysconf`.

This fixes one of the remaining blockers for building Clang against
LLVM-libc (https://github.com/llvm/llvm-project/issues/97191)
DeltaFile
+22-12libc/test/src/unistd/sysconf_test.cpp
+8-0libc/src/unistd/linux/sysconf.cpp
+4-1libc/test/src/unistd/CMakeLists.txt
+4-0libc/include/unistd.yaml
+2-0libc/include/llvm-libc-macros/linux/unistd-macros.h
+40-135 files

LLVM/project 1f388eallvm/test/Transforms/SLPVectorizer/AArch64 splat-gather-subtree-drop.ll

[SLP][NFC]Add a test with missed vectorization, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/222141
DeltaFile
+144-0llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop.ll
+144-01 files