[RISCV] Try to disassemble 48-bit and larger instructions as 32-bit instructions first. (#175122)
The encoding scheme for 48-bit and larger instructions has not
been ratified yet. The RISC-V ISA manual previously included a
proposal that included 4 reserved major opcodes. LLVM's
disassembler implements this proposal as does binutils.
A vendor extension might have used the reserved opcodes,
as a non-conforming 32-bit extension. Try to decode as a
32-bit instruction first to catch these cases.
Should help with #174571.
[Offload] Fix failing Fortran test w/ line number (#175247)
This test also depends on the line number. Following similar approach as
other with [[@LINE]] macro.
[lldb] fix a problem in the ValueObject::GetExpressionPath method (#171521)
Consider the following program:
```
int main() {
int foo[2][3][4];
int (*bar)[3][4] = foo;
return 0;
}
```
If we:
- compile this program
- launch an LLDB debugging session
- launch the process and let it stop at the `return 0;` statement
then the following LLDB command:
```
(lldb) script lldb.frame.FindVariable("bar").GetChildAtIndex(0).get_expr_path()
```
will produce the following output:
[15 lines not shown]
[flang][cuda] Avoid inserting GetDeviceAddress call in offload regions (#175225)
In regions destined for GPU offload, computing an address_of means
getting device address directly - no need (and actually incorrect) to
insert a runtime call to get the address. This was already working for
regions such as `gpu.launch` - but now it applies to acc regions as
well.
[flang] Visit "source" member in all AST nodes (#175211)
Some AST nodes had their "source" member visited by the parse tree
visitor, while others, in particular those that were handled by the
trait-based visitors, did not.
Make sure that we call the Walk function on the "source" member for all
classes that have it.
[AMDGPU] Handle `s_setreg_imm32_b32` targeting `MODE` register (#174681)
On certain hardware, this instruction clobbers VGPR MSB `bits[12:19]`,
so we need to restore the current mode.
Fixes SWDEV-571581.
[SPIR-V] Permit implicit conversion to generic AS (#175109)
Summary:
We rely on this in most places we work with address spaces. This allows
target address spaces to implicity convert to generic ones.
I actually have no clue if this is valid or correct with SPIR-V, hoping
someone with more target / backend knowledge can chime in.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
