LLVM/project 700b77bllvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/Transforms/InstCombine sink-dereferenceable-assume.ll

[InstCombine] Don't sink if it would require dropping deref assumptions. (#166945)

Currently sinking assumes in instcombine drops assumes if they would
prevent sinking. Removing dereferenceable assumptions earlier on can
inhibit vectorization of early-exit loops in practice.

Special-case deferenceable assumptions so that they block sinking. This
can be combined with a separate change to drop dereferencebale
assumptions after vectorization: https://clang.godbolt.org/z/jGqcx3sbs

PR: https://github.com/llvm/llvm-project/pull/166945

DeltaFile
+99-7llvm/test/Transforms/InstCombine/sink-dereferenceable-assume.ll
+46-56llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
+9-2llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+154-653 files

LLVM/project 8e0d7d8clang/lib/Analysis/LifetimeSafety Origins.cpp, clang/test/Sema warn-lifetime-safety.cpp

lifetime-safety-paren
DeltaFile
+31-0clang/test/Sema/warn-lifetime-safety.cpp
+17-0clang/unittests/Analysis/LifetimeSafetyTest.cpp
+2-0clang/lib/Analysis/LifetimeSafety/Origins.cpp
+50-03 files

LLVM/project 63fe60fllvm/utils/gn/secondary/bolt/lib/Rewrite BUILD.gn

[gn build] Port f2c50f930540
DeltaFile
+1-0llvm/utils/gn/secondary/bolt/lib/Rewrite/BUILD.gn
+1-01 files

LLVM/project f2c50f9bolt/include/bolt/Rewrite MetadataRewriters.h, bolt/lib/Rewrite RSeqRewriter.cpp RewriteInstance.cpp

[BOLT] Support restartable sequences in tcmalloc (#167195)

Add `RSeqRewriter` to detect code references from `__rseq_cs` section
and ignore function referenced from that section. Code references are
detected via relocations (static or dynamic).

Note that the abort handler is preceded by a 4-byte signature byte
sequence and we cannot relocate the handler without that the signature,
otherwise the application may crash. Thus we are ignoring the function,
i.e. making sure it's not separated from its signature.
DeltaFile
+72-0bolt/lib/Rewrite/RSeqRewriter.cpp
+38-0bolt/test/X86/rseq.s
+4-2bolt/include/bolt/Rewrite/MetadataRewriters.h
+2-0bolt/lib/Rewrite/RewriteInstance.cpp
+1-0bolt/lib/Rewrite/CMakeLists.txt
+117-25 files

LLVM/project 4023bebmlir/docs LangRef.md

Fix typo in LangRef.md regarding regions (#167242)

DeltaFile
+1-1mlir/docs/LangRef.md
+1-11 files

LLVM/project 818b350clang/lib/Analysis/LifetimeSafety Origins.cpp, clang/test/Sema warn-lifetime-safety.cpp

lifetime-safety-paren
DeltaFile
+24-0clang/test/Sema/warn-lifetime-safety.cpp
+17-0clang/unittests/Analysis/LifetimeSafetyTest.cpp
+2-0clang/lib/Analysis/LifetimeSafety/Origins.cpp
+43-03 files

LLVM/project 0daf453clang/lib/Analysis/LifetimeSafety Origins.cpp

lifetime-safety-paren
DeltaFile
+2-0clang/lib/Analysis/LifetimeSafety/Origins.cpp
+2-01 files

LLVM/project b90459cclang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

lifetime-safety-cxx-conditional
DeltaFile
+53-0clang/test/Sema/warn-lifetime-safety.cpp
+17-0clang/test/Sema/warn-lifetime-safety-dataflow.cpp
+8-0clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+1-2clang/unittests/Analysis/LifetimeSafetyTest.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+80-25 files

LLVM/project c10b25alldb/test/API/functionalities/breakpoint/breakpoint_locations/after_rebuild TestLocationsAfterRebuild.py

[lldb] Disable TestLocationsAfterRebuild for remote targets (#167239)

#160199 broke buildbots `lldb-remote-linux-ubuntu` and
`lldb-remote-linux-win`.
This patch must make these buildbots green for now.
DeltaFile
+2-1lldb/test/API/functionalities/breakpoint/breakpoint_locations/after_rebuild/TestLocationsAfterRebuild.py
+2-11 files

LLVM/project acf52a7clang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

lifetime-safety-cxx-conditional
DeltaFile
+53-0clang/test/Sema/warn-lifetime-safety.cpp
+17-0clang/test/Sema/warn-lifetime-safety-dataflow.cpp
+7-0clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+1-2clang/unittests/Analysis/LifetimeSafetyTest.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+79-25 files

LLVM/project 1c5ea66llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv.ll

[AArch64] Decompose faddv with known zero elements

FADDV is matched into FADDPv4f32 + FADDPv2i32p but this can be relaxed
when one element (usually the 4th) or more are known to be zero.

Before:
movi d1, #0000000000000000
mov v0.s[3], v1.s[0]
faddp v0.4s, v0.4s, v0.4s
faddp s0, v0.2s

After:
mov s1, v0.s[2]
faddp s0, v0.2s
fadd s0, s0, s1
DeltaFile
+75-0llvm/test/CodeGen/AArch64/faddv.ll
+38-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+113-02 files

LLVM/project ba384f7clang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

lifetime-safety-cxx-conditional
DeltaFile
+53-0clang/test/Sema/warn-lifetime-safety.cpp
+17-0clang/test/Sema/warn-lifetime-safety-dataflow.cpp
+7-0clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+78-04 files

LLVM/project c8f168cllvm/include/llvm/SandboxIR Instruction.h, llvm/lib/SandboxIR Instruction.cpp

[SandboxIR] Remove tight-coupling with LLVM's SwitchInst::CaseHandle (#167093)

SandboxIR's SwitchInst CaseHandle was relying on LLVM IR's
SwitchInst::CaseHandleImpl template, which may call private functions of
SandboxIR's SwitchInst. This creates a dependency cycle which is against
the design principles of Sandbox IR.

The issue was exposed by:
https://github.com/llvm/llvm-project/pull/166842 Thanks to @aengelke for
raising the issue.
DeltaFile
+92-21llvm/include/llvm/SandboxIR/Instruction.h
+27-0llvm/lib/SandboxIR/Instruction.cpp
+119-212 files

LLVM/project 36e9a0bllvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp, llvm/test/CodeGen/AArch64 neon-mov.ll

[AArch64][GlobalISel] Correct instructions for 64bit fneg constant vectors. (#166537)

This code was assuming that the vectors were 128bit. Add handling for
64bit vectors. Some of the tests do not apply yet due to not matching
non-splat vectors.

Fixes #166400
DeltaFile
+106-22llvm/test/CodeGen/AArch64/neon-mov.ll
+14-4llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+120-262 files

LLVM/project d4b41b9mlir/include/mlir/Analysis/DataFlow SparseAnalysis.h

[mlir] Consolidate two implementations of meet (NFC) (#167208)

This patch consolidates two implementations of meet using
"if constexpr", migrating away from the SFINAE-based approach.
DeltaFile
+15-18mlir/include/mlir/Analysis/DataFlow/SparseAnalysis.h
+15-181 files

LLVM/project 6de4f06clang/include/clang/AST DeclBase.h, clang/lib/StaticAnalyzer/Checkers BlockInCriticalSectionChecker.cpp

[clang] Remove redundant typename (NFC) (#167207)

Identified with readability-redundant-typename.
DeltaFile
+1-2clang/lib/StaticAnalyzer/Checkers/BlockInCriticalSectionChecker.cpp
+1-1clang/include/clang/AST/DeclBase.h
+2-32 files

LLVM/project d939823llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/lib/Target/ARM/Disassembler ARMDisassembler.cpp

[Target] Fix misleading indentation (NFC) (#167206)

Identified with readability-misleading-indentation.
DeltaFile
+5-5llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+2-2llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+9-94 files

LLVM/project 3d82370mlir/include/mlir/Dialect/Shard/Transforms Simplifications.h, mlir/lib/Analysis FlatLinearValueConstraints.cpp

[mlir] Use llvm::transform (NFC) (#167205)

Identified with llvm-use-ranges.
DeltaFile
+5-8mlir/lib/Analysis/Presburger/Utils.cpp
+4-4mlir/lib/IR/PatternMatch.cpp
+2-4mlir/include/mlir/Dialect/Shard/Transforms/Simplifications.h
+2-2mlir/lib/Analysis/FlatLinearValueConstraints.cpp
+1-2mlir/lib/Dialect/Affine/Analysis/AffineStructures.cpp
+1-1mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+15-216 files

LLVM/project 6ef3218llvm/docs SPIRVUsage.rst, llvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp SPIRVSymbolicOperands.td

[SPIRV] Add support for `bfloat16` atomics via the `SPV_INTEL_16bit_atomics` extension (#166257)

This enables support for atomic RMW ops (add, sub, min and max to be
precise) with `bfloat16` operands, via the [SPV_INTEL_16bit_atomics
extension](https://github.com/intel/llvm/pull/20009). It's logically a
successor to #166031 (I should've used a stack), but I'm putting it up
for early review.

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+33-13llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+34-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomicrmw_faddfsub_bfloat16.ll
+28-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomicrmw_fminfmax_bfloat16.ll
+3-0llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+2-0llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+2-0llvm/docs/SPIRVUsage.rst
+102-131 files not shown
+103-147 files

LLVM/project 5abef40llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/PowerPC vector-popcnt-128-ult-ugt.ll

Rebase

Created using spr 1.3.7
DeltaFile
+64,053-56,973llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+22,442-22,438llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+40,677-0llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
+16,411-16,010llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+25,622-0llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
+23,706-0llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
+192,911-95,42128,252 files not shown
+2,616,667-792,17328,258 files

LLVM/project c3b31baclang-tools-extra/clang-tidy/readability ContainerDataPointerCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix `readability-container-data-pointer` check (#165636)

Fix issue in readability-container-data-pointer when the container
expression is a dereference (e.g., `&(*p)[0]`). The previous fix-it
suggested `*p.data()`, which changes semantics because `.` binds tighter
than `*`. The fix now correctly suggests `(*p).data()`.

Closes [#164852](https://github.com/llvm/llvm-project/issues/164852)

---------

Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
DeltaFile
+23-0clang-tools-extra/test/clang-tidy/checkers/readability/container-data-pointer.cpp
+5-2clang-tools-extra/clang-tidy/readability/ContainerDataPointerCheck.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+32-23 files

LLVM/project e5650cellvm/lib/Target/AArch64 AArch64RegisterInfo.cpp, llvm/test/Transforms/LoopStrengthReduce/AArch64 vscale-fixups.ll

Address review comments
DeltaFile
+9-7llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+2-3llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
+11-102 files

LLVM/project d2eda43llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 vec3-faddv-combine.ll

[AArch64] Decompose faddv with known zero elements
DeltaFile
+59-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+57-0llvm/test/CodeGen/AArch64/vec3-faddv-combine.ll
+116-02 files

LLVM/project de1ad82llvm/lib/Target/AArch64 AArch64RegisterInfo.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-int-minmax.ll sve-streaming-mode-fixed-length-int-minmax.ll

[AArch64][SVE] Avoid movprfx by reusing register for _UNDEF pseudos.

For predicated SVE instructions where we know that the inactive
lanes are undef, it is better to pick a destination register that
is not unique. This avoids introducing a movprfx to copy a unique
register to the destination operand, which would be needed to comply
with the tied operand constraints.

For example:

  %src1 = COPY $z1
  %src2 = COPY $z2
  %dst = SDIV_ZPZZ_S_UNDEF %p, %src1, %src2

Here it is beneficial to pick $z1 or $z2 as the destination register,
because if it would have chosen a unique register (e.g. $z0) then
the pseudo expand pass would need to insert a MOVPRFX to expand
the operation into:


    [10 lines not shown]
DeltaFile
+71-13llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+32-48llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
+32-48llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
+30-45llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
+24-36llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
+24-36llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
+213-22623 files not shown
+413-52429 files

LLVM/project 2095ea5llvm/include/llvm/TargetParser RISCVISAInfo.h, llvm/include/llvm/Telemetry Telemetry.h

Remove unused <set> and <map> inclusion (#167175)

DeltaFile
+1-2llvm/tools/llvm-lto/llvm-lto.cpp
+2-0llvm/tools/llvm-rc/ResourceFileWriter.h
+0-2llvm/lib/DebugInfo/PDB/Native/PDBStringTableBuilder.cpp
+0-1llvm/include/llvm/TargetParser/RISCVISAInfo.h
+0-1llvm/include/llvm/Telemetry/Telemetry.h
+0-1llvm/lib/Support/DeltaAlgorithm.cpp
+3-718 files not shown
+3-2524 files

LLVM/project 04b0599llvm/include/llvm/DebugInfo/LogicalView/Core LVScope.h, llvm/include/llvm/ExecutionEngine/Orc CompileOnDemandLayer.h RTDyldObjectLinkingLayer.h

Remove unused <array> and <list> inclusion (#167116)

DeltaFile
+0-2llvm/lib/ExecutionEngine/JITLink/COFFLinkGraphBuilder.h
+0-2llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
+0-1llvm/include/llvm/DebugInfo/LogicalView/Core/LVScope.h
+0-1llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h
+0-1llvm/include/llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h
+0-1llvm/include/llvm/ProfileData/InstrProf.h
+0-88 files not shown
+0-1614 files

LLVM/project 0367711llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines BUILD.gn, llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/misc BUILD.gn

[gn build] Port 8d950d27d686
DeltaFile
+3-3llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/misc/BUILD.gn
+2-2llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
+1-1llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines/BUILD.gn
+1-1llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/performance/BUILD.gn
+1-1llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/objc/BUILD.gn
+8-85 files

LLVM/project eef5225llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone BUILD.gn, llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cert BUILD.gn

[gn build] Port 00eacc29f009
DeltaFile
+1-0llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
+0-1llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cert/BUILD.gn
+1-12 files

LLVM/project d858aadlldb/test/Shell/Recognizer registration-unique.test verbose_trap-objc.test

[NFCI][lldb][test][Recognizer] Fix mismatched C/C++ frontend subtitutions (#167220)

The explicit language specifications for Objective C/C++ don't seem necessary either so I've removed
them too.

I found these by using Clang frontend configuration files containing language-specific options for
both C and C++ (e.g. `-std=c2y` and `-std=c++26`).

Prior-art: 21041c9
DeltaFile
+3-3lldb/test/Shell/Recognizer/registration-unique.test
+1-1lldb/test/Shell/Recognizer/verbose_trap-objc.test
+4-42 files

LLVM/project 6616f07llvm/utils/gn/secondary/llvm/lib/Target/BPF BUILD.gn

[gn] port c940bfd7e621 (BPF SDNodeInfo)
DeltaFile
+7-0llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
+7-01 files