[Clang][counted_by] Use the expr's RecordDecl that transitively contains the counter field (#205903)
The counted field could be in nested structs. This can happen when the
Expr is pointing to a field that has a struct type. The original code
didn't do a good job at finding the best RecordDecl to build the GEP off
of. It made too many assumptions about how structs' layouts.
This rewrite finds the RecordDecl that transitively contains the
__counted_by__'s counter field.
Fixes: #205652
[AArch64] Support 4-byte stack protector with large code model. (#205956)
This is a simple extension to existing code. We might need this in the
future.
CI: move libclang python byindings tests to main CI
This removes the separate python bindings CI, which run on the GitHub free
runners and take more than one hour to build libclang.
The tests are executed instead in the monolithic pipelines,
whenever clang would be tested.
This is fine in terms of resources because all the dependencies are
built anyway, and the tests themselves take less than one second to
run on the free runners.
[VPlan] Refine hasEarlyExit check. (#207791)
Currently hasEarlyExit misses cases where we have things like dead exit
blocks or simplified the middle block.
Update to check by counting the predecessors.
This fixes a case where we missed properly updating LoopInfo due to
incorrect results.
Fixes https://github.com/llvm/llvm-project/issues/206007.
Update clang/include/clang/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.h
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
[lldb] Remove ConstString from SectionList::FindSectionByName (#207296)
By having ConstString in this interface, we are forcing callers to
create a ConstString in order to perform a lookup. In many cases,
`FindSectionByName` is a best-effort interface, meaning we're creating
ConstStrings speculatively. In other cases, we were creating a
ConstString at the call-site instead of computing it once and re-using
it.
I audited all the callsites and changed all the callsites that created a
ConstString for the purpose of calling `FindSectionByName`. Other
callsites will take more time to change.
[libc++][ranges] Applied `[[nodiscard]]` to `views::zip_transform` (#207120)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.zip.transform
Towards #172124
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
[flang][OpenMP][NFC] Share SetSymbolDSA between semantics and lowering
Move the DSA helper from the private OmpAttributeVisitor::SetSymbolDSA into the
public openmp-dsa header next to GetSymbolDSA, and share the DSA flag set
through a single GetDataSharingAttributeFlags().
This lets an upcoming metadirective lowering change reuse the helper to set the
predetermined DSA of the loop induction variables of a selected variant. A
loop-associated variant is resolved during lowering, so the usual semantic DSA
resolution never runs on its loop nest and lowering must set those flags itself.
Assisted with Copilot.
[AMDGPU] Add SIPromoteGlobalLoadSAddr: promote loop-carried ptr phi to SADDR
Adds a pre-RA peephole pass that promotes global loads whose address is a
loop-carried vreg_64 phi of the form (sgpr_base + divergent_tid_offset) to the
SADDR addressing mode, replacing the VGPR address advance with scalar
S_ADD_U32/S_ADDC_U32 instructions.
Problem
-------
When a uniform global pointer is advanced by a uniform stride inside a loop
and indexed by threadIdx.x, the compiler fails to select the
`global_load ... SADDR+VADDR` form. Instead it keeps the full 64-bit address
as a per-lane VGPR induction variable and emits a pure-VGPR
`global_load ... off`, advancing the address with two V_ADD_CO_U32 per
iteration. This is the textbook SADDR+VADDR shape, but the compiler's
SelectionDAG divergence analysis conservatively treats the loop-carried phi
as divergent even though all incoming values are uniform.
Root cause
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[clang] fix getTemplateInstantiationArgs
This implements a new strategy for collecting the template arguments, by
relying on the qualifiers and template parameter lists to navigate the template
context of out-of-line definitions.
This greatly simplifies the signature of that function, by removing a bunch
of workarounds, and simpliffying a couple that weren't removed yet.
Since this now relies on qualifiers and template parameter lists,
this patch expends most of its effort making sure these are placed,
transformed and propagated to template instantiations.
Also makes the explicit specialization AST nodes stop abusing the template
parameter lists by storing it's own template parameter list, creating a
dedicated field for them, similar to partial specializations.
[Clang] Enable -Wunused-template under -Wall (#206123)
Uncomment `UnusedTemplate` in the `Unused` diagnostic group so
`-Wunused-template` becomes part of `-Wall`.
`-Wunused-template` flags unused function and variable templates with
internal linkage. In a header, such a template gives every translation
unit its own internal-linkage copy, which is a latent ODR violation
(ill-formed, no diagnostic required), so enabling this surfaces a real
class of bugs and keeps the pattern from reappearing.
### Depends on
The in-tree occurrences were cleaned up first in a series of NFC PRs
tracked by #202945. This change only builds clean once those land, so CI
will be red on any area whose cleanup is not yet merged. Remaining
prerequisites:
Approved
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clang/AMDGPU: Stop passing redundant -target-cpu to cc1
Now that the exact target is encoded in the triple's subarch field,
-target-cpu is redundant. This avoids polluting the resultant IR with
unwanted "target-cpu" attributes. The net result is the desired codegen
when compiling libraries for a major subarch and linking it into a
program compiled for a specific arch. e.g., compiling for "gfx9-generic"
would pollute the IR with "target-cpu"="gfx9-generic", so codegen
would ultimately be performed for the generic target even after
linking into the concrete gfx9 cpu. The specialization will now be
achieved by merging the triples without the linker or optimization
passes needing to fixup function attributes.
clang/AMDGPU: Validate -target-cpu in cc1 is valid for the subarch
Restrict the reported list of valid target-cpus based on the triple's
subarch. This is more consistent with how other targets validate the
target CPU name. Currently we have split handling validating the target
name for the triple in both the driver and here. The driver based diagnostic
seems to be an amdgpu-ism in 2 different places (though there is one arm
validation emitting the same diagnostic). In the future we could probably
drop those.
AMDGPU: Migrate unittests to subarch triples
Replace specifying a processor name with the triple
subarch.
The register-limit helpers in AMDGPUUnitTests.cpp that enumerate every
valid CPU via fillValidArchListAMDGCN still pass the CPU explicitly, as
does the MC Disassembler smoke test (its C disassembler API derives the
subtarget from the CPU, not the triple subarch).
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang: Start using new amdgpu subarch triples
Fixup invocations using --target=amdgcn + -mcpu to introduce
the subarch in the triple.
For offload toolchains, a single toolchain is constructed for the
top level amdgpu architecture, and the effective triple is used for
target specific tool invocations.
The specifics of the resource directory layout are tbd. This does
try to find resources in the subarch named directory. The paths
are searched at toolchain creation time, so that does not work
when there are multiple subarches.
Fixes #154925
AMDGPU: Introduce amdgpu triple arch
Move towards using the triple for representing incompatible
ISA changes. Use the subarch field to represent the various
incompatible cases. Previously we pretended a single triple arch
was universally compatible, and only distinguished by function
level subtargets. Move towards using distinct triples to enable
more sophisticated toolchain handling in the future, like proper
runtime library linking.
Introduce a new subarch per unique ISA, but also introduce
"major subarches" which are compatible by a set of covered
minor ISA versions. These map to the existing generic targets.
There are a few placeholder subarch entries, which currently
have missing backing generic arches for codegen.
This should be the preferred triple arch name going forward,
but is treated as an alias of amdgcn. This does not yet change
clang to emit the new triples.
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[docs][NFC] Some small cleanup in llvm_sphinx (#207818)
Format the doc-comment suggested import to match what `black` prefers,
and isolate the `import` as the only statement in the `try` for
`myst_parser`.
