LLVM/project 59f3a48clang/test/Preprocessor riscv-target-features.c, llvm/docs ReleaseNotes.md

[llvm][RISCV] Bump svukte to 1.0 (#211199)

The PR updated: https://github.com/riscv/riscv-isa-manual/pull/1564

---------

Co-authored-by: Craig Topper <craig.topper at sifive.com>
DeltaFile
+3-3clang/test/Preprocessor/riscv-target-features.c
+2-2llvm/test/MC/RISCV/attribute-arch.s
+2-2llvm/test/CodeGen/RISCV/attributes.ll
+1-1llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+1-1llvm/lib/Target/RISCV/RISCVFeatures.td
+2-0llvm/docs/ReleaseNotes.md
+11-92 files not shown
+13-118 files

LLVM/project 6fd20a2llvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.h LoongArchELFStreamer.h

address @MaskRay's comments

Created using spr 1.3.7
DeltaFile
+18-18llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+12-9llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp
+11-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.h
+3-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+44-274 files

LLVM/project afa36ecllvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.h LoongArchELFStreamer.h

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+23-20llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+12-9llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp
+11-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.h
+3-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+49-294 files

LLVM/project bce5312llvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.h LoongArchELFStreamer.h

rebase

Created using spr 1.3.7
DeltaFile
+23-20llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+12-9llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp
+11-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.h
+3-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+49-294 files

LLVM/project 6879fafllvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.h LoongArchELFStreamer.h

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+23-20llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+12-9llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp
+11-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.h
+3-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+49-294 files

LLVM/project adb5a33llvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.h LoongArchELFStreamer.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+23-20llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+12-9llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp
+11-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.h
+3-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+49-294 files

LLVM/project 4132205llvm/lib/Target/X86/MCTargetDesc X86EncodingOptimization.cpp, llvm/test/MC/X86 symbolic-vcmp-predicate.s

[X86] Don't shrink VEX3 to VEX2 on a symbolic compare predicate (#213172)

`llvm-mc` asserts on a VCMP predicate given as a symbol:

```asm
vcmpps $f0, %xmm0, %xmm1, %xmm2
```

```
Assertion failed: isImm() && "This is not an immediate", MCInst.h:85
```

`optimizeInstFromVEX3ToVEX2` reads the predicate with `getImm()` to
decide whether the operands commute. A symbolic predicate is not known
until link time, so that decision cannot be made here. Decline the
shrink instead.

Unlike the sibling FPCLASS issues (#185364, #185365) this one is on the
encoding path and asserts under `--filetype=obj` too, so a release build

    [6 lines not shown]
DeltaFile
+20-0llvm/test/MC/X86/symbolic-vcmp-predicate.s
+6-0llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+26-02 files

LLVM/project 7a618a2llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv fold-binary-reduce-zve32x-crash.ll

[RISCV] Fix assertion in combineBinOpOfExtractToReduceTree on type mismatch (#202201)

combineBinOpOfExtractToReduceTree asserts that the extract source
vector's element type equals the binop's value type
(SrcVecVT.getVectorElementType() == VT). This invariant does not hold
for all valid inputs.

A <1 x i1> binary operation under -mattr=+zve32x reaches this point with
the source vector element type differing from VT, which trips the
assertion in an assertions-enabled build and silently proceeds on a
false assumption otherwise.

Convert the assertion into an early return, so the combine declines when
its precondition is not met. This matches the existing bail-out style in
the same function (the isScalableVector and getScalarSizeInBits() >
getELen() checks immediately following). The change only ever skips the
fold; it never alters correct output.

Generative AI was used for the test case. The fix

    [3 lines not shown]
DeltaFile
+17-0llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce-zve32x-crash.ll
+2-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+19-12 files

LLVM/project abe5aa5llvm/lib/Analysis LoopAccessAnalysis.cpp, llvm/test/Analysis/LoopAccessAnalysis negative-step-deref-off-by-eltsize.ll

[LAA][NFC] Refactor deref no-wrap check; expose broken reverse-loop bounds (#211960)

Split evaluatePtrAddRecAtMaxBTCWillNotWrap into two stages: compute
MaxOffset based on the step direction, then apply the shared
MaxOffset <= DerefBytes check.

Rename intermediate values to reflect what they actually represent.

This restructuring makes two long-standing off-by-EltSize issues in
the negative-step path explicit:

* The lower-bound check is over-conservative by EltSize.
* The upper-bound check under-counts by EltSize.
DeltaFile
+126-0llvm/test/Analysis/LoopAccessAnalysis/negative-step-deref-off-by-eltsize.ll
+35-25llvm/lib/Analysis/LoopAccessAnalysis.cpp
+161-252 files

LLVM/project 9c5eb3allvm/lib/Target/AMDGPU AMDGPUStaticSimulator.cpp, llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll

[AMDGPU] gfx1250 co-execution scheduler

Snapshot of the gfx1250 co-execution scheduling work, squashed into a
single commit on top of llvm/llvm-project e2a39f504fee.

Includes the co-execution window model (AMDGPUCoExecInfo.h), the
CoExecSchedStrategy window-slot-demand machinery, pre-RA and post-RA
co-execution hazard tracking in GCNHazardRecognizer, the gfx1250 static
simulator (AMDGPUStaticSimulator), expert-mode waitcnt work in
SIInsertWaitcnts, and the supporting lit and MIR tests.

Authored by, in no particular order:

  Austin Kerbow, Jeffrey Byrnes, Alexey Sachkov, Lucas Ramirez,
  Volkan Keles, Hideki Saito, Jay Foad, Brendon Cahoon,
  Ilia Cherniavskii, Alexander Weinrauch, Vigneshwar, proaditya,
  mssefat, Lei Zhang
DeltaFile
+18,466-18,814llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,015-1,902llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,590-1,599llvm/test/CodeGen/AMDGPU/bf16.ll
+1,471-1,408llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,791-0llvm/lib/Target/AMDGPU/AMDGPUStaticSimulator.cpp
+1,419-1,356llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+27,752-25,079322 files not shown
+68,393-36,204328 files

LLVM/project 07379fellvm/lib/Target/AMDGPU AMDGPUStaticSimulator.cpp, llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll

[AMDGPU] gfx1250 co-execution scheduler

Snapshot of the gfx1250 co-execution scheduling work, squashed into a
single commit on top of llvm/llvm-project 7570d2daec56.

Includes the co-execution window model (AMDGPUCoExecInfo.h), the
CoExecSchedStrategy window-slot-demand machinery, pre-RA and post-RA
co-execution hazard tracking in GCNHazardRecognizer, the gfx1250 static
simulator (AMDGPUStaticSimulator), expert-mode waitcnt work in
SIInsertWaitcnts, and the supporting lit and MIR tests.

Authored by, in no particular order:

  Austin Kerbow, Jeffrey Byrnes, Alexey Sachkov, Lucas Ramirez,
  Volkan Keles, Hideki Saito, Jay Foad, Brendon Cahoon,
  Ilia Cherniavskii, Alexander Weinrauch, Vigneshwar, proaditya,
  mssefat, Lei Zhang
DeltaFile
+18,232-18,737llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,041-1,932llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,720-1,697llvm/test/CodeGen/AMDGPU/bf16.ll
+1,471-1,408llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,791-0llvm/lib/Target/AMDGPU/AMDGPUStaticSimulator.cpp
+1,419-1,356llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+27,674-25,130538 files not shown
+91,465-48,858544 files

LLVM/project f1116ccclang/lib/CodeGen CodeGenModule.cpp, clang/lib/CodeGen/Targets PPC.cpp

clang: Emit "long-double-type" module flag generically

Move emission of the "long-double-type" module flag out of PowerPC
and into generic code, so it describes the long double format for all
targets.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+0-25clang/lib/CodeGen/Targets/PPC.cpp
+24-0clang/lib/CodeGen/CodeGenModule.cpp
+23-0clang/test/CodeGen/long-double-type-module-flag.c
+0-17clang/test/CodeGen/ppc64-long-double-type-attr.c
+47-424 files

LLVM/project be70866llvm/test/CodeGen/AMDGPU maximumnum.ll amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-local.mir

Merge main
DeltaFile
+9,398-9,218llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+9,385-9,006llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,993-6,921llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,803-5,808llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+5,575-5,393llvm/test/CodeGen/AMDGPU/maximumnum.ll
+50,222-36,34610,642 files not shown
+596,831-421,22010,648 files

LLVM/project 6466eb4lld/ELF Symbols.h

Review feedback
DeltaFile
+4-9lld/ELF/Symbols.h
+4-91 files

LLVM/project f740764llvm/test/CodeGen/AMDGPU maximumnum.ll amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-local.mir

Merge main
DeltaFile
+9,398-9,218llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+9,385-9,006llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,993-6,921llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,803-5,808llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+5,575-5,393llvm/test/CodeGen/AMDGPU/maximumnum.ll
+50,222-36,34610,642 files not shown
+596,827-421,21110,648 files

LLVM/project 8a5d565llvm/test/tools/TargetParser get-triple-system-name.test

TargetParser: Fix test quoting lit substitution in run line (#213570)
DeltaFile
+1-1llvm/test/tools/TargetParser/get-triple-system-name.test
+1-11 files

LLVM/project 7891000llvm/test/CodeGen/AMDGPU maximumnum.ll amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-local.mir

Merge main
DeltaFile
+9,398-9,218llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+9,385-9,006llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,993-6,921llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,803-5,808llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+5,575-5,393llvm/test/CodeGen/AMDGPU/maximumnum.ll
+50,222-36,34610,642 files not shown
+596,827-421,21110,648 files

LLVM/project 1d5ea98llvm/test/CodeGen/AMDGPU maximumnum.ll amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-private.mir legalize-load-local.mir

Merge main
DeltaFile
+9,398-9,218llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+9,385-9,006llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,993-6,921llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,803-5,808llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+5,575-5,393llvm/test/CodeGen/AMDGPU/maximumnum.ll
+50,222-36,34610,642 files not shown
+596,827-421,21110,648 files

LLVM/project 6849789llvm/test/CodeGen/AMDGPU sink-fmul-fadd.ll, llvm/test/Transforms/CodeGenPrepare/AMDGPU sink-fmul-fadd-contract-fast.ll sink-fmul-fadd.ll

[NFC][AMDGPU] Add tests for an fmul split from its fadd/fsub user (#213303)

Record the current behaviour over the types and subtargets where the
fusion rules differ, f32, f16, bf16, f64, v2f32 and v2f16, with
denormals both enabled and flushed, with and without the contract flags,
and under -fp-contract=fast.

Contributes to https://github.com/llvm/llvm-project/issues/211092
DeltaFile
+1,011-0llvm/test/CodeGen/AMDGPU/sink-fmul-fadd.ll
+571-0llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-fmul-fadd.ll
+57-0llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-fmul-fadd-contract-fast.ll
+1,639-03 files

LLVM/project db8d8fdllvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination xor-as-sub.ll

[ConstraintElim] Decompose xor %a, -1 as -1 - %a in the signed system. (#213476)

InstCombine canonicalizes sub nsw i8 -1, %a -> xor i8 %a, -1. Decompose
the XOR as `sub nsw -1, %a` in the signed system

Alive2 Proof: https://alive2.llvm.org/ce/z/f_YVjH

This triggers quite rarely in C/C++ workloads (no end-to-end changes in
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/840), found
one instance in Blender. One simple end-to-end C example is
https://clang.godbolt.org/z/G343shYje

This is part of an effort to improve ConstraintElimination support for
IR generated by the Swift compiler, where such patterns are more common
due to a number of signed runtime checks.

PR: https://github.com/llvm/llvm-project/pull/213476
DeltaFile
+45-0llvm/test/Transforms/ConstraintElimination/xor-as-sub.ll
+8-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+53-02 files

LLVM/project 029a853lld/ELF SyntheticSections.cpp SyntheticSections.h, lld/test/ELF ppc32-ifunc-nonpreemptible-pic.s ppc32-ifunc-nonpreemptible-nopic.s

[ELF] Emit synthetic local in symbol table for non-preemptible IFUNC

Currently we create an internal alias of the original symbol and then
rewrite the latter to point to the IPLT entry, which means we lose
symbol table information for the actual resolver. In practice compilers
also emit a normal function symbol for the resolver due to how IFUNCs
are represented in GNU C so that at least shows up, but we shouldn't be
relying on it. By emitting a synthetic local we can keep having a symbol
for the resolver whilst still redirecting references to the IPLT entry.
DeltaFile
+18-0lld/test/ELF/gnu-ifunc-i386.s
+2-3lld/ELF/Relocations.cpp
+1-2lld/ELF/SyntheticSections.h
+1-1lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s
+1-1lld/test/ELF/ppc32-ifunc-nonpreemptible-nopic.s
+1-1lld/ELF/SyntheticSections.cpp
+24-86 files

LLVM/project 529700dlld/ELF Symbols.h

[NFC][ELF] Remove Symbol's unused copy constructor

Now that we are no longer copying symbols via the copy constructor we
can remove it. Given we track symbol pointers in various data structures
it can be dangerous to have multiple objects for the same symbol that
would risk being viewed inconsistently, or even moved and the original
lost, though no such cases exist upstream that I'm aware of.

Copying a symbol entirely is also a weird thing to do, and can be
inefficient, so when copies are being made it's best to be explicit
about the members to copy. This also makes it clearer to understand what
members are relevant, rather than implicitly copying all the members,
most of which aren't relevant in practice.

Whilst the copy/move constructors/assignment operators are currently
implicitly deleted due to the atomic flags member, explicitly delete
them all so they remain deleted in case that ever changes.
DeltaFile
+11-3lld/ELF/Symbols.h
+11-31 files

LLVM/project 4ee575blld/ELF Relocations.cpp

[NFC][ELF] Create fresh alias in handleNonPreemptibleIfunc

We don't need to copy the full symbol here, we just want an internal
alias to use for the IPLT and IGOTPLT entries and IRELATIVE relocation's
addend.
DeltaFile
+3-1lld/ELF/Relocations.cpp
+3-11 files

LLVM/project f12f76clld/ELF Relocations.cpp

[NFC][ELF] Only create alias in handleNonPreemptibleIfunc if needed

In the no direct relocations case, the original IFUNC symbol keeps its
value, and so there's no need to create a separate alias; it's only
needed when the original symbol is being redirected to the IPLT as a
normal function symbol.

This change also shifts the isInIplt assignment to be explicit and
mirror the allocateAux/pltIdx uses, rather than relying on makeDefined
copying it, and to be clear that this is in fact deliberately and
consistently being copied like them.
DeltaFile
+23-18lld/ELF/Relocations.cpp
+23-181 files

LLVM/project 42b86celld/ELF Relocations.cpp

[NFC][ELF] Avoid need to copy Symbol in replaceWithDefined (#210612)

Firstly, by overwriting the symbol, it will have its existing flags, so
there is no need to copy them back; all we need to do is mask out the
other bits on the existing symbol.

Secondly, copying the whole symbol just to preserve the symbol version
that gets cleared by Defined::overwrite is a waste; just copy the single
member to reinstate it.
DeltaFile
+3-4lld/ELF/Relocations.cpp
+3-41 files

LLVM/project 9409601llvm/test/CodeGen/AArch64/GlobalISel form-bitfield-extract-from-and.mir opt-shifted-reg-compare.mir, llvm/test/CodeGen/M68k/Atomics rmw.ll

rebase for new test case showing changes

Created using spr 1.3.8-wip
DeltaFile
+1,042-470llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
+521-235llvm/test/CodeGen/M68k/Atomics/rmw.ll
+180-180llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir
+323-0mlir/test/Dialect/X86/move-acc-for-contract-loop.mlir
+112-112llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
+68-142llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
+2,246-1,139319 files not shown
+7,402-3,330325 files

LLVM/project b5f3a82clang/test/SemaOpenCL builtins-image-store-param-gfx942-err.cl builtins-image-store-image-feature-err.cl

clang/AMDGPU: Fix confused image builtin availability tests

These tests appear to have been copy paste from other image error
tests, which were checking for invalid argument validation. The point
of these tests were to reject image builtins on unsupported targets,
and not just gfx942. Rename the tests, and fix the invalid argument usage.
Each builtin should be used in a valid way.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+0-230clang/test/SemaOpenCL/builtins-extended-image-param-gfx942-err.cl
+230-0clang/test/SemaOpenCL/builtins-extended-image-err.cl
+0-219clang/test/SemaOpenCL/builtins-image-load-param-gfx942-err.cl
+219-0clang/test/SemaOpenCL/builtins-image-load-image-feature-err.cl
+0-129clang/test/SemaOpenCL/builtins-image-store-param-gfx942-err.cl
+129-0clang/test/SemaOpenCL/builtins-image-store-image-feature-err.cl
+578-5786 files

LLVM/project 8bdbeacflang/lib/Optimizer/Builder MIFCommon.cpp

[flang] Remove unused includes in MIFCommon.cpp to fix GCC debug-build link errors (#213508)

An undefined symbol error when building Flang in debug mode. This PR fix
this by remove unused include file. Here is a brief error log:
`/usr/bin/ld:lib/libFIRBuilder.a(MIFCommon.cpp.o): in function
Fortran::evaluate::FunctionRef<Fortran::evaluate::Type<(Fortran::common::TypeCategory)4,
1> >::~FunctionRef()':`.
DeltaFile
+0-2flang/lib/Optimizer/Builder/MIFCommon.cpp
+0-21 files

LLVM/project e7dd336llvm/lib/Target/M68k M68kSubtarget.h M68kInstrInfo.td, llvm/test/CodeGen/M68k/Atomics rmw.ll

[M68k] Prevent COPY instruction from killing live condition flags (#168485)
DeltaFile
+1,042-470llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
+521-235llvm/test/CodeGen/M68k/Atomics/rmw.ll
+112-56llvm/lib/Target/M68k/M68kInstrInfo.cpp
+4-10llvm/lib/Target/M68k/M68kInstrData.td
+3-0llvm/lib/Target/M68k/M68kInstrInfo.td
+1-0llvm/lib/Target/M68k/M68kSubtarget.h
+1,683-7716 files

LLVM/project 6be9888libcxx/include variant

Speed up std::visit() compile times by another 42% (#213203)

This avoids defining an `enum`, which appears to be expensive for Clang.
DeltaFile
+30-30libcxx/include/variant
+30-301 files