[LoopPeel] Peel last iteration to enable load widening
In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., i32) for
all other N-1 iterations.
Patterns such as:
```
%a = load i8, ptr %p
%b = load i8, ptr %p+1
%c = load i8, ptr %p+2
...
%p.next = getelementptr i8, ptr %p, 3
```
Can be transformed to:
```
%wide = load i32, ptr %p ; Read 4 bytes
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[BOLT] Fixed PerfScript unittest for X86 (#207408)
The test was not prepared to run on X86 target.
This change parameterized the test function to ensure proper
initialization for different targets.
[libc] Implement sockatmark (#205400)
This patch implements sockatmark as a simple wrapper around
ioctl(SIOCATMARK).
I don't test it with actual out of band data, as that requires a TCP
connection, which is more complicated to set up.
Assisted by Gemini.
[AArch64][Bitcode] Use target memory for SME state (#205829)
Model AArch64 ZA and ZT0 intrinsic state using target_mem instead of
inaccessiblemem.
Bump the bitcode memory-attribute encoding and upgrade old AArch64
bitcode so prior inaccessiblemem effects are preserved on the new target
memory locations. Non-AArch64 bitcode keeps the old interpretation.
[Clang] Require X86 backend for some coroutine tests (#207681)
The wrapper functions are generated without target features.
They can still be inlined based on target-specific logic, but this
requires the target to be available.
We should fix this by properly generating the target features,
but for now add a REQUIRES to unbreak the tests.
[NVPTX] Add missing Range attr to tensormap.replace intrinsics. (#207099)
Add missing `Range=[0, 5)` for `%ord imm` operand in
`nvvm.tensormap.replace` intrinsics.
[mlir][memref] Implement ValueBoundsOpInterface for memref.extract_strided_metadata/assume_alignment (#206466)
Add ValueBoundsOpInterface external models for memref.assume_alignment
and memref.extract_strided_metadata, so dimension and metadata bounds
can be propagated through these view-like ops during value-bounds
analysis.
[AArch64] Fold -smin/-smax(X,0) to neg + masked AND
smin(X, 0) lowers to X & M and smax(X, 0) to X & ~M, where M is X
arithmetically shifted right by the bit width minus one (a 0 or -1 sign
mask). When negation is applied, -(X & M) is equivalent to (-X) & M. The
latter form is slightly better because the shift no longer depends on the
negation and the two can issue in parallel. Instruction count is unchanged.
The fold is suppressed when the result feeds a comparison because then the
negation is folded into a cmn for free. This covers the compare feeding a
SETCC, SELECT_CC, or BR_CC.
smin: https://alive2.llvm.org/ce/z/SfmPfH
smax: https://alive2.llvm.org/ce/z/_lVM0r
Assisted-by: Opus 4.8
[libc++abi] Always enable -fvisibility=hidden (#207333)
Building with `-fvisibility=hidden` is generally a good idea, since it
avoids unnecessary relocations when loading a dylib. For libc++abi this
should be a no-op, since most things are annotated explicitly. By
enabling `-fvisibility=hidden` we can remove these explicit annotations
however.
[LoongArch] Remove inaccurate LASX conversion pattern and use [X]VFFINT.S.L instead (#207107)
Original LASX signed/unsigned 64-bit integer & floating point will
suffer from double rounding issue, due to it implements such logic: `i64
-> double -> float` that will lead to precision loss. So delete it and
introduce the `[X]VFFINT.S.L` instruction, which could convert 4 or 8
signed 64-bit integer into float in one instrunction.
Also, create the `MergeBlocksConvert` helper function to reuse the logic
about merge two blocks into one, avoid unnecessary code size bloat.
[libc++] Split the multidimensional algorithms out of uninitialized_algorithms.h (#207447)
While these algorithms are conceptually related to other
`uninitialized_*` algorithms, they're likely only ever going to be used
by `shared_ptr`. `uninitialized_algorithms.h` itself is also getting
rather large, so it makes sense to split the multidimensional versions
into their own header.
Fixes #207417
[InlineCost] Never inline functions with incompatible target features (#205113)
If inlining is unsound due to incompatible target feature attributes, we
should not inline the call even if alwaysinline is set. This will likely
result in a crash during instruction selection.
We tried this previously in
https://github.com/llvm/llvm-project/commit/d6f994acb3d545b80161e24ab742c9c69d4bbf33,
but the change had to be reverted because the quality of our
areInlineCompatible() hooks was very bad at the time, which resulted in
inlining not happening in many cases where it was safe.
I think we're in a much better position now. Most notably, we now have a
default areInlineCompatible() implementation that actually does
something sensible (https://github.com/llvm/llvm-project/pull/117493),
inlining compatibility for target features is now specified in TableGen
(https://github.com/llvm/llvm-project/pull/205348). Various
target-specific issues have been fixed as well, e.g. ARM's overly strict
feature whitelist (https://github.com/llvm/llvm-project/pull/205763) and
X86's overly conservative ABI compatibility checks
(https://github.com/llvm/llvm-project/pull/205106).
[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic
The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.
Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:
- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
Operations use APInt arithmetic at WideBits, chosen to guarantee no
intermediate overflow:
$$
WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
$$
This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
extra bits.
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[clangd] Null-check AutoTypeLoc in CollectExtraHighlightings::VisitDeclaratorDecl (#207323)
A Decl's getType() can have a getContainedAutoType() without
its TypeSourceInfo's type having one, because the two types
can differ in type sugar such as DecltypeType which
getContainedAutoType[Loc]() deliberately does not look through.
Fixes https://github.com/llvm/llvm-project/issues/207139
[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic
The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.
Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:
- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
Operations use APInt arithmetic at WideBits, chosen to guarantee no
intermediate overflow:
$$
WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
$$
This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
extra bits.
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[Hexagon] Allow reservation of caller saved registers via -ffixed-rXX (#205733)
Previously, hexagon allowed only callee saved registers to be reserved
since reserving caller saved regs can create problems, since it cannot
be sure that the callee (from a different module) also reserves the
register.
The responsibility of reserving register and managing it is now on the
user. However, a warning will be displayed if the user tries to reserve a
caller saved register.
---------
Co-authored-by: quic-santdas <quic_santdas at qti.qualcomm.com>
