LLVM/project fa2eabdclang/test/Headers __clang_hip_math.hip, llvm/lib/Transforms/Utils SimplifyCFG.cpp

[SimplifyCFG] Hoist common code for switch multi-case destinations (#165700)

Previously, hoistCommonCodeFromSuccessors did not support hoisting
common code for multi-case destinations of `switch`.

However, if all the predecessors of a given Succ are the same (i.e.,
multi-case destination), it is safe to hoist the common code from Succ
to Pred, which is what this PR does.

See discussion
https://github.com/llvm/llvm-project/pull/165570#discussion_r2473290327.
Alive2 proof: https://alive2.llvm.org/ce/z/cYuczq
Optimization Impact:
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/3003
DeltaFile
+180-201clang/test/Headers/__clang_hip_math.hip
+27-17llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+35-5llvm/test/Transforms/SimplifyCFG/hoist-common-code.ll
+242-2233 files

LLVM/project 5fc8e87mlir/include/mlir/Dialect/XeGPU/IR XeGPUOps.td, mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp

[MLIR][XeGPU] Retain anchor op layouts for XeGPU nD ops (#170934)

This PR adds support to retain the anchor op layouts (after dropping
what's not required) for xegpu nD ops during workgroup to subgroup &
unroll transformation
DeltaFile
+12-3mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
+9-6mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+12-3mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+13-0mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+8-4mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+6-3mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+60-192 files not shown
+64-228 files

LLVM/project 8fe38c4clang/lib/AST/ByteCode Pointer.cpp Interp.h

[clang][bytecode] Allocate InitMaps via Program/InterpState allocators (#170272)

Save them as a pointer intead of using a shared_ptr. This we we can use
the pointer integer value to differentiate the "no initmap yet" and "all
values initialzed" cases.

This regresses one test case in const-eval.c, but as it turns out, that
only worked coincidentally before.
DeltaFile
+57-67clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+20-38clang/lib/AST/ByteCode/Descriptor.cpp
+20-19clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+26-6clang/lib/AST/ByteCode/Descriptor.h
+11-9clang/lib/AST/ByteCode/Pointer.h
+165-1706 files not shown
+185-18812 files

LLVM/project 75aa7bdcompiler-rt/test/asan/TestCases scariness_score_test.cpp

[ASan] Disable another test on Darwin due to ulimit stack issues

Similar to #170786.
DeltaFile
+4-0compiler-rt/test/asan/TestCases/scariness_score_test.cpp
+4-01 files

LLVM/project 9e9e64aclang/lib/CodeGen CGOpenMPRuntime.cpp, clang/test/OpenMP target_firstprivate_pointer_codegen.cpp target_defaultmap_codegen_01.cpp

[OpenMP] Fix defaultmap(firstprivate:pointer) handling  (#169622)

This fixes a bug where pointers from defaultmap(firstprivate:pointer)
were incorrectly treated as firstprivate literals, causing
OMP_MAP_LITERAL to be set. This prevented the runtime from performing
device address lookup.
Realted PR https://github.com/llvm/llvm-project/pull/167879

Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net>
DeltaFile
+169-0clang/test/OpenMP/target_firstprivate_pointer_codegen.cpp
+65-12clang/lib/CodeGen/CGOpenMPRuntime.cpp
+2-2clang/test/OpenMP/target_defaultmap_codegen_01.cpp
+1-1clang/test/OpenMP/target_map_codegen_26.cpp
+237-154 files

LLVM/project 58b319bclang/lib/CIR/Analysis FallThroughWarning.cpp, clang/lib/Frontend CompilerInvocation.cpp

[CIR][Analyzer] Revamping codebase and switch implementation
DeltaFile
+159-63clang/lib/CIR/Analysis/FallThroughWarning.cpp
+141-0clang/test/CIR/Analysis/fallthrough_2.cir
+6-0clang/lib/Frontend/CompilerInvocation.cpp
+3-2clang/test/CIR/Analysis/fallthrough_switch.c
+3-0clang/lib/Sema/SemaDecl.cpp
+1-1clang/test/CIR/Analysis/fallthrough_1.c
+313-662 files not shown
+316-678 files

LLVM/project b889df3llvm/lib/Transforms/Instrumentation MemProfUse.cpp, llvm/test/Transforms/PGOProfile memprof-dump-matched-alloc-site.ll

[MemProf] Add option to print function GUIDs during matching (#170946)

For debugging, add -memprof-print-function-guids option that will cause
memprof matching to emit the computed function GUID for every function
definition in the module to stderr. This is helpful because the profile
only contains the function GUID and not the names.
DeltaFile
+8-0llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
+5-2llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
+13-22 files

LLVM/project 06f9deellvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,628 files not shown
+211,870-242,6594,634 files

LLVM/project 367ebafllvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,626 files not shown
+211,867-242,6564,632 files

LLVM/project e5397f1mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp, mlir/test/Dialect/XeGPU subgroup-distribute-unit.mlir subgroup-distribute.mlir

add unit tests and fix bugs
DeltaFile
+40-28mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+65-0mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
+1-1mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
+106-293 files

LLVM/project 23591c3llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,626 files not shown
+211,867-242,6564,632 files

LLVM/project 9e98712llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,625 files not shown
+211,863-242,6524,631 files

LLVM/project 58c6006llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,625 files not shown
+211,863-242,6524,631 files

LLVM/project 2ec72dallvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,608 files not shown
+211,746-242,5784,614 files

LLVM/project 3196a54llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,608 files not shown
+211,746-242,5784,614 files

LLVM/project 75d6068llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,608 files not shown
+211,746-242,5784,614 files

LLVM/project acbd52bllvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,608 files not shown
+211,746-242,5784,614 files

LLVM/project f96bf3bllvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,605 files not shown
+211,736-242,5644,611 files

LLVM/project 3f3fd2fllvm/lib/Target/AArch64 AArch64AsmPrinter.cpp, llvm/lib/Transforms/Scalar SROA.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+78-5llvm/lib/Transforms/Scalar/SROA.cpp
+73-0llvm/test/Transforms/SROA/protected-field-pointer.ll
+7-2llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+6-0llvm/test/CodeGen/AArch64/ptrauth-irelative.ll
+164-74 files

LLVM/project e198097llvm/lib/Transforms/Scalar SROA.cpp, llvm/test/Transforms/SROA protected-field-pointer.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+78-5llvm/lib/Transforms/Scalar/SROA.cpp
+73-0llvm/test/Transforms/SROA/protected-field-pointer.ll
+151-52 files

LLVM/project 90e3ac6llvm/include/llvm-c Core.h, llvm/include/llvm/IR Instructions.h

Revert "[IR] Don't store switch case values as operands" (#170962)

Reverts llvm/llvm-project#166842

Breaks Mips LLVM tests, and LLD on bots.
See llvm/llvm-project#166842
DeltaFile
+13-22llvm/include/llvm/IR/Instructions.h
+15-18llvm/lib/IR/Instructions.cpp
+0-24llvm/include/llvm-c/Core.h
+0-23llvm/unittests/IR/InstructionsTest.cpp
+10-10llvm/lib/IR/User.cpp
+9-8llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+47-1057 files not shown
+55-14113 files

LLVM/project 72d5fe5clang/lib/Headers cpuid.h

[clang] [doc] Added documentation to intrinsics in cpuid.h (#170507)

Added doxygen comments to 4 intrinsincs in cpuid.h
DeltaFile
+96-0clang/lib/Headers/cpuid.h
+96-01 files

LLVM/project 7e39ae7llvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests import.ll

[LTT] Add `unknown` branch weights when lowering type tests with conditional
DeltaFile
+13-10llvm/test/Transforms/LowerTypeTests/import.ll
+5-1llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+0-2llvm/utils/profcheck-xfail.txt
+18-133 files

LLVM/project 4294dc7llvm/include/llvm-c Core.h, llvm/include/llvm/IR Instructions.h

Revert "[IR] Don't store switch case values as operands (#166842)"

This reverts commit f26360f2150e7ff916f2aa5d5fe3ff32d1780c8c.
DeltaFile
+13-22llvm/include/llvm/IR/Instructions.h
+15-18llvm/lib/IR/Instructions.cpp
+0-24llvm/include/llvm-c/Core.h
+0-23llvm/unittests/IR/InstructionsTest.cpp
+10-10llvm/lib/IR/User.cpp
+9-8llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+47-1057 files not shown
+55-14113 files

LLVM/project 6a148c5llvm/test/Transforms/LowerTypeTests import.ll

[NFC] Run UTC --check-globals on LowerTypeTests/import.ll
DeltaFile
+154-136llvm/test/Transforms/LowerTypeTests/import.ll
+154-1361 files

LLVM/project 472fd70llvm/utils/git code-lint-helper.py

[Github][CI] Introduce `LintHelper` class in `code-lint-helper.py`  (#168827)

This commit introduces a new `LintHelper` class to
`llvm/utils/git/code-lint-helper.py`, which lays the groundwork for
integrating additional linters (`doc8`) into Github Action workflow.

---------

Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
DeltaFile
+231-195llvm/utils/git/code-lint-helper.py
+231-1951 files

LLVM/project e546d0fllvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/RISCV fshl_fshr.ll

[RISCV][TTI] Add cost model for ROTL/ROTR (#170824)

A funnel shift with the same first two operands is a rotate. When
`Zbb/Zbkb` is enabled we can use the `ROL(W)/ROR(I)(W)` instruction to
represent this. Add cost model support for this.

Similar to https://github.com/llvm/llvm-project/pull/169335 for AArch64.
DeltaFile
+181-0llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
+17-0llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+198-02 files

LLVM/project b1ee4d0llvm/lib/Target/RISCV RISCVMergeBaseOffset.cpp

[RISCV] Refactor some code in RISCVMergeBaseOffset.NFC (#170839)

DeltaFile
+21-17llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+21-171 files

LLVM/project 6d8714bclang/docs ClangIRCodeDuplication.rst index.rst

[Clang][CIR][Doc] Document CIR code duplication plans (#166457)

This adds a document describing known problems with code duplication in
the CIR codegen implementation, strategies to mitigate the risks caused
by that code duplication, and a general long-term plan for minimizing
the problem.
DeltaFile
+245-0clang/docs/ClangIRCodeDuplication.rst
+1-1clang/docs/index.rst
+246-12 files

LLVM/project ee77c58llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-cfg.ll

Reland "AMDGPU/PromoteAlloca: Simplify how deferred loads work (#170510)" (#170955)

The second pass of promotion to vector can be quite simple. Reflect that
simplicity in the code for better maintainability.

v2:
- don't put placeholders into the SSAUpdater, and add a test that shows
the problem
DeltaFile
+36-46llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+33-0llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll
+69-462 files