LLVM / project - FreshBSD

LLVM/project ae3d310 — clang-tools-extra/clangd SemanticHighlighting.cpp, clang-tools-extra/clangd/unittests SemanticHighlightingTests.cpp

2026-07-06 07:03:07 UTC by ingoneuse via GitHub on ⎇

main

[clangd] Null-check AutoTypeLoc in CollectExtraHighlightings::VisitDeclaratorDecl (#207323)

A Decl's getType() can have a getContainedAutoType() without
its TypeSourceInfo's type having one, because the two types
can differ in type sugar such as DecltypeType which
getContainedAutoType[Loc]() deliberately does not look through.

Fixes https://github.com/llvm/llvm-project/issues/207139

Delta		File
+8	-3	clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
+4	-2	clang-tools-extra/clangd/SemanticHighlighting.cpp
+12	-5	2 files

LLVM/project 8cc99f7 — llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

2026-07-06 06:58:52 UTC by Ruoyu Qiu on ⎇

users/cabbaken/rewriteBanerjeeTest

[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic

The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.

Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:

- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
  Operations use APInt arithmetic at WideBits, chosen to guarantee no
  intermediate overflow:
  $$
    WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
  $$
  This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
  bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
  extra bits.

    [15 lines not shown]

Delta		File
+381	-466	llvm/lib/Analysis/DependenceAnalysis.cpp
+0	-73	llvm/include/llvm/Analysis/DependenceAnalysis.h
+55	-0	llvm/test/Analysis/DependenceAnalysis/banerjee-overflow.ll
+2	-4	llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
+1	-1	llvm/test/Analysis/DependenceAnalysis/PR51512.ll
+439	-544	5 files

LLVM/project f44ec21 — clang/lib/AST/ByteCode Interp.h Interp.cpp

2026-07-06 06:44:30 UTC by Timm Baeder via GitHub on ⎇

main

[clang][bytecode][NFC] Move float->ap cast ops to the source file (#207592)

And deduplicate the code.

Delta		File
+4	-44	clang/lib/AST/ByteCode/Interp.h
+33	-0	clang/lib/AST/ByteCode/Interp.cpp
+37	-44	2 files

LLVM/project a280b1b — clang/include/clang/Basic DiagnosticDriverKinds.td, clang/include/clang/Options Options.td

2026-07-06 05:49:28 UTC by Santanu Das via GitHub on ⎇

main

[Hexagon] Allow reservation of caller saved registers via -ffixed-rXX (#205733)

Previously, hexagon allowed only callee saved registers to be reserved
since reserving caller saved regs can create problems, since it cannot
be sure that the callee (from a different module) also reserves the
register.

The responsibility of reserving register and managing it is now on the
user. However, a warning will be displayed if the user tries to reserve a
caller saved register.

---------

Co-authored-by: quic-santdas <quic_santdas at qti.qualcomm.com>

Delta		File
+49	-2	clang/test/Driver/hexagon-toolchain-elf.c
+32	-16	clang/lib/Driver/ToolChains/Hexagon.cpp
+7	-4	clang/include/clang/Options/Options.td
+6	-0	llvm/test/CodeGen/Hexagon/reserved-regs.ll
+5	-0	clang/include/clang/Basic/DiagnosticDriverKinds.td
+2	-0	llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+101	-22	1 files not shown
+102	-23	7 files

LLVM/project 0ac6b4b — clang/lib/AST/ByteCode Compiler.cpp

2026-07-06 05:15:10 UTC by Timm Baeder via GitHub on ⎇

main

[clang][bytecode][NFC] Remove unnecessary loop variable (#207649)

No reason to have the extra `N`.

Delta		File
+1	-1	clang/lib/AST/ByteCode/Compiler.cpp
+1	-1	1 files

LLVM/project aae9f9e — clang/lib/AST/ByteCode Compiler.cpp Compiler.h

2026-07-06 05:04:43 UTC by Timm Baeder via GitHub on ⎇

main

[clang][bytecode][NFC] Move Scope classes to source file (#207647)

Delta		File
+234	-0	clang/lib/AST/ByteCode/Compiler.cpp
+0	-234	clang/lib/AST/ByteCode/Compiler.h
+234	-234	2 files

LLVM/project a929f64 — llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp AMDGPUAsmPrinter.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

2026-07-06 05:03:10 UTC by Vikram Hegde via GitHub on ⎇

main

[AMDGPU][NPM] Complete AsmPrinter support (#203509)

Delta		File
+45	-4	llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+22	-0	llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+15	-3	llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+10	-1	llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+92	-8	4 files

LLVM/project 467390e — llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine vec_demanded_elts.ll

2026-07-06 04:24:11 UTC by Chengjun via GitHub on ⎇

main

[InstCombine] Skip redundant demanded element queries in insert chains (#205948)

Avoid re-running `SimplifyDemandedVectorElts` on intermediate
`insertelement` chain nodes when a bounded scan proves the top-level
all-lanes query cannot change the IR.

The skip is implemented inside the `InsertElement` case of
`SimplifyDemandedVectorElts` and is limited to the top-level all-lanes
query (`Depth == 0 && DemandedElts.isAllOnes()`). The bounded scan
matches the existing SDVE depth window and only skips chains with
distinct in-range constant insert indices. This keeps the normal SDVE
path for duplicate indices, variable indices, out-of-range indices,
multi-use chains, and the final chain root.

This was motivated by a cutile matmul compile-time case where loop
unrolling produced 128-lane vector insert/extract chains. Before this
change, InstCombine repeatedly invoked SDVE on intermediate
`insertelement` nodes in those chains. On the representative IR, the
affected InstCombine pass time went from about `44.9 ms` to `29.8 ms`,

    [4 lines not shown]

Delta		File
+94	-0	llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
+60	-0	llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+154	-0	2 files

LLVM/project 45574a5 — llvm/lib/Target/RISCV RISCVSubtarget.cpp, llvm/test/Analysis/CostModel/RISCV fixed-vector-scatter.ll fixed-vector-gather.ll

2026-07-06 03:53:51 UTC by Luke Lau via GitHub on ⎇

main

[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max option (#207312)

Whilst reviewing https://github.com/llvm/llvm-project/pull/207254, I
threw claude at it and it found a crash when passing in a non-default
-riscv-v-fixed-length-vector-lmul-max flag.

This option was added 5 years ago around the time initial fixed vector
support was being added in a719b667a9794, and IIUC it was added so that
support for more LMULs could be added over time.

We don't have any substantial codegen testing for it and I couldn't find
any downstream users either. So rather than trying to fix
https://github.com/llvm/llvm-project/pull/207254 to handle it it seems
easier just to remove it now that fixed vector support for RVV has
matured.

Delta		File
+93	-37	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lmul-max.ll
+24	-24	llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
+24	-24	llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
+24	-23	llvm/test/CodeGen/RISCV/rvv/pr52475.ll
+6	-6	llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
+1	-10	llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+172	-124	1 files not shown
+173	-125	7 files

LLVM/project 4eb56cf — llvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/GVN/PRE pre-load-through-select.ll

2026-07-06 03:44:39 UTC by Pengcheng Wang via GitHub on ⎇

main

[InstSimplify] Fold value-preserving zext/sext of trunc (#204089)

Fold a value-preserving `zext (trunc nuw X)` / `sext (trunc nsw X)` back
to
`X` in `simplifyCastInst` (when the trunc source type equals the extend
result type and the no-wrap flag guarantees the round-trip is identity).

After indvars canonicalizes a min-index loop, the running-index select
has a
`trunc nuw nsw i64 %iv to i32` on its true side while `arr[i]` is
addressed
directly with the i64 `%iv`. When PHI-translating the select-dependent
address along the backedge (see #203863), the true side becomes
`gep base, zext nneg (trunc nuw %iv)`, which has no matching instruction
in
the loop, so the select dependency is never formed and the redundant
load
survives.


    [11 lines not shown]

Delta		File
+72	-0	llvm/test/Transforms/GVN/PRE/pre-load-through-select.ll
+66	-0	llvm/test/Transforms/InstSimplify/cast.ll
+11	-0	llvm/lib/Analysis/InstructionSimplify.cpp
+149	-0	3 files

LLVM/project 4d7b4fd — .github/workflows test-suite.yml

2026-07-06 03:26:00 UTC by Luke Lau via GitHub on ⎇

main

[GitHub] Build llvm-size for test-suite.yml workflow (#207642)

This is also needed by llvm-test-suite

Delta		File
+1	-1	.github/workflows/test-suite.yml
+1	-1	1 files

LLVM/project d5288e7 — llvm/lib/Target/BPF BPFCodeGenPassBuilder.cpp BPFTargetMachine.cpp

2026-07-06 03:25:25 UTC by Aiden Grossman on ⎇

users/boomanaiden154/bpfnewpm-introduce-bpfcodegenpassbuilder

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+123	-0	llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
+2	-38	llvm/lib/Target/BPF/BPFTargetMachine.cpp
+7	-0	llvm/lib/Target/BPF/BPF.h
+6	-0	llvm/lib/Target/BPF/BPFTargetMachine.h
+6	-0	llvm/lib/Target/BPF/BPFPassRegistry.def
+3	-0	llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+147	-38	1 files not shown
+150	-38	7 files

LLVM/project 4536fa6 — llvm/lib/Target/BPF BPF.h BPFPassRegistry.def

2026-07-06 03:25:25 UTC by Aiden Grossman on ⎇

users/boomanaiden154/main.bpfnewpm-introduce-bpfcodegenpassbuilder

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]

Delta		File
+7	-0	llvm/lib/Target/BPF/BPF.h
+6	-0	llvm/lib/Target/BPF/BPFPassRegistry.def
+3	-0	llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+16	-0	3 files

LLVM/project b2cb2eb — llvm/lib/Target/BPF BPF.h BPFPassRegistry.def

2026-07-06 03:03:05 UTC by Aiden Grossman on ⎇

users/boomanaiden154/bpfnewpm-port-selectiondag-isel

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+7	-0	llvm/lib/Target/BPF/BPF.h
+6	-0	llvm/lib/Target/BPF/BPFPassRegistry.def
+3	-0	llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+16	-0	3 files

LLVM/project 774f8a0 — libc/src/complex/generic cabsf.cpp cabs.cpp, libc/test/src/complex CAbsTest.h cabsf_test.cpp

2026-07-06 02:55:08 UTC by jinge90 via GitHub on ⎇

main

[libc][complex] Enable cabs and cabsf in libc (#206677)

This PR adds basic implementation for cabs and cabsf in LLVM libc and
also extend current MPC infrastructure to support cabs operation.

---------

Signed-off-by: jinge90 <ge.jin at intel.com>

Delta		File
+119	-0	libc/test/src/complex/CAbsTest.h
+37	-0	libc/test/src/complex/cabsf_test.cpp
+36	-0	libc/test/src/complex/cabs_test.cpp
+28	-0	libc/src/complex/generic/cabsf.cpp
+28	-0	libc/src/complex/generic/cabs.cpp
+28	-0	libc/src/complex/generic/CMakeLists.txt
+276	-0	15 files not shown
+399	-1	21 files

LLVM/project f7d7502 — lldb/source/Plugins/ObjectFile/ELF ObjectFileELF.cpp, llvm/include/llvm/BinaryFormat DynamicTags.def

2026-07-06 02:43:18 UTC by Phoebe Wang via GitHub on ⎇

main

[SPARC] Make SPARC_REGISTER Sparc specific in llvm-readobj and LLDB (#206316)

The commit 4418a8e5 failed to limit SPARC_REGISTER to Sparc targets
only, which causes conflict when adding new dynamic tags for other
targets.

Delta		File
+12	-0	lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+12	-0	llvm/lib/Object/ELF.cpp
+4	-0	llvm/include/llvm/BinaryFormat/DynamicTags.def
+28	-0	3 files

LLVM/project 311c3ce — llvm/include/llvm InitializePasses.h, llvm/include/llvm/CodeGen StaticDataAnnotator.h Passes.h

2026-07-06 02:42:44 UTC by Aiden Grossman via GitHub on ⎇

main

[NewPM] Port StaticDataAnnotator

Standard NewPM pass porting. The PassBuilder wireup/test coverage will
come in the next PR.

Reviewers: arsenm, teresajohnson, mingmingl-llvm

Pull Request: https://github.com/llvm/llvm-project/pull/207629

Delta		File
+29	-16	llvm/lib/CodeGen/StaticDataAnnotator.cpp
+25	-0	llvm/include/llvm/CodeGen/StaticDataAnnotator.h
+1	-1	llvm/include/llvm/CodeGen/Passes.h
+1	-1	llvm/lib/CodeGen/TargetPassConfig.cpp
+1	-1	llvm/include/llvm/InitializePasses.h
+1	-1	llvm/lib/CodeGen/CodeGen.cpp
+58	-20	3 files not shown
+60	-21	9 files

LLVM/project 17ccf17 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

2026-07-06 02:42:06 UTC by Aiden Grossman on ⎇

users/boomanaiden154/main.newpm-port-staticdataannotator

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

Delta		File
+271	-0	llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+159	-90	libcxx/include/set
+244	-0	clang/test/CodeGen/RISCV/rvp-intrinsics.c
+207	-0	cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+146	-0	llvm/docs/AMDGPUDMAOperations.md
+109	-0	llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+1,136	-90	74 files not shown
+2,145	-484	80 files

LLVM/project dc56f71 — llvm/include/llvm InitializePasses.h, llvm/include/llvm/CodeGen StaticDataSplitter.h Passes.h

2026-07-06 02:41:49 UTC by Aiden Grossman via GitHub on ⎇

users/boomanaiden154/main.newpm-port-staticdataannotator

[NewPM] Port StaticDataSplitter

Standard pass porting. Remove the MBPI member given it was unused.

Reviewers: arsenm, teresajohnson, mingmingl-llvm

Pull Request: https://github.com/llvm/llvm-project/pull/207627

Delta		File
+68	-27	llvm/lib/CodeGen/StaticDataSplitter.cpp
+28	-0	llvm/include/llvm/CodeGen/StaticDataSplitter.h
+1	-1	llvm/lib/CodeGen/TargetPassConfig.cpp
+1	-1	llvm/include/llvm/CodeGen/Passes.h
+1	-1	llvm/include/llvm/InitializePasses.h
+1	-1	llvm/include/llvm/Passes/MachinePassRegistry.def
+100	-31	2 files not shown
+102	-32	8 files

LLVM/project 224b9d2 — libcxx/include set, libcxx/test/std/containers/associative/multiset iterator.pass.cpp merge.pass.cpp

2026-07-06 02:32:47 UTC by Vinay Deshmukh via GitHub on ⎇

users/boomanaiden154/main.newpm-port-staticdataannotator

[libc++] Make `<set>` `std::multiset` constexpr as part of P3372R3 (#206257)

Delta		File
+159	-90	libcxx/include/set
+20	-15	libcxx/test/std/containers/associative/multiset/multiset.cons/copy_assign.pass.cpp
+21	-13	libcxx/test/std/containers/associative/multiset/iterator.pass.cpp
+22	-11	libcxx/test/std/containers/associative/multiset/merge.pass.cpp
+18	-6	libcxx/test/std/containers/associative/multiset/equal_range_transparent.pass.cpp
+17	-5	libcxx/test/std/containers/associative/multiset/count_transparent.pass.cpp
+257	-140	57 files not shown
+841	-301	63 files

LLVM/project 9b2d44a — llvm/include/llvm/ObjectYAML ContiguousBlobAccumulator.h, llvm/lib/ObjectYAML ELFEmitter.cpp ContiguousBlobAccumulator.cpp

2026-07-06 02:11:47 UTC by Haohai Wen via GitHub on ⎇

main

[ObjectYAML][NFC] Hoist ContiguousBlobAccumulator into a shared header (#207306)

Move ContiguousBlobAccumulator out of ELFEmitter.cpp's anonymous
namespace so other yaml2obj emitters can reuse it.

Delta		File
+2	-103	llvm/lib/ObjectYAML/ELFEmitter.cpp
+98	-0	llvm/include/llvm/ObjectYAML/ContiguousBlobAccumulator.h
+69	-0	llvm/lib/ObjectYAML/ContiguousBlobAccumulator.cpp
+1	-0	llvm/lib/ObjectYAML/CMakeLists.txt
+170	-103	4 files

LLVM/project 4a62c05 — lld/ELF AMDGPUObjectLinking.cpp, lld/test/ELF amdgpu-lds-link-time-ordering-multigroup.s amdgpu-lds-link-time-random-layout.s

2026-07-06 01:49:38 UTC by Shilei Tian on ⎇

users/shiltian/rfc-amdgpu-object-linking

[RFC][AMDGPU][lld] Add object linking support

Add AMDGPU ELF object-linking support in lld, including resource propagation,
LDS layout, indirect-call handling, named-barrier updates, target compatibility
checks, and kernel descriptor/metadata patching.

This is a large PR because the linker needs to understand and validate several
AMDGPU object-linking concepts end to end. I tried to keep the changes scoped to
the necessary linker support and related metadata plumbing, but I'm open to
suggestions on how to split or structure the review to make it easier.

Delta		File
+1,726	-0	lld/ELF/AMDGPUObjectLinking.cpp
+505	-0	lld/test/ELF/amdgpu-lds-link-time-ordering-multigroup.s
+432	-0	lld/test/ELF/amdgpu-lds-link-time-random-layout.s
+425	-0	lld/test/ELF/amdgpu-lds-link-time-grouped.s
+402	-0	lld/test/ELF/amdgpu-lds-link-time-ordering-complex.s
+400	-0	lld/test/ELF/amdgpu-resource-usage.s
+3,890	-0	45 files not shown
+10,087	-4	51 files

LLVM/project 760f940 — llvm/docs AMDGPUUsage.rst, llvm/include/llvm/Support AMDGPUObjLinkingInfo.h

2026-07-06 01:43:18 UTC by Shilei Tian on ⎇

users/shiltian/amdgpu-func-info-flag-wave32

[AMDGPU] Add FUNC_WAVE32 for object linking info flag

Delta		File
+17	-17	llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
+5	-5	llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s
+3	-1	llvm/include/llvm/Support/AMDGPUObjLinkingInfo.h
+4	-0	llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+1	-0	llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+1	-0	llvm/docs/AMDGPUUsage.rst
+31	-23	2 files not shown
+33	-23	8 files

LLVM/project 5ed0716 — llvm/docs AMDGPUUsage.rst, llvm/include/llvm/Support AMDGPUObjLinkingInfo.h

2026-07-06 01:43:17 UTC by Shilei Tian on ⎇

users/shiltian/amdgpu-func-info-flag-wgp-mode

[AMDGPU] Add FUNC_WGP_MODE for object linking info flag

Delta		File
+18	-0	llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
+5	-5	llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s
+4	-0	llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+3	-1	llvm/include/llvm/Support/AMDGPUObjLinkingInfo.h
+1	-0	llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+1	-0	llvm/docs/AMDGPUUsage.rst
+32	-6	2 files not shown
+34	-6	8 files

LLVM/project 4f844b9 — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp AMDGPUMCResourceInfo.cpp

2026-07-06 01:43:16 UTC by Shilei Tian on ⎇

users/shiltian/object-linking-occupancy-abi

[AMDGPU] Introduce ABI occupancy for object linking

This PR introduces ABI occupancy as the contract used to compile functions under
object linking. The default is derived from the occupancy needed for a 1024
workitem workgroup, can be overridden with `-amdgpu-abi-waves-per-eu`, and can
be overridden per function by `amdgpu-flat-work-group-size` or tightened by an
accepted `amdgpu-waves-per-eu` hint.

The backend emits the selected occupancy in `.amdgpu.info` and uses it to
enforce the object linking register budget.

Delta		File
+67	-35	llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+56	-7	llvm/docs/AMDGPUUsage.rst
+34	-3	llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
+34	-0	llvm/test/CodeGen/AMDGPU/object-linking-abi-occupancy-preserves-attr.ll
+32	-2	llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+31	-0	llvm/test/CodeGen/AMDGPU/object-linking-abi-occupancy-kernel-no-attr.ll
+254	-47	15 files not shown
+446	-48	21 files

LLVM/project deecf8d — llvm/docs AMDGPUDMAOperations.md AMDGPUAsyncOperations.rst

2026-07-06 01:39:17 UTC by Sameer Sahasrabuddhe via GitHub on ⎇

main

[docs][AMDGPU] move DMA operations to a separate file (#206917)

This includes the various `.async` and `.tensor` operations. Various
scattered bits of information are now in one place. Also added the
missing documentation for tensor intrinsics.

Delta		File
+146	-0	llvm/docs/AMDGPUDMAOperations.md
+10	-46	llvm/docs/AMDGPUAsyncOperations.rst
+26	-28	llvm/docs/AMDGPUUsage.rst
+7	-1	llvm/docs/UserGuides.md
+189	-75	4 files

LLVM/project 29fa6a8 — clang/lib/CodeGen/TargetBuiltins RISCV.cpp, clang/test/CodeGen/RISCV rvp-intrinsics.c

2026-07-06 01:29:30 UTC by TelGome via GitHub on ⎇

main

[RISCV][P-ext] Support Packed Merge. (#207110)

Delta		File
+271	-0	llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+244	-0	clang/test/CodeGen/RISCV/rvp-intrinsics.c
+207	-0	cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+109	-0	llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+47	-4	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24	-1	clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+902	-5	3 files not shown
+945	-5	9 files

LLVM/project 3aea741 — llvm/include/llvm/CodeGen StaticDataSplitter.h StaticDataAnnotator.h, llvm/lib/CodeGen StaticDataSplitter.cpp StaticDataAnnotator.cpp

2026-07-06 01:01:52 UTC by Aiden Grossman on ⎇

users/boomanaiden154/newpm-port-staticdataannotator

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+68	-27	llvm/lib/CodeGen/StaticDataSplitter.cpp
+29	-16	llvm/lib/CodeGen/StaticDataAnnotator.cpp
+28	-0	llvm/include/llvm/CodeGen/StaticDataSplitter.h
+25	-0	llvm/include/llvm/CodeGen/StaticDataAnnotator.h
+2	-2	llvm/lib/CodeGen/TargetPassConfig.cpp
+2	-2	llvm/include/llvm/CodeGen/Passes.h
+154	-47	5 files not shown
+162	-53	11 files

LLVM/project 32b0279 — llvm/include/llvm/CodeGen StaticDataSplitter.h Passes.h, llvm/include/llvm/Passes MachinePassRegistry.def

2026-07-06 01:01:51 UTC by Aiden Grossman on ⎇

users/boomanaiden154/main.newpm-port-staticdataannotator

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]

Delta		File
+68	-27	llvm/lib/CodeGen/StaticDataSplitter.cpp
+28	-0	llvm/include/llvm/CodeGen/StaticDataSplitter.h
+1	-1	llvm/lib/CodeGen/CodeGen.cpp
+1	-1	llvm/lib/CodeGen/TargetPassConfig.cpp
+1	-1	llvm/include/llvm/Passes/MachinePassRegistry.def
+1	-1	llvm/include/llvm/CodeGen/Passes.h
+100	-31	2 files not shown
+102	-32	8 files

LLVM/project 3ad2a76 — llvm/include/llvm InitializePasses.h, llvm/include/llvm/CodeGen StaticDataSplitter.h

2026-07-06 00:32:41 UTC by Aiden Grossman on ⎇

users/boomanaiden154/newpm-port-staticdatasplitter

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+68	-27	llvm/lib/CodeGen/StaticDataSplitter.cpp
+28	-0	llvm/include/llvm/CodeGen/StaticDataSplitter.h
+1	-1	llvm/lib/CodeGen/TargetPassConfig.cpp
+1	-1	llvm/lib/CodeGen/CodeGen.cpp
+1	-1	llvm/include/llvm/Passes/MachinePassRegistry.def
+1	-1	llvm/include/llvm/InitializePasses.h
+100	-31	2 files not shown
+102	-32	8 files