LLVM/project a3093f1llvm/lib/Support/rpmalloc rpmalloc.c, llvm/test/CodeGen/AArch64 atomic-ops-lse.ll

Rebase

Created using spr 1.3.5
DeltaFile
+10,680-0llvm/test/tools/llvm-mca/AArch64/Olympus/sve-instructions.s
+7,585-2,403llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+4,040-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+4,532-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+6,871-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+39,671-9,5945,437 files not shown
+301,525-121,7095,443 files

LLVM/project b8061cbllvm/lib/Support/rpmalloc rpmalloc.c, llvm/test/CodeGen/AArch64 atomic-ops-lse.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5

[skip ci]
DeltaFile
+10,680-0llvm/test/tools/llvm-mca/AArch64/Olympus/sve-instructions.s
+7,585-2,403llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+4,040-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+4,532-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+6,871-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+39,671-9,5945,437 files not shown
+301,525-121,7095,443 files

LLVM/project c7f1d50llvm/lib/Support/rpmalloc rpmalloc.c, llvm/test/CodeGen/AArch64 atomic-ops-lse.ll

Rebase

Created using spr 1.3.5
DeltaFile
+10,680-0llvm/test/tools/llvm-mca/AArch64/Olympus/sve-instructions.s
+7,585-2,403llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+4,040-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+4,532-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+6,871-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+39,671-9,5945,437 files not shown
+301,525-121,7095,443 files

LLVM/project ad45dbdllvm/lib/Support/rpmalloc rpmalloc.c, llvm/test/CodeGen/AArch64 atomic-ops-lse.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5

[skip ci]
DeltaFile
+10,680-0llvm/test/tools/llvm-mca/AArch64/Olympus/sve-instructions.s
+7,585-2,403llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+4,040-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+4,532-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+6,871-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+39,671-9,5945,437 files not shown
+301,525-121,7095,443 files

LLVM/project dfa2abfllvm/lib/Support/rpmalloc rpmalloc.c, llvm/test/CodeGen/AArch64 atomic-ops-lse.ll

Rebase

Created using spr 1.3.5
DeltaFile
+10,680-0llvm/test/tools/llvm-mca/AArch64/Olympus/sve-instructions.s
+7,585-2,403llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+4,040-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+4,532-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+6,871-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+39,671-9,5945,437 files not shown
+301,525-121,7095,443 files

LLVM/project fa6722bbolt/utils/docker-tests Dockerfile

Addressing reviewers
DeltaFile
+16-6bolt/utils/docker-tests/Dockerfile
+16-61 files

LLVM/project 251724cllvm/include/llvm/AsmParser AsmParserContext.h FileLoc.h, llvm/lib/AsmParser AsmParserContext.cpp

[AsmParser] Faster location -> value lookups (#172702)

Uses IntervalMap to make location -> value lookups faster.

Adds some tests with this feature.
DeltaFile
+24-18llvm/lib/AsmParser/AsmParserContext.cpp
+21-0llvm/include/llvm/AsmParser/AsmParserContext.h
+6-0llvm/unittests/AsmParser/AsmParserTest.cpp
+5-0llvm/include/llvm/AsmParser/FileLoc.h
+56-184 files

LLVM/project f3ab256llvm/include/llvm/Passes PassPlugin.h, llvm/include/llvm/Plugins PassPlugin.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+142-0llvm/include/llvm/Plugins/PassPlugin.h
+0-142llvm/include/llvm/Passes/PassPlugin.h
+49-0llvm/lib/Plugins/PassPlugin.cpp
+0-49llvm/lib/Passes/PassPlugin.cpp
+6-0llvm/lib/Plugins/CMakeLists.txt
+1-1polly/lib/Support/RegisterPasses.cpp
+198-19233 files not shown
+230-21439 files

LLVM/project 6d00b40lld/ELF Writer.cpp SyntheticSections.h, lld/ELF/Arch AArch64.cpp

[ELF][AArch64][PAC] Replace R_AARCH64_AUTH_ABS64 addend hack

Rather than trying to infer deep down in AArch64::relocate whether we
need to actually write anything or not, we should instead mark the
relocations that we no longer want so we don't actually apply them. This
is similar to how X86_64::deleteFallThruJmpInsn works, although given
the target is still valid we don't need to mess with the offset, just
the expr.

This is mostly NFC, but if the addend ever exceeded 32-bits but then
came back in range then previously we'd pointlessly write it, but now we
do not. We also validate that the addend is actually 32-bit so will
catch errors in our implementation rather than silently assuming any
relocations where that isn't true have been moved to .rela.dyn.

Reviewers: kovdan01, MaskRay

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/171192
DeltaFile
+7-11lld/ELF/Arch/AArch64.cpp
+2-1lld/ELF/Writer.cpp
+1-1lld/ELF/SyntheticSections.h
+10-133 files

LLVM/project 669c755lld/ELF InputSection.cpp Relocations.cpp, lld/ELF/Arch AArch64.cpp

[NFC][ELF][AArch64][MTE] Replace addend hack with less-confusing code

The current implementation in addRelativeReloc makes it look like we're
writing the symbol's VA + addend to the section, because that's what the
given relocation will evaluate to, but we're supposed to be writing the
negated original addend (since the relative relocation's addend will be
the sum of the symbol's VA and the original addend). This only works
because deep down in AArch64::relocate we throw away the computed value
and peek back inside the relocation to extract the addend and negate it.

Do this properly by having a relocation that evaluates to the right
value instead.

Reviewers: kovdan01, MaskRay

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/171182
DeltaFile
+1-13lld/ELF/Arch/AArch64.cpp
+2-0lld/ELF/InputSection.cpp
+1-1lld/ELF/Relocations.cpp
+1-0lld/ELF/Relocations.h
+5-144 files

LLVM/project 79d9cf8lld/ELF Relocations.cpp

[NFC][ELF][AArch64][PAC] Use existing addSymbolReloc for R_AARCH64_AUTH_ABS64

The only difference between these calls is whether rel or type is passed
as the first argument, but AArch64::getDynRel returns type unchanged for
R_AARCH64_AUTH_ABS64, so they are the same.

Reviewers: MaskRay, kovdan01

Pull Request: https://github.com/llvm/llvm-project/pull/171179
DeltaFile
+6-7lld/ELF/Relocations.cpp
+6-71 files

LLVM/project e94e165lld/ELF SyntheticSections.h Relocations.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5

[skip ci]
DeltaFile
+1-24lld/ELF/SyntheticSections.h
+9-5lld/ELF/Relocations.cpp
+1-0lld/ELF/SyntheticSections.cpp
+11-293 files

LLVM/project 248a5a2llvm/docs LangRef.rst, llvm/lib/CodeGen StackProtector.cpp

[StackProtector] Add metadata to opt-out (#170229)

This is the LLVM piece of this work. There is also a clang piece, which
adds this metadata to AllocaInst when the source does
`__attribute__((no_stack_protector))` on a variable.

We already have `__attribute__((no_stack_protector))` on functions, but
opting out the whole function might be too heavy a hammer. Instead this
allows us to opt out of stack protectors on specific allocations we
might have audited an know to be safe, but still allow the function to
generate a stack protector if other allocations necessitate it.
DeltaFile
+55-0llvm/test/CodeGen/AArch64/stack-protector-metadata.ll
+17-0llvm/docs/LangRef.rst
+5-0llvm/lib/CodeGen/StackProtector.cpp
+77-03 files

LLVM/project 2634a2bclang/include/clang/Frontend CompilerInstance.h, clang/lib/CodeGen BackendUtil.cpp

Revert "[LLVM][NFC] Move PassPlugin from Passes to Extensions lib" and subsequent commit

This reverts commit d87b47d3a893b849cfd1ee5309b9fec2b0aec8cd.
This reverts commit f7ed3d44a198bfe689a1aa284452e875d5bb8a55.
DeltaFile
+142-0llvm/include/llvm/Passes/PassPlugin.h
+0-142llvm/include/llvm/Extensions/PassPlugin.h
+49-0llvm/lib/Passes/PassPlugin.cpp
+0-49llvm/lib/Extensions/PassPlugin.cpp
+11-4clang/lib/CodeGen/BackendUtil.cpp
+0-12clang/include/clang/Frontend/CompilerInstance.h
+202-20734 files not shown
+225-26640 files

LLVM/project 3cfe144lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime AppleObjCClassDescriptorV2.cpp AppleObjCClassDescriptorV2.h

[lldb] Use ReadCStringsFromMemory to speed-up AppleObjCClassDescriptorV2::method_t lookup (#172031)

With this improvement, compiling a simple Objective-C program like:

```
int main() {
    @autoreleasepool {
        NSDictionary *mapping = @{ @"one": @1, @"two": @2, @"three": @3 };
        return 0; //breakhere
    }
}
```

And running `expr -O -- mapping[@"one"]`, we can observe the following
packet count for the expression evaluation:

```
Before:
  multi mem read ($MultiMemRead)        :    94

    [12 lines not shown]
DeltaFile
+24-7lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
+4-0lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.h
+28-72 files

LLVM/project 80bc071llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 arm64-cvtf-simd-intrinsics.ll

[AArch64][llvm] Add codegen for simd fpcvt intrinsics

Add tablegen patterns to provide codegen for SCVTF and UCVTF
operating purely on SIMD & FP registers, using explicit bitcasts.
DeltaFile
+30-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+10-17llvm/test/CodeGen/AArch64/arm64-cvtf-simd-intrinsics.ll
+40-172 files

LLVM/project 9c77705mlir/docs LangRef.md, mlir/docs/DefiningDialects Assembly.md

Dialect alias docs and allow disabling

Signed-off-by: Fabian Mora <fmora.dev at gmail.com>
DeltaFile
+56-0mlir/docs/DefiningDialects/Assembly.md
+35-1mlir/docs/LangRef.md
+24-1mlir/lib/IR/AsmPrinter.cpp
+10-0mlir/include/mlir/IR/OperationSupport.h
+2-0mlir/test/IR/print-attr-type-dialect-aliases.mlir
+127-25 files

LLVM/project ec18557lldb/test/API/commands/platform/launchgdbserver TestPlatformLaunchGDBServer.py

[lldb][windows] skip TestPlatformProcessLaunchGDBServer.test_launch_with_unusual_process_name (#173250)

This patch skips
TestPlatformProcessLaunchGDBServer.test_launch_with_unusual_process_name
on Windows which is flaky.

The test will be reenabled once it has been fixed.
DeltaFile
+1-0lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
+1-01 files

LLVM/project 2c841b7llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU rsq.f64.ll amdgpu-codegenprepare-fdiv.f64.ll

AMDGPU: Introduce f64 rsq pattern in AMDGPUCodeGenPrepare (#172053)

DeltaFile
+4,532-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+306-56llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+131-12llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+4,969-3,2633 files

LLVM/project 9008922llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer crash_exceed_scheduling.ll extract-many-users-buildvector.ll

Revert "[SLP]Enable float point math ops as copyables elements."

This reverts commit e644f06c2ffc23b3415f3478b05c627303aef614 to fix
crashes found during internal testing
DeltaFile
+46-92llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
+102-26llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
+20-60llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+38-34llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
+26-18llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
+20-20llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
+252-25013 files not shown
+338-34119 files

LLVM/project a281656llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Revert "[SLP][NFC]Add parens to silence a warning message, NFC"

This reverts commit 366f6eb607dab74b7be28d3bd72736273329d647.
DeltaFile
+10-10llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+10-101 files

LLVM/project 37e3641flang/docs DebugGeneration.md

[Flang][Docs] Formatting change (#173257)

The flang.llvm.org page listed two entries (Testing, Resources) from the
Debug generation document in the table of contents. Change the
formatting to only include the top-level title.
DeltaFile
+2-2flang/docs/DebugGeneration.md
+2-21 files

LLVM/project 153ece5llvm/test/CodeGen/AArch64 arm64-vshift.ll

[AArch64][GlobalISel] Added test coverage for sri intrinsic

Previously, generation of sri intrinsics was tested during the ACLE -> IR stage, but not in the IR -> MIR stage. Now, correct generation of sri intrinsics is tested in both stages.
DeltaFile
+110-6llvm/test/CodeGen/AArch64/arm64-vshift.ll
+110-61 files

LLVM/project ed9b903llvm/lib/Target/AArch64 AArch64InstrGISel.td, llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp AArch64RegisterBankInfo.cpp

[AArch64][GlobalISel] Added support for sri intrinsic
DeltaFile
+8-0llvm/lib/Target/AArch64/AArch64InstrGISel.td
+7-0llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+2-0llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+17-03 files

LLVM/project c515914llvm/lib/Target/AArch64 SVEInstrFormats.td, llvm/test/CodeGen/AArch64 sve-lrint.ll sve-llrint.ll

[AArch64][SVE] Add MOVPRFX hints for unary undef pseudos. (#173031)

Extend the hints added in #166926 to unary pseudos with undef inactive
lanes.
DeltaFile
+200-209llvm/test/CodeGen/AArch64/sve-lrint.ll
+200-209llvm/test/CodeGen/AArch64/sve-llrint.ll
+160-167llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+38-41llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+34-43llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
+34-34llvm/lib/Target/AArch64/SVEInstrFormats.td
+666-7035 files not shown
+714-75611 files

LLVM/project 945cc50llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 fma-fneg-combine-3.ll

[X86] isFNEG - add concat_vectors(fneg(x),fneg(y)) -> concat_vectors(x,y) handling (#173255)

Fixes #173172
DeltaFile
+32-68llvm/test/CodeGen/X86/fma-fneg-combine-3.ll
+13-0llvm/lib/Target/X86/X86ISelLowering.cpp
+45-682 files

LLVM/project b380116llvm/test/CodeGen/AArch64 arm64-cvtf-simd-intrinsics.ll

[AArch64][llvm] Pre-commit tests for new fpcvt codegen
DeltaFile
+90-0llvm/test/CodeGen/AArch64/arm64-cvtf-simd-intrinsics.ll
+90-01 files

LLVM/project caf649fllvm/test/CodeGen/SPIRV ga-gep.ll ga-inttoptr.ll

Replace test.
DeltaFile
+0-13llvm/test/CodeGen/SPIRV/ga-gep.ll
+11-0llvm/test/CodeGen/SPIRV/ga-inttoptr.ll
+11-132 files

LLVM/project e5551a6mlir/lib/Dialect/MemRef/IR MemRefOps.cpp, mlir/test/Dialect/MemRef canonicalize.mlir

[mlir][memref] memref.view canonicalizations fixes (#173237)

* Do not fold if offset is not zero
* Remove unnecessary alloc check
DeltaFile
+36-5mlir/test/Dialect/MemRef/canonicalize.mlir
+10-13mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
+46-182 files

LLVM/project f512576llvm/utils/gn/secondary/clang-tools-extra/clang-change-namespace BUILD.gn, llvm/utils/gn/secondary/clang/lib/Frontend BUILD.gn

[gn] fix mistake from 2815358c68ddd
DeltaFile
+0-1llvm/utils/gn/secondary/clang-tools-extra/clang-change-namespace/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
+1-12 files