[AArch64][ARM64EC] Preserve native alignment in thunk names (#238613)
`getThunkArgTypes` gave every ordinary parameter alignment 1, so types
with different native alignment (e.g. `i128` vs `[2 x i64]`) mapped to
the same thunk name and shared a thunk that reads the wrong argument
registers. This PR makes it use the `DataLayout` ABI alignment so the
names differ and the right thunk is used.
---------
Co-authored-by: Breno Campos <brenoc at microsoft.com>
Co-authored-by: Copilot <223556219+Copilot at users.noreply.github.com>
Check arm64e ABI markers in static links too
Static links skipped the check, but ld64 takes only unversioned and
kernel objects there besides version 0, and ignores the other markers.
Assisted-by: Claude Code
Use hdr->cpusubtype directly in compatWithTargetArch
Drop the local sub, which held the full CPU subtype right next to subtype, the masked one.
Assisted-by: Claude Code
Set IsLittleEndian in arm64e-input-abi.s
#238122 makes IsLittleEndian required in Mach-O YAML. Set it here so this test works whichever of the two lands first.
Assisted-by: Claude Code
[lld-macho] Reject incompatible arm64e object ABI markers
The CPU subtype of an arm64e object carries a pointer authentication ABI
marker. In a dynamic link, ld64 accepts only objects marked userland ABI
version 0, even on macOS and Mac Catalyst, whose executables are marked
version 1. It names any other marker as another architecture
(arm64e.old, arm64e.v1, arm64e.kernel, arm64e.kernel.v1 or unknown) and,
as with an arm64 object, ignores the file with a warning, or reports an
error with -arch_errors_fatal. This applies to archive members too.
lld linked these objects. Check the marker in the same way. ld64 accepts
unversioned and kernel-ABI objects in static links, so those links are
not checked.
Assisted-by: Claude Code
[lld-macho] Sign arm64e TLV bootstrap binds and list __auth_got in map files (#234004)
Two small arm64e changes:
1. Sign the arm64e TLV bootstrap pointer as ld64 does. The first word of
a thread-local variable descriptor is bound to `__tlv_bootstrap`, which
dyld replaces with a pointer to `tlv_get_addr` that TLV accesses call
with `blraaz`. On arm64e, write that bind as an auth'd bind with the IA
key and no diversity, even though the object asks for a plain pointer.
2. List arm64e `__auth_got` entries in the map file. The map file
printed the entries of `__got` but not those of `__auth_got`, which
holds the targets of the stubs and the personalities.
Assisted-by: Claude
[AMDGPU] Price misaligned flat and LDS accesses with the LDS misaligned bug
In WGP mode on subtargets with the LDS misaligned bug, a flat access is
split into pieces no wider than its alignment and no narrower than 4
bytes, and an LDS access aligned below 4 bytes uses 8-byte pieces as one
aligned to 4 does.
[AMDGPU] Price buffer fat pointer memory operations
Price buffer fat pointer accesses as global accesses, except that an
aligned load is not widened and a vector of odd width elements is not
split element by element. Without relaxed buffer bounds checking, a
vector of elements that are a multiple of 32 bits wide is accessed in
pieces no wider than its alignment and no narrower than 4 bytes, and a
vector of other byte-sized or power of 2 wide elements in pieces of the
largest power of 2 bytes that divides the element size. The width comes
from buffer fat pointer lowering, which now exposes it. When the pointer
is a buffer resource plus a constant offset, the offset and a constant
number of records give the same bounds facts lowering uses to access it
in wider pieces.
[SystemZ] Define isTypeDesirableForOp to use in DAGCombine (#239841)
SystemZ widens vector integer sources to the fp element width in its
combine and the generic narrowing undid it alternating forever on
<4 x i16> and masked <4 x i64> sources of <4 x double>.
Consult isTypeDesirableForOp before narrowing, passing the node rather
than the opcode so the target can see the fp result type next to the
candidate operand type. SystemZ rejects vector operands narrower than
the fp elements.
Fixes #239444
[AMDGPU] Price misaligned flat and LDS accesses with the LDS misaligned bug
In WGP mode on subtargets with the LDS misaligned bug, a flat access is
split into pieces no wider than its alignment and no narrower than 4
bytes, and an LDS access aligned below 4 bytes uses 8-byte pieces as one
aligned to 4 does.
[AMDGPU] Price buffer fat pointer memory operations
Price buffer fat pointer accesses as global accesses, except that an
aligned load is not widened and a vector of odd width elements is not
split element by element. Without relaxed buffer bounds checking, a
vector of elements that are a multiple of 32 bits wide is accessed in
pieces no wider than its alignment and no narrower than 4 bytes, and a
vector of other byte-sized or power of 2 wide elements in pieces of the
largest power of 2 bytes that divides the element size. The width comes
from buffer fat pointer lowering, which now exposes it. When the pointer
is a buffer resource plus a constant offset, the offset and a constant
number of records give the same bounds facts lowering uses to access it
in wider pieces.
[AMDGPU] Price constant address space memory operations (#238840)
Price constant address space accesses as global accesses, except for
loads selected to scalar loads of up to 64 bytes. These are loads from
the 32-bit constant address space, and loads from the constant address
space whose pointer is an argument passed in SGPRs or a constant, plus
constant offsets, both aligned to 4 bytes or to their size. A scalar
load is widened as its lowering does. An integer whose size is not a
multiple of 4 bytes is loaded as whole dwords, plus a byte load when its
size is 7 modulo 8, since the last byte of such a remainder is left out
of the scalar load. A type with no legal dword vector equivalent is
split into the largest power of 2 pieces that fit, and once the
remainder fits in the alignment it is widened to a power of 2 piece of
up to the alignment, at most 8 bytes for byte vectors. A 3-dword
remainder of a legal dword vector takes a fourth dword when aligned to 8
on a subtarget without scalar dwordx3 loads.
Assisted-By: Claude Code Opus 5
[llvm-strings] Initialise UCh. (#240607)
Although mbrtoc32() will only return 1 if UCh has been written to, that
write comes from an uninstrumented libc and triggers an MSAN false
positive. Explicitly initialise UCh from the LLVM side to suppress this.
[VPlan] Hoist invariant base of pointer adds in runtime checks. (#240542)
When expanding a variant pointer add for the runtime checks of an inner
loop in a loop nest, operands invariant in the outer loop were expanded
individually and added to the pointer inside the outer loop.
If the pointer itself is invariant in the outer loop, use the sum of all
invariant operands as ptradd base instead, so it is expanded in IR and
hoisted out of the outer loop whole. The sum of the variant operands is
expanded as offset, as for integer adds.
[InferAddressSpaces] Don't replace uses in other functions
`performPointerReplacement` visits every use of a value in the postorder
list. When the value is a constant expression, some of these uses can be
in other functions. It already skipped such uses, but only after
`replaceIfSimplePointerUse`, so when the pass ran on one function, it
could still rewrite a load, store, `atomicrmw`, or `cmpxchg` in another
function, even in an `optnone` function.
This PR skips a use in another function before any replacement, like
#70611 did for the other users of a constant.
This PR was assisted by AI but I reviewed all the changes.
[mlir][XeGPU] Retry smaller inst_data when picking subgroup layouts (#239888)
Subgroup layout propagation always used the largest hardware block as
`inst_data`. When each subgroup's tile is smaller than that block, no
layout was found and propagation failed. For example, `64x16xf32` over
32 subgroups gives each subgroup `2x16`, which is smaller than the
`8x16` block.
This PR retries with smaller blocks until a subgroup layout fits:
- store_nd / prefetch_nd: try smaller block sizes.
- dpas / dpas_mx: try smaller M.
The largest block is still tried first, so existing results don't
change.
assisted-by-claude
---------
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[MC][MachO] Add an option to relocate cross-section offsets in DWARF (#239793)
Mach-O objects store references from one DWARF section into another as
bare offsets rather than relocations. For comparison in ELF, DWARF
references are relocations against sections that start at address 0.
Because of this Mach-O DWARF sections cannot be concatenated by tools
such as ld -r. However, this would be useful for some niche use-cases
such as doing an incremental (ld -r) link and then creating a static
archive that is then distributed to another machine.
This patch adds MCTargetOptions::MachORelocatableDwarf and a
-macho-relocatable-dwarf flag, which sets
DwarfUsesRelocationsAcrossSections for Darwin targets. When it is set,
every __DWARF section is also assigned address 0, like in ELF.
Assisted-by: Claude
Revert "[test][llvm-strings] Use printf for interpreting octal of echo -e" (#240613)
Reverts llvm/llvm-project#240529
Apparently this breaks things for z/OS. Not that it's easy to tell given
there's no upstream CI for z/OS as far as I can tell.
Co-authored-by: Jackson Stogel <jtstogel at gmail.com>
SystemZ: Lower sub-word atomicrmw during type legalization (#238532)
Produce the ATOMIC_LOADW_* nodes when replacing the illegal i8/i16
results, instead of custom lowering the promoted node later. This
removes the no-op custom type legalization case.
Constants are now any-extended, so one test materializes an immediate
with llill instead of lhi.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[LV] Expand alias-mask pointer bounds after the SCEV checks. (#240556)
materializeAliasMask expanded the diff-check pointer bounds via
VPExpandSCEVRecipes in the entry block, before the SCEV checks. The
bounds come from LAA's SCEVs, which are computed under LAA's predicates
(e.g. versioned strides), so they are only valid if the predicates hold.
For example a bound could become%n /u (%y + 1) after versioning
%stride == 1, which divides by zero for %y == -1 and %stride != 1,
while the original loop is well defined.
Expand the bounds directly in the alias-mask check block using
VPSCEVExpander, which is dominated by the SCEV checks.
[Clang][OBT] Diagnose overflow handlers in local class member functions
The overflow handler diagnostics skipped any body finished while another
function scope was active, so that a lambda is diagnosed with its
enclosing function. That also skipped member functions of local classes,
which the enclosing walk does not visit, so they were never diagnosed.
Skip only nested lambdas. A local class member function is a separate
function, so it can warn under -Woverflow-behavior-no-handler but never
under -Woverflow-behavior-unreachable-handler.
Also inline the three single-use diagnostic groups, and use %enum_select
for the lambda or block in -Woverflow-behavior-unreachable-handler.
Signed-off-by: Justin Stitt <justinstitt at google.com>
