[libc] Fix mbstate proxy header dep (#231984)
The proxy header for mbstate_t listed the dependency on the
llvm-libc-types definition as a regular `DEPENDS` and not a
`FULL_BUILD_DEPENDS`. This PR move the dependency to the right category.
[msan] Handle vector.partial.reduce.{add,fadd} (#229649)
The key insight is that after reducing the shadow of each element of the
vector to either a single 0 bit (fully initialized) or 1 (not fully
initialized), we can apply vector.partial.reduce.add to obtain the
output shadow (with a few type conversions in between).
When the first and second arguments are the same (e.g., `<4 x i32>
@llvm.vector.partial.reduce.add(<4 x i32>, <4 x i32>`), the new
instrumentation will propagate using "all-or-nothing" semantics (vs. the
bitwise OR of the heuristic handler which currently applies). These
all-or-nothing semantics are necessary in the worst case (e.g., for
8-bit integer, 11111111 + 0000000? could result in either 00000000 or
11111111; for floating-point, single bit changes can likewise have
avalanche effects).
This likewise propagates the shadow when the first and second arguments
are not the same (e.g., `<4 x i32> @llvm.vector.partial.reduce.add(<4 x
i32>, <8 x i32>`), unlike the default handler which currently applies.
[CIR][SPIR-V] Update HIP atomic scope checks (#231970)
PR #230829 made CIR translate AMDGPU scope names to their SPIR-V
equivalents, matching classic CodeGen. PR #231754 subsequently added HIP
atomic scope coverage with checks that still expected the AMDGPU names
for wavefront and agent scopes.
Expect subgroup and device for those scopes, share the LLVM checks
between CIR and classic CodeGen, and remove the obsolete FIXME.
Assisted-by: Codex / GPT-6
[IR] Remove Instruction::isDebugOrPseudoInst (NFC) (#231766)
This patch replaces Instruction::isDebugOrPseudoInst with
isa<PseudoProbeInst> at most call sites and drops the check altogether
where PseudoProbeInst is already handled or cannot occur.
Note that debug info is now represented with DbgRecord rather than
debug intrinsics outside the DirectX backend. None of the callers are
in the DirectX backend, so the DbgInfoIntrinsic check is dead.
Assisted-by: Antigravity
Reapply "clang: Use TargetID parsing from AMDGPUTargetParser" (#213824) (#231420)
This reverts commit 6327754ad4eb21b3c27034bc170e8b9944e5e318.
Resolve conflicts with the addition of FEAT_SRAMECC_ON_OFF_MODES.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[RISCV] Add more vaadd test coverage to match vaaddu. NFC (#231627)
Drop the sext test cases from the vaaddu files since equivalent tests
are in the vaadd files.
Assisted-by: Claude
[SelectionDAG] Remove isOnesOrOnesSplat in favor of isOneOrOneSplat (#231742)
These names are too similar.
The only difference between these is that isOneOrOneSplat allows
implicit truncation of build_vector operands. If we really need to
disable implicit truncation that should be done with a bool argument,
not the presence of two 's' letters in the function name.
[CIR][OpenMP] Add support for omp teams
This patch adds support for the OpenMP 'teams' directive, both standalone
and as the combined `target teams` construct. isCombinableLeaf now also
recognizes teams, so an explicitly-nested `target` + `teams` pair gets
the same omp.combined marking as the combined case.
Assisted-by: Cursor / Claude Sonnet 5 High
[VPlan] Strip IR trunc around IntOrFp inductions (NFC) (#231837)
The IR trunc instruction is completely unnecessary as the scalar types
of recipes are already embedded within them. Strip it entirely, and
rework the logic around it.
[clang][ssaf][orchestrator] Merge transformation reports per link unit (#231957)
In the transformation pass, the ar and ld shims now also merge the
transformation reports of what they consume, with
clang-ssaf-merge-transformation-report, and their conflict reports, with
clang-ssaf-merge-conflict-report, adding the conflicts of their own edit
merge. The link unit's reports therefore cover every translation unit
and every merge behind it, and the run names them on stdout in place of
the conflict files of the individual merges.
A compilation whose transformation fails leaves no report behind, as it
leaves no edits.
[AtomicExpand] Add elementwise expansion (#196464)
## Summary
Currently, `atomicrmw elementwise` operations are treated exactly like
the corresponding `atomicrmw` without `elementwise`.
Here I add support for `elementwise` atomic expansion in
`AtomicExpandPass`, which exploits the fact that we can legally break up
`elementwise` atomics into a sequence of smaller vector or scalar
atomics. Note that this is legal because, as the LangRef states, an
`elementwise` atomic `behaves as if it were expanded into one scalar
``atomicrmw`` per element, that are not ordered with respect to each
other.` So by scalarizing, we are only ever constraining the ordering of
atomic operations, which is legal because we give no ordering guarentee.
## Elementwise expansion implementation
This is the header for the expansion function:
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[AMDGPU] Remove redundant GFX9 VOP2b assembler aliases (#231950)
Remove the GFX9 VOP2bInstAliases for
v_{add,addc,sub,subb,subrev,subbrev}_co_u32. Unlike the GFX10+ e32
reals,
which drop the vcc operands from their AsmString and rely on
VOP2bInstAliases to accept the explicit vcc/vcc_lo forms, the GFX9 e32
reals keep the explicit vcc operands in their AsmString, so the wave64
aliases were exact duplicates and the wave32 (vcc_lo) aliases were
unusable since GFX9 does not support wave32.
79f67cae91ed mistakenly updated the v_add_co_u32, v_sub_co_u32 and
v_subrev_co_u32 aliases to use the carryless V_{ADD,SUB,SUBREV}_U32
pseudos instead of V_*_CO_U32, so they took their syntax from the
carryless instructions and accepted a form with no vcc operand (e.g.
"v_add_co_u32 v5, v1, v2"). That syntax is now rejected.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
Co-authored-by: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[CIR] Lay out allocas in the order classic codegen does
At -O0 the order of a function's entry-block allocas is its stack frame
layout. CIR now creates the return value's alloca before the
parameters', and keeps hoisted block-scope allocas after the function's
own, matching classic codegen.
CIRGen creates `__retval` before the parameters, as classic's
StartFunction does, and the implicit `return 0` store for `main` moves
into emitFunctionProlog, where classic emits it. HoistAllocas places
each hoisted alloca after the allocas already at the start of the
destination block instead of in front of them.
Assisted-by: Cursor / claude-opus-5.5
AArch64: Use minimal tablegen inputs for TargetParser (#231954)
Generate AArch64TargetParserDef.inc from a minimal file instead of all
of AArch64.td. The scheduling models referenced by the processor
definitions are defined in the scheduling files, which depend on the
instruction definitions. TargetParser does not use them, so the minimal
file defines empty placeholder models instead.
llvm-min-tblgen -gen-arm-target-def
Gigainstructions Peak RSS .td deps
AArch64.td 3.36 169 MB 100
AArch64TargetParserDef.td 0.04 7 MB 8
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CIR] Reject language address spaces in DirectToLLVM pointer conversion
Reject unlowered language address spaces in pointer types when bypassing TargetLowering. Guard pointer-producing lowerings, including generated patterns, so failed conversions report legalization failures instead of silently selecting address space zero or constructing invalid LLVM operations.
Assisted-by: Codex / GPT-6
fix(SelectionDAG): Preserve operand sharing
Demanded-bits simplification can bypass a shared producer without
removing it or its bitwise user. Reusing its previously single-use input
extends its live range and can introduce two-address copies.
Keep the shared value in this case for AND, OR, and XOR. Still bypass
bitwise producers to enable reassociation. Folds that remove the user
and rewrites using already-shared inputs remain available.
Remove three redundant copies in vector-bo-select without target or
subtarget checks.
The RISC-V checks each lose one instruction. GFX9 v_sdiv_i24 moves five
vector operations to scalar operations and adds a final move, growing
by four bytes; the other AMDGPU changes only affect register allocation.
fix(X86): restore CCMP through boolean NOT
Demanded-bits simplification can turn XOR with 1 into NOT, hiding
SETCC operands from CCMP formation. Invert the condition under AND
when the other SETCC masks high bits and the NOT has one use.
Restore the original ccmp.ll checks for all four configurations.
Refs #230700
fix(x86): reuse shifted masks in SSE ANDNP
Demanded-bit simplification can bypass a shared arithmetic shift when
ANDNP only needs sign bits. Reuse the existing shift to avoid keeping
its input live across a two-address SSE instruction.
Restore the original SSE2 vector select checks.
Refs #230700
fix(x86): generalize boolean NOT folding
Use known bits to prove the other AND operand clears every bit above
bit zero. This permits non-SETCC booleans without changing the upper
bits of an arbitrary byte or duplicating a shared inversion.
Cover a shifted boolean, arbitrary bytes, and shared inversions.
revert(x86): drop shared-shift ANDNP workaround
Keep the CCMP fix separate from the SSE copy regression. The shared-shift
workaround relies on GetDemandedMasks, whose poison handling is under
review, and needs a different approach.
Refs #230770
