[NFCI][ELF][Mips] Refactor MipsGotSection to avoid explicit writes (#150730)
Splitting the VA / addend calculations between build and writeTo means
having to keep them in sync and duplicating some of the logic. Move all
such calculations into build, mirroring how the normal non-MIPS code in
Relocations.cpp ensures the addend and initial memory contents are set.
[LLVM][Coroutines] Introduce TBAA metadata for coro frame object (#176543)
This helps subsequent passes to determine that aliasing between frame
objects and all other types is impossible.
There were cases where this AA issue seriously harmed the performance
of compute intensive code running inside a coroutine, since it broke
LICM and caused it to reload frame data inside tight loops over and over.
Co-authored-by: Yoni Lavi <yoni.lavi at nextsilicon.com>
[lldb] Fix padding for settings in `apropos` output (#177295)
In the `apropos` output, commands are padded to the longest command so
that their descriptions are aligned. This PR does the same thing for the
settings.
Fixes #177284
[lldb] Improve error message when we can't save core (#177496)
When you specify a filename to `process save core`, we'll write it in
the current working directory. In Xcode the CWD is `/` and you can't
generally write there.
```
(lldb) process save-core --style full foo
error: failed to save core file for process: Read-only file system
```
This PR improves the error message by including the output file when we
can't save core. However, just printing the filename isn't that much
more helpful, because FileSystem::Resolve only makes a path absolute if
it exists.
```
error: failed to save core file for process to 'foo': Read-only file system
```
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[orc-rt] Fix some Session::shutdown bugs. (#177528)
All calls to Session::shutdown were enquing their on-shutdown-complete
callbacks in Session's ShutdownInfo struct, but this queue is only
drained once by the thread that initiates shutdown. After the queue is
drained, subsequent calls to Session::shutdown were enquing their
callbacks in a queue that would never be drained.
This patch updates Session::shutdown to check whether shutdown has
completed already and, if so, run the on-shutdown-complete immediately.
This patch also fixes a concurrency bug: Session::shutdownComplete was
accessing SI->OnCompletes outside the session mutex, but this could lead
to corruption of SI->OnCompletes if a concurrent call to
Session::shutdown tried to enqueue a new callback to SI->OnCompletes
concurrently. This has been fixed by moving the SI->OnCompletes queue to
a new variable under the Session mutex, then draining the new queue
outside the mutex. (No testcase yet: this was discovered by observation,
and replicating the bug would depend on timing).
[RISCV] Improve vector pseudo table's experiences on translating between two different pseudo opcodes. NFC (#177232)
Sometimes we might need to translate from one vector pseudo -- like
`PseudoVFMUL_ALT_VV_M8_E16` -- to its `VFSUB_VV` counterpart, namely
`PseudoVFSUB_ALT_VV_M8_E16`. It's difficult to do this efficiently with
the current vector pseudo search table infrastructure. So I propose two
changes in this patch:
1. Currently both `RISCVVInversePseudosTable` and `RISCVVPseudosTable`
does not distinguish between F16 and BF16. This will be problematic
during lookup -- especially for `RISCVVInversePseudosTable`. So I added
a new single-bit field `IsAltFmt` into both tables.
2. It'd be great for `RISCVVPseudosTable` to return not just the base
instruction opcode but also LMUL & SEW (if there is any). Because the
alternative will require multiple additional steps (e.g. calling
`getLMul(TSFlags)`) -- especially for the SEW-specific pseudos -- that
are not really ergonomic. So I added `VLMul`, `SEW`, and `IsAltFmt` to
the result of `RISCVVPseudosTable::getPseudoInfo`. The downside of this
is of course bloating the table size, which is why I tried to mitigate
it with using bit fields.
This should be a NFC
[LangRef] Clarify semantics of undef in shufflevector masks (#171453)
The current phrasing of `shufflevector` in the language reference
states:
> A poison element in the mask vector specifies that the resulting
element is poison. For backwards-compatibility reasons, LLVM temporarily
also accepts undef mask elements, which will be interpreted the same way
as poison elements.
This is a bit ambiguous. Does it mean that an undef mask element
produces a poison result element, or an undef result element?
Per https://reviews.llvm.org/D148637, the answer is the former. I've
updated the docs to make this explicit.
As part of the same paragraph, the language reference also currently
states:
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[AArch64] Stop using TargetFlags as RegState for LOADgot (#177411)
The register state flags have been represented using `unsigned`, but we
intend to make this an `enum class` in llvm/llvm-project#177090.
That change has shown there is some strange behaviour in this AArch64
function, which uses operand TargetFlags (usually used for representing
some abstract form of relocation information to clarify global accesses,
also represented with `unsigned`) to initialise the register state flags
(used for representing how the register operand is used by an
instruction). These TargetFlags are always 0 in the tests, so remove the
variable and assignment.
[msan][NFCI] Check number of operands in handleVectorComparePackedIntrinsic() (#177291)
handleVectorComparePackedIntrinsic() can currently handle x86 and Arm
NEON vector comparisons, but is a bit lax about checking the number of
operands. This patch parameterizes the handler to check for the correct
number of operands, and also that the 3rd operand in x86 vector
comparisons is an ImmArg.
[clangd] Add support for additional symbol tags proposed for LSP 3.18 (#167536)
Implements support for symbol tags proposed for LSP 3.18 in
https://github.com/microsoft/language-server-protocol/pull/2003,
in the `documentSymbols` and `workspace/symbols` requests.
Fixes https://github.com/clangd/clangd/issues/2123.
---------
Co-authored-by: chouzz <zhouhua258 at outlook.com>
Co-authored-by: Dimitri Ratz <dimitri.ratz at thinkdigital.cc>
[AArch64] Add test coverage for roundeven + float-to-int conversions (#173515)
Split off from https://github.com/llvm/llvm-project/pull/170018, which
was becoming a bit of a rats' nest.
This PR:
- Cleans up the `arm64-cvt-simd-fptoi.ll`, `round-conv.ll`,
`round-fptosi-sat-scalar.ll`, and `round-fptoui-sat-scalar.ll`
regression tests, removing `nounwind readnone` annotations from the
rounding function calls. These were changed in #171288 to be LLVM
intrinsics instead of libcalls, so we no longer need to annotate them in
order for them to be compiled to native instructions. I've also removed
the declaration blocks at the end of the files, since they're no longer
necessary.
- Adds `roundeven` tests to the 4 regression tests mentioned above, to
go along with the other rounding functions currently tested.
- Changes `round-conv.ll` to have autogenerated CHECK lines/assertions,
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Infer visionOS availability from iOS availability (#176990)
Automatically infer and apply availability or unavailable attributes for
visionOS based on the corresponding iOS availability of the same
declaration using the version mapping information provided in
SDKSettings.json.
rdar://162148639
