LLVM/project 52361c6 — clang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGen debugger-tuning-flag.c

clang: Emit the "debugger-tuning" module flag

Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
DeltaFile
+21-0clang/test/CodeGen/debugger-tuning-flag.c
+3-0clang/lib/CodeGen/CodeGenModule.cpp
+24-02 files

LLVM/project ec43339 — llvm/include/llvm/Support CodeGen.h, llvm/include/llvm/Target TargetOptions.h

IR: Introduce "debugger-tuning" module flag

Prepare to replace TargetOptions::DebuggerTuning with a module flag. Unlike
other TargetOptions recently moved to module flags, debugger tuning is not a
firm ABI property. Mismatches and unrecognized names are tolerated.

Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
DeltaFile
+53-0llvm/include/llvm/Support/CodeGen.h
+37-0llvm/test/Linker/module-flags-debugger-tuning.ll
+31-0llvm/test/Assembler/module-flags-debugger-tuning.ll
+31-0llvm/test/Verifier/module-flags-debugger-tuning.ll
+24-0llvm/unittests/TargetParser/TripleTest.cpp
+0-21llvm/include/llvm/Target/TargetOptions.h
+176-216 files not shown
+239-2112 files

LLVM/project 250c405 — clang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver lto-aix.c

CodeGen: Replace TargetOptions::DebuggerTuning with module flag

Read the debugger tuning from the module's "debugger-tuning" flag instead of
TargetOptions. Delete the now-dead -debugger-tune= cl::opt and the
TargetOptions::DebuggerTuning field.

Update the tests relying on it to directly use the module flag. The cases
that exercise multiple values do a text substitution to swap the value.
Alternatively this could be changed to synthesize the module flag in the
llc flag like some of the other widely used module flags do.

Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
DeltaFile
+24-19llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
+6-16llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+12-9llvm/test/DebugInfo/X86/convert-debugloc.ll
+6-14clang/test/Driver/lto-aix.c
+13-5llvm/test/DebugInfo/X86/debugger-tune.ll
+0-17clang/lib/Driver/ToolChains/CommonArgs.cpp
+61-8058 files not shown
+243-25164 files

LLVM/project 612b8b1 — llvm/lib/Target/AMDGPU SIPreEmitPeephole.cpp, llvm/test/CodeGen/AMDGPU si-pre-emit-peephole-unpack-dst-flags.mir unpack-non-coissue-insts-post-ra-scheduler.mir

[AMDGPU] Keep dst flags when unpacking packed F32 instructions (#234858)

performF32Unpacking copied the new instructions' dst operands by value,
so
its setIsUndef and setIsRenamable calls never reached the instructions.
Take
the operands by reference.


Assisted-by: Claude Opus 5.5
DeltaFile
+44-44llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
+20-0llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-unpack-dst-flags.mir
+2-2llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+66-463 files

LLVM/project 1a62c9c — llvm/test/CodeGen/AMDGPU flat-saddr-atomics.ll, llvm/test/CodeGen/AMDGPU/GlobalISel extractelement.ll llvm.amdgcn.image.atomic.dim.a16.ll

AMDGPU: Don't reserve the implicit buffer pointer with architected flat scratch

Mesa shaders always had s[0:1] reserved for the implicit buffer
pointer, which is only needed to set up the scratch buffer
resource. With architected flat scratch, scratch is initialized by the
hardware and the pointer is unused. The driver stopped passing this
pointer so all user SGPRs were off by 2.

Don't reserve it on targets with architected flat scratch, so the user
SGPRs of Mesa shaders start at s0. Diagnose the use in the unsupported
contexts. This fixes many test failures on my system when running
piglit.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2,112-452llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,222-1,222llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+738-856llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+779-753llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+84-1,344llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
+673-574llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+5,608-5,201107 files not shown
+17,248-15,047113 files

LLVM/project c2013b0 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/asm-rm-4-regallocfast-fold' into users/void/asm-rm-5-prefer-reg
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project ec468f3 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/asm-rm-3-direct-mem-output-error' into users/void/asm-rm-4-regallocfast-fold
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project 1863ded — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/asm-rm-2-fold-tied-operands' into users/void/asm-rm-3-direct-mem-output-error
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project 3111c20 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/mir-inline-asm-operand-count' into users/void/asm-rm-2-fold-tied-operands
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project 54cda14 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

[MIR] Address review: merge error tests, un-lambda count parsing

Merge the three "ops:N" error tests into one with split-file, move the
operand count parsing out of a lambda into MIParser, and shorten the
round-trip test's comment.

Assisted-by: Claude Opus 5.5
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+2-6llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+62-676 files

LLVM/project 95384c3 — llvm/test/CodeGen/MIR/X86 inline-asm-operand-count.mir

Remove -verify-machineinstrs command line flag

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
DeltaFile
+1-1llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+1-11 files

LLVM/project ee8cfbf — llvm/lib/Target/AMDGPU SOPInstructions.td, llvm/test/CodeGen/AMDGPU add-max.ll uaddsat.ll

AMDGPU: Use S_ADD_I32 to select uniform uaddsat (#235242)

95ff1fa00ed4 selected uniform uaddsat.i32 to an S_ADD_U32 sequence.
S_ADD_U32 defines a carry out, so when the instructions have to be
moved to the VALU it is replaced with V_ADD_CO_U32_e32, which doesn't
exist on gfx10+. This would later assert when encoded. moveToVALU
should probably learn to handle that correctly, or at least assert.
The carry isn't needed, so use S_ADD_I32 like the usubsat pattern,
which is moved to V_ADD_U32_e64 where available.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+83-4llvm/test/CodeGen/AMDGPU/uaddsat.ll
+1-1llvm/test/CodeGen/AMDGPU/add-max.ll
+1-1llvm/lib/Target/AMDGPU/SOPInstructions.td
+85-63 files

LLVM/project 29c09be — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+74-16llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+263-1245 files not shown
+366-16311 files

LLVM/project 664306a — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+61-14llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+250-1224 files not shown
+326-15110 files

LLVM/project 32d286f — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+61-14llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+250-1224 files not shown
+326-15110 files

LLVM/project 379eb89 — llvm/lib/Target/RISCV RISCVMakeCompressible.cpp RISCVIndirectBranchTracking.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+52-12llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+32-8llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+242-1173 files not shown
+283-1369 files

LLVM/project c467c6b — clang/lib/AST ExprConstant.cpp

[clang][ExprConst] Add missing `FastEvaluateAsRValue` in `EvaluateKnownConstInt{,CheckOverflow}` (#234552)

This was missing for some reason.
DeltaFile
+14-0clang/lib/AST/ExprConstant.cpp
+14-01 files

LLVM/project b968e74 — libcxx/test/benchmarks/numeric reduce.bench.cpp transform_reduce.bench.cpp

[libc++] Add benchmarks for std::reduce and std::transform_reduce (#233374)

The PR adds benchmarks for these algorithms:
- `std::reduce()`
- `std::transform_reduce()`, unary transform
- `std::transform_reduce()`, binary transform

The benchmarks run minimal reduction and transformation operators with
`int`, `float` and `double` parameters.
`std::vector` and `std::list` containers are tested, `std::deque` is not
included to reduce the number of added benchmarks.

Fixes #226211

---------

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
DeltaFile
+127-0libcxx/test/benchmarks/numeric/transform_reduce.bench.cpp
+80-0libcxx/test/benchmarks/numeric/reduce.bench.cpp
+207-02 files

LLVM/project 4531bae — llvm/lib/Target/RISCV RISCVLandingPadSetup.cpp RISCVMakeCompressible.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+43-10llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+32-8llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+22-7llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+194-642 files not shown
+210-748 files

LLVM/project bc18c48 — llvm/lib/Target/RISCV RISCVMakeCompressible.cpp RISCVIndirectBranchTracking.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+52-12llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+32-8llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+242-1173 files not shown
+283-1369 files

LLVM/project 9c20e5e — clang/lib/CIR/Dialect/IR CIRDialect.cpp, clang/test/CIR/Transforms canonicalize.cir

[CIR] Fix cir.cast fold crash on a same type integral cast (#234236)

The fold called fold() on the source defining op, which is null for
block arguments
DeltaFile
+1-7clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+7-0clang/test/CIR/Transforms/canonicalize.cir
+8-72 files

LLVM/project 73c0f4b — clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenExprScalar.cpp

[CIR] Narrow blanket -fopenmp NYI guards to OGCG conditions (#233671)

Ordinary code compiled with -fopenmp hit errorNYI on every assignment,
inc/dec, member access and global reference
DeltaFile
+76-0clang/test/CIR/CodeGenOpenMP/non-openmp-code.cpp
+4-5clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+2-4clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+2-4clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
+2-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-0clang/include/clang/CIR/MissingFeatures.h
+88-156 files

LLVM/project 471de9d — llvm/lib/Target/AMDGPU SOPInstructions.td, llvm/test/CodeGen/AMDGPU add-max.ll uaddsat.ll

AMDGPU: Use S_ADD_I32 to select uniform uaddsat

95ff1fa00ed4 selected uniform uaddsat.i32 to an S_ADD_U32 sequence.
S_ADD_U32 defines a carry out, so when the instructions have to be
moved to the VALU it is replaced with V_ADD_CO_U32_e32, which doesn't
exist on gfx10+. This would later assert when encoded. moveToVALU
should probably learn to handle that correctly, or at least assert.
The carry isn't needed, so use S_ADD_I32 like the usubsat pattern,
which is moved to V_ADD_U32_e64 where available.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+83-4llvm/test/CodeGen/AMDGPU/uaddsat.ll
+1-1llvm/test/CodeGen/AMDGPU/add-max.ll
+1-1llvm/lib/Target/AMDGPU/SOPInstructions.td
+85-63 files

LLVM/project a4bd6bd — llvm/test/CodeGen/AArch64 aarch64-combine-gather-lanes.mir

AArch64: Fix missing ... function separators in mir test (#235119)

update_mir_test_checks misbehaves when the end of function marker
is missing.
DeltaFile
+138-114llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir
+138-1141 files

LLVM/project fc78f4f — lld/MachO ExportTrie.cpp, lld/test/MachO export-trie-high-bytes.s

 [lld-macho] Fix export trie for names containing 0xff bytes (#233399)

On signed-char hosts, charAt() promotes a 0xff byte to -1, aliasing the
end-of-string sentinel used by the three-way radix sort. As a result, an
export could be silently dropped or truncated. Fix is to convert the
byte to unsigned char before promoting it to int. I also verified that
ld-prime handles 0xff perfectly fine.

Assisted by Opus 5.5

---------

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+33-0lld/test/MachO/export-trie-high-bytes.s
+3-1lld/MachO/ExportTrie.cpp
+36-12 files

LLVM/project 7f43291 — clang/test lit.cfg.py, clang/test/Interpreter emulated-tls.cpp

[Clang] Detect emutls separately

OSes like FreeBSD support clang-rapl but doesn't provide emutls
implementation. In this case, the test fails to run. To fix it, we
detect thread local and set a new flag.
DeltaFile
+32-0clang/test/lit.cfg.py
+4-0clang/test/Interpreter/emulated-tls.cpp
+36-02 files

LLVM/project 5382bfb — compiler-rt/lib/tsan/rtl tsan_platform_linux.cpp

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+86-76compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
+86-761 files

LLVM/project dc3e262 — llvm/lib/Transforms/Scalar TailRecursionElimination.cpp, llvm/test/Transforms/TailCallElim tre-byval-parameter.ll tre-byval-parameter-2.ll

[TailCallElim] Place byval copy-back after trailing instructions (#234699)

Fix the insertion point of the byval copy operation we insert when
updating our incoming byval argument when transforming tail calls into
loops. We should insert the argument update memcpy at the point of the
**return**, not the call. There may be side-effect free instructions
between the call and the return, and they may read the incoming
argument, and using the incorrect insertion point results in a
miscompile.

Fixes #234334

LLM-aided
DeltaFile
+87-0llvm/test/Transforms/TailCallElim/tre-byval-trailing-load.ll
+8-5llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
+2-2llvm/test/Transforms/TailCallElim/tre-byval-parameter-2.ll
+1-1llvm/test/Transforms/TailCallElim/tre-byval-parameter.ll
+98-84 files

LLVM/project b577aec — llvm/test/CodeGen/AArch64 aarch64-combine-gather-lanes.mir

AArch64: Fix missing ... function separators in mir test

update_mir_test_checks misbehaves when the end of function marker
is missing.
DeltaFile
+138-114llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir
+138-1141 files

LLVM/project a6e45cc — clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/Transforms/abi-lowering indirect-aliased-nyi.cir

update error
DeltaFile
+1-2clang/test/CIR/Transforms/abi-lowering/indirect-aliased-nyi.cir
+1-2clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+2-42 files