1,032,003 commits found in 71 milliseconds
LLVM /project fa2eabd — clang/test/Headers __clang_hip_math.hip, llvm/lib/Transforms/Utils SimplifyCFG.cpp [SimplifyCFG] Hoist common code for switch multi-case destinations (#165700)
Previously, hoistCommonCodeFromSuccessors did not support hoisting
common code for multi-case destinations of `switch`.
However, if all the predecessors of a given Succ are the same (i.e.,
multi-case destination), it is safe to hoist the common code from Succ
to Pred, which is what this PR does.
See discussion
https://github.com/llvm/llvm-project/pull/165570#discussion_r2473290327.
Alive2 proof: https://alive2.llvm.org/ce/z/cYuczq
Optimization Impact:
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/3003 LLVM /project 5fc8e87 — mlir/include/mlir/Dialect/XeGPU/IR XeGPUOps.td, mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp [MLIR][XeGPU] Retain anchor op layouts for XeGPU nD ops (#170934)
This PR adds support to retain the anchor op layouts (after dropping
what's not required) for xegpu nD ops during workgroup to subgroup &
unroll transformation [clang][bytecode] Allocate InitMaps via Program/InterpState allocators (#170272)
Save them as a pointer intead of using a shared_ptr. This we we can use
the pointer integer value to differentiate the "no initmap yet" and "all
values initialzed" cases.
This regresses one test case in const-eval.c, but as it turns out, that
only worked coincidentally before. [ASan] Disable another test on Darwin due to ulimit stack issues
Similar to #170786.
LLVM /project 9e9e64a — clang/lib/CodeGen CGOpenMPRuntime.cpp, clang/test/OpenMP target_firstprivate_pointer_codegen.cpp target_defaultmap_codegen_01.cpp [OpenMP] Fix defaultmap(firstprivate:pointer) handling (#169622)
This fixes a bug where pointers from defaultmap(firstprivate:pointer)
were incorrectly treated as firstprivate literals, causing
OMP_MAP_LITERAL to be set. This prevented the runtime from performing
device address lookup.
Realted PR https://github.com/llvm/llvm-project/pull/167879
Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net> LLVM /project 58b319b — clang/lib/CIR/Analysis FallThroughWarning.cpp, clang/lib/Frontend CompilerInvocation.cpp [CIR][Analyzer] Revamping codebase and switch implementation
LLVM /project b889df3 — llvm/lib/Transforms/Instrumentation MemProfUse.cpp, llvm/test/Transforms/PGOProfile memprof-dump-matched-alloc-site.ll [MemProf] Add option to print function GUIDs during matching (#170946)
For debugging, add -memprof-print-function-guids option that will cause
memprof matching to emit the computed function GUID for every function
definition in the module to stderr. This is helpful because the profile
only contains the function GUID and not the names. LLVM /project 06f9dee — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll Rebase
Created using spr 1.3.6-beta.1
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,628 files not shown +211,870 -242,659 4,634 files
LLVM /project 367ebaf — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,626 files not shown +211,867 -242,656 4,632 files
LLVM /project e5397f1 — mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp, mlir/test/Dialect/XeGPU subgroup-distribute-unit.mlir subgroup-distribute.mlir add unit tests and fix bugs
LLVM /project 23591c3 — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll Rebase
Created using spr 1.3.6-beta.1
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,626 files not shown +211,867 -242,656 4,632 files
LLVM /project 9e98712 — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,625 files not shown +211,863 -242,652 4,631 files
LLVM /project 58c6006 — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll Address review comments
Created using spr 1.3.6-beta.1
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,625 files not shown +211,863 -242,652 4,631 files
LLVM /project 2ec72da — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,608 files not shown +211,746 -242,578 4,614 files
LLVM /project 3196a54 — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll Address review comments
Created using spr 1.3.6-beta.1
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,608 files not shown +211,746 -242,578 4,614 files
LLVM /project 75d6068 — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,608 files not shown +211,746 -242,578 4,614 files
LLVM /project acbd52b — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll Address review comments
Created using spr 1.3.6-beta.1
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,608 files not shown +211,746 -242,578 4,614 files
LLVM /project f96bf3b — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +17,522 -20,773 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +4,734 -0 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +4,725 -0 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s +1,529 -1,529 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s +46,489 -44,493 4,605 files not shown +211,736 -242,564 4,611 files
LLVM /project 3f3fd2f — llvm/lib/Target/AArch64 AArch64AsmPrinter.cpp, llvm/lib/Transforms/Scalar SROA.cpp [𝘀𝗽𝗿] initial version
Created using spr 1.3.6-beta.1
LLVM /project e198097 — llvm/lib/Transforms/Scalar SROA.cpp, llvm/test/Transforms/SROA protected-field-pointer.ll [𝘀𝗽𝗿] changes to main this commit is based on
Created using spr 1.3.6-beta.1
[skip ci]
Revert "[IR] Don't store switch case values as operands" (#170962)
Reverts llvm/llvm-project#166842
Breaks Mips LLVM tests, and LLD on bots.
See llvm/llvm-project#166842 [clang] [doc] Added documentation to intrinsics in cpuid.h (#170507)
Added doxygen comments to 4 intrinsincs in cpuid.h LLVM /project 7e39ae7 — llvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests import.ll [LTT] Add `unknown` branch weights when lowering type tests with conditional
Revert "[IR] Don't store switch case values as operands (#166842)"
This reverts commit f26360f2150e7ff916f2aa5d5fe3ff32d1780c8c .
[NFC] Run UTC --check-globals on LowerTypeTests/import.ll
[Github][CI] Introduce `LintHelper` class in `code-lint-helper.py` (#168827)
This commit introduces a new `LintHelper` class to
`llvm/utils/git/code-lint-helper.py`, which lays the groundwork for
integrating additional linters (`doc8`) into Github Action workflow.
---------
Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com> LLVM /project e546d0f — llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/RISCV fshl_fshr.ll [RISCV][TTI] Add cost model for ROTL/ROTR (#170824)
A funnel shift with the same first two operands is a rotate. When
`Zbb/Zbkb` is enabled we can use the `ROL(W)/ROR(I)(W)` instruction to
represent this. Add cost model support for this.
Similar to https://github.com/llvm/llvm-project/pull/169335 for AArch64. [RISCV] Refactor some code in RISCVMergeBaseOffset.NFC (#170839)
[Clang][CIR][Doc] Document CIR code duplication plans (#166457)
This adds a document describing known problems with code duplication in
the CIR codegen implementation, strategies to mitigate the risks caused
by that code duplication, and a general long-term plan for minimizing
the problem. LLVM /project ee77c58 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-cfg.ll Reland "AMDGPU/PromoteAlloca: Simplify how deferred loads work (#170510)" (#170955)
The second pass of promotion to vector can be quite simple. Reflect that
simplicity in the code for better maintainability.
v2:
- don't put placeholders into the SSAUpdater, and add a test that shows
the problem 