LLVM/project a941e15mlir/lib/Dialect/Transform/IR TransformOps.cpp, mlir/test/Dialect/Transform include-failure-propagation.mlir

[MLIR][Transform] Return empty handles when the included sequence fails (#169782)

This fixes a bug in the interpreter for transform.include op, which
crashes when attempting to copy out the handles from the yield op of a
failing sequence.
DeltaFile
+38-0mlir/test/Dialect/Transform/include-failure-propagation.mlir
+4-0mlir/lib/Dialect/Transform/IR/TransformOps.cpp
+42-02 files

LLVM/project 4088bbaclang/include/clang/AST CXXInheritance.h, clang/lib/AST CXXInheritance.cpp

[clang][NFC] Declare `CXXBasePaths::isAmbiguous` as `const`

To make this change, we have to use `lookup` instead of `operator[]` on a map. They both return the same thing: a default constructed value. The difference is that `lookup` default constructs a value and then returns it, whereas `operator[]` default constructs a value, inserts it into the map, and then returns a reference to that. Given that we are using a by-value return, the only way this is different is if a later use of the map depends on a value being at that key.

The map is a private variable of the class, so the only possible users are are other member functions. The only other use of the map that cares about the contents of the map is in `lookupInBases`, and it accesses the map with `operator[]`. This means that attempting to access the same element in this function will default construct the value before doing anything with it, which means it would do the exact thing it needs to do in the case where we are looking up a non-existent key, therefore no behavior has changed.

In terms of performance, this would either be a win or neutral. The benefit is that in some cases, we can avoid a memory allocation just read the contents of a 32-bit `0`. If a call to `isAmbiguous` is always followed up with a call to `lookupInBases`, then we allocate the memory just a little bit later for no difference in performance.
DeltaFile
+2-2clang/lib/AST/CXXInheritance.cpp
+1-1clang/include/clang/AST/CXXInheritance.h
+3-32 files

LLVM/project 442f853compiler-rt/lib/builtins/cpu_model x86.c

[compiler-rt] Add missing cpuid check for clflushopt (#169900)

As in title.
DeltaFile
+2-0compiler-rt/lib/builtins/cpu_model/x86.c
+2-01 files

LLVM/project 1fb4651clang/lib/Sema SemaDeclCXX.cpp

[clang][NFC] Use range-based for loop and algorithms in `SemaDeclCXX.cpp`

This changes most for loops in `SemaDeclCXX.cpp` to use a range-based for loop or a named algorithm. The ones unchanged were more complicated loops that used an index to iterate over multiple ranges, used an index to handle elements being added during insertion, or otherwise were not obvious how to transform them.
DeltaFile
+75-103clang/lib/Sema/SemaDeclCXX.cpp
+75-1031 files

LLVM/project b38ed00lldb/test/Shell/SymbolFile/PDB add-symbols.cpp

[LLDB][PDB] Relax check for resolving breakpoint (#169932)

The test was flaky, because it assumed that the breakpoint was always
resolved before `r` was executed
(https://github.com/llvm/llvm-project/pull/169728#issuecomment-3589799783).
This PR removes the check for this order. It still checks that the
breakpoint is resolved before it is hit.
DeltaFile
+1-1lldb/test/Shell/SymbolFile/PDB/add-symbols.cpp
+1-11 files

LLVM/project 2a7443ellvm/test/CodeGen/AMDGPU shufflevector.v4p0.v4p0.ll shufflevector.v4i64.v4i64.ll, llvm/test/tools/llvm-dwarfdump/X86 simplified-template-names.s

Rebase

Created using spr 1.3.7
DeltaFile
+5,975-8,879llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+5,975-8,879llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+7,387-7,087llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,420-8,636llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+3,880-6,644llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
+3,880-6,644llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
+32,517-46,7695,117 files not shown
+273,472-327,1585,123 files

LLVM/project 14d7b87bolt/lib/Passes PointerAuthCFIAnalyzer.cpp, bolt/test/runtime/AArch64 pacret-synchronous-unwind.cpp

[BOLT][PAC] Warn about synchronous unwind tables

BOLT currently ignores functions with synchronous PAuth DWARF info.
When more than 10% of functions get ignored for inconsistencies, we
should emit a warning to only use asynchronous unwind tables.

See also: #165215
DeltaFile
+33-0bolt/test/runtime/AArch64/pacret-synchronous-unwind.cpp
+8-1bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+41-12 files

LLVM/project a0677d1bolt/lib/Passes PointerAuthCFIAnalyzer.cpp

[BOLT] Add comment about the chosen threshold
DeltaFile
+10-0bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+10-01 files

LLVM/project b9eea6dbolt/lib/Passes PointerAuthCFIAnalyzer.cpp, bolt/test/AArch64 pacret-cfi-incorrect.s

[BOLT] Use opts::Verbosity in PointerAuthCFIAnalyzer
DeltaFile
+17-10bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+1-1bolt/test/AArch64/pacret-cfi-incorrect.s
+18-112 files

LLVM/project 14a19b5bolt/lib/Passes PointerAuthCFIAnalyzer.cpp

[BOLT] PointerAuthCFIAnalyzer: return early if there is no work

- makes sure we do not divide by zero, to calculate the % of ignored
  functions.
DeltaFile
+3-0bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+3-01 files

LLVM/project a9254a3bolt/include/bolt/Passes PointerAuthCFIFixup.h PointerAuthCFIAnalyzer.h, bolt/lib/Rewrite BinaryPassManager.cpp

[BOLT] Add --print flags for PointerAuthCFI* passes
DeltaFile
+13-2bolt/lib/Rewrite/BinaryPassManager.cpp
+7-1bolt/unittests/Passes/PointerAuthCFIFixup.cpp
+2-1bolt/include/bolt/Passes/PointerAuthCFIFixup.h
+2-1bolt/include/bolt/Passes/PointerAuthCFIAnalyzer.h
+24-54 files

LLVM/project 51459fbbolt/docs PointerAuthDesign.md PacRetDesign.md, bolt/test/AArch64 negate-ra-state-incorrect.s pacret-cfi-incorrect.s

[NFC] Rename PAuth tests to have a common prefix
DeltaFile
+236-0bolt/docs/PointerAuthDesign.md
+0-236bolt/docs/PacRetDesign.md
+0-78bolt/test/AArch64/negate-ra-state-incorrect.s
+78-0bolt/test/AArch64/pacret-cfi-incorrect.s
+0-76bolt/test/AArch64/negate-ra-state.s
+76-0bolt/test/AArch64/pacret-cfi.s
+390-3908 files not shown
+556-55614 files

LLVM/project 8215199bolt/docs PointerAuthDesign.md

[BOLT][doc] Add two resolutions for CFI
DeltaFile
+4-0bolt/docs/PointerAuthDesign.md
+4-01 files

LLVM/project 33165d4bolt/docs PacRetDesign.md

Update PacRetDesign.md
DeltaFile
+1-1bolt/docs/PacRetDesign.md
+1-11 files

LLVM/project 77d37a4bolt/docs PacRetDesign.md

Update bolt/docs/PacRetDesign.md

Co-authored-by: Paschalis Mpeis <paschalis.mpeis at arm.com>
DeltaFile
+1-1bolt/docs/PacRetDesign.md
+1-11 files

LLVM/project a4bdfd5bolt/lib/Passes InsertNegateRAStatePass.cpp PointerAuthCFIFixup.cpp, bolt/unittests/Passes PointerAuthCFIFixup.cpp InsertNegateRAState.cpp

[BOLT][NFC] Rename Pointer Auth DWARF rewriter passes

Original names were "working titles". After initial patches are merged,
I'd like to rename these passes to names that reflect their intent
better and show their relationship to each other:

InsertNegateRAStatePass renamed to PointerAuthCFIFixup,
MarkRAStates renamed to PointerAuthCFIAnalyzer.
DeltaFile
+335-0bolt/unittests/Passes/PointerAuthCFIFixup.cpp
+0-335bolt/unittests/Passes/InsertNegateRAState.cpp
+0-268bolt/lib/Passes/InsertNegateRAStatePass.cpp
+268-0bolt/lib/Passes/PointerAuthCFIFixup.cpp
+0-145bolt/lib/Passes/MarkRAStates.cpp
+145-0bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+748-74813 files not shown
+885-88419 files

LLVM/project aa45ad9bolt/lib/Passes InsertNegateRAStatePass.cpp, bolt/unittests/Passes InsertNegateRAState.cpp CMakeLists.txt

Review fixes
DeltaFile
+13-20bolt/lib/Passes/InsertNegateRAStatePass.cpp
+12-2bolt/unittests/Passes/InsertNegateRAState.cpp
+1-1bolt/unittests/Passes/CMakeLists.txt
+26-233 files

LLVM/project 6960ecellvm/lib/Analysis Delinearization.cpp

fix spell
DeltaFile
+1-1llvm/lib/Analysis/Delinearization.cpp
+1-11 files

LLVM/project 78defc8llvm/lib/Target/AMDGPU SIDefines.h, llvm/lib/Target/AMDGPU/Utils AMDGPUAsmUtils.cpp

[AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE (#169840)

Expose HW_REG_WAVE_SCHED_MODE to the s_getreg_b32, s_setreg_b32,
s_setreg_imm32_b32 instructions.
DeltaFile
+9-0llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
+9-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
+1-0llvm/lib/Target/AMDGPU/SIDefines.h
+1-0llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+20-04 files

LLVM/project a5dba76llvm/test/tools/llvm-mca/RISCV/SpacemitX60 vlseg-vsseg.s vlxe-vsxe.s

Pre-commit tests for x60 vector ld/st latency PR

Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
DeltaFile
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+586-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlxe-vsxe.s
+540-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vle-vse-vlm.s
+314-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlse-vsse.s
+6,165-04 files

LLVM/project 73d1602clang/lib/Tooling/Transformer SourceCode.cpp, clang/unittests/Tooling SourceCodeTest.cpp

[clang][Tooling] Fix `getFileRange` returning a range spanning macro invocation (#169842)

A followup to 40991215f4aba37fd43b65d96ad0a445dcd041b2.

When the start or end token is inside a macro argument and the other is
outside of the macro, we want to reject the range for a similar reason.
The range will include half of the macro call, either the closing paren
or the macro name and open paren.
DeltaFile
+1-6clang/lib/Tooling/Transformer/SourceCode.cpp
+2-0clang/unittests/Tooling/SourceCodeTest.cpp
+3-62 files

LLVM/project 8c31b12compiler-rt/test/ubsan/TestCases/Misc/Posix print_stack_trace.cpp

[TySan](test-only) Mark ubsan-tysan test as unsupported for now (#169934)

DeltaFile
+3-0compiler-rt/test/ubsan/TestCases/Misc/Posix/print_stack_trace.cpp
+3-01 files

LLVM/project ac45052openmp/module CMakeLists.txt

Fix DEPENDS
DeltaFile
+1-1openmp/module/CMakeLists.txt
+1-11 files

LLVM/project 318236dclang/include/clang/Basic BuiltinsAMDGPU.def, clang/test/SemaHIP amdgpu-gfx950-load-to-lds.hip

[HIP][AMDGPU] Remove 't' from all __builtin_*_load_lds builtins (#165389)

Allows for type checking depending on the builtin signature.

Stacked on top of: https://github.com/llvm/llvm-project/pull/165387 and
https://github.com/llvm/llvm-project/pull/165388
DeltaFile
+15-15clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
+3-3clang/include/clang/Basic/BuiltinsAMDGPU.def
+18-182 files

LLVM/project 7ddc7a6openmp/module CMakeLists.txt

Reuse original file location where check-flang expects them
DeltaFile
+10-10openmp/module/CMakeLists.txt
+10-101 files

LLVM/project c2eb332lldb/packages/Python/lldbsuite/test dotest.py

[lldb][dotest] use unused variable (#169903)

DeltaFile
+1-5lldb/packages/Python/lldbsuite/test/dotest.py
+1-51 files

LLVM/project 3eb057cbolt/lib/Passes Inliner.cpp, bolt/test/AArch64 inline-bti-dbg.s inline-bti.s

Reapply "[BOLT][BTI] Skip inlining BasicBlocks containing indirect tailcalls" (#169881)

This reverts commit 9bffb10e8b77b00033f2e997731193f81676cd60.

Fix: added assertions to the requirements of the test

--------

Original commit message:

In the Inliner pass, tailcalls are converted to calls in the inlined
BasicBlock. If the tailcall is indirect, the `BR` is converted to `BLR`.

These instructions require different BTI landing pads at their targets.

As the targets of indirect tailcalls are unknown, inlining such blocks
is unsound for BTI: they should be skipped instead.
DeltaFile
+40-0bolt/test/AArch64/inline-bti-dbg.s
+38-0bolt/test/AArch64/inline-bti.s
+26-0bolt/lib/Passes/Inliner.cpp
+104-03 files

LLVM/project 10136adllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis gcd-miv-overflow.ll

[DA] Remove special handling for SCEVAddExpr in GCD MIV
DeltaFile
+0-17llvm/lib/Analysis/DependenceAnalysis.cpp
+4-5llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
+4-222 files

LLVM/project 207627flldb/packages/Python/lldbsuite/test/tools/lldb-dap dap_server.py lldbdap_testcase.py, lldb/test/API/tools/lldb-dap/databreakpoint TestDAP_setDataBreakpoints.py

[lldb-dap] Add data breakpoints for bytes (#167237)

This patch adds support for `dataBreakpointInfoBytes` capability from
DAP. You can test this feature in VSCode (`Add data breakpoint at
address` button in breakpoints tab).
DeltaFile
+89-22lldb/test/API/tools/lldb-dap/databreakpoint/TestDAP_setDataBreakpoints.py
+39-14lldb/tools/lldb-dap/Handler/DataBreakpointInfoRequestHandler.cpp
+8-6lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
+8-1lldb/tools/lldb-dap/JSONUtils.cpp
+3-0lldb/tools/lldb-dap/Handler/RequestHandler.h
+1-0lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
+148-431 files not shown
+149-437 files

LLVM/project 3a766dcllvm/lib/Target/AArch64 AArch64SchedNeoverseN3.td, llvm/test/tools/llvm-mca/AArch64/Neoverse N3-sve-instructions.s

[AArch64] Fix throughout of 64-bit SVE gather loads (#168572)

In the Neoverse N3 Software Optimisation Guide, SVE non termporal gather
load, vector+scalar 64-bit element size and gather load, vector + imm,
64-bit element size both show throughput of 4/5. However, it currently
shows as 2/3. This patch adds a new resource group in order to show the
correct throughput.
DeltaFile
+243-243llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+16-4llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
+259-2472 files