[HIP] Link profile runtime in device-only lld path (#211675)
HIP device-only code object links can use the direct lld path in
HIPAMD.cpp. That path did not add the profile runtime, so device-only
builds with profile generation missed `libclang_rt.profile.a`.
This patch adds the normal profile runtime handling to that linker path
and covers it with a driver test.
RISCV: Fix using getVRegDef on a physical register
This was looking through a VL operand to find a materialized
ADDI $x0, imm. The VL register can be physical, so avoid calling
getVRegDef.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
clang/AMDGPU: Don't emit target-features on AMDGCN-flavored SPIR-V
The spirv64-amd-amdhsa target unions every GPU's features in its feature
map so it can report builtins as available. The CodeGen doesn't have
any use of the target-features. Putting it into the IR just results
in an annoying to update test every time a new feature is added. The
ultimate SPIRV codegen doesn't do anything with it, and if it did
survive to AMDGPU codegen, it would be actively harmful.
This isn't an ideal solution. The target-features spam is also
noisy and useless in the AMDGPU case, but solving that is more
intricate because we do currently rely on this for some features,
most notably the wavesize.
Co-authored-by: Claude (Claude-Opus-4.8)
CodeGen: Fix machine sink critical edge crash on an undef register
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
CodeGen: Fix MachineSink trivial coalescing crash on an undef register
PerformTrivialForwardCoalescing dereferences getVRegDef() for a copy's
source register without a null check. A source register defined only by an
undef use has no defining instruction, so coalescing a copy from it crashes.
Bail out when there is no defining instruction.
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang/AMDGPU: Use feature bitset instead of ArchAttr
Convert from the legacy getArchAttrAMDGCN manual bitmask checks to using
the new generated bitset. These are the easy cases. sramecc and xnack
require more supporting work so will be done later.
Co-authored-by: Claude (Claude-Opus-4.8)
[SLP]Recalculate cleared deps for all cancelled copyable elements
Deps of a cancelled copyable element were recalculated only for
control-dependency nodes; a speculatable one stayed unschedulable and
deadlocked the final scheduling. Recalculate unconditionally.
Fixes #216544
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/216734
NVPTX: Fix using getVRegDef on a physical register
This was calling getVRegDef on the frame register; change to
getOneDef instead. This still seems like a dubious way to deal
with any kind of frame setup optimization though.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[MLIR][NVVM] Spell strict assembly properties directly
Bind every NVVM inherent property in its operation assembly format and
re-enable strict property parsing for the dialect. Use direct named clauses
for declarative formats and custom MMA parsers while retaining dictionaries
for discardable attributes.
Assisted-by: Codex
[MLIR][NVVM] Enable strict property assembly format
Enable strict property assembly format mode for the NVVM dialect and update
custom assembly formats to expose property dictionaries explicitly.
Refresh NVVM tests so inherent operation properties are printed and parsed
through the property dictionary while non-property attributes remain in the
attribute dictionary.
Assisted-by: Codex
[AArch64] Fold vector select with power-of-2 bit-test to CMTST+BSP (#209100)
Fixes: #107088
* A vector select whose condition is (X & Mask) == Mask, where Mask is a
power-of-2 constant splat, was generating suboptimal code: AND + CMEQ +
BIF instead of CMTST + BIF.
* This happens because the condition is canonicalized to (X & Mask) ==
0, and AArch64 was not folding the resulting SETCC(AND(X, Mask), 0,
SETEQ) into a CMTST based mask.
* This patch adds a SelectionDAG fold in AArch64ISelLowering.cpp to
lower vector SETCC(AND(X, Mask), 0, SETEQ) to an inverted
AArch64ISD::CMTST. The existing bitselect lowering can then absorb the
inversion and emit CMTST.
Note: Test cases were derived from those reported by the original
author.
Revert "workflows/release-binaries: Disable flang on Darwin (#164667)" (#216667)
This reverts commit 6d54a5e5b83ce3502b7a3488fea5afe1c8bf9c5c.
Flang Darwin builds were reverted due to #160546. That issue has not
been reproducible (at least on my machine) for several months. There was
a request for MacOS builds on the most recent flang community call.
Flang is not enabled in the MacOS pre-commit CI.
Closes #160546
[lldb][test] Fix skip in TestWriteMemoryWithHWBreakpoint.py (#216723)
In a87b27fd5161ec43527fc3356852046a321ea82c, the opposite
skip was put in. It should skip if hardware breakpoints are
*not* supported.
Also that commit added a stray "skip". I have removed that and
fixed the incorrect variable name.
AMDGPU: Use mi_match for more manual selector patterns
Use mi_match G_SHUFFLE_VECTOR/G_FRAME_INDEX/G_SUB checks. Add new
matchers to check the shufflevector and frame index cases, avoiding
raw getVRegDef uses.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[X86] Fold scalar ABS_MIN_POISON store of a load to PABS (#216697)
Extend the scalar load→abs→store SIMD fold from #210654 to `ISD::ABS_MIN_POISON` (`llvm.abs(..., i1 true)`).
That form was left on `neg`+`cmov` while `llvm.abs(..., i1 false)` already
used `PABS`. Vector `PABS` is `ISD::ABS`; `PABS(INT_MIN)` is `INT_MIN`,
which is a valid refinement of poison.
[SLP] Check the fmul's own flags in canConvertToFMA (#216599)
CheckForContractable ran the operand bundle through the fadd's
InstructionsState, so every fmul in it failed the main/alt op test and
was skipped. The flags stayed set and allowContract was trivially true,
which priced a plain fmul feeding a contract fadd as if it would fuse.
The backend will not do that. Give the lambda the state to assess
against and pass the fmul's own.
Assisted-by: Claude Code Opus 5
[GlobalISel] Add G_EXTRACT_SUBVECTOR to computeKnownBits (#214533)
Port the SDAG EXTRACT_SUBVECTOR computeKnownBits handling to GlobalISel.
Offsets the demanded elements by the subvector index to propagate known
bits from the source vector to the extracted subvector.
Part of #150515.
AMDGPU: Fix machine sink crash on an undef SGPR operand
isSafeToSink dereferenced the defining instruction of an
SGPR use without checking for a null def, which crashes on
an undef operand that has no defining instruction.
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[mlir][SPIR-V] Add ComplexToSPIRV lowering for complex.angle (#214172)
Lower complex.angle to spirv.GL.Atan2/spirv.CL.Atan2 on the real and
imaginary components, following the existing complex.abs pattern
[libc++] Define behaviour for calling target() and target_type() on -fno-rtti std::functions (#209471)
The main aim of this change is to have the same vtable between
`-fno-rtti` and `-frtti`. Since it's very cheap to do, this also asserts
if the `function` object was created in `-fno-rtti` mode.
The vtable can be extended, since the members are either never accessed
in `-fno-rtti` mode, or are already expected to exist in `-frtti` mode.
This means that we either define behaviour that wasn't before, or we add
some extra bytes that are never accessed.
