LLVM/project aaa2c08 — mlir/lib/Dialect/Linalg/IR LinalgOps.cpp, mlir/test/Dialect/Linalg canonicalize.mlir

by Wijkqwe via GitHub on ⎇
[mlir][linalg] Extend FoldReduceBroadcast to float maximumf/minimumf (#233417)

Extend `FoldReduceBroadcast` to fold `reduce(broadcast(x))` into `x`
for `arith.maximumf`/`arith.minimumf` when the init is the identity
(`-inf`/`+inf`). The identity check gains a `FloatAttr` branch.

Safety: `maximumf(-inf, x) == x` for all values — finite, ±inf,
-0.0, and NaN (NaN-propagating semantics). Only an exact ±inf init
passes the check; finite/NaN inits are rejected by negative tests.
`maxnumf`/`minnumf` are deliberately excluded: they ignore NaN, so
`reduce(broadcast(NaN))` with init `-inf` would yield `-inf`, not NaN
(covered by a negative test).

Assisted-by: AI.
DeltaFile
+116-2mlir/test/Dialect/Linalg/canonicalize.mlir
+22-0mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+138-22 files

LLVM/project d5de383 — llvm/lib/Transforms/Scalar SROA.cpp, llvm/test/Transforms/SROA byte-conversion-big-endian.ll byte-conversion.ll

by Pedro Lobo on ⎇
[SROA] Don't widen byte values through integers
DeltaFile
+228-15llvm/lib/Transforms/Scalar/SROA.cpp
+19-62llvm/test/Transforms/SROA/byte-conversion.ll
+7-23llvm/test/Transforms/SROA/byte-conversion-big-endian.ll
+254-1003 files

LLVM/project 12293d3 — llvm/test/Transforms/SROA byte-conversion-big-endian.ll byte-conversion.ll

by Pedro Lobo on ⎇
[SROA] Pre-commit tests for byte conversions
DeltaFile
+476-0llvm/test/Transforms/SROA/byte-conversion.ll
+99-0llvm/test/Transforms/SROA/byte-conversion-big-endian.ll
+575-02 files

LLVM/project cced08f — llvm/lib/Transforms/InstCombine InstCombineInternal.h InstructionCombining.cpp, llvm/test/Transforms/InstCombine bitinsert-bitextract.ll

by Pedro Lobo via GitHub on ⎇
[InstCombine] Fold full-width `bitinsert` and `bitextract` to `bitcast` (#229147)

Add InstCombine visitors for `bitinsert` and `bitextract`.
A full-width `bitextract` or `bitinsert` at offset zero becomes a
`bitcast`.

```llvm
%a = bitextract i64, b64 %x, i32 0                ; bitcast b64 %x to i64
%b = bitinsert b64 %x, ptr %y, i32 0              ; bitcast ptr %y to b64
%c = bitextract ptr addrspace(1), b32 %x, i32 0   ; bitcast b32 %x to ptr addrspace(1)
```
DeltaFile
+150-0llvm/test/Transforms/InstCombine/bitinsert-bitextract.ll
+31-0llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+2-0llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+183-03 files

LLVM/project 77a364a — llvm/lib/Transforms/Utils VNCoercion.cpp, llvm/test/Transforms/GVN byte-conversion.ll

by Pedro Lobo via GitHub on ⎇
[GVN] Don't coerce forwarded byte values through integers (#226583)

GVN forwards a store to a load of a different type through an integer.
It casts the stored value to `iN`, then shifts and truncates it. For
byte values that cast is wrong, as it drops pointer provenance, and a
single `poison` bit makes the whole result `poison`.

Byte stores, and pointer stores that feed byte loads, no longer go
through an integer. GVN takes the loaded bits with `bitextract`,
bitcasting through `bN` where needed.

```llvm
 store b32 %x, ptr %p
 %v = load b8, ptr %q        ; %q = %p + 1
```

```diff
-%1 = bitcast b32 %x to i32
-%2 = lshr i32 %1, 8

    [17 lines not shown]
DeltaFile
+234-0llvm/test/Transforms/GVN/byte-conversion.ll
+25-6llvm/lib/Transforms/Utils/VNCoercion.cpp
+259-62 files

LLVM/project 2a566c2 — llvm/include/llvm/Analysis InstSimplifyFolder.h InstructionSimplify.h, llvm/include/llvm/IR PatternMatch.h

by Pedro Lobo via GitHub on ⎇
[InstSimplify] Simplify `bitinsert` and `bitextract` (#229125)

Simplify `bitinsert` and `bitextract` with non-constant operands.

- An out-of-range, `poison` or `undef` offset returns `poison`.
- A full-width byte `bitextract` or `bitinsert` at offset zero is a
no-op.
- Extracting the bits just inserted, at the same offset and type,
returns the inserted value.
- Reinserting byte bits extracted from the base, at the same offset,
returns the base.

```llvm
%a = bitextract b32, b32 %x, i32 0     ; %x
%b = bitinsert b32 %x, b32 %y, i32 0   ; %y
%c = bitextract ptr, b64 %w, i32 32    ; poison

%i = bitinsert b32 %x, i8 %z, i32 %n
%d = bitextract i8, b32 %i, i32 %n     ; %z

    [8 lines not shown]
DeltaFile
+296-0llvm/test/Transforms/InstSimplify/bitinsert-bitextract.ll
+85-0llvm/lib/Analysis/InstructionSimplify.cpp
+29-0llvm/unittests/IR/PatternMatch.cpp
+15-0llvm/include/llvm/IR/PatternMatch.h
+8-0llvm/include/llvm/Analysis/InstructionSimplify.h
+2-4llvm/include/llvm/Analysis/InstSimplifyFolder.h
+435-46 files

LLVM/project f3d4f2a — llvm/lib/Target/AArch64 AArch64MacroFusion.cpp, llvm/test/CodeGen/AArch64 misched-fusion-fmin-fmax-post-ra.mir

by Tomer Shafir via GitHub on ⎇
Revert "[AArch64][MacroFusion] Check register overlap in WAW check" (#234172)

This reverts commit 77be0679c76d6763f8d2b348a7555d75891e2c09.

Restricting WAW check back to exact match of same dest, as overlap
should not generally be the default and should not have an existing
user.
DeltaFile
+13-17llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+0-18llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir
+13-352 files

LLVM/project 4493a8a — clang-tools-extra/clangd ClangdServer.h ClangdServer.cpp, clang-tools-extra/clangd/tool ClangdMain.cpp

by Tomáš Slanina via GitHub on ⎇
[clangd] Make the --skip-preamble-build option take an enum (#229515)

Add a new value `never` allowing the preamble skipping to be
force-disabled, in addition to `modules` and `always`.

The default is `modules`, equivalent to the old behavior.

Closes #212403
DeltaFile
+9-3clang-tools-extra/clangd/tool/ClangdMain.cpp
+11-1clang-tools-extra/clangd/ClangdServer.cpp
+7-3clang-tools-extra/clangd/ClangdServer.h
+27-73 files

LLVM/project 7e3c571 — llvm/lib/Target/AArch64 AArch64PrologueEpilogue.cpp AArch64FrameLowering.cpp, llvm/test/CodeGen/AArch64 win64-nocfi.ll

by Benjamin Maxwell via GitHub on ⎇
[AArch64] Fix crash on ghccc functions on windows (#234156)

These don't have a prologue/epilogue (or any callee saves).

Fixes #234056
DeltaFile
+14-7llvm/test/CodeGen/AArch64/win64-nocfi.ll
+5-2llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+5-0llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
+24-93 files

LLVM/project e892aa6 — clang/test/AST ast-dump-attr-type.cpp, clang/test/CodeGen constantexpr-fneg.c

by Pranjal Srivastava via GitHub on ⎇
[clang][test][NFC] Fix missing colons in FileCheck directives      (#235342)

The `:` was missing from:

- `CHECK-NEXT` in `clang/test/AST/ast-dump-attr-type.cpp`.
- `CHECK-LABEL` in `clang/test/CodeGen/constantexpr-fneg.c`.

Also, in `clang/test/CodeGen/constantexpr-fneg.c`, adding the missing
`:` to `CHECK-LABEL` exposed that `clang -cc` (without an explicit
`-triple`) emits `define dso_local i32 @main()` on Linux, so `{{.*}}` is
added to match across targets.

Assisted-by: Gemini
DeltaFile
+3-3clang/test/AST/ast-dump-attr-type.cpp
+1-1clang/test/CodeGen/constantexpr-fneg.c
+4-42 files

LLVM/project 11c8b89 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVInsertWriteVXRM.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+114-25llvm/lib/Target/RISCV/RISCV.h
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+43-18llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
+25-25llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+365-20311 files not shown
+620-29817 files

LLVM/project c8d31c4 — llvm/lib/Target/RISCV RISCVInsertWriteVXRM.cpp RISCVRedundantCopyElimination.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+127-27llvm/lib/Target/RISCV/RISCV.h
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+41-23llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+43-18llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
+394-20313 files not shown
+678-32619 files

LLVM/project 121b0e6 — compiler-rt/cmake/Modules AllSupportedArchDefs.cmake, compiler-rt/lib/hwasan CMakeLists.txt

by Vitaly Buka on ⎇
[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+1-5compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+4-2compiler-rt/test/hwasan/lit.cfg.py
+1-1compiler-rt/lib/hwasan/CMakeLists.txt
+6-83 files

LLVM/project d25d9a8 — compiler-rt/cmake/Modules AllSupportedArchDefs.cmake, compiler-rt/lib/hwasan CMakeLists.txt

by Vitaly Buka on ⎇
[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+2-4compiler-rt/test/hwasan/lit.cfg.py
+5-1compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+1-1compiler-rt/lib/hwasan/CMakeLists.txt
+8-63 files

LLVM/project 1c65d18 — compiler-rt/lib/hwasan CMakeLists.txt

by Vitaly Buka on ⎇
[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+1-1compiler-rt/lib/hwasan/CMakeLists.txt
+1-11 files

LLVM/project b2b0b3e — compiler-rt/test/hwasan lit.cfg.py

by Vitaly Buka on ⎇
[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+4-2compiler-rt/test/hwasan/lit.cfg.py
+4-21 files

LLVM/project b84a015 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVInsertWriteVXRM.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+114-25llvm/lib/Target/RISCV/RISCV.h
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+43-18llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
+25-25llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+365-20311 files not shown
+620-29817 files

LLVM/project cef41f0 — llvm/lib/Target/RISCV RISCVInsertReadWriteCSR.cpp RISCVDeadRegisterDefinitions.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+105-23llvm/lib/Target/RISCV/RISCV.h
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+30-18llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+356-18710 files not shown
+564-27516 files

LLVM/project 1884a3b — clang/lib/Driver Driver.cpp, clang/test/Driver save-temps-input-overwrite-case-insensitive.c save-temps-input-overwrite.c

by Bill Wendling on ⎇
[clang][Driver] Don't let -save-temps overwrite the input file

With -save-temps, an intermediate file named after the input can be the
input itself, e.g. the preprocessed output of a .s file on Darwin. The
driver catches this, but only checked for it when the output's name was
the input's file name. It missed two cases, and overwrote the input with
the preprocessed output:

- With -save-temps=obj, the output is in the output's directory, so
  "clang -c -save-temps=obj sub/t.s -o sub/t.o" wrote "sub/t.s".
- On a case-insensitive file system, such as macOS's default, the
  preprocessed output "t.s" of an input "t.S" is the same file.

Check whether the output is the same file as the input whenever temps
are saved.

Fixes #7002.

Assisted-by: Claude Opus 5.5
DeltaFile
+26-0clang/test/Driver/save-temps-input-overwrite.c
+7-8clang/lib/Driver/Driver.cpp
+11-0clang/test/Driver/save-temps-input-overwrite-case-insensitive.c
+44-83 files

LLVM/project 5f57670 — llvm/lib/Target/NVPTX NVPTXISelLowering.cpp, llvm/test/CodeGen/NVPTX atomicrmw.py atomicrmw-sm90.ll

by Christian Sigg via GitHub on ⎇
[NVPTX] Set default value of nvptx-allow-ftz-atomics to false (#231429)

This restores the strict FTZ default originally introduced in #200732 and temporarily relaxed in #206154.

Frontends can now explicitly opt in to native FTZ-mismatched atomics on a per-instruction basis using `!atomic.ignore.denormal.mode` metadata (#217585, #217586, #217587, #217588, #232725, #232726), which is supported in Clang, Flang, MLIR, and XLA. Users who need the previous behavior globally can still pass `-nvptx-allow-ftz-atomics=true`.

Update test cases to verify the new default disallow behavior.
DeltaFile
+36-37llvm/test/CodeGen/NVPTX/atomicrmw-ignore-denormal-mode.ll
+6-5llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+4-4llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
+2-2llvm/test/CodeGen/NVPTX/atomicrmw.py
+2-2llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+2-2llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+52-524 files not shown
+60-6010 files

LLVM/project 6b98f6f — llvm/lib/Target/RISCV RISCVLateBranchOpt.cpp RISCVDeadRegisterDefinitions.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+96-21llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+345-1859 files not shown
+520-25215 files

LLVM/project 335d950 — llvm/lib/Target/RISCV RISCVInsertReadWriteCSR.cpp RISCVDeadRegisterDefinitions.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+105-23llvm/lib/Target/RISCV/RISCV.h
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+30-18llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+356-18710 files not shown
+564-27516 files

LLVM/project f17204b — llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

by Eric Ross via GitHub on ⎇
[KnownFPClass] Combine fpext and fptrunc into a shared routine (#225188)

Implements https://github.com/llvm/llvm-project/issues/219847
Partially addresses https://github.com/llvm/llvm-project/issues/219300
Fixes:
- `DenormalMode` handling by `fptrunc`/`fpext`
- `fpext` no longer rules out `qNaN` if the input could be `sNaN`.

Changes:
- `fptrunc` now takes the input/output types.
- `fpext`/`fptrunc` take the `DenormalMode` of the source/destination
types.

I completely rewrote `fpext` and `fptrunc` to use a shared `fpconvert`
routine. Using an approach of starting from `fcAllFlags` and removing
classes instead of starting from `KnownSrc` and adding classes. This
rewrite also improves some deductions for `fptrunc`.

The internal `fpconvert` routine I added should also be able to handle

    [13 lines not shown]
DeltaFile
+227-3llvm/test/Transforms/Attributor/nofpclass-fpext.ll
+207-17llvm/test/Transforms/Attributor/nofpclass-fptrunc.ll
+122-29llvm/lib/Support/KnownFPClass.cpp
+21-2llvm/lib/Analysis/ValueTracking.cpp
+17-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+12-6llvm/include/llvm/Support/KnownFPClass.h
+606-594 files not shown
+630-7510 files

LLVM/project f90ebb2 — llvm/lib/Target/RISCV RISCVQCRelaxMarking.cpp RISCVLateBranchOpt.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+86-18llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+288-1477 files not shown
+427-19913 files

LLVM/project 97298f7 — llvm/lib/Target/RISCV RISCVLateBranchOpt.cpp RISCVDeadRegisterDefinitions.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+96-21llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+345-1859 files not shown
+520-25215 files

LLVM/project 2a0a572 — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+74-16llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+263-1245 files not shown
+366-16311 files

LLVM/project 4a62511 — llvm/lib/Target/RISCV RISCVQCRelaxMarking.cpp RISCVLateBranchOpt.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+86-18llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+288-1477 files not shown
+427-19913 files

LLVM/project 3e00dc0 — libc/src/__support/math tanpif16.h tanpif.h

by c8ef on ⎇
address review comments
DeltaFile
+7-6libc/src/__support/math/tanpif16.h
+7-6libc/src/__support/math/tanpif.h
+14-122 files

LLVM/project 35c7d63 — llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86 pr234931.ll expand-post-ra-pseudo.mir

by Matt Arsenault on ⎇
X86: Fix inconsistent dead flags when expanding MOV32ri64

The expansion added a live implicit-def of the 64-bit register and
kept the original dead flag on the 32-bit def. The implicit-def is
unnecessary since the 32-bit def covers the same register units.
Drop it, and only mark the 32-bit def dead if the instruction has no
other live def of it, matching what LiveVariables would produce.

Fixes #234931

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+40-0llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir
+20-0llvm/test/CodeGen/X86/pr234931.ll
+6-4llvm/lib/Target/X86/X86InstrInfo.cpp
+66-43 files

LLVM/project 458d7b5 — llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86/apx compress-evex-shld-shrd-commute.mir two-address-shld-shrd-commute.mir

by Feng Zou via GitHub on ⎇
[X86][APX] Fix commuting SHLD/SHRD NF, NF_ND and EVEX variants (#233873)

All SHLD/SHRD rri8 variants are marked commutable, but
commuteInstructionImpl only rewrote the legacy and _ND opcodes as SHLD
B, C, I <-> SHRD C, B, (BitWidth - I). The _NF, _NF_ND and _EVEX
variants fell through to the generic commute, which only swaps the
sources and changes the result.

This is reachable when optimizeCompareInstr converts an EFLAGS clobber
to its NF form (e.g. SHLD16rri8_ND -> SHLD16rri8_NF_ND) and RA assigns
the destination to the second source: X86CompressEVEX commutes it to
drop the redundant NDD destination and emits the wrong shift. The
TwoAddressInstruction pass can hit the same bug when commuting the
non-NDD _NF and _EVEX forms.

Assisted-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+422-0llvm/test/CodeGen/X86/apx/two-address-shld-shrd-commute.mir
+189-0llvm/test/CodeGen/X86/apx/compress-evex-shld-shrd-commute.mir
+30-20llvm/lib/Target/X86/X86InstrInfo.cpp
+641-203 files