[RISCV][NFC] Rename `Zvvmm` instruction file to `Zvvm` (#196692)
Renames `RISCVInstrInfoZvvmm.td` to `RISCVInstrInfoZvvm.td` so `Zvvmm`
and `Zvvfmm` share the same IME instruction file according to the spec.
And all future instructions from the `Zvvm family` will be placed here
too.
This PR is required for reviewing #196486 in order to make GitHub show
the diff correcrly.
[CI] Ignore TidyFastChecks.inc for formatter CI. NFC. (#196682)
`TidyFastChecks.inc` is generated and its contents should not be checked
by clang-format CI workflow. Add a local `.clang-format-ignore` entry so
the PR formatting check does not report diffs for this file.
Related run:
https://github.com/llvm/llvm-project/pull/194516#issuecomment-4332061836
[clang-tidy] Avoid `use-nodiscard` false positives for class templates (#196661)
Do not suggest adding `[[nodiscard]]` to functions returning a class
template specialization whose primary template is already marked
`[[nodiscard]]`.
Class template specializations do not carry the `[[nodiscard]]`
attribute on their own declarations, so `modernize-use-nodiscard`
previously missed this case and emitted redundant diagnostics for return
types such as:
```cpp
template <class T>
struct [[nodiscard]] Result;
Result<int> f() const;
```
Fixes #163425.
[ObjectYAML][NFC] Extract BBAddrMap YAML types into shared namespace (#196019)
Move BBAddrMapEntry and PGOAnalysisMapEntry out of namespace ELFYAML
into a new format-agnostic namespace BBAddrMapYAML so that COFF
YAML support can reuse the same schema and MappingTraits.
[AArch64][NFC] Remove unused TRI member from class (#184363)
I’ve removed the TRI member and its initialization, leaving only MRI and
TII as the stored pointers.
---------
Co-authored-by: Benjamin Maxwell <benjamin.maxwell at arm.com>
[AArch64][GlobalISel] Enable BF16 legalization for fadd and friends. (#196081)
This enabled bf16 promotion for the following operations in GISel,
promoting them to f32 and truncating the result back:
G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM,
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT, G_FNEARBYINT,
G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN
[clang][AMDGPU] Reject malformed target IDs with empty components (#196140)
Fixes #196078
An extra colon in `-mcpu` (e.g. `gfx900::xnack+`) produced an empty
feature component and triggered an assertion in `StringRef::back()`.
Return `std::nullopt` for malformed target IDs instead.
[RISCV][GISel] Add test coverage for the srliw+shXadd patterns. NFC (#196676)
GISel isn't canonicalizing the shift pair to an AND the same way
SelectionDAG does so the patterns weren't firing. Add more directed
tests that use an And explicitly.
[DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214)
`SoftPromoteHalfOperand` had no case for `ISD::BR_CC`, causing a crash
when a half-typed `fcmp` result fed directly into a conditional branch.
All other comparison-related nodes (`SETCC, SELECT_CC`) were already
handled. Add `SoftPromoteHalfOp_BR_CC` following the same pattern as
`SoftPromoteHalfOp_SELECT_CC`.
Fixes #195562
---------
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
[Utils] Fix duplicate DomTree updates in SplitIndirectBrCriticalEdges (#196475)
SplitIndirectBrCriticalEdges generates DomTree Insert/Delete pairs for
each predecessor in OtherPreds. However, OtherPreds can contain
duplicate entries when a conditional branch has both targets pointing to
the same block (e.g., `br i1 %c, label %X, label %X`). This produces
duplicate DomTree updates for the same edge, triggering the assertion
`std::abs(NumInsertions) <= 1 && "Unbalanced operations!"` in
LegalizeUpdates.
Fix by tracking which source blocks have already had DomTree updates
emitted, and skipping duplicates.
[Clang] Do not eat SFINAE diagnostics for explicit template arguments (#139066)
Instead of merely suggesting the template arguments are invalid, we now
provide an explanation of why the explicit template argument is invalid.
[clang] Don't warn on __COUNTER__ in system macros
The introduction of extension and compatibility warnings means
that __COUNTER__ has started causing warnings (and -Werror= build
failures) due to use of system APIs.
This PR simply ensures that these diagnostics don't get reported
for system macro expansions as well.
Revert "[lldb] Handle SIGINT via the MainLoop signal thread (on POSIX)" (#196684)
Reverts llvm/llvm-project#195959 because it caused
`TestIOHandlerCompletion.py` to fail in CI (GreenDragon).
[OpenMP][MLIR] Modify lowering OpenMP Dialect lowering to support attach mapping
This PR adjusts the LLVM-IR lowering to support the new attach map type that the runtime
uses to link data and pointer together, this swaps the mapping from the older
OMP_MAP_PTR_AND_OBJ map type in most cases and allows slightly more complicated ref_ptr/ptee
and attach semantics.
[Flang][OpenMP][Offload] Modify MapInfoFinalization to handle attach mapping and 6.1's ref_* and attach map keywords
This PR is one of four required to implement the attach mapping semantics in Flang, alongside the
ref_ptr/ref_ptee/ref_ptr_ptee map modifiers and the attach(always/never/auto) modifiers.
This PR is the MapInfoFinalization changes required to support these features, it mainly deals with
applying the correct attach map type and manipulating the descriptor types maps for base address
and descriptor so that when we specify ref_ptr/ref_ptee we emit one of the two maps and when we
emit ref_ptr_ptee we emit our usual default maps. In all cases we add the "glue" of an new
attach map except in cases where a user has provided attach never. In cases where we are
provided an always, we apply the always map type to our attach maps.
It's important to note the runtime has a toggle for the auto map behaviour, which will flip the
attach behaviour to the newer semantics or the older semantics for backwards compatability (outside
the purview of this PR but good to mention).
[AMDGPU] Support atomic load and store for vector float types (v2f16, v2i16, v4i16, v4f16, v2f32) (#192904)
Add support for atomic load and store on <2 x half>, <4 x half>, and
<2 x float> vector types in the AMDGPU backend.
These types are promoted to equivalently sized integer types before
instruction selection:
<2 x half> -> i32
<4 x half> -> i64
<2 x i16> -> i32
<4 x i16> -> i64
<2 x float> -> i64
[Flang][MLIR][OpenMP] Add distinct var_ptr_ptr_type to omp.map.info operations & remove ref_ptr_ptee
This is a precursor patch to attach and ref_ptr/ptee mapping that I intend to upstream
over the next few weeks. The attach maps require both the type of the descriptor and
the pointed to data to calculate the appropriate offload/base pointers and size. In
the base case of ref_ptr_ptee all of this information can be gathered from the pointer
and pointee maps, but in cases where we have only one (i.e. ref_ptr/ref_ptee) we will
be missing one of the key elements required to create an corresponding attach map.
So, this PR basically adds the ability to ferry around the type of both var_ptr and
var_ptr_ptr as opposed to just var_ptr, then we can emit attach maps as seperate
map.info's that carry all the pre-requisite informaion for lowering to LLVM-IR. But,
otherwise it seems reasonable to have var_ptr_ptr mirror var_ptr in all aspects for
consistency.
It also removes ref_ptr_ptee, instead opting to use the setting of both ref_ptr and
ref_ptee to mean ref_ptr_ptee.
