[M68k] Use UADDO_CARRY/USUBO_CARRY instead of ADDC/ADDE/SUBC/SUBE. (#235569)
Type legalization now expands wide add/sub using UADDO/USUBO and
UADDO_CARRY/USUBO_CARRY, which are lowered to M68kISD::ADD/SUB and
M68kISD::ADDX/SUBX with the carry passed through the X flag of CCR.
ADDX/SUBX no longer receive a glue operand, so their verifyTargetNode
waivers can be removed.
This improves the code for i64 uadd/usub.with.overflow. Previously the
overflow bit was computed by redoing the subtraction, and usubo also
saved and restored CCR.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Reject bundles that cannot be scheduled
canVectorizeLSV() created a CantSchedule result when the scheduler
failed, but did not return it, so such bundles were still reported as
Widen. For a load chain like
%ld0 = load i32, ptr %p0
store i32 %ld0, ptr %p1
%ld1 = load i32, ptr %p1
the vector load was placed after %ld1 and the store was rewritten to
use a lane extracted from it, producing a use before its definition.
Return the CantSchedule result.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[TargetParser][Clang] Parse Intel GPU architecture names (#229247)
Add support for Intel GPU names in --offload-arch.
#222072 added the mapping from a detected GPU version to its name. This
PR adds the reverse mapping, needed when a user names a GPU through
--offload-arch. Previously, clang recognized only the hardcoded name
bmg_g21.
The shared Intel GPU list now recognizes device names such as
xe-bmg-g21, compatibility names such as xe-dg2, aliases for products on
the same GPU IP such as xe-arl-u, and numeric names such as xe_20.1.0.
The driver keeps each name as given, so it reaches ocloc unchanged.
bmg_g21 is replaced by xe-bmg-g21.
Building one device job per IGCA target follows once IGCA targets are an
OffloadArch (#227468). Selecting the SPIR-V target from an Intel GPU
name and diagnosing unknown names follow in #229248 and #229249.
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[SPARC] Fix the f128 one and ueq compares without hard quad (#234315)
_Q_cmp returns 0 for equal, 1 for less, 2 for greater, and 3 for
unordered. Masking with 3 does not do anything. fcmp one should return
true when ordered and not equal, so add 1 and mask with 2.
```
1 001 equal - false
2 010 less - true
3 011 greater - true
4 100 unordered - false
```
fcmp ueq is the complement.
Found when building glibc.
Assisted-by: Claude
[MemProf] Include callsite/alloc index in duplicate clone hash (#236790)
The ThinLTO backend computes a hash of each function clone's callsite
clone numbers and allocation hints, in order to detect clones that are
duplicates of an earlier clone (or the original function), which are
then emitted as aliases instead of separate copies. However, the hash
only included the non-default values, not which callsite or allocation
they were for. Therefore, for example, a clone whose callsites call
callee clones [1, 0] had the same hash as one with [0, 1], and was
incorrectly emitted as an alias of the latter, causing its callers to
call the wrong callee clones.
Include the index of each callsite or allocation, along with a tag
distinguishing the two kinds, in the hash.
Assisted-by: Gemini
[X86] Remove dead code from LowerADDSUBO_CARRY. Improve variable names. NFC (#236830)
The illegal type checks are unreachable as this code is only called
after type legalization.
Move a getValue(1) call earlier and give it its own variable name.
This matches the review feedback I received when copying the current
code structure to M68k in #235569.
[MIR] Serialize MachineBasicBlock::LabelMustBeEmitted (#234850)
Preserve `MachineBasicBlock::LabelMustBeEmitted` when printing and
parsing MIR using a `label-must-be-emitted` block attribute.
Assisted-by: GPT-6
[libc][math] Return a floating NaN from the cbrtf16 signaling path (#236478)
Return a floating quiet NaN from cbrtf16's signaling-NaN path instead of
numerically converting the integer NaN encoding. Use conditional
FE_INVALID
reporting and add a regression checking NaN quietness, flags and errno.
The ordinary cube-root approximation is unchanged.
Tests: two smoke configurations per compiler with GCC 13 and Clang 18 on
x86-64 Linux.
Assisted-by: GitHub Copilot
Signed-off-by: sriramshastry <sriramshastry at gmail.com>
[OpenMP] Mostly remove experimental taskgraph support from runtime (#194046)
Because the changes to runtime support for taskgraph record/replay
are quite extensive, they will likely be more comprehensible if the
existing parts are removed before the new parts are added. This is the
removal part.
[SPIR-V] Fix and enforce minimum versions of decoration operands (#229058)
Version lookups decoded the hex table values as decimal, so no minimum
version was ever met, also add the missing minimum versions for
UniformId (1.4), BufferBlock (1.3), AlignmentId and MaxByteOffsetId
(1.2)
Requirement contract for operands without capabilities:
- Version only: the target version must meet it
- Version and extension: a met version is enough and the extension is
not emitted (e.g. NoSignedWrap at 1.4+), otherwise an enabled extension
stands in for the unmet version
[AMDGPU] Retire dead uses before adding defs in GCNDownwardRPTracker (#228294)
Before this patch, the downward order for each instruction was the
following: advanceToNext() added an instruction's defs to the live set
while the uses that died at that instruction were still in it. Then it
sampled MaxPressure. At the next step, advanceBeforeNext() called
retireDeadOperands to drop the dead uses and defs. Then it sampled
MaxPressure. But this order could lead to inflated register pressure
reporting that could adversely affect the scheduler stages. This was
additionally inconsistent with the add/drop order of the generic
tracker.
The changes in this patch apply the transfer function in the order the
generic tracker uses in RegPressureTracker::advance(). Retire the lanes
that die at the instruction first, then add its defs. Early-clobber defs
are the exception. PHIs are skipped because nothing dies there. All of
these are now done by advanceToNext().
advanceBeforeNext() now only drops dead def lanes, the uses having been
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[ASan][test] Keep Posix/waitid.cpp overflow within stack redzone (#236825)
`waitid.cpp` previously pointed `siginfo_t *si` completely past a
12-byte local `int x[3]`, causing the kernel `waitid` syscall to write
128 bytes beyond `x`'s right stack redzone.
On AArch64 without UAR (such as Android, where
`detect_stack_use_after_return` defaults to `false`), at `-O3` the
64-byte ASan stack frame sits immediately below `main`'s saved `[x29,
x30]` whenever ASLR aligns `x29` to 32 bytes (~50% of runs), so `waitid`
overwrote the caller frame pointer on the stack before
`COMMON_INTERCEPTOR_WRITE_RANGE` ran. Commit `be8b3f0c2204` previously
attempted to disable the test on AArch64 with `UNSUPPORTED: aarch64`,
which did not match compiler-rt lit's `aarch64-target-arch` feature.
Size `x` to `sizeof(siginfo_t)` and offset `si` by `argc * sizeof(void
*)` so the overflow stays inside ASan's right stack redzone without
corrupting the caller frame record, and remove the ineffective `aarch64`
exclusion.
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[clang][docs] Fix the __block import example in the Block ABI (#226626)
The helpers in this example passed `BLOCK_FIELD_IS_BYREF |
BLOCK_BYREF_CALLER`, but clang passes only `BLOCK_FIELD_IS_BYREF` there,
as the rest of the document says.
Also fixed the field names, the type of `forwarding`, the helpers of the
`int` variable and a missing comma, to match what clang generates.
Checked with `clang -cc1 -rewrite-objc -fblocks` from clang 3.0 on this
example; current clang passes the same flag.
See also #90341.
Assisted-by: Claude
[Clang][DebugInfo] Use macro expansion locations by default (#235205)
Sample PGO testing of -debug-info-macro-expansion-loc is complete. Make
its expansion-location behavior unconditional and remove the temporary
cc1 flag, code generation option, and location helper.
Update the macro debug-info regression test to check the default
behavior, including function line and column locations, and document the
removed flag in the release notes.
Fixes #175249
Assisted-by: Argon
[libc] Make ffma functions constexpr (#226872)
Make ffma functions constexpr along with tests
---------
Co-authored-by: Zorojuro <sawantsukumar at gmail.com>
[AMDGPU] Truncate BF16 literals to 16 bits when printing (#225117)
The printer emitted the full 32-bit value, so a literal with high bits
set printed as text the assembler rejects
Match printImmediateF16/Int16 functions
[libc] Fix the values of TCOFLUSH and TCIOFLUSH (#236513)
tcflush passes its argument straight to the TCFLSH ioctl, so the values
must be the kernel's, which are 0 for TCIFLUSH, 1 for TCOFLUSH and 2 for
TCIOFLUSH. The last two were swapped, so a caller asking to discard
unsent output also discarded the input it had not read yet
Add a test that leaves a line of input waiting on a pseudoterminal and
checks which of the three flushes drops it
AI disclosure: this patch was written with Claude Code. I reviewed the
change and ran the new test; it fails without the fix and passes with it
Assisted-by: Claude
[SPIRV][NFC] Add SPIRVAddrSpace.h address space enum (#235175)
The SPIR-V address space numbering is hardcoded in the backend, in
Clang's SPIR address space maps, and in the LLVM ABI library. Add
llvm/Support/SPIRVAddrSpace.h so they can share one definition, like
AMDGPUAddrSpace.h (#73944) and NVPTXAddrSpace.h.
Use it in the backend in place of the hardcoded numbers. Clang and the
ABI library will follow separately.
Related to the comment in #224699
---------
Co-authored-by: Alexey Bader <alexey.bader at intel.com>
[skip ci] Overview snapshot of the taskgraph series
This empty commit only keeps CI from running on the overview PR, which
carries the whole series for reading and building. The series is reviewed
and tested through its individual PRs.
