LLVM/project 58566dd.github new-prs-labeler.yml

[CI] Add more glob patterns for `mlir:python` label

Right now, some paths for `mlir:python` are missing, which means the right maintainers don’t always get notified. This PR adds those paths.
DeltaFile
+3-0.github/new-prs-labeler.yml
+3-01 files

LLVM/project 55eaa6cllvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine/AArch64 neon-shift-intrinsics.ll

[InstCombine][AArch64] Lower NEON shift intrinsics when possible (#172465)

DeltaFile
+429-0llvm/test/Transforms/InstCombine/AArch64/neon-shift-intrinsics.ll
+50-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+479-02 files

LLVM/project b4ed102clang/lib/Sema SemaModule.cpp, clang/test/Modules pr174543.cppm

[C++20] [Modules] Avoid infinite loop when checking TU local exposures (#174704)

Close https://github.com/llvm/llvm-project/issues/174543

The root cause of the problem is that the recursion in the code pattern
triggers infinite loop in the checking process for TU local exposure.
DeltaFile
+8-0clang/lib/Sema/SemaModule.cpp
+8-0clang/test/Modules/pr174543.cppm
+16-02 files

LLVM/project 3fbe927llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[LV][EVL] Add test case for issue #173260. nfc (#173262)

DeltaFile
+197-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+197-01 files

LLVM/project 62ac813mlir/lib/Target/Cpp TranslateToCpp.cpp, mlir/test/Target/Cpp global.mlir

[mlir][emitc] Fix creating pointer from constant array (#162083)

Modify the C++ emitter to detect when an AddressOf op traces back to a const global. If it does, emit a C-style cast `(T*)(&...)` to strip the const qualification.
DeltaFile
+105-3mlir/test/Target/Cpp/global.mlir
+55-3mlir/lib/Target/Cpp/TranslateToCpp.cpp
+160-62 files

LLVM/project 50de34e

Revert "[UniformityAnalysis] Remove an incorrect assertion in uniformity anal…"

This reverts commit 371fad28244a16f64e707eb8e9889202fdacf85f.
DeltaFile
+0-00 files

LLVM/project 0501950llvm/include/llvm/ADT GenericUniformityImpl.h, llvm/test/Analysis/UniformityAnalysis/AMDGPU incorrect-assertion-issue-170048.ll

Revert "[UniformityAnalysis] Remove an incorrect assertion in uniformity analysis (#174117)"

This reverts commit 371fad28244a16f64e707eb8e9889202fdacf85f.

The change only fixes the superficial assertion. The real problem is that bb.3
and bb.4 should not have been identified as joins of bb.5
DeltaFile
+0-56llvm/test/Analysis/UniformityAnalysis/AMDGPU/incorrect-assertion-issue-170048.ll
+3-1llvm/include/llvm/ADT/GenericUniformityImpl.h
+3-572 files

LLVM/project 2451172clang/lib/Serialization ASTWriterDecl.cpp, clang/test/Modules class-instantiate-no-change.cppm malformed-constraint-template-non-type-parm-decl.cpp

[C++20] [Modules] Don't update MarkAsUsed information for decls from named modules (#174687)

Declarations from named modules are used naturally. Thet are
declarations in other TU. We don't need to record the information for
updating them.
DeltaFile
+50-0clang/test/Modules/class-instantiate-no-change.cppm
+12-12clang/test/Modules/malformed-constraint-template-non-type-parm-decl.cpp
+4-1clang/lib/Serialization/ASTWriterDecl.cpp
+66-133 files

LLVM/project 4ac6431mlir/lib/Transforms/Utils RegionUtils.cpp, mlir/test/Transforms canonicalize-block-merge.mlir

[mlir] Fix crash in dropRedundantArguments with produced operands. (#172759)

dropRedundantArguments was incorrectly indexing into forwardedOperands
using the block argument index directly. This crashes when the block has
produced operands (generated by the terminator, not forwarded from
predecessors) because forwardedOperands doesn't include them.

The fix checks isOperandProduced() to skip produced arguments and uses
SuccessorOperands::operator[] which handles the offset correctly.
DeltaFile
+33-0mlir/test/Transforms/canonicalize-block-merge.mlir
+13-3mlir/lib/Transforms/Utils/RegionUtils.cpp
+46-32 files

LLVM/project 74e7ffdclang/include/clang/Basic BuiltinsAMDGPU.def, clang/test/CodeGenHIP builtins-amdgcn-gfx950-cvt.hip

[AMDGPU] Modifies cvt and atomic builtin def to take _Float16 for HIP/C++
DeltaFile
+419-0clang/test/CodeGenHIP/builtins-amdgcn-gfx950-cvt.hip
+22-22clang/include/clang/Basic/BuiltinsAMDGPU.def
+441-222 files

LLVM/project 16be2c0lld/ELF ScriptLexer.cpp ScriptParser.cpp, lld/test/ELF dynamic-list-extern.s version-script.s

[ELF] Add VersionNode lexer state for better version script parsing

... so that `local:*;` will be lexed as three tokens instead of a single
one in a version node. This is used by both version scripts and dynamic
lists. Fix #174363

In addition, clean up special code for space-separated `local :` and `global :`.

This patch brings our lexer behavior closer to GNU ld. While GNU ld
additionally rejects more characters like `~/+,=`, we don't implement
this additional validation.

Pull Request: https://github.com/llvm/llvm-project/pull/174530
DeltaFile
+42-17lld/ELF/ScriptLexer.cpp
+10-0lld/test/ELF/dynamic-list-extern.s
+4-2lld/ELF/ScriptParser.cpp
+2-1lld/test/ELF/version-script.s
+2-1lld/test/ELF/linkerscript/version-script.s
+2-0lld/ELF/ScriptLexer.h
+62-216 files

LLVM/project 5a63367clang/lib/Sema SemaAMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-wmma-w32.cl

Reapply "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674) (#174697)

This reverts commit 0b2f3cfb72a76fa90f3ec2a234caabe0d0712590.
DeltaFile
+57-0llvm/lib/IR/AutoUpgrade.cpp
+26-26llvm/test/CodeGen/AMDGPU/wmma-coececution-valu-hazards.mir
+20-20llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
+34-0clang/lib/Sema/SemaAMDGPU.cpp
+23-4llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+24-2clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
+184-5212 files not shown
+279-8918 files

LLVM/project 5ab8368llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVTargetObjectFile.h

[RISC-V][Mach-O] Implement and select the RISCVMachOTargetObjectFile. (#174677)

The RISCVTargetMachine was still selecting RISCVELFTargetObjectFile,
which was making llc crash when running the test at
llvm/test/CodeGen/RISCV/riscv-macho.ll
DeltaFile
+7-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+5-0llvm/lib/Target/RISCV/RISCVTargetObjectFile.h
+12-12 files

LLVM/project 7d6dc25llvm/test/MC/RISCV xqcili-relocations.s xqcilb-relocations.s, llvm/test/tools/llvm-objdump/ELF/RISCV riscv-vendor-reloc.s

[RISCV][llvm-readobj,llvm-objdump] Use getRISCVVendorRelocationTypeName for RISCV vendor relocations (#172811)

Use getRISCVVendorRelocationTypeName to resolve RISCV vendor-specific
relocation names (R_RISCV_CUSTOM192-255) when preceded by
R_RISCV_VENDOR.

This improves the output of llvm-readobj and llvm-objdump to show
vendor-specific names like R_RISCV_QC_ABS20_U, R_RISCV_QC_E_BRANCH
(QUALCOMM) and R_RISCV_NDS_BRANCH_10 (ANDES) instead of generic
R_RISCV_CUSTOM* names.

Per RISC-V psABI, R_RISCV_VENDOR must be placed immediately before its
associated vendor-specific relocation, so the vendor symbol is consumed
after one use. Unknown vendors fall back to R_RISCV_CUSTOM*.
DeltaFile
+92-0llvm/test/tools/llvm-objdump/ELF/RISCV/riscv-vendor-reloc.s
+90-0llvm/test/tools/llvm-readobj/ELF/RISCV/riscv-vendor-reloc.s
+63-8llvm/tools/llvm-readobj/ELFDumper.cpp
+56-7llvm/tools/llvm-objdump/llvm-objdump.cpp
+11-11llvm/test/MC/RISCV/xqcili-relocations.s
+10-10llvm/test/MC/RISCV/xqcilb-relocations.s
+322-367 files not shown
+349-6313 files

LLVM/project 00e3a3clibcxx/test/libcxx/algorithms nodiscard.verify.cpp, libcxx/test/libcxx/diagnostics filesystem.nodiscard.verify.cpp algorithm.nodiscard.verify.cpp

[libc++][NFC] Refactor `[[nodiscard]]` tests (#173451)

Originally some `[[nodiscard]]` tests were implemented in
`*/test/libcxx/diagnostics`. The Standard has a library `Diagnostics`
and this folder should be reserved for it by convention. Most newer
tests were added to their respective sub-folders. This patch moves
around the already implemented `[[nodiscard]]` tests to their respective
folders where they belong and standardizes the name to
`nodiscard.verify.cpp` wherever possible.

N.B. This refactors only tests, which were merged. The remaining
(in-progress) ones will be moved in a future patch to reduce merge
conflicts.
DeltaFile
+454-0libcxx/test/libcxx/input.output/filesystems/nodiscard.verify.cpp
+0-454libcxx/test/libcxx/diagnostics/filesystem.nodiscard.verify.cpp
+400-0libcxx/test/libcxx/algorithms/nodiscard.verify.cpp
+0-400libcxx/test/libcxx/diagnostics/algorithm.nodiscard.verify.cpp
+329-0libcxx/test/libcxx/time/nodiscard.verify.cpp
+0-329libcxx/test/libcxx/diagnostics/chrono.nodiscard.verify.cpp
+1,183-1,18370 files not shown
+3,858-3,95076 files

LLVM/project 28ed942clang/lib/Sema SemaAMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-wmma-w32.cl

Reapply "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674)

This reverts commit 0b2f3cfb72a76fa90f3ec2a234caabe0d0712590.
DeltaFile
+57-0llvm/lib/IR/AutoUpgrade.cpp
+26-26llvm/test/CodeGen/AMDGPU/wmma-coececution-valu-hazards.mir
+20-20llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
+34-0clang/lib/Sema/SemaAMDGPU.cpp
+23-4llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+24-2clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
+184-5212 files not shown
+279-8918 files

LLVM/project afe8257llvm/test/CodeGen/X86 scmp.ll fast-isel-fcmp.ll, llvm/test/CodeGen/X86/apx ccmp.ll ctest.ll

[X86][APX] Emit SetZUCC instead of legacy setcc when ZU is enabled (#173965)

To avoid false dependency.
DeltaFile
+1,196-0llvm/test/CodeGen/X86/scmp.ll
+764-0llvm/test/CodeGen/X86/fast-isel-fcmp.ll
+516-0llvm/test/CodeGen/X86/apx/ccmp.ll
+443-0llvm/test/CodeGen/X86/apx/ctest.ll
+370-0llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
+370-0llvm/test/CodeGen/X86/pr32284.ll
+3,659-09 files not shown
+3,848-6715 files

LLVM/project af8bb1dutils/bazel/llvm-project-overlay/mlir BUILD.bazel

Fix Bazel build for 4dc9a0e (#174691)

DeltaFile
+3-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+3-01 files

LLVM/project 42d8bc9clang-tools-extra/clang-doc/assets comment-template.mustache clang-doc-mustache.css, clang-tools-extra/test/clang-doc basic-project.mustache.test templates.cpp

[clang-doc] Add a border box to comments in HTML (#174541)

Comments weren't very visually distinctive in HTML. They immediately
proceeded the declaration header and didn't have spacing between them.
To visually organize them, they now have a thin border around them.
Different comment types are also now separated by a small gap. This also
allows them to be easily changed in the future. Some extraneous `<div>`
tags are also removed or merged.
DeltaFile
+199-217clang-tools-extra/test/clang-doc/basic-project.mustache.test
+34-26clang-tools-extra/clang-doc/assets/comment-template.mustache
+20-31clang-tools-extra/test/clang-doc/templates.cpp
+17-25clang-tools-extra/test/clang-doc/namespace.cpp
+24-16clang-tools-extra/test/clang-doc/json/compound-constraints.cpp
+18-1clang-tools-extra/clang-doc/assets/clang-doc-mustache.css
+312-3166 files not shown
+326-33512 files

LLVM/project 39d6f10llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize tail-folding-div.ll first-order-recurrence-sink-replicate-region.ll

[LV] Conservatively predicate SDiv/SRem (#170818)

Conservatively predicate sdiv/srem:
- RHS may carry poison in masked‑off lanes.
- RHS could be −1 while LHS has masked‑off lanes (risking INT_MIN/−1
overflow).

We’ll relax this once we can prove non‑wrap/non‑poison conditions.

Fixes #170775.
DeltaFile
+555-0llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
+381-9llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
+39-21llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
+29-5llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
+5-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+4-2llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
+1,013-391 files not shown
+1,015-407 files

LLVM/project 25c7a36clang-tools-extra/clang-doc/assets comment-template.mustache clang-doc-mustache.css, clang-tools-extra/test/clang-doc basic-project.mustache.test templates.cpp

fix conflicts
DeltaFile
+199-217clang-tools-extra/test/clang-doc/basic-project.mustache.test
+34-26clang-tools-extra/clang-doc/assets/comment-template.mustache
+20-31clang-tools-extra/test/clang-doc/templates.cpp
+17-25clang-tools-extra/test/clang-doc/namespace.cpp
+24-16clang-tools-extra/test/clang-doc/json/compound-constraints.cpp
+18-1clang-tools-extra/clang-doc/assets/clang-doc-mustache.css
+312-3166 files not shown
+326-33512 files

LLVM/project 1eb0bbdllvm/lib/Target/RISCV RISCVLoadStoreOptimizer.cpp

[RISCV] Fix typo from 6e86037. NFC (#174679)

DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+1-11 files

LLVM/project e8bf7e8clang-tools-extra/clang-tidy/bugprone MacroParenthesesCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] fix false positives for bugprone-macro-parentheses in C++ templates (#174329)

Closes #91155
DeltaFile
+35-0clang-tools-extra/test/clang-tidy/checkers/bugprone/macro-parentheses.cpp
+21-11clang-tools-extra/clang-tidy/bugprone/MacroParenthesesCheck.cpp
+9-5clang-tools-extra/docs/ReleaseNotes.rst
+65-163 files

LLVM/project c249664llvm/test/CodeGen/AMDGPU carryout-selection.ll llvm.amdgcn.wmma.gfx1250.w32.ll

[AMDGPU] Handle `s_setreg_imm32_b32` targeting `MODE` register

On certain hardware, this instruction clobbers VGPR MSB `bits[12:19]`, so we need to restore the current mode.
DeltaFile
+713-2llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+246-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+220-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+212-0llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+174-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+166-0llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+1,731-2146 files not shown
+6,212-3152 files

LLVM/project 4435d43llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rv64p.ll

[RISCV] Add computeKnownBits for CLSW. (#174636)

DeltaFile
+64-0llvm/test/CodeGen/RISCV/rv64p.ll
+15-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+79-02 files

LLVM/project 6e86037llvm/lib/Target/RISCV RISCVLoadStoreOptimizer.cpp, llvm/test/CodeGen/RISCV xqcilsm-lwmi-swmi.mir

[RISCV] Improve load/store pairing for Xqcilsm instructions in RISCVLoadStoreOptimizer (#174612)

If we did not pair two viable `Xqcilsm` load/store instructions in
`RISCVLoadStoreOptimizer` we iterated over the second instruction when
looking for other pairs to merge. This leads to us missing out on
opportunities where the second instruction could have been the start of
another potential pair that could have been merged.
DeltaFile
+57-0llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir
+14-4llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+71-42 files

LLVM/project 1ec343dlibclc CMakeLists.txt

[libclc] Add support for `nvptx64-nvidia-cuda` triple (#174611)

Summary:
The OS here is the standard CUDA support target, which is the ABI used
for all of the same intrinsics the `nvidiacl` target uses. These can be
aliases asn `cuda` in the triple is the canonical form for most all GPU
compute.
DeltaFile
+5-0libclc/CMakeLists.txt
+5-01 files

LLVM/project 8136cb9lldb/docs index.rst, lldb/docs/resources lldbdap-contributing.md lldbdap.md

[lldb] Update LLDB DAP documentation. (#172580)

This adds a new page to lldb.llvm.org that includes a user guide for
lldb-dap.

The overall structure for documentation:

* https://lldb.llvm.org/resources/lldbdap.html - represents the user
facing documentation for lldb-dap, a high level overview of lldb-dap and
a place we can point users to for basic usage information.
* https://lldb.llvm.org/resources/lldbdap-contributing.html - represents
the contributing documentation for lldb-dap.
* llvm-project/lldb/tools/lldb-dap/README.md - The lldb-dap VSCode
Extension specific documentation.

This is a first pass at the documentation, I expect to expand on it
further as needed.
DeltaFile
+209-0lldb/docs/use/lldbdap.md
+195-0lldb/docs/resources/lldbdap-contributing.md
+0-195lldb/docs/resources/lldbdap.md
+3-1lldb/tools/lldb-dap/README.md
+2-1lldb/docs/index.rst
+409-1975 files

LLVM/project 0b2f3cfclang/lib/Sema SemaAMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-wmma-w32.cl

Revert "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674)

Reverts llvm/llvm-project#174310

This change is causing 2 cross-project-test failures on
https://lab.llvm.org/buildbot/#/builders/174/builds/29695
DeltaFile
+0-57llvm/lib/IR/AutoUpgrade.cpp
+26-26llvm/test/CodeGen/AMDGPU/wmma-coececution-valu-hazards.mir
+20-20llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
+0-34clang/lib/Sema/SemaAMDGPU.cpp
+4-23llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+2-24clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
+52-18412 files not shown
+90-28018 files

LLVM/project 551d553llvm/lib/Target/RISCV RISCVOptWInstrs.cpp RISCVISelLowering.cpp

[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW. (#174542)

This matches what we do for CLZW and other W instructions.
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+1-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1-0llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+3-03 files