[lldb] Add requireSocketPermission decorator for tests that bind sockets (#219208)
We sometimes run tests in sandboxed environments that deny all calls to
`bind`. This breaks a few of our tests that e.g. use a mock GDB server
or any other functionality involving sockets.
This patch adds a requireSocketPermission decorator (and an equivalent
utility for unittests) that check whether we are allowed to call bind.
If we aren't allowed to call bind, we skip the few tests that need this
functionality.
[Hexagon] Add GlobalArrayAlignment pass (#217850)
Add a module pass that raises the alignment of global integer arrays
(char, short, int), including multi-dimensional arrays, to an 8-byte
boundary. This gives their base address a wider alignment, which is
beneficial for the wide (double-word) loads and stores available on
Hexagon.
At -O1/-O2 the pass keeps byte and half-word arrays at their natural
alignment to reduce .rodata size; full 8-byte alignment is applied at
-O3. This size-reduction behavior can be disabled with
-hexagon-disable-align-opt-byte-half.
The pass is enabled by default and can be disabled with
-hexagon-disable-global-array-align.
Co-Authored by: Jyotsna Verma jverma at quicinc.com
PowerPC: Use use_instructions in TLSDynamicCall user collection
The loop only collects the using instructions, so iterate
use_instructions() instead of the operands to get their parents.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[libc++] Use __copy_n in vector::__assign_with_size (#218370)
This was originally part of #214132. However, that patch has some
difficult to track down performance issue. I'm splitting this up to make
the search easier.
X86: Use use_instructions in CompressEVEX cross-block check
The loop only checks the using instruction's parent block, so iterate
use_instructions() instead of the operands and checking their parents.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[MLIR][NVVM] Support tcgen05.mma{.block_scale}.decompress_b Ops (#218354)
This change adds support for `tcgen05.mma.decompress_b` and
`tcgen05.mma.block_scale.decompress_b` MLIR Ops.
Hexagon: Use use_instructions in EarlyIfConversion predicate check
The loop only checks whether any user is a PHI, so iterate
use_instructions() instead of the operands to query the parents.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
AMDGPU: Use use_nodbg_instructions in GCNSchedStrategy MFMA check
The loop only inspects the using instruction, so iterate
use_nodbg_instructions() instead of the operands and their parents.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
RISCV: Pass MachineRegisterInfo to isVLKnownLE
isVLKnownLE and its getEffectiveImm helper used the VL operands to reach
the MachineRegisterInfo. Pass it directly so they no longer depend on
MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Hexagon: Use use_instructions in BitSimplify use scans (#219308)
This only inspects the parent instruction, so use use_instructions
instead.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[RISCV][P-ext][NFC] Overload scalar mqacc/mqracc intrinsics by element width (#219345)
Collapse the scalar halfword (`mqacc.h*`, i32) and word (`mqacc.w*`,
i64) forms of the Packed Q-format Multiply Parts Accumulate intrinsics
into one overloaded intrinsic per element selection
(`int_riscv_mqacc_00` covers both `mqacc.h00` and `mqacc.w00`, via
result/operand types), mirroring #218875. Packed form (`pmqacc_h*`) and
C builtins stay split. No functional change to the generated code.
[clang][AST] Un-template LazyGenerationalUpdatePtr (#219187)
It is only used in Redeclarable with a single set of template
arguments. Rename to LazyGenerationalDeclPtr and simplify the code.
[orc-rt] Add include/orc-rt-internal for internal APIs. (#219386)
Headers here are not installed. A prefix directory rather than a
separate include root, so that internality is visible at each #include
site.
Moved in: support/{Endian,StringExtras}.h; orc-rt-utils/CommandLine.h
becomes orc-rt-internal/tools/CommandLine.h, retiring orc-rt-utils/ as a
third include root; and lib/bedrock/{Environment,GDBJITRegistrar,
TargetDetails}.h, so lib/ now holds only translation units and the two
Unix/*.inc fragments. That also removes the last "../" include, and
orc-rt-bedrock-impl-headers, which existed only to expose lib/ for
cross-directory includes.
[ADT] Fix FoldingSetIterator::operator* pointer adjustment for multiple inheritance (#219349)
b7dc8e356b89 replaced the void*->FoldingSetNode*->T* cast in
FoldingSetIteratorImpl::getNode() with a direct void*->T* cast, dropping
the base-to-derived adjustment needed when FoldingSetNode isn't T's
first base. Restore the FoldingSetNode* intermediate cast.
Found via a downstream user with a multiply-inherited FoldingSetNode
type that iterates its FoldingSet directly (via find_if over
begin()/end()), corrupting the dereferenced pointer and crashing.
---------
Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
[RISCV] Attach VLMAX range attribute for vsetvli/vsetvlimax in InstCombine
Attach a range return attribute to riscv_vsetvli/vsetvlimax so the generic
value analyses can reason about the result via CallBase::getRange(), using the
subtarget's real VLEN instead of the architectural maximum.
VLMAX = VLEN * LMUL / SEW. vsetvlimax returns exactly VLMAX; vsetvli returns
0 <= vl <= min(AVL, VLMAX), which equals AVL only when AVL cannot exceed the
smallest possible VLMAX. Otherwise vl may shrink below VLMAX (to 0 at runtime),
so we only claim the VLMAX-derived upper bound.
Fixes #217784.
Assisted-by: TRAE CLI (Opus 4.8)
Reviewers: efriedma-quic, preames, lenary, lukel97
Reviewed By: lukel97
Pull Request: https://github.com/llvm/llvm-project/pull/218652
[lld-macho] Remove symbol name assumptions from category merging (#217276)
The category merger required every __objc_catlist entry to point to a
symbol named with the `__OBJC_$_CATEGORY_` or `__CATEGORY_` prefix and
hit llvm_unreachable otherwise. Such names cannot be relied upon: `ld
-r` rewrites the names of category body symbols to generated names like
`l002`, and linking its output crashes lld.
The merger also used symbol names to predict the layout of protocol
lists, which is fragile even for conventionally named inputs. The repro
https://github.com/llvm/llvm-project/pull/95124#issuecomment-4267900795
fired the "Protocol list does not match expected size" assertion.
Remove the category symbol name requirement, and drop the layout
assertion together with the SourceLanguage machinery.
[BOLT][RISCV] Implement indirect PLT calls (#219184)
This patch implements `MCPlusBuilder::createIndirectPLTCall` for RISC-V,
enabling BOLT's `--plt=hot` and `--plt=all` optimizations for RISC-V
binaries.
The PLT call pass replaces direct calls and tail calls to PLT entries
with indirect calls through the corresponding resolved GOT slot. The
generated sequence is:
auipc t3, %pcrel_hi(target at GOT)
l[dw] t3, %pcrel_lo(.Lpcrel_hi)(t3)
jalr ra, t3, 0
[WebAssembly] Expand v8f16 SELECT_CC (#218922)
Follow up for #213280 (read
https://github.com/llvm/llvm-project/pull/213280#discussion_r3797603654)
Mark `v8f16 SELECT_CC` for expansion so scalar comparison-based selects
lower through the existing comparison and `v128.select` patterns
[orc-rt] Split headers into support/ and bedrock/ layers. NFC. (#219374)
Follow-up to 8c7563a40a5b, which nested the runtime's headers under
include/orc-rt/bedrock/ and noted that library-neutral headers would
later be split back out.
The split names a layer -- who may include whom. support/ holds
vocabulary and utilities that depend on nothing else in orc-rt; bedrock/
holds the runtime components (Session, Service, the memory map, the
dylib manager, the SPS controller interfaces) and may include support/.
SPIRE will be able to include both. orc-rt-c/ gains the same layering.
Note that support/ is a layer inside the bedrock library, not a separate
one: Error.cpp and RTTI.cpp still compile into orc-rt-bedrock.
Also folded in: bedrock/sps-ci/ -> bedrock/sps/ in both include/ and
lib/; include guards derived from each header's path, as LLVM does
(ORC_RT_SUPPORT_ERROR_H); test/unit/ mirrored onto the new layout, with
cross-layer test helpers left at its root; test-target FOLDER properties
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[mlir][SPIRV] Fix `StorageBuffer` access conversion for emulated i16 (#218693)
Follows up on commit 202ece6. In the absence of `Int16` and
`StorageBuffer16BitAccess` in the target, `i16` isn't any different from
byte & sub-byte types. As exposed by downstream smoke tests of the IREE
project, an edge case where this causes issues is a 0/1-rank memref.
Semantically:
```
memref<i16> -> ptr<struct<array<1 x i32>>>
```
Since the array lengths are the same in the absence of actual packing,
just the index bounds check doesn't catch this and `InBoundsAccessChain`
still gets chosen. In the end, the memref op fails to lower through the
same restriction in `MemRefToSPIRV` that the original change apparently
had to work around - only `AccessChain` is expected there.
As a more general criterion, the change just compares array the element
types and picks `AccessChain` upon mismatch.
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[X86] Emit adox instead of adc for overflow add (#216609)
ADOX is like ADC but with OF instead of the CF and can only be encoded
with a pair of 32 or 64 bit regs.
Basically this applies in cases where the overflow flag is being added.
[WebAssembly] Select lane stores for floating-point vectors (#219186)
This extends the existing integer vector lane-store patterns to the
equivalent floating-point vector types. The underlying WebAssembly
instructions are type-agnostic lane stores.
That being said I think something like `STORE_LANE_I32x4_A32` can be
misleading when dealing with floating-point vectors. (should there be a
rename or something ?)
[WebAssembly] Fold offsets into extending SIMD loads (#219144)
I saw this TODO and realized that instead of lowering to
```
local.get 0
i32.const 8
i32.add
v128.load64_zero 0
f64x2.promote_low_f32x4
```
We could choose
```
local.get 0
v128.load64_zero 8
f64x2.promote_low_f32x4
```
So I used the existing WebAssembly address operand patterns when
lowering v2f32-to-v2f64 extending loads.
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[Clang-Tidy] Improve `bugprone-implicit-widening-of-multiplication-result`. (#214501)
Implicit integer promotions make it a bit difficult to deduce the
correct type in the following expression:
```
std::uint64_t calc_array_size(std::uint16_t width, std::uint16_t height) {
return width * height;
}
```
Originally, Clang-Tidy suggested to use the following code:
```
return static_cast<long long>(width) * height;
```
It is fully correct according to the C++ rules, but it makes it a bit
harder to reason for people. This change adds a more readable "FixIt"
taking into account the source type and avoid intermediate
representations.
Co-authored-by: Dmitrii Kuragin <dkuragin at adobe.com>
