LLVM/project 07d0f8allvm/lib/Target/AMDGPU AMDGPUWaitcntTracking.cpp AMDGPUWaitcntTracking.h

Merge #210741
DeltaFile
+17-2llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.cpp
+3-0llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.h
+20-22 files

LLVM/project d66f47fllvm/lib/Target/AMDGPU AMDGPUWaitcntTracking.cpp

Merge #201619, #178711
DeltaFile
+41-16llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.cpp
+41-161 files

LLVM/project f08b47cllvm/lib/Target/AMDGPU AMDGPUWaitcntTracking.cpp

Fix merge
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.cpp
+2-21 files

LLVM/project 63dcdd8llvm/lib/Target/AMDGPU AMDGPUWaitcntTracking.cpp AMDGPUWaitcntTracking.h

Avoid virtual dispatch
DeltaFile
+43-66llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.cpp
+40-24llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.h
+25-19llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+108-1093 files

LLVM/project acba7e1llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUWaitcntTracking.cpp

[RFC][AMDGPU][InsertWaitcnts] Move `WaitcntBrackets` to a separate file

My previous stack of patches de-tangled quite a bit of InsertWaitcnt,
and now `WaitcntBrackets` can be moved into a separate file fairly
easily. I'm proposing this as a RFC. While I think this is a net
positive, I don't want to force this through if others feel it's unnecessary.

Implementation:
This pretty much moves `WaitcntBrackets` as-is, with a few changes:

- Instead of having a pointer to `SIInsertWaitcnts` for the "context"
  there is now a "Info" class that `SIInsertWaitcnts` implements.
  This enforces a small separation between the classes, not enough to
  force a massive redesign, but enough that we can't just access the
  entire state of `InsertWaitcnts` at will.
- Some unused/unnecessary functions were removed or made private.
- I reorganized the code a bit: moved all private functions together,
  moved method implementations to the .cpp if they had more than 2 lines of code.
  The goal is to keep things somewhat organized so it's easy to glance at the

    [23 lines not shown]
DeltaFile
+35-1,387llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+1,124-0llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.cpp
+311-0llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.h
+5-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+1-0llvm/lib/Target/AMDGPU/CMakeLists.txt
+1,476-1,3875 files

LLVM/project ef13d46llvm/lib/CodeGen/AsmPrinter CodeViewDebug.cpp, llvm/lib/DebugInfo/CodeView CodeViewRecordIO.cpp

[CodeView] Encode signed enumerators as signed integers (#210352)

In #210338 I noticed that enumerator constants were always encoded as
unsigned integers. MSVC (usually) uses the correct signedness
(comparison: https://godbolt.org/z/rbrchhjTT). It only uses signed
values for 64 bit unsigned values (probably a bug).

We know the signedness in `DIEnumerator` and we should use it.

The change in `llvm/lib/DebugInfo/CodeView/CodeViewRecordIO.cpp` was
needed, because the max/min values need all the bits to encode their
value - otherwise we hit an assertion.

This also encodes the saturated value (`INT64_MIN = 0x8000000000000000`)
in the int128 test correctly (initially added in
https://reviews.llvm.org/D105320).
DeltaFile
+431-0llvm/test/DebugInfo/COFF/enum-limits.ll
+4-4llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
+3-4llvm/lib/DebugInfo/CodeView/CodeViewRecordIO.cpp
+2-2llvm/test/DebugInfo/COFF/integer-128.ll
+440-104 files

LLVM/project 04327b1libcxx/test/libcxx/text/text_encoding environment.pass.cpp

Revert "[libc++][test] XFAIL `text/text_encoding/environment.pass.cpp` test on Armv7/Linux Ubuntu targets." (#211112)

Reverts #206188

XFAIL'ed wrong test
DeltaFile
+0-4libcxx/test/libcxx/text/text_encoding/environment.pass.cpp
+0-41 files

LLVM/project 6f47123llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU expert_scheduling_gfx12.mir

[AMDGPU] Remove some unneeded waits for VA_VDST (#210741)

Add some internal consistency checks on WaitcntBrackets before and after
processing each instruction. In particular, check that VA_VDST_RD and
VA_VDST_WR agree on the range of values of the underlying hardware
counter. Fix some cases where this was not true, which has the effect of
removing some unneeded waits for VA_VDST where it was already known to
be zero.
DeltaFile
+23-4llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+2-3llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
+25-72 files

LLVM/project 29575a3llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp, llvm/lib/MC MachObjectWriter.cpp

[MachO] Preserve weak linkage for aliases (#198148)

Mach-O aliases with weak or linkonce linkage were emitted as weak
references, which is appropriate for undefined references but not for
alias definitions. Emit Mach-O aliases through the same linkage path as
other global definitions so weak aliases get .weak_definition.

When writing aliased symbols, keep the aliasee flags and include the
alias symbol's own flags so N_WEAK_DEF is preserved in the Mach-O n_desc
field.

Fixes #111321

#196047 was closed as a duplicate of #111321.
DeltaFile
+17-0llvm/test/CodeGen/AArch64/macho-weak-alias.ll
+6-1llvm/lib/MC/MachObjectWriter.cpp
+3-1llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+26-23 files

LLVM/project f5430c5llvm/lib/CodeGen Rematerializer.cpp

[NFC] Reword comment per post-merge feedback on #211031 (#211234)

As discussed with krzysz00
DeltaFile
+3-6llvm/lib/CodeGen/Rematerializer.cpp
+3-61 files

LLVM/project 77c7993clang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGenOpenCL builtins-amdgcn-global-async-load-lds.cl

[AMDGPU] Add gfx13 support for global_load_async_to_lds
DeltaFile
+91-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
+50-0clang/test/CodeGenOpenCL/builtins-amdgcn-global-async-load-lds.cl
+48-0llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
+4-4clang/include/clang/Basic/BuiltinsAMDGPU.td
+6-2llvm/lib/Target/AMDGPU/FLATInstructions.td
+2-1llvm/lib/Target/AMDGPU/AMDGPU.td
+201-71 files not shown
+202-77 files

LLVM/project 37314b8llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 fmuladd-copyable-add-part.ll resized-bv-values-non-power-of2-node.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+60-51llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-add-part.ll
+41-14llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+5-5llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll
+106-703 files

LLVM/project bad9ad3llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-partial-reduce.ll

[AArch64][SVE] Fix v16i8 -> v2i64 partial_reduce for VL > 128 (#204938)

A fixed-length `llvm.vector.partial.reduce.add` reducing `<16 x i8>`
into `<2 x i64>` is lowered on `+sve` by converting the reduction to a
scalable one and finishing with `convertFromScalableVector`. The i8 ->
i64 fold splits the `(nx)v4i32` dot before converting it back to fixed
length, but splitting a scalable container is not equivalent to
splitting the fixed vector it holds: at vscale=2 an `nxv4i32` container
splits into two `nxv2i32`, each holding four i32s, not the two-lane
halves of the underlying `v4i32`. The high partial sums land in lanes
that `convertFromScalableVector` then discards, so any runtime VL > 128
silently drops them — on a 256-bit machine (e.g. Neoverse V1) exactly
half the result is lost (#204939; downstream miscompile
rust-lang/rust#158144).

Convert the dot back to a fixed-length i32 vector before splitting, so
the split, widen and accumulate all happen in fixed length and no lanes
are dropped. The fixed dot width is derived from the result (two i32
lanes per i64 result lane) so the wider, VL-pinned `<4 x i64> <- <32 x

    [3 lines not shown]
DeltaFile
+532-126llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll
+26-16llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+558-1422 files

LLVM/project 6f71193llvm/lib/Transforms/Vectorize LoopVectorizationLegality.cpp VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize early_exit_combined_exits.ll

[LV] Vectorize uncountable early exit store loops with combined conditions

Support the case where both the countable and uncountable exit conditions
have been combined by earlier passes.
DeltaFile
+70-0llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+44-24llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+55-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+36-4llvm/test/Transforms/PhaseOrdering/AArch64/countable-and-uncountable-exits-combined.ll
+29-3llvm/test/Transforms/LoopVectorize/early_exit_combined_exits.ll
+21-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+255-315 files not shown
+291-3411 files

LLVM/project 8a25c7dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorizationLegality.cpp, llvm/test/Transforms/LoopVectorize early_exit_combined_exits.ll

Address comments
DeltaFile
+41-41llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+57-2llvm/test/Transforms/LoopVectorize/early_exit_combined_exits.ll
+39-16llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+22-15llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+6-0llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
+165-745 files

LLVM/project 3369dddllvm/lib/Target/AMDGPU GCNVOPDUtils.cpp VOP3PInstructions.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

AMDGPU: Reland: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3 (#196516)

For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark
them with usesCustomInserter which will be used to add pre-RA register
allocation hints to preferably assign dst and src2 to the same physical
register. When the hint is satisfied, canMapVOP3PToVOPD recognises the
instruction as eligible for VOPD pairing by checking if it is VOP2 like:
dst==src2, no source modifiers, no clamp, and src1 is a register.
Mark both instructions as commutable to allow a literal in src1 to be
moved to src0, since VOPD only permits a literal in src0.

Original patch had a bug where it did not check if physical src
registers match register class of appropriate operand in fullVOPD
instructions, check is now done via isValidVOPDSrc.
DeltaFile
+442-520llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+163-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+34-1llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+8-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+661-5951 files not shown
+663-5977 files

LLVM/project 3407cd1llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Validate VOPD/VOPD3 physical source registers against operand RC (#196515)

Replace isVGPR checks with isValidVOPDSrc that validates physical source
registers against the actual combined VOPD/VOPD3 instruction's operand
register classes. Now we also validate operands for VOPD instructions.
DeltaFile
+56-10llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+56-101 files

LLVM/project 3ac7573clang/bindings/python/clang cindex.py, clang/docs ReleaseNotes.md

[libclang/python] Remove CompletionChunk.isKind methods (#210678)

This completes the third step of
https://github.com/llvm/llvm-project/issues/156680
This change is a follow-up to
https://github.com/llvm/llvm-project/pull/177854, following the release
branching, to ensure a one release-cycle deprecation period.
DeltaFile
+0-51clang/bindings/python/clang/cindex.py
+6-0clang/docs/ReleaseNotes.md
+6-512 files

LLVM/project 05daf2allvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp

[LLVM][AArch64TargetTransformInfo] Fix typos in SVEIntrinsicInfo. (#211230)

Correct Propery->Property and sprinkle a couple of extra comments.
DeltaFile
+13-5llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+13-51 files

LLVM/project 31810a1llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Refactor checkVOPDRegConstraints (#196514)
DeltaFile
+28-41llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+28-411 files

LLVM/project 9ca046eclang/lib/CodeGen CodeGenModule.cpp, clang/lib/CodeGen/Targets PPC.cpp

clang: Emit "long-double-type" module flag generically

Move emission of the "long-double-type" module flag out of PowerPC
and into generic code, so it describes the long double format for all
targets.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+26-0clang/lib/CodeGen/CodeGenModule.cpp
+23-0clang/test/CodeGen/long-double-type-module-flag.c
+0-23clang/lib/CodeGen/Targets/PPC.cpp
+0-17clang/test/CodeGen/ppc64-long-double-type-attr.c
+49-404 files

LLVM/project c2e9ff2clang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGen amdgpu-builtin-processor-is.c amdgpu-builtin-is-invocable.c

[AMDGPU] Add FeatureSubtarget for global async load/store lds
DeltaFile
+18-8llvm/lib/Target/AMDGPU/FLATInstructions.td
+8-8clang/include/clang/Basic/BuiltinsAMDGPU.td
+10-0llvm/lib/Target/AMDGPU/AMDGPU.td
+2-2clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
+1-1clang/test/CodeGen/amdgpu-builtin-processor-is.c
+1-1clang/test/CodeGen/amdgpu-builtin-is-invocable.c
+40-201 files not shown
+42-207 files

LLVM/project 590b878llvm/include/llvm/Support CodeGen.h, llvm/include/llvm/TargetParser Triple.h

Triple: Add query for the default long double format

The long double format changes the library call info, which needs
to be computed independently of codegen. Implement this based on the
clang target code.
DeltaFile
+161-0llvm/unittests/TargetParser/TripleTest.cpp
+58-0llvm/lib/TargetParser/Triple.cpp
+9-0llvm/include/llvm/Support/CodeGen.h
+4-0llvm/include/llvm/TargetParser/Triple.h
+232-04 files

LLVM/project 5329e3bllvm/docs LangRef.md, llvm/lib/IR Verifier.cpp

IR: Accept x86_fp80 and float as a long-double-type value

Prepare to emit long-double-type for all targets.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+12-0llvm/test/Assembler/module-flags-long-double-type.ll
+6-0llvm/docs/LangRef.md
+3-1llvm/lib/IR/Verifier.cpp
+21-13 files

LLVM/project 88840f2clang/lib/CIR/CodeGen CIRGenBuiltinNVPTX.cpp, clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets NVPTX.cpp

[CIR][CUDA] Add support for scoped NVVM atomic builtins (#210863)

Adds codegen support for the block and system-scoped NVVM atomic
builtins: add, and, or, xor, min, max, inc and dec.

These are lowered to the corresponding CIR `cir.atomic.fetch` operations
and subsequently lowered to LLVM `atomicrmw` instructions.
DeltaFile
+448-0clang/test/CIR/CodeGenCUDA/builtins-nvvm-atomic.cu
+51-72clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
+8-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+7-0clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/NVPTX.cpp
+514-734 files

LLVM/project 1c7c783llvm/docs DeveloperPolicy.md

[Docs] Remove dead Phabricator link from DeveloperPolicy (#210934)

The Phabricator committing-a-change anchor no longer resolves since
Phabricator has been discontinued, so drop the reference and keep the
GitHub Issues guidance for linking reviewed/closed bugs.
DeltaFile
+1-3llvm/docs/DeveloperPolicy.md
+1-31 files

LLVM/project 8a2691cllvm/docs LangRef.md, llvm/include/llvm/Support CodeGen.h

IR: Introduce "float-abi" module flag

This is intended to eliminate the FloatABIType TargetOptions field.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+37-0llvm/test/Verifier/module-flags-float-abi.ll
+31-0llvm/docs/LangRef.md
+28-0llvm/test/Linker/module-flags-float-abi.ll
+16-12llvm/lib/IR/AutoUpgrade.cpp
+25-0llvm/include/llvm/Support/CodeGen.h
+16-0llvm/test/Bitcode/upgrade-ppc-float-abi.ll
+153-124 files not shown
+191-1210 files

LLVM/project 119a0fbllvm/docs LangRef.md, llvm/lib/IR AutoUpgrade.cpp

PowerPC: Rename "float-abi" module flag to "long-double-type"

PPC was emitting a "float-abi" module flag for indicating the type of long
double. The "float ABI" naming is already widely taken by soft vs. hard
float controls (e.g., the clang flag is called -mfloat-abi), so this shouldn't
have taken it. This should also not be PPC specific; x86 has the same problem.
Rename the flag to the more specific long-double-type, and add appropriate
verification and documentation (which was also missing). Also changes the value
names to match the IR type names.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+45-0llvm/test/Bitcode/upgrade-ppc-float-abi.ll
+28-11llvm/test/CodeGen/PowerPC/gnu-attribute.ll
+37-0llvm/test/Verifier/module-flags-long-double-type.ll
+31-0llvm/test/Linker/module-flags-long-double-type.ll
+30-0llvm/docs/LangRef.md
+20-0llvm/lib/IR/AutoUpgrade.cpp
+191-116 files not shown
+254-4212 files

LLVM/project f61499bmlir/lib/Conversion/RaiseWasm RaiseWasmMLIR.cpp, mlir/test/Conversion/RaiseWasm wasm-comparisons-to-arith-cmp.mlir wasm-blocks-to-cf.mlir

[MLIR][WASM] Introduce full support for raising WASM MLIR to other dialects (#205990)

Following https://github.com/llvm/llvm-project/pull/164562 where
RaiseWasm was introduced.
This PR completes the support for rewriting the currently supported Wasm
MLIR operators to arith, math, cf and memref.

---------

Co-authored-by: Ferdinand Lemaire <ferdinand.lemaire at woven-planet.global>
DeltaFile
+455-1mlir/lib/Conversion/RaiseWasm/RaiseWasmMLIR.cpp
+421-0mlir/test/Conversion/RaiseWasm/wasm-comparisons-to-arith-cmp.mlir
+366-0mlir/test/Conversion/RaiseWasm/wasm-blocks-to-cf.mlir
+201-0mlir/test/Conversion/RaiseWasm/wasm-loop-to-cf.mlir
+77-0mlir/test/Conversion/RaiseWasm/wasm-rotr-to-arith.mlir
+76-0mlir/test/Conversion/RaiseWasm/wasm-extend-to-arith-ext.mlir
+1,596-13 files not shown
+1,713-19 files

LLVM/project b9ecf45llvm/test/CodeGen/AArch64 smul_fix_sat.ll umul_fix_sat.ll

[AArch64][GlobalISel] Update and cleanup s/umul.fix tests. NFC (#211232)
DeltaFile
+659-40llvm/test/CodeGen/AArch64/smul_fix_sat.ll
+564-53llvm/test/CodeGen/AArch64/umul_fix_sat.ll
+161-45llvm/test/CodeGen/AArch64/smul_fix.ll
+171-22llvm/test/CodeGen/AArch64/umul_fix.ll
+1,555-1604 files