LLVM/project a9a6edbllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/PhaseOrdering/X86 avg.ll

[SLP]Vectorize single-user instructions as the last-attempt seeds

Instructions with the single user cost one extract per lane, so they are
vectorized after all other roots in the function are exhausted, grouped by
the key/subkey pairs. Loads, addresses, compares and the operations, folded
away or contracted into the scalar FMA, are excluded. The rejected bundles
and the members of the priced minimal nodes are not retried, unless the
tree was dropped by the repacking overhead rather than by the members.

Reviewers: hiraditya, RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/212579
DeltaFile
+301-86llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+145-94llvm/test/Transforms/PhaseOrdering/X86/avg.ll
+33-66llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
+49-30llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
+48-30llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
+35-36llvm/test/Transforms/SLPVectorizer/X86/reused-mask-with-poison-index.ll
+611-34238 files not shown
+1,020-73144 files

LLVM/project ab4f210clang/include/clang/Basic OffloadArch.h, clang/lib/Basic Cuda.cpp

clang: Replace Is*OffloadArch free functions with OffloadArch methods (#213363)
DeltaFile
+29-19clang/unittests/Basic/OffloadArchTest.cpp
+6-6clang/lib/Driver/Driver.cpp
+0-9clang/include/clang/Basic/OffloadArch.h
+4-4clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
+2-2clang/lib/Basic/Cuda.cpp
+1-1clang/lib/Driver/ToolChains/Clang.cpp
+42-411 files not shown
+43-427 files

LLVM/project 08a8739lldb/bindings/interface SBValueListExtensions.i SBValueExtensions.i, lldb/bindings/python python-extensions.swig python.swig

[lldb][Python] Inline `lldb_iter` for better type inference (#214000)

Currently, the `lldb_iter` helper is used for providing `__iter__` in
the Python bindings:
```python
def lldb_iter(obj, getsize, getelem):
    """A generator adaptor to support iteration for lldb container objects."""
    size = getattr(obj, getsize)
    elem = getattr(obj, getelem)
    for i in range(size()):
        yield elem(i)
```

A type checker or LSP can't see through this function. Currently, that's
no problem, because it doesn't know the return type of any Swig wrapper,
but when we add type annotations (hopefully with Swig 4.5 in #213463),
`__iter__` remains untyped. So iterating through the wrappers won't show
the correct type.

As the functionality is fairly simple, it's easier to inline it. That's
what this PR does. Then a type checker can infer the return type.
DeltaFile
+0-12lldb/bindings/python/python.swig
+6-3lldb/bindings/interface/SBTargetExtensions.i
+6-3lldb/bindings/interface/SBModuleExtensions.i
+2-1lldb/bindings/python/python-extensions.swig
+2-1lldb/bindings/interface/SBValueListExtensions.i
+2-1lldb/bindings/interface/SBValueExtensions.i
+18-2119 files not shown
+56-4025 files

LLVM/project 1f69a16llvm/lib/Target/X86 X86TargetTransformInfo.cpp, llvm/test/Transforms/SLPVectorizer/X86 reduced-value-stored.ll

[CostModel][X86] getArithmeticReductionCost - ensure we test the vXi1 reductions types before legalisation (#211043)

Pre-AVX512 these will be legalized to wider vector types and might match
against other reductions tables.

Noticed while working on improving logic reductions, but hit a case
with/without popcnt for bool sum reduction patterns - I've added a AVX2
test pass to check the (corrected) costs are still working
DeltaFile
+36-46llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+43-19llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll
+79-652 files

LLVM/project cafd36bclang/include/clang/CIR LoweringHelpers.h, clang/include/clang/CIR/Dialect/IR CIROps.td

[NFC][CIR] Propagate SymbolTables better (#213972)

This came up during self-build, we are spending a lot of time in some
cases looking up using the global symbol table, which does no caching.
Previously we'd propagated this in a few places, but this patch removes
all uses of SymbolTable::lookup and adds the cache everywhere.

This involved changing the tablegen to include it in each of our
rewriters, plus the CirAttr lowering everywhere.

The only thing we have to take care of is to make sure we invalidate the
cache/update the cache whenever we add something with a name (see
createLLVMFuncOpIfNotExist).

This is NFC, as it isn't observable, other than being a build time
improvement.
DeltaFile
+47-34clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+26-28clang/lib/CIR/Lowering/LoweringHelpers.cpp
+6-8clang/include/clang/CIR/LoweringHelpers.h
+5-2clang/utils/TableGen/CIRLoweringEmitter.cpp
+0-6clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
+85-786 files

LLVM/project c9f2ba2llvm/lib/Target/RISCV RISCVMacroFusionXQCI.td, llvm/test/CodeGen/RISCV macro-fusions-xqci.mir

[RISCV] Fix Xqci Fusions with Frame Indexes (#213815)

Pre-RA, the ADDI can contain a frame index rather than a register, which
causes `getReg()` to assert. These were missing the `CheckIsRegOperand`
that most other fusions have.
DeltaFile
+17-0llvm/test/CodeGen/RISCV/macro-fusions-xqci.mir
+6-1llvm/lib/Target/RISCV/RISCVMacroFusionXQCI.td
+23-12 files

LLVM/project 6326f14clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp

[CIR] Lower variadic calls in CallConvLowering for x86_64 (#213315)

CallConvLowering classified each function once from its declared
signature and reused that classification at every call site. An argument
passed through an ellipsis has no entry in the callee's parameter list,
so on x86_64 an ellipsis argument that needed an extension attribute, a
register coercion, or a byval slot was emitted unchanged whenever the
callee's declared parameters happened to need no rewrite, and reported
NYI when they did.

An ellipsis argument competes for the same registers as a declared one,
so the same two-eightbyte record goes in a register pair early in the
list and byval once the integer registers are gone. Variadic call sites
under the x86_64 driver are now classified from the call's own operand
types, and the declared parameter count reaches
`llvm::abi::FunctionInfo::create` as its `NumRequired` argument, which
is what lets the classifier tell a named argument from one passed
through the ellipsis. Today that flag only decides whether a large
vector goes in a register, and the CIR type bridge admits no vector

    [25 lines not shown]
DeltaFile
+299-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-variadic.c
+242-37clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+240-0clang/test/CIR/Transforms/abi-lowering/x86_64-variadic-nyi.cir
+209-0clang/test/CIR/Transforms/abi-lowering/x86_64-variadic-call.cir
+62-0clang/test/CIR/Transforms/abi-lowering/x86_64-indirect-try-call.cir
+29-22clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+1,081-598 files not shown
+1,204-7814 files

LLVM/project 70ecc5bllvm/test/CodeGen/AMDGPU llvm.amdgcn.intersect_ray.ll, llvm/test/CodeGen/AMDGPU/GlobalISel orn2.ll legalize-extract.mir

Revert "[GlobalISel] Combine merge-unmerge with mixed scalar and vector types" (#214010)

Reverts llvm/llvm-project#213086
DeltaFile
+0-177llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
+34-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+34-18llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+16-5llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
+12-8llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+15-4llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
+111-2302 files not shown
+122-2448 files

LLVM/project 5009622llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine minmax-fp-loop-carried.ll

[InstCombine]Fold fcmp+select to min/max if its zero sign is missing

Look through phis, chained selects and the loop back edge to the
select itself and fold if no use can observe the sign of zero of the
result. This restores the fold for loop-carried and unrolled running
min/max values (fcsel -> fminnm on AArch64) lost to the signed zero
handling fix in matchSelectPattern (#210077).

Reviewers: nikic, dtcxzyw

Pull Request: https://github.com/llvm/llvm-project/pull/213133
DeltaFile
+242-0llvm/test/Transforms/InstCombine/minmax-fp-loop-carried.ll
+31-6llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+273-62 files

LLVM/project 2a2addellvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.bf16.bf16.ll

[AMDGPU][GISel] Add RegBankLegalize rules for llvm.amdgcn.fdot2.bf16.bf16 (#214013)
DeltaFile
+76-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+77-42 files

LLVM/project af14456openmp/runtime/src kmp_invoke_microtask.cpp

[OpenMP] Simplify generic microtask dispatch (#214004)

Replace the generic microtask dispatcher's handwritten function-pointer
types and calls with a variadic-template helper and a macro for each
supported argument count.

The dispatcher still casts each microtask to the exact fixed-arity
signature required by platforms such as WebAssembly. This is intended as
a refactor only: the existing limit of 15 microtask arguments and the
diagnostic for larger argument counts remain unchanged.

This reduces the repetitive code and makes future changes to the
supported argument range easier to review.

Split out from #211071
DeltaFile
+39-110openmp/runtime/src/kmp_invoke_microtask.cpp
+39-1101 files

LLVM/project 5382f7dllvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AArch64 masked_compress_load.ll

[CostModel][AArch64] Add initial costs for `masked.compressstore` (#213712)

This adds an initial cost model for `masked.compressstore`. The tests
are based on `masked_expand_load.ll`, which covers all configurations
for the `expand`/`compact` instructions.

Note: Right now, we only report valid costs for `masked.compressstore`
operations that can be lowered with SVE1 (as that's all we handle ISEL
for at the moment).
DeltaFile
+281-0llvm/test/Analysis/CostModel/AArch64/masked_compress_load.ll
+15-1llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+296-12 files

LLVM/project 2c52baallvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.scalef32.sr.pk16.ll llvm.amdgcn.cvt.scale.pk.ll

[AMDGPU][GISel] RegBankLegalize rules for CVT Scale and SR intrinsics
DeltaFile
+352-172llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
+236-116llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
+115-119llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
+165-65llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
+55-27llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
+56-25llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+979-5246 files not shown
+1,015-56212 files

LLVM/project f134fb4llvm/include/llvm/Transforms/Utils LoopPeel.h, llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopPeel] Peel last iteration to enable load widening

In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., b32) for
all other N-1 iterations.

Patterns such as:
```
  %a = load i8, ptr %p
  %b = load i8, ptr %p+1
  %c = load i8, ptr %p+2
  ...
  %p.next = getelementptr i8, ptr %p, 3
```

Can be transformed to:
```
  %wide = load b32, ptr %p     ; Read 4 bytes

    [19 lines not shown]
DeltaFile
+652-131llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening.ll
+324-10llvm/lib/Transforms/Utils/LoopPeel.cpp
+51-16llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-be.ll
+55-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-disabled.ll
+6-0llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+6-0llvm/include/llvm/Transforms/Utils/LoopPeel.h
+1,094-1571 files not shown
+1,098-1577 files

LLVM/project 7609cb8llvm/lib/Target/DirectX DXILResourceAccess.cpp, llvm/test/CodeGen/DirectX/ResourceAccess phi-insert-point.ll

[DirectX] Prevent `dxil-resource-access` from inserting a resource access in-between phi nodes (#211343)

The pass can incorrectly place a load/store within the phi nodes at top
of the basic block: https://godbolt.org/z/x5Ec4GWGT

This is resolved by updating `replaceHandleWithIndices` to adjust the
insertion point when the ptr comes from a phi node.

Resolves, in part, https://github.com/llvm/llvm-project/issues/211121

Assisted by: Claude Opus 4.8
DeltaFile
+36-0llvm/test/CodeGen/DirectX/ResourceAccess/phi-insert-point.ll
+2-0llvm/lib/Target/DirectX/DXILResourceAccess.cpp
+38-02 files

LLVM/project d62a997llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.bf16.bf16.ll

[AMDGPU][GISel] Add RegBankLegalize rules for llvm.amdgcn.fdot2.bf16.bf16
DeltaFile
+76-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+77-42 files

LLVM/project fe35af3flang-rt/lib/runtime tools.cpp assign.cpp, flang-rt/unittests/Runtime Assign.cpp

[flang-rt] - Lightweight runtime assignment function (AssignSimple) for intrinsic-type assignments.

This PR introduces a lightweight assignment runtime path (`_FortranAAssignSimple`) for intrinsic-type arrays
with the goal of reducing compile-time overhead seen primarily in the form of severly increased time taken by LTO.
This PR includes only the changes to the runtime (flang-rt) and as such just with this PR compile-time improvements
will not be visible.

**Problem**

When compiling Fortran code with OpenMP GPU offload and `firstprivate(allocatable_array)`, LLVM's Attributor creates excessive abstract attributes analyzing complex runtime assignment machinery:

**Symptom:**
- **Test case:** 8-element allocatable integer array with `firstprivate` clause
- **Compile time:** 24.97s (vs 0.78s for `private` - **32x slower**)
- **Root cause:** LLVM Attributor analyzing complex Fortran runtime functions

**Why this happens:**

1. `firstprivate` requires copying arrays from host to device

    [43 lines not shown]
DeltaFile
+214-0flang-rt/lib/runtime/assign.cpp
+151-0flang-rt/unittests/Runtime/Assign.cpp
+4-0flang/include/flang/Runtime/assign.h
+1-0flang-rt/lib/runtime/tools.cpp
+370-04 files

LLVM/project 842c1caflang-rt/lib/runtime assign.cpp

Fix formatting issues
DeltaFile
+2-3flang-rt/lib/runtime/assign.cpp
+2-31 files

LLVM/project 8797966flang-rt/lib/runtime assign.cpp

more formatting fixes
DeltaFile
+3-3flang-rt/lib/runtime/assign.cpp
+3-31 files

LLVM/project 7552542llvm/test/tools/llvm-objcopy/ELF binary-output-target.test cross-arch-headers.test

[llvm-objcopy] Address reviewer feedback on AMDGPU test cleanups

- Remove unused -DMACHINE yaml2obj template variable in cross-arch-headers.test,
  hardcode Machine: EM_NONE directly in the YAML instead
- Remove unused Flags: [[FLAGS=<none>]] template variable in cross-arch-headers.test
- Add comment in binary-output-target.test explaining that Arch: unknown is
  intentional when converting from binary (e_flags=0, no EF_AMDGPU_MACH set)
DeltaFile
+2-3llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
+2-0llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
+4-32 files

LLVM/project 958a9bbclang/include/clang/Basic arm_neon.td arm_immcheck_incl.td, clang/lib/Sema SemaARM.cpp

[Clang][ARM] Fix immediate range for NEON widening left-shifts (#212459)

The ACLE specifies the C intrinsic 'vshll_n to have a valid immediate
range size of [0..eltsize] but it has a range of [0..((eltsize*2) - 1)].
Update the range check to match the specified behavior

---------

Co-authored-by: Lukacma <Marian.Lukac at arm.com>
DeltaFile
+217-18llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
+22-21clang/include/clang/Basic/arm_immcheck_incl.td
+25-18clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-left.c
+5-6clang/include/clang/Basic/arm_neon.td
+4-0clang/lib/Sema/SemaARM.cpp
+273-635 files

LLVM/project d4ca2e5llvm/lib/Target/SPIRV SPIRVPostLegalizer.cpp, llvm/test/CodeGen/SPIRV/hlsl-intrinsics atan2_mat.ll

[SPIR-V] Preserve float types through wide float shuffles and atan2 legalization (#213785)

fixes https://github.com/llvm/llvm-project/issues/213783

Propagate result types through G_SHUFFLE_VECTOR and G_FATAN2 during
post-legalizer type deduction. This prevents wide float vectors from
producing integer-typed OpCompositeExtract instructions.

Add generic float shuffle and wide atan2 regression coverage.

assisted by Copilot (GPT-5.6-Sol)
DeltaFile
+17-0llvm/test/CodeGen/SPIRV/legalization/vector-legalization-shader.ll
+9-5llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2_mat.ll
+2-0llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+28-53 files

LLVM/project 3d1a37fllvm/lib/Target/X86/MCTargetDesc X86InstComments.cpp, llvm/test/MC/X86 symbolic-fpclass-imm.s

[X86] Don't assume the FPCLASS category mask is a literal (#213171)

`llvm-mc` asserts on a FPCLASS category mask given as a symbol:

```asm
vfpclassps $f0, %zmm1, %k1
```
```
Assertion failed: isImm() && "This is not an immediate", MCInst.h:85
```

`printFPCLASSComments` reads the last operand with `getImm()` without
checking it is one. The value is only known at link time, so there is no
category to describe; return early and print no comment.

Note this is a comment printer, so encoding is unaffected.
`--filetype=obj` already succeeds today and emits a placeholder
immediate plus an `R_X86_64_8` relocation, which is correct. The issues
describe this as producing a wrong encoding in release builds, which I

    [7 lines not shown]
DeltaFile
+19-0llvm/test/MC/X86/symbolic-fpclass-imm.s
+5-0llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+24-02 files

LLVM/project e5cd456flang/include/flang/Optimizer/Transforms Passes.td, flang/test/Transforms vscale-attr.fir

[flang] Add LLVM dialect dependency to VScaleAttr (#213931)

`VScaleAttr` creates an LLVM `VScaleRangeAttr`, but did not declare the
LLVM dialect as a pass dependency. This aborts when the input does not
otherwise load LLVM.

Declare the dependency and remove the unused FIR-typed argument from the
existing test. Parsing `!fir.ref` loads `FIROpsDialect`, which loads
`LLVMDialect` as a dependency and previously masked the missing pass
dependency.

Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
DeltaFile
+1-1flang/test/Transforms/vscale-attr.fir
+1-0flang/include/flang/Optimizer/Transforms/Passes.td
+2-12 files

LLVM/project c1e828fllvm/test/Analysis/CostModel/AArch64 ctpop.ll ctlz.ll

[AArch64] Update cttz and ctlz cost model test. NFC (#213999)

This updates the tests to match ctpop, how we test other operations.
Some extra
type coverage and cssc is added.
DeltaFile
+66-200llvm/test/Analysis/CostModel/AArch64/cttz.ll
+61-196llvm/test/Analysis/CostModel/AArch64/ctlz.ll
+3-3llvm/test/Analysis/CostModel/AArch64/ctpop.ll
+130-3993 files

LLVM/project 3c0badfllvm/test/CodeGen/AMDGPU buffer-fat-pointer-atomicrmw-fmin.ll buffer-fat-pointer-atomicrmw-fadd.ll

Rebase

Created using spr 1.3.7
DeltaFile
+3,809-3,814llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+3,809-3,814llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+3,465-3,511llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+3,465-3,511llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+3,299-3,240llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+2,594-2,524llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+20,441-20,4142,485 files not shown
+154,056-90,0332,491 files

LLVM/project 0160d12llvm/test/Transforms/SLPVectorizer/RISCV vec3-base.ll

[SLP][NFC]Remove undef mentions from test, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/213992
DeltaFile
+2-2llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
+2-21 files

LLVM/project 32f3ae6clang/test/ClangScanDeps canonicalize-macros-multiarch.c

[Clang] Restrict ClangScanDeps darwin-specific test not to run in cross-compile (#213884)

The test added in 316a29603228c5d5000e0ddf8dfba2a494ac7ee9 fails when
run on MacOS but targeting Linux as a cross compiler.
DeltaFile
+1-1clang/test/ClangScanDeps/canonicalize-macros-multiarch.c
+1-11 files

LLVM/project 8cd7452mlir/lib/Target/SPIRV/Deserialization Deserializer.cpp, mlir/lib/Target/SPIRV/Serialization Serializer.cpp

[mlir][SPIR-V] Handle Volatile decoration in (de)serialization (#212951)
DeltaFile
+7-0mlir/test/Target/SPIRV/decorations.mlir
+1-0mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
+1-0mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
+9-03 files

LLVM/project 1c00b2cllvm/lib/Transforms/Vectorize VPlanRecipes.cpp

Restore type checks in computeScalarTypeForInstruction()
DeltaFile
+7-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+7-01 files