LLVM/project 3091381 — clang/lib/AST/ByteCode InterpBuiltin.cpp

by Timm Baeder via GitHub on ⎇
[clang][bytecode][NFC] Avoid an APFloat copy (#215543)
DeltaFile
+1-1clang/lib/AST/ByteCode/InterpBuiltin.cpp
+1-11 files

LLVM/project 6069eb9 — clang/lib/AST/ByteCode Interp.cpp

by Timm Baeder via GitHub on ⎇
[clang][bytecode][NFC] Remove redundant isInvalidDecl() check (#215546)

This is already checked earlier in the same function.
DeltaFile
+0-4clang/lib/AST/ByteCode/Interp.cpp
+0-41 files

LLVM/project c4f449f — clang/include/clang/InstallAPI FileList.h

by Timm Baeder via GitHub on ⎇
[clang][InstallAPI] Fix doc comment weirdness (#215462)

We shouldn't be using a documentation comment here.
DeltaFile
+3-3clang/include/clang/InstallAPI/FileList.h
+3-31 files

LLVM/project 0813837 — llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/WebAssembly simd-extending-convert.ll

by Anutosh Bhat via GitHub on ⎇
[WebAssembly][DAGCombine] Avoid scalarizing v8i8 to v8f16 conversions (#213636)

WebAssembly FP16 can convert `v8i16` to `v8f16`, but direct `v8i8` to
`v8f16` conversions were scalarized during SelectionDAG type
legalization.

This results in lane extractions, scalar conversions, calls to
`__truncsfhf2`, and reconstruction of the result vector.

We should extend `v8i8` to `v8i16` in `performVectorExtendToFPCombine`
before type legalization. This allows the existing WebAssembly combines
to select:

- `i16x8.extend_low_i8x16_{s,u}`
- `f16x8.convert_i16x8_s`
DeltaFile
+25-0llvm/test/CodeGen/WebAssembly/simd-extending-convert.ll
+6-4llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+31-42 files

LLVM/project da69184 — mlir/include/mlir/Bytecode BytecodeImplementation.h, mlir/include/mlir/IR AffineMap.h OpDefinition.h

by Aditya Medhane via GitHub on ⎇
[mlir][NFC] Remove internal linkage from core header function templates (#214756)

These are more of the cases fixed alongside #208001, which enabled
-Wunused-template under -Wall. Each template is `static` in a widely
included header, so clang warns in every TU that includes it without
instantiating it. Dropping `static` gives them vague linkage and
silences the warning.
DeltaFile
+8-11mlir/include/mlir/IR/PDLPatternMatch.h.inc
+6-7mlir/include/mlir/IR/OpDefinition.h
+3-3mlir/include/mlir/Pass/PassOptions.h
+2-2mlir/include/mlir/IR/AffineMap.h
+2-2mlir/include/mlir/Bytecode/BytecodeImplementation.h
+21-255 files

LLVM/project 1376072 — mlir/include/mlir/Dialect/Utils ReshapeOpsUtils.h

by Aditya Medhane via GitHub on ⎇
[mlir][NFC] Remove internal linkage from reshape op helper templates (#214759)

Another case of the cleanup done for #208001, which enabled
-Wunused-template under -Wall. Both helpers are `static` in
ReshapeOpsUtils.h, which reaches many TUs via Linalg.h, Tensor.h and
MemRef.h, so clang warns wherever they are not instantiated. Dropping
`static` gives them vague linkage.
DeltaFile
+4-4mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h
+4-41 files

LLVM/project 69653c1 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 077b10d — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 4be849c — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV prefer-w-inst.mir

by Sam Elliott on ⎇
[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+88-297 files not shown
+97-3113 files

LLVM/project 5236852 — llvm/lib/Target/RISCV RISCVPassRegistry.def RISCV.h

by Sam Elliott on ⎇
[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+78-213 files not shown
+81-219 files

LLVM/project 8dce5c8 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

by Sam Elliott on ⎇
[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project ecaa557 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV/rvv vl-opt.mir

by Sam Elliott on ⎇
[RISCV] Port VL Optimizer to NewPM

Assisted-by: AI
DeltaFile
+56-31llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+36-0llvm/lib/Target/RISCV/RISCVVLOptimizer.h
+1-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+98-363 files not shown
+101-369 files

LLVM/project f13ce96 — llvm/lib/Target/RISCV RISCV.h

by Sam Elliott on ⎇
Remove useless header
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCV.h
+0-11 files

LLVM/project 64d780a — bolt/lib/Profile DataAggregator.cpp

by Jinjie Huang via GitHub on ⎇
[Perf2bolt] Support multi-PID filtering for multiple perf inputs (#215541)

#199324 added support for multiple perf inputs in perf2bolt. Building on
that, this patch additionally supports filtering by multiple PIDs via
--pid=pid1,pid2...
DeltaFile
+25-16bolt/lib/Profile/DataAggregator.cpp
+25-161 files

LLVM/project 035c725 — llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll f32x2-instructions.ll

by Alex MacLean via GitHub on ⎇
[NVPTX] Cleanup PTX ISA subtarget features (#214623)
DeltaFile
+1,514-802llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+654-654llvm/test/CodeGen/NVPTX/tcgen05-st.ll
+573-573llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+493-301llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
+354-298llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
+276-276llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+3,864-2,90489 files not shown
+8,229-7,04695 files

LLVM/project f47dbac — llvm/unittests/ADT SmallVectorTest.cpp, llvm/unittests/IR IntrinsicsTest.cpp

by NAKAMURA Takumi via GitHub on ⎇
llvm/unittests: Prune unused templates [-Wunused-template] (#215565)
DeltaFile
+0-5llvm/unittests/Support/RecyclerTest.cpp
+0-5llvm/unittests/ADT/SmallVectorTest.cpp
+0-3llvm/unittests/IR/IntrinsicsTest.cpp
+0-133 files

LLVM/project 826edca — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project cde8d00 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project aeebb24 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV fold-mem-offset.mir

by Sam Elliott on ⎇
[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/fold-mem-offset.mir
+78-213 files not shown
+81-219 files

LLVM/project 83abe65 — llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVOptWInstrs.h, llvm/test/CodeGen/RISCV O3-newpm-pipeline.ll O1-newpm-pipeline.ll

by Sam Elliott on ⎇
[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+2-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+2-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+90-277 files not shown
+97-3113 files

LLVM/project 5d27eb9 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

by Sam Elliott on ⎇
[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project 9b25bfb — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV/rvv vl-opt.mir

by Sam Elliott on ⎇
[RISCV] Port VL Optimizer to NewPM

Assisted-by: AI
DeltaFile
+56-31llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+36-0llvm/lib/Target/RISCV/RISCVVLOptimizer.h
+1-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+98-363 files not shown
+101-369 files

LLVM/project f922643 — llvm/lib/Target/RISCV RISCV.h

by Sam Elliott on ⎇
Remove useless header
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCV.h
+0-11 files

LLVM/project 1a499d7 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-strided-load-store.ll

by Sam Elliott via GitHub on ⎇
[RISCV] Port Gather/Scatter Lowering to NewPM (#215669)

This change also adds some missing pass dependencies to the legacy
version of the pass, to reflect some analyses that are already being
used.

Assisted-by: AI
DeltaFile
+72-45llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+40-0llvm/lib/Target/RISCV/RISCVGatherScatterLowering.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
+118-505 files not shown
+124-5011 files

LLVM/project 60936b3 — llvm/lib/CodeGen TypePromotion.cpp, llvm/test/CodeGen/RISCV pr148084.ll

by Craig Topper via GitHub on ⎇
[TypePromotion][RISCV][ARM] Ignore the condition operand of selects. (#215685)

We don't need to promote the condition operand in order to promote a
select. It must always be an i1 type so it doesn't matter where it comes
from.

The change to pr148084.ll is a regression, but I don't think it's
directly related to select. TypePromotion is using a zero extend
promotion which makes constants that are harder to materialize and
prevents the use of `not`. This kind of thing can happen independent of
selects being involved.
DeltaFile
+29-29llvm/test/Transforms/TypePromotion/ARM/casts.ll
+17-10llvm/test/CodeGen/RISCV/pr148084.ll
+7-0llvm/lib/CodeGen/TypePromotion.cpp
+53-393 files

LLVM/project 602c4b5 — llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx vec-extract-brcond.ll

by WANG Rui on ⎇
[LoongArch] Fold shifted vector extract comparisons

Fold comparisons of the form:

  (shl (extract_vector_elt X, I), GRLen - EleBits) ==/!= 0

into:

  (extract_vector_elt X, I) ==/!= 0

When the shift amount equals `GRLen - EleBits`, the left shift only moves
the extracted element into the most significant bits without affecting
whether the value is zero. This canonicalization exposes
EXTRACT_VECTOR_ELT to later combines and enables selecting
VPICKVE2GR_* instructions directly.
DeltaFile
+12-27llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll
+12-27llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll
+17-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+41-543 files

LLVM/project ab1e23c — llvm/test/CodeGen/LoongArch/lasx vec-extract-brcond.ll, llvm/test/CodeGen/LoongArch/lsx vec-extract-brcond.ll

by WANG Rui on ⎇
[LoongArch][NFC] Add tests for vector extract comparison combines
DeltaFile
+137-0llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll
+137-0llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll
+274-02 files

LLVM/project c402a3b — clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGen lambda-generic-in-cxx11abi-lambda.cpp

by Erich Keane via GitHub on ⎇
[CIR] Fix a linking problem with a abi_tag deduced lambda (#215702)

This showed up in self build, but only happens when there is a lambda
with a deduced return type inside another lambda, that returns a type
with an abi_tag on it (std::string in this case). The problem was that
we weren't pulling our mangled name out of the cache, and instead were
re-calculating it every time. This takes code effectively-exactly from
classic-codegen an d puts it into CIRGenModule.cpp

Note the teest is a little fragile for the reproducer, so it needs to be
its own file. Also, there are some parts that are not necessary in it to
reproduce (the 'i' in particular) because this avoids us having 'padded'
lambdas, which results in a call-conv NYI. I considered disabling that,
but it is more work to go back and un-do that flag later, than to just
deal with an extra 'i' for the near future.
DeltaFile
+49-0clang/test/CIR/CodeGen/lambda-generic-in-cxx11abi-lambda.cpp
+10-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+59-02 files

LLVM/project e7efe8f — clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded vwabdau.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded vwabdau.c

by Bohan (Garth) Lei via GitHub on ⎇
[Clang][RISCV] Fix vwabda[u] operand order (#215494)

See https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/435.
DeltaFile
+195-195clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
+195-195clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
+187-187clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
+187-187clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
+102-102clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
+102-102clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
+968-9682 files not shown
+1,166-1,1668 files

LLVM/project 2b46188 — llvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU merge-tbuffer-gfx9.mir merge-tbuffer-gfx12.mir

by Harrison Hao via GitHub on ⎇
[AMDGPU] Gate TBUFFER merging on relaxed OOB mode (#212695)

SILoadStoreOptimizer can combine adjacent TBUFFER accesses into a wider
typed buffer instruction. This changes the granularity of hardware OOB
handling and may affect neighboring components when an access is
partially
out of bounds.

Only allow TBUFFER load/store merging when
`amdgpu.tbuffer.oob.mode` is set to relaxed. Keep the accesses separate
when
the flag is absent, any, or strict to preserve strict OOB semantics.

Reference: https://github.com/llvm/llvm-project/pull/160922
DeltaFile
+189-257llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
+127-175llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
+127-175llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
+127-175llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
+6-0llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+576-7825 files