LLVM/project 5d7b436 — mlir/include/mlir/Dialect/Arith/IR ArithOps.td, mlir/include/mlir/Dialect/LLVMIR LLVMOps.td

[mlir][arith][llvm] Mark floordivsi/urem/srem as ConditionallySpeculatable (#235770)

These ops can trap (division/remainder by zero, and signed overflow for
the signed variants). They were incorrectly marked `Pure`, which allowed
LICM to hoist them out of loops that may execute zero times.

This change makes them `ConditionallySpeculatable`, following the same
pattern already used by `divsi`/`remsi` and `udiv`/`sdiv`.

Fixes #233213

Related discussion:
https://discourse.llvm.org/t/ub-op-semantics-of-arith-integer-division-remainder/92558

---------

Co-authored-by: Matthias Springer <me at matthiasspringer.de>
DeltaFile
+131-0mlir/test/Dialect/LLVMIR/urem-srem-speculatability.mlir
+109-0mlir/test/Dialect/Arith/floordivsi-speculatability.mlir
+28-0mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+11-0mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+6-2mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+6-1mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+291-36 files

LLVM/project 404aa5d — llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-type-enum-multiple-cu.ll debug-type-enum-unrepresentable.ll

[SPIRV] Emit NSDI opcode DebugTypeEnum (#234752)

This makes `SPIRVNonSemanticDebugHandler` emit
[`DebugTypeEnum`](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugTypeEnum)
for a `DICompositeType` tagged `DW_TAG_enumeration_type`, with one Value
and Name pair per `DIEnumerator`. Each CU lists its file-scope enums in
`enums:`. Each of those enums takes that compile unit as its Parent.

Three operands need special handling:

1. Underlying Type: an enum declared without a type, such as `enum E { A
}`, defaults to `int`, so this emits `int` rather than `DebugInfoNone`.
2. Size must be an `OpConstant`, so an incomplete enum, whose size is
recorded as 0, is dropped.
3. Each Value is a 32-bit integer `OpConstant`. If an enumerator needs
more bits, we leave it out.

This does not handle cycles, such as a struct with a member of an enum
declared inside it. [PR

    [10 lines not shown]
DeltaFile
+98-0llvm/test/CodeGen/SPIRV/debug-info/debug-type-enum.ll
+90-0llvm/test/CodeGen/SPIRV/debug-info/debug-type-enum-unrepresentable.ll
+74-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+67-0llvm/test/CodeGen/SPIRV/debug-info/debug-type-enum-multiple-cu.ll
+19-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+348-05 files

LLVM/project 1b8ac5e — mlir/test/mlir-opt expected-unknown-loc-unmatched.mlir

[nspr] update
DeltaFile
+2-2mlir/test/mlir-opt/expected-unknown-loc-unmatched.mlir
+2-21 files

LLVM/project e322673 — mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp, mlir/test/Dialect/OpenMP cli-canonical_loop-invalid.mlir

[mlir][OpenMP] Diagnose non-loop-transformation uses of omp.new_cli (#235164)

The verifier assumed every user of the CLI implements
LoopTransformationInterface, so it asserted on other operations such as
func.call.

Replaced the cast with dyn_cast so the verifier emits an error pointing
at the invalid use instead, and added a test.

Fixes #234635
DeltaFile
+11-0mlir/test/Dialect/OpenMP/cli-canonical_loop-invalid.mlir
+7-1mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+18-12 files

LLVM/project 8c884ee — libcxx/test/support test_allocator.h

[libcxx][test-support] Implement fancy_pointer_allocator (#196187)

In order to make sure that our further modifications of basic_string
will make it able to handle fancy pointers such as boost::ipc::offset_ptr,
we need some testable fancy pointers. Unfortunately, offset pointers
themselves are a bad idea for that, as they cannot be constant evaluated.

Instead, we are implementing a test fancy pointer that has nontrivial
special member functions that are C++20 constexpr and have side effects
that can be checked on correctness even in constant evaluated test contexts,
backed by a similarly C++20 constexpr fancy pointer allocator.

The idea is that the allocator has a state that counts how many pointer
instances originated from the allocator exist at the moment, the
pointers in their special methods update this shared state, and the
state checks at its destruction that there exactly 0 pointers are recorded
as still existing. The state is unique per instance of default-constructed
allocator but shared between the instances of copy/move-constructed
allocators.

    [10 lines not shown]
DeltaFile
+280-10libcxx/test/support/test_allocator.h
+280-101 files

LLVM/project 6399323 — llvm/lib/Target/AVR AVRCodeGenPassBuilder.cpp AVRTargetMachine.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+144-110llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+82-53llvm/lib/Target/AVR/AVRFrameLowering.cpp
+19-3llvm/lib/Target/AVR/AVR.h
+2-7llvm/lib/Target/AVR/AVRPassRegistry.def
+5-3llvm/lib/Target/AVR/AVRTargetMachine.cpp
+2-2llvm/lib/Target/AVR/AVRCodeGenPassBuilder.cpp
+254-1781 files not shown
+256-1787 files

LLVM/project 86906cb — llvm/lib/Target/AVR AVRPassRegistry.def AVR.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+144-110llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+82-53llvm/lib/Target/AVR/AVRFrameLowering.cpp
+38-0llvm/lib/Target/AVR/AVRAsmPrinter.h
+34-0llvm/lib/Target/AVR/AVRAsmPrinter.cpp
+19-3llvm/lib/Target/AVR/AVR.h
+10-7llvm/lib/Target/AVR/AVRPassRegistry.def
+327-1733 files not shown
+343-1819 files

LLVM/project f161cd3 — llvm/test/CodeGen/AArch64 vec-combine-compare-to-bitmask.ll overflow-vec.ll, llvm/test/CodeGen/AArch64/GlobalISel combine-simplify-demanded-bits-trunc-xor-select.mir

feat(gisel): Mirror trunc/xor/select demanded bits

Extend scalar demanded-bits simplification to G_TRUNC, G_XOR, and
G_SELECT, following SelectionDAG traversal, known-bit propagation,
shared-use handling, and final folds. Honor GISel legality and target
profitability when rewriting or narrowing operations.

Share AArch64's logical-immediate search through a narrow XOR hook and
adapt XOR/shift profitability queries for both selectors. Preserve
SelectionDAG's constant-shrinking interface and node construction.

Share shift-amount validation in CodeGenCommonISel using templated
callbacks for selector-specific lane access and KnownBits queries.

Preserve recursive constant bypasses and use-specific rewrites of shared
producers. Recognize constants at the analysis depth limit, matching
SelectionDAG, and retain KnownBits-based bypasses as a fallback.

Keep G_ASHR of G_SEXT_INREG arithmetic unless the top C + BW - W bits are

    [5 lines not shown]
DeltaFile
+1,302-0llvm/test/CodeGen/AArch64/GlobalISel/combine-simplify-demanded-bits-trunc-xor-select.mir
+509-509llvm/test/CodeGen/AArch64/overflow-vec.ll
+388-390llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+210-314llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+201-222llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+188-191llvm/test/CodeGen/AMDGPU/ds-alignment.ll
+2,798-1,62658 files not shown
+4,529-3,01164 files

LLVM/project 340505d — mlir/lib/Conversion/ReconcileUnrealizedCasts ReconcileUnrealizedCasts.cpp

[mlir] Preserve all analyses in reconcile-unrealized-casts when no casts (#236336)

This lets the pass manager skip the post pass verifier, visible on large
modules

Without casts the pass changes nothing, so re-verifying the whole module
is a waste of time
DeltaFile
+2-0mlir/lib/Conversion/ReconcileUnrealizedCasts/ReconcileUnrealizedCasts.cpp
+2-01 files

LLVM/project c58db52 — llvm/lib/Target/AVR AVRCodeGenPassBuilder.cpp AVRTargetMachine.cpp, llvm/test/CodeGen/AVR newpm-pipeline.ll

[AVR] Port ShiftExpand to NewPM

Standard NewPM pass porting.

Reviewers: arsenm, benshi001

Pull Request: https://github.com/llvm/llvm-project/pull/236253
DeltaFile
+49-38llvm/lib/Target/AVR/AVRShiftExpand.cpp
+9-2llvm/lib/Target/AVR/AVR.h
+6-1llvm/lib/Target/AVR/AVRPassRegistry.def
+2-2llvm/lib/Target/AVR/AVRTargetMachine.cpp
+1-1llvm/lib/Target/AVR/AVRCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/AVR/newpm-pipeline.ll
+68-446 files

LLVM/project 9f2fbe7 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.256bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-mca/AArch64/Cortex A53-neon-instructions.s A510-sve-instructions.s

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+14,649-17,027llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+4,663-5,725llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,624-2,114llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+22-3,412llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
+22-3,412llvm/test/tools/llvm-mca/AArch64/Cortex/A320-sve-instructions.s
+3,151-0llvm/test/tools/llvm-mca/AArch64/Cortex/A53-neon-instructions.s
+24,131-31,690750 files not shown
+56,956-57,360756 files

LLVM/project a27d128 — mlir/lib/Dialect/Shard/IR ShardOps.cpp, mlir/test/Dialect/Shard canonicalization.mlir

[mlir][shard] Fix FoldDuplicateShardOp assertion on duplicates in different blocks (#232953)

`FoldDuplicateShardOp` looks for another `shard.shard` of the same value
and checks `otherOp->isBeforeInBlock(op)` to decide which one is the
duplicate. `isBeforeInBlock` asserts when the two ops are not in the
same block, so a value that is annotated once in the function body and
once inside a region (for example a `linalg.generic` or `scf.if` body)
crashes `--canonicalize`:

```
Operation.cpp:382: bool mlir::Operation::isBeforeInBlock(mlir::Operation *): Assertion `other && other->block == block && "Expected other operation to have the same parent block."' failed.
```

The pattern was written for the same-block duplicates that sharding
propagation produces, so just skip the fold when the other op lives in a
different block. Both annotations stay in place, which is always valid.

Adds a canonicalization test with a duplicate inside an `scf.if` region.


    [2 lines not shown]
DeltaFile
+25-0mlir/test/Dialect/Shard/canonicalization.mlir
+3-1mlir/lib/Dialect/Shard/IR/ShardOps.cpp
+28-12 files

LLVM/project ab0d6e9 — llvm/lib/Transforms/Utils SimplifyIndVar.cpp, llvm/test/Transforms/IndVarSimplify iv-widen-elim-ext.ll

[IndVarSimplify] Use context to prove a narrow IV def non-negative

When IndVars widens an IV, it checks for each narrow def
(the IV and values computed from it) whether it is
non-negative on every iteration.

If it is, zext and sext of it are equal. Then when IndVars
idens the def's users, they can choose to use either
the sext or zext of the def.

Previously, we didn't use context to prove the non-negativity of def.

Now ask SCEV about the def non-negativity at its context -
the def instruction itself.
This allows SCEV to infer facts from the dominating guards and assumes.

This in turn allows eliminating unnecessary truncs/zexts. E.g. in

  if (m > 0)

    [9 lines not shown]
DeltaFile
+18-24llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+2-2llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
+20-262 files

LLVM/project 4ad3d5e — llvm/lib/Target/AVR CMakeLists.txt AVRTargetMachine.h, llvm/test/CodeGen/AVR newpm-pipeline.ll

[AVR] Introduce AVRCodeGenPassBuilder

Mostly mirrors the existing TargetPassConfig. This is for supporting the
NewPM which will eventually replace the LegacyPM.

Reviewers: arsenm, benshi001

Pull Request: https://github.com/llvm/llvm-project/pull/236244
DeltaFile
+96-0llvm/lib/Target/AVR/AVRCodeGenPassBuilder.cpp
+89-0llvm/test/CodeGen/AVR/newpm-pipeline.ll
+28-0llvm/lib/Target/AVR/AVRPassRegistry.def
+8-0llvm/lib/Target/AVR/AVRTargetMachine.h
+1-0llvm/lib/Target/AVR/CMakeLists.txt
+222-05 files

LLVM/project 343690f — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.256bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-mca/AArch64/Cortex A53-neon-instructions.s A510-sve-instructions.s

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+14,649-17,027llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+4,663-5,725llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,624-2,114llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+22-3,412llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
+22-3,412llvm/test/tools/llvm-mca/AArch64/Cortex/A320-sve-instructions.s
+3,151-0llvm/test/tools/llvm-mca/AArch64/Cortex/A53-neon-instructions.s
+24,131-31,690589 files not shown
+50,228-54,995595 files

LLVM/project 77a1494 — llvm/lib/Target/AVR AVR.h AVRPassRegistry.def, llvm/test/CodeGen/AVR newpm-pipeline.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+82-53llvm/lib/Target/AVR/AVRFrameLowering.cpp
+96-0llvm/lib/Target/AVR/AVRCodeGenPassBuilder.cpp
+91-0llvm/test/CodeGen/AVR/newpm-pipeline.ll
+49-38llvm/lib/Target/AVR/AVRShiftExpand.cpp
+33-0llvm/lib/Target/AVR/AVRPassRegistry.def
+19-3llvm/lib/Target/AVR/AVR.h
+370-943 files not shown
+382-979 files

LLVM/project b72d5cf — llvm/lib/Target/AVR AVR.h AVRShiftExpand.cpp, llvm/test/CodeGen/AVR newpm-pipeline.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+144-110llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+82-53llvm/lib/Target/AVR/AVRFrameLowering.cpp
+96-0llvm/lib/Target/AVR/AVRCodeGenPassBuilder.cpp
+92-0llvm/test/CodeGen/AVR/newpm-pipeline.ll
+49-38llvm/lib/Target/AVR/AVRShiftExpand.cpp
+28-5llvm/lib/Target/AVR/AVR.h
+491-2064 files not shown
+535-21110 files

LLVM/project ba09b30 — llvm/lib/Target/AMDGPU SIFrameLowering.h SIFrameLowering.cpp, llvm/test/CodeGen/AMDGPU cfi-fp-copy-to-vcc.ll

[AMDGPU] Fix invalid CFI when a prologue copies a register to a VCC half (#236119)

A prologue can save the frame pointer or base pointer by copying it to
an unused SGPR, and that SGPR can be vcc_lo or vcc_hi. Their DWARF
register numbers, VCC_32_LO (512) and VCC_32_HI (513), are only defined
in wave32, so in wave64 the CFI named registers that do not exist there.
In wave64, describe the copy as a 32-bit lane of VCC_64 instead.

Assissted By: Cursor
DeltaFile
+52-0llvm/test/CodeGen/AMDGPU/cfi-fp-copy-to-vcc.ll
+36-2llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+7-0llvm/lib/Target/AMDGPU/SIFrameLowering.h
+95-23 files

LLVM/project 4fa292b — lldb/source/Target Statistics.cpp

[lldb] Skip debugInfo modules in stats without IncludeModules (#236412)

GetStatistics got every module's symbol file path and debug info modules
unless only a summary was requested.
They arere only reported if the `IncludeModules` option is enabled.
Without `IncludeModules` they were computed and dropped.

Only get them when modules are included.
DeltaFile
+3-1lldb/source/Target/Statistics.cpp
+3-11 files

LLVM/project d7eece8 — offload/liboffload/API Device.td, offload/liboffload/src OffloadImpl.cpp

Revert "[Offload][Omp] Compute getBlockLimit through liboffload" (#236468)

Reverts llvm/llvm-project#236400
DeltaFile
+16-26offload/libompaccsupport/device.cpp
+13-4offload/plugins-nextgen/amdgpu/src/rtl.cpp
+5-7offload/plugins-nextgen/common/include/PluginInterface.h
+0-6offload/liboffload/API/Device.td
+2-4offload/unittests/OffloadAPI/common/Properties.hpp
+0-5offload/liboffload/src/OffloadImpl.cpp
+36-522 files not shown
+36-588 files

LLVM/project 577fd3c — flang/lib/Optimizer/OpenMP DoConcurrentConversion.cpp, flang/test/Transforms/DoConcurrent local_init_multidim.mlir local_init_host.mlir

[flang][OpenMP] Implement LOCAL_INIT support in do concurrent to OpenMP conversion (#234925)

Implement conversion of the Fortran `LOCAL_INIT` locality specifier to OpenMP in the `DoConcurrentConversion` pass. Previously, encountering `LOCAL_INIT` would hit a `TODO` and abort compilation. This PR removes that `TODO` and implements correct per-iteration initialization semantics.

Fortran's `LOCAL_INIT` locality specifier requires that at the start of **each iteration** of a `do concurrent` loop, the private variable is re-initialized from the host (original) variable. The naive approach of mapping this to OpenMP's `firstprivate` (i.e., placing the copy in `omp.private`'s `copy_region`) is incorrect because that would set up the local copy once per thread but not once per iteration as required by `LOCAL_INIT`

The solution in this PR mirrors what `SimplifyFIROperations` already does for the
non-OpenMP path:

1. **Privatizer creation**: `LOCAL_INIT` creates the same `omp.private  {type = private}` as `LOCAL` — with `init` and `dealloc` regions but **no `copy_region`**. This gives each thread its own storage.

2. **Per-iteration copy inlining**: The `fir.local` op's `copy_region`  operations are inlined at the top of the `omp.loop_nest` body, so re-initialization happens every iteration. This is done via a new  `inlineCopyRegionToLoopBody()` helper that clones the copy_region ops one-by-one using an `IRMapping`, substituting the region's block arguments  with the original variable and the private block arg.

The inlining happens in `matchAndRewrite()` after block argument remapping (where stale `fir.do_concurrent.loop` block args are replaced with the final `omp.wsloop`/`omp.parallel` block args), ensuring the correct SSA values are used.


Generated IR (host path)
------------------------


    [21 lines not shown]
DeltaFile
+229-22flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
+104-0flang/test/Transforms/DoConcurrent/local_local_init_reduce.mlir
+89-0flang/test/Transforms/DoConcurrent/local_init_reduce.mlir
+81-0flang/test/Transforms/DoConcurrent/multi_local_init.mlir
+80-0flang/test/Transforms/DoConcurrent/local_init_host.mlir
+74-0flang/test/Transforms/DoConcurrent/local_init_multidim.mlir
+657-225 files not shown
+927-2211 files

LLVM/project 0fcaf83 — llvm/lib/Target/NVPTX NVPTXISelLowering.cpp, llvm/test/CodeGen/NVPTX i32x2-instructions.ll

[NVPTX] add truncating store action for v2i32 to v2i1 (#235390)

expand action for `v2i32` to `v2i1` truncating stores was never set, so
they hit a scalar-only path in `LegalizeStoreOps` and crashed.

added it and the repro as a test.

fixes #235365.
DeltaFile
+44-0llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
+1-0llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+45-02 files

LLVM/project 8f02357 — .github/workflows libcxx-pr-conformance-tests.yaml

[libcxx] [ci] Update the Windows clang-cl configurations to 22.1.8 (#236389)
DeltaFile
+1-1.github/workflows/libcxx-pr-conformance-tests.yaml
+1-11 files

LLVM/project 8549a7b — llvm/lib/Transforms/Vectorize LoopVectorize.cpp

Add assert
DeltaFile
+1-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-01 files

LLVM/project 4d88cae — llvm/lib/Transforms/Utils SimplifyIndVar.cpp, llvm/test/Transforms/IndVarSimplify iv-widen-elim-ext.ll

[IndVarSimplify] Use context to prove a narrow IV def non-negative

When IndVars widens an IV, it checks for each narrow def (the IV and
values computed from it) whether it is non-negative on every iteration.

If it is, zext and sext of it are equal. Then when IndVars widens IV's
users, they can use both the sext and zext of it.

Now ask SCEV about def non-negativity using its context.
This allows it to infer facts from the dominating guards and assumes.

Assisted-By: Claude
DeltaFile
+18-24llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+2-2llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
+20-262 files

LLVM/project 5d49b30 — llvm/test/Transforms/IndVarSimplify iv-widen-elim-ext.ll

[IndVarSimplify][NFC] Add tests for widening non-negative IV users

Add tests for widening provably non-negative IV users.

Assisted-By: Claude
DeltaFile
+372-0llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+372-01 files

LLVM/project 179487d — llvm/test/Analysis/ScalarEvolution max-trip-count-smax-exit-bound.ll, llvm/test/Transforms/IndVarSimplify lftr-smax-exit-bound.ll

[IndVarSimplify][SCEV][NFC] Add tests for LFTR losing the constant max trip count

When IndVars rewrites a loop exit like i >s C, where i starts at a
variable start, to i + 1 == smax(start, C + 1), SCEV's constant max
backedge-taken count of the loop gets worse: C - SINT_MIN before the
rewrite, all ones after it.

Add tests where those counts could be improved.

Assisted-By: Claude
DeltaFile
+60-0llvm/test/Analysis/ScalarEvolution/max-trip-count-smax-exit-bound.ll
+43-0llvm/test/Transforms/IndVarSimplify/lftr-smax-exit-bound.ll
+103-02 files

LLVM/project 7129d40 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Remove ref
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-11 files

LLVM/project fa05ea9 — llvm/test/CodeGen/AArch64 aarch64-dup-ext.ll aarch64-matrix-umull-smull.ll, llvm/test/CodeGen/AMDGPU freeze.ll

fix(gisel): Keep ashr of sext_inreg and update checks

G_TRUNC roots now pass narrowed demand into the G_ASHR case, which turned
ashr(sext_inreg X, W), C into lshr whenever the top C bits were
undemanded. SelectionDAG folds that pair into a single sra by C + BW - W
before the same check, so it keeps the arithmetic shift. Use the folded
amount here too. This keeps AArch64 sbfx selection (neon-dotreduce.ll and
sext.ll no longer churn).

Regenerate the remaining AArch64 and AMDGPU checks affected by the new
TRUNC/XOR/SELECT roots.
DeltaFile
+201-222llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+52-103llvm/test/CodeGen/AArch64/hadd-combine-scalar.ll
+62-62llvm/test/CodeGen/AArch64/combine-sdiv.ll
+21-24llvm/test/CodeGen/AMDGPU/freeze.ll
+20-24llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+12-25llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
+368-46012 files not shown
+433-53018 files

LLVM/project 06ed5b4 — offload/liboffload/API Device.td, offload/liboffload/src OffloadImpl.cpp

[Offload][Omp] Compute getBlockLimit through liboffload (#236400)

Add two new device properties accessible through liboffload:
LAUNCH_MAX_NUM_WORK_GROUPS (max blocks) and LAUNCH_MAX_GRID_SIZE (max
total work-items). Using them compute the getBlockLimit in libomptarget
in a backend agnostic way.

Remove getBlockLimit from the Plugin Interface as it's no longer needed.

Assisted by Claude.
DeltaFile
+26-16offload/libompaccsupport/device.cpp
+4-13offload/plugins-nextgen/amdgpu/src/rtl.cpp
+7-5offload/plugins-nextgen/common/include/PluginInterface.h
+4-2offload/unittests/OffloadAPI/common/Properties.hpp
+6-0offload/liboffload/API/Device.td
+5-0offload/liboffload/src/OffloadImpl.cpp
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