LLVM/project f9c6626llvm/lib/AsmParser Parser.cpp LLParser.cpp, llvm/lib/CodeGen/MIRParser MIRParser.cpp MIParser.cpp

[MIR] Round-trip all machine metadata nodes (#219612)

MIR only emitted definitions for a subset of metadata referenced by
machine
functions. Other nodes were printed as pointer values and could not be
parsed
back.

Collect metadata referenced by machine instructions, memory operands,
and
variable debug information. Keep debug locations inline so the output
remains
readable.

Parse each machine metadata item with LLVM IR's metadata parser while
preserving the YAML item boundaries. This supports specialized nodes,
cycles,
and forward references without accepting definitions split across list
items,
and removes the old tuple-only parser.
DeltaFile
+0-153llvm/lib/CodeGen/MIRParser/MIParser.cpp
+83-0llvm/lib/AsmParser/LLParser.cpp
+49-0llvm/lib/AsmParser/Parser.cpp
+20-18llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+38-0llvm/test/CodeGen/MIR/X86/machine-metadata-specialized.mir
+35-0llvm/test/CodeGen/MIR/X86/machine-metadata-round-trip.mir
+225-17119 files not shown
+348-18725 files

LLVM/project 997e4eeclang/docs LibASTMatchers.md

[docs] Remove stale FIXMEs in LibASTMatchers.md (#219741)

Replace the stale "Introduce link to ASTMatchersTutorial.html" FIXMEs
with a link to the existing LibASTMatchersTutorial, drop the
ASTMatchersCookbook FIXMEs (no cookbook exists), and fix the "macros
(see below)" reference which should point to the AST_MATCHER_P section
above.
DeltaFile
+3-12clang/docs/LibASTMatchers.md
+3-121 files

LLVM/project f95911cllvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU merge-image-load-gfx11.mir merge-image-load-gfx10.mir

[AMDGPU] Reject image load merges with mismatched dim (#219923)

dim was missing from the operand equality check, so loads with different
dim could wrongly get merged into one
DeltaFile
+90-0llvm/test/CodeGen/AMDGPU/merge-image-load-dim.ll
+20-0llvm/test/CodeGen/AMDGPU/merge-image-load-gfx12.mir
+18-0llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
+18-0llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir
+2-1llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+148-15 files

LLVM/project faab176llvm/test/tools/llvm-reduce reduce-flags.ll, llvm/tools/llvm-reduce ReducerWorkItem.cpp

llvm-reduce: Handle the addrspacecast nonnull flag

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+24-0llvm/test/tools/llvm-reduce/reduce-flags.ll
+3-0llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
+3-0llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+30-03 files

LLVM/project 68b22d5llvm/include/llvm/Analysis InstructionSimplify.h, llvm/lib/Analysis InstructionSimplify.cpp

InstSimplify: Fold nonnull addrspacecast of null to poison

Perform the definitional fold if the source value is null
in the default address space.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+69-0llvm/test/Transforms/InstSimplify/addrspacecast-nonnull.ll
+23-0llvm/lib/Analysis/InstructionSimplify.cpp
+4-0llvm/include/llvm/Analysis/InstructionSimplify.h
+96-03 files

LLVM/project ed57bballvm/lib/IR Operator.cpp Instruction.cpp, llvm/test/Transforms/EarlyCSE flags.ll

IR: Intersect and drop the addrspacecast nonnull flag

Teach the flag-propagation controls about the nonnull flag
on addrspacecast.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+44-0llvm/test/Transforms/EarlyCSE/flags.ll
+30-0llvm/test/Transforms/SimplifyCFG/HoistCode.ll
+21-0llvm/unittests/IR/InstructionsTest.cpp
+20-0llvm/lib/IR/Instruction.cpp
+4-0llvm/lib/IR/Operator.cpp
+119-05 files

LLVM/project 0ae5bd6llvm/include/llvm/IR Instructions.h IRBuilder.h, llvm/lib/AsmParser LLParser.cpp

IR: Add nonnull flag to addrspacecast

Introduce the nonnull flag on the addrspacecast instruction,
asserting that the source pointer is not the null value of its
source address space. If the source is the source-address-space null
value, the result is poison.

The LangRef does not yet acknowdlege the existence of non-0 null
pointers, or null pointers for address spaces other than default,
but will "soon".

This gives the target a way to omit the runtime null check to map
between the null values. Currently AMDGPU works around the lack of
this flag by introducing the hacky llvm.amdgcn.addrspacecast.nonnull
intrinsic in a late target codegen pass.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+40-0llvm/test/Transforms/InstCombine/addrspacecast.ll
+19-0llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-addrspacecast.ll
+10-3llvm/include/llvm/IR/IRBuilder.h
+12-0llvm/test/Assembler/flags.ll
+10-0llvm/include/llvm/IR/Instructions.h
+8-1llvm/lib/AsmParser/LLParser.cpp
+99-47 files not shown
+125-713 files

LLVM/project 194b860clang/docs ReleaseNotes.md, clang/include/clang/Basic DiagnosticLexKinds.td DiagnosticGroups.td

Give the __COUNTER__ pedantic diagnostic a group (#218669)

Adding the pedantic diagnostic after supporting the extension for so
long without correctly diagnosing it is disruptive, so this gives folks
a way to disable just the `__COUNTER__` pedantic diagnostic without
losing all other pedantic diagnostics.

Fixes #196557
DeltaFile
+5-0clang/docs/ReleaseNotes.md
+2-1clang/include/clang/Basic/DiagnosticLexKinds.td
+2-1clang/include/clang/Basic/DiagnosticGroups.td
+3-0clang/test/C/C2y/n3457.c
+12-24 files

LLVM/project 8f5e928llvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis DependenceAnalysis.cpp ScalarEvolution.cpp

[SCEV] Make predicates optional in isKnownMultipleOf (NFC) (#219935)

This allows us to simplify some code in DependenceAnalysis, and brings
the routine in line with other SCEV routines.
DeltaFile
+8-5llvm/lib/Analysis/ScalarEvolution.cpp
+5-7llvm/lib/Analysis/DependenceAnalysis.cpp
+3-3llvm/include/llvm/Analysis/ScalarEvolution.h
+16-153 files

LLVM/project ebcd32ellvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Improve code in isKnownPredicate using || (NFC) (#219939)
DeltaFile
+3-8llvm/lib/Analysis/ScalarEvolution.cpp
+3-81 files

LLVM/project e87770allvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Use IsaPred to improve code (NFC) (#219937)
DeltaFile
+3-4llvm/lib/Analysis/ScalarEvolution.cpp
+3-41 files

LLVM/project efbf606clang/lib/AST ASTContext.cpp, llvm/test/CodeGen/LoongArch select-binop-combine.ll

Merge branch 'main' into users/c8ef/generator
DeltaFile
+975-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
+757-0llvm/test/CodeGen/LoongArch/select-binop-combine.ll
+412-316llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+551-0llvm/test/CodeGen/NVPTX/convert-ue5m3x2.ll
+247-288clang/lib/AST/ASTContext.cpp
+461-0llvm/test/Transforms/Attributor/nofpclass-bitcast-int-to-fp.ll
+3,403-604367 files not shown
+9,388-3,611373 files

LLVM/project bc89ca3llvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp

RISCV: Pass instruction and operand index to replacePtrWithInt

The helper used the operand's parent instruction as the insertion point.
Pass the containing instruction and operand index directly so it no longer
depends on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+9-9llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+9-91 files

LLVM/project 25f76c9clang/docs ReleaseNotes.md, clang/lib/Sema SemaLookup.cpp

[clang] Find conversion function templates for in-class specializations (#218316)

Allow redeclaration lookup to consider conversion function templates
allowing Clang to match an in-class specialization such as `template<>
operator int()` against a prior conversion function template
`template<class T> operator T()`.

Fixes #218261
DeltaFile
+18-0clang/test/SemaCXX/conversion-function.cpp
+5-0clang/docs/ReleaseNotes.md
+1-1clang/lib/Sema/SemaLookup.cpp
+24-13 files

LLVM/project cabad35llvm/lib/Target/X86 X86CmovConversion.cpp, llvm/test/CodeGen/X86 select-ext.ll pr15981.ll

[X86] Fix X86CmovConversion sinking volatile loads into conditional branches (#219827)

The `X86CmovConversion` pass unfolds memory operands of `CMOVrm`
instructions and sinks the resulting load into a conditionally executed
basic block. While safe for ordinary loads, doing this for a volatile
load violates the LLVM LangRef since it causes a volatile memory access
to conditionally not execute.

Fix this by not converting with hasOrderedMemoryRef is true.

Fixes #219814
DeltaFile
+15-0llvm/test/CodeGen/X86/cmov-conversion-volatile.ll
+1-4llvm/test/CodeGen/X86/select-ext.ll
+1-4llvm/test/CodeGen/X86/pr15981.ll
+1-1llvm/lib/Target/X86/X86CmovConversion.cpp
+18-94 files

LLVM/project a98a56alibcxx/include/__algorithm ranges_fold.h, libcxx/test/std/algorithms/alg.nonmodifying/alg.fold ranges.fold_right.pass.cpp ranges.fold_left.pass.cpp

[libc++] fix incorrect definition of __indirectly_binary_right_foldable
DeltaFile
+1-5libcxx/include/__algorithm/ranges_fold.h
+6-0libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/ranges.fold_right.pass.cpp
+6-0libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/ranges.fold_left.pass.cpp
+13-53 files

LLVM/project 3c39ff4clang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver hip-cuid.hip amdgpu-xnack-sramecc-flags.c

clang/AMDGPU: Stop passing redundant -target-cpu to cc1

Now that the exact target is encoded in the triple's subarch field,
-target-cpu is redundant. This avoids polluting the resultant IR with
unwanted "target-cpu" attributes. The net result is the desired codegen
when compiling libraries for a major subarch and linking it into a
program compiled for a specific arch. e.g., compiling for "gfx9-generic"
would pollute the IR with "target-cpu"="gfx9-generic", so codegen
would ultimately be performed for the generic target even after
linking into the concrete gfx9 cpu. The specialization will now be
achieved by merging the triples without the linker or optimization
passes needing to fixup function attributes.
DeltaFile
+63-63clang/test/Driver/amdgpu-mcpu.cl
+26-26clang/test/Driver/hip-sanitize-options.hip
+12-16clang/test/Driver/hip-rdc-device-only.hip
+18-8clang/lib/Driver/ToolChains/CommonArgs.cpp
+10-10clang/test/Driver/amdgpu-xnack-sramecc-flags.c
+5-7clang/test/Driver/hip-cuid.hip
+134-13026 files not shown
+189-21032 files

LLVM/project 76080a4llvm/test/TableGen AMDGPUTargetDefSubArchSpelling.td AMDGPUTargetDefErrors.td, llvm/utils/TableGen/Basic AMDGPUTargetDefEmitter.cpp

AMDGPU: Harden assumed subarch triple spelling (#219480)

Guard against values that require multiple hex digits or
don't fit in the IsaVersion struct fields.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+68-2llvm/test/TableGen/AMDGPUTargetDefErrors.td
+23-10llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+12-1llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
+103-133 files

LLVM/project 5d702abllvm/test/CodeGen/AMDGPU scalar-float-sop1.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.buffer.store.format.f16.ll fma.bf16.ll

AMDGPU/GlobalISel: Bitcasting G_TRUNC combine

Creating the G_TRUNC that changes type as well. This is really
the LLT::scalar trunc style that we inherited from switching to
extended LLTs, very common on non-true16 targets.
Affects inst-select pattern matching that were blocked by bitcast.
DeltaFile
+99-115llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+65-139llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll
+6-22llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
+10-12llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
+6-10llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll
+5-9llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
+191-3078 files not shown
+216-34314 files

LLVM/project 291f1ebllvm/test/CodeGen/AMDGPU load-atomic-flat.ll dagcombine-fmul-sel.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshr.ll fptrunc.bf16.ll

AMDGPU/GlobalISel: Fold (trunc (lshr x, 16)) to unmerge high half

Huge performance impact in some shaders with high register pressure.
What this really does is selects _hi16 register classes, and true16
machinery takes over later. Trunc + shift ends up in _lo16!
This requires allocating an extra register when the _lo16 half of the
original real 32-bit VGPR is still live.
DeltaFile
+566-304llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
+558-300llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
+387-222llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+275-158llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll
+231-126llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
+180-132llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+2,197-1,24223 files not shown
+3,188-2,28929 files

LLVM/project 0b0f86dlibc/test/src/math/smoke fabsf128_test.cpp copysignf128_test.cpp

nits
DeltaFile
+2-2libc/test/src/math/smoke/CMakeLists.txt
+1-1libc/test/src/math/smoke/fabsf128_test.cpp
+1-1libc/test/src/math/smoke/copysignf128_test.cpp
+4-43 files

LLVM/project 36d4f5alibcxx/test/libcxx/transitive_includes cxx29.csv

cxx29 transitive include
DeltaFile
+9-0libcxx/test/libcxx/transitive_includes/cxx29.csv
+9-01 files

LLVM/project 7ae1befmlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp, mlir/lib/Dialect/LLVMIR/IR LLVMDialect.cpp

[mlir][LLVM] Tighten the constant verifier's attr and res type match check (#218887)

`llvm.mlir.constant` only checked that the kind of the value attribute
suits the kind of the result type, never that the types themselves
agree. All of the following verified:

```
%0 = llvm.mlir.constant(1 : index) : i64
%1 = llvm.mlir.constant(1 : i8) : i16
%2 = llvm.mlir.constant(dense<1> : vector<4xi32>) : vector<4xi64>
```

Translation ignores the attribute type and uses the result type, so the
attribute type was effectively decorative for integers, and passes that
read it back could observe a type that has nothing to do with the value.

Require exact type equality for integer attributes and exact element
type equality for integer elements attributes, mirroring the
`AllTypesMatch` constraint `arith.constant` gets from ODS. The op cannot

    [15 lines not shown]
DeltaFile
+56-0mlir/test/Dialect/LLVMIR/invalid.mlir
+42-11mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+12-12mlir/test/Dialect/LLVMIR/roundtrip.mlir
+23-0mlir/test/Conversion/ArithToLLVM/constant-index-bitwidth.mlir
+11-4mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+7-7mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+151-3414 files not shown
+181-6020 files

LLVM/project 5e0390bllvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU merge-s-load.mir

[AMDGPU] Fix XNACK alignment check in SILoadStoreOptimizer merges (#219886)

Alignment of a merged scalar load depends on the lower offset load, not
whichever load comes first in program order, so checking the first load
could miss cases needing the constrained opcode
DeltaFile
+44-0llvm/test/CodeGen/AMDGPU/merge-s-load.mir
+5-12llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+49-122 files

LLVM/project 57c3212llvm/test/TableGen RuntimeLibcallEmitter.td, llvm/utils/TableGen/Basic RuntimeLibcalls.h RuntimeLibcalls.cpp

RuntimeLibcalls: Remove the dead IsDefault emitter machinery

The IsDefault bit on RuntimeLibcallImpl fed a LibCallToDefaultImpl map in the
TableGen backend that was populated but never read.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+4-7llvm/test/TableGen/RuntimeLibcallEmitter.td
+0-8llvm/utils/TableGen/Basic/RuntimeLibcalls.cpp
+0-5llvm/utils/TableGen/Basic/RuntimeLibcalls.h
+4-203 files

LLVM/project 3c25c42llvm/include/llvm/IR RuntimeLibcalls.h RuntimeLibcallsImpl.td, llvm/test/TableGen RuntimeLibcallEmitter-library-ref.td

RuntimeLibcalls: Add LibraryRef for dispatch-with-exclusion

Let a SystemRuntimeLibrary dispatch a shared provider library while dropping the
impls the target replaces, since a library reference cannot nest inside (sub ...).
This is a compromise from the ideal of explicitly listing all calls, but getting
to that point is prooving to be difficult.

The opt-out is emitted inside setAvailableLibFuncs_<lib>, so the single library's
logic is self contained.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+89-18llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+53-0llvm/test/TableGen/RuntimeLibcallEmitter-library-ref.td
+8-0llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+4-0llvm/include/llvm/IR/RuntimeLibcalls.h
+154-184 files

LLVM/project f09322ellvm/test/TableGen RuntimeLibcallEmitter-library-dispatch.td, llvm/utils/TableGen/Basic RuntimeLibcallsEmitter.cpp

RuntimeLibcalls: Dispatch to library functions from SystemRuntimeLibrary

When a SystemRuntimeLibrary names LibcallLibrary defs, setTargetRuntimeLibcallSets
now dispatches each under an isLibraryAvailable guard, so an impl can be homed
into a library without dropping it from the target. Non-library members keep the
inline path. No target names a library yet, so output is unchanged.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+52-0llvm/test/TableGen/RuntimeLibcallEmitter-library-dispatch.td
+39-2llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+91-22 files

LLVM/project 1504d80clang/docs ReleaseNotes.md, clang/lib/Sema SemaOverload.cpp

  [Clang] Fix wording of ref-qualifier overload diagnostic (#219905)

When a member function is redeclared with a conflicting ref-qualifier,
  the diagnostic described the new declaration before the previous
  declaration, which read in the opposite order from the source. For
  example,

    struct C { void f(); };
    void C::f() & {}

  previously produced:

cannot overload a member function with ref-qualifier '&' with a member
    function without a ref-qualifier

  Swap the two qualifier descriptions so the previous declaration is
  described first, matching source order:

cannot overload a member function without a ref-qualifier with a member

    [2 lines not shown]
DeltaFile
+3-3clang/test/CXX/over/over.load/p2-0x.cpp
+3-3clang/test/CXX/drs/cwg24xx.cpp
+2-2clang/test/CXX/drs/cwg5xx.cpp
+4-0clang/docs/ReleaseNotes.md
+1-1clang/test/SemaCXX/cxx1y-contextual-conversion-tweaks.cpp
+1-1clang/lib/Sema/SemaOverload.cpp
+14-106 files

LLVM/project 4f3e99allvm/include/llvm/IR Instructions.h, llvm/lib/AsmParser LLParser.cpp

[IR] `select` should reject token-like types

Target extension types with the IsTokenLike property are meant to behave like
tokens. The change in #154620 already rejected such types in phi nodes, function
arguments, function return types and call parameters. Added this missing check
in SelectInst::areInvalidOperands().

Also refactored PHINode to follow the same pattern, so that the token type is
checked in the constructor, LLParser and Verifier.

Some DirectX lit tests deliberately use token-like types in Phi or Select
instructions, while disabling the verifier. This change breaks all of them
because the check is in more places than just the verifier.

Assisted-By: AI Code Assistant

wip
DeltaFile
+9-1llvm/lib/IR/Instructions.cpp
+9-0llvm/test/Verifier/tokenlike2.ll
+5-0llvm/include/llvm/IR/Instructions.h
+2-1llvm/lib/IR/Verifier.cpp
+3-0llvm/lib/AsmParser/LLParser.cpp
+28-25 files

LLVM/project 08eb97dclang/lib/Serialization ASTReaderDecl.cpp, clang/test/Modules pr219639.cppm

[C++20] [Modules] Correct the redecl chain (#219926)

Close https://github.com/llvm/llvm-project/issues/219639

The root cause of the problem is the incorrect redecl chain.

A valid redecl chain should be a circle where each decl refers to the
previous one and the first decl refers to the most recent decl (latest
one). However, in the example, the redecl chain became to:

D2 -> D1 -> D1 ....

so that the range of `for (... : D->redecls())` never ends.

The real cause of the issue is we didn't merge correctly in the
ASTReader. Previous code assumes about the most recent decl while the
new code makes the behavior more clearly.
DeltaFile
+45-0clang/test/Modules/pr219639.cppm
+8-7clang/lib/Serialization/ASTReaderDecl.cpp
+53-72 files