LLVM/project dbbd4e0llvm/docs LangRef.md

[LangRef] select: describe behavior for undef and poison (#208724)

The poison semantics is based on
https://llvm.org/docs/UndefinedBehavior.html#propagation-of-poison-through-select.
IMO this definitely should appear in the "semantics" section of the
`select` instruction. If this isn't part of the `select` semantics I
don't know what is.

The undef semantics are based on what Alive does.
DeltaFile
+2-1llvm/docs/LangRef.md
+2-11 files

LLVM/project 272e691llvm/include/llvm/Analysis CGSCCPassManager.h, llvm/include/llvm/CodeGen MachinePassManager.h

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+83-40llvm/include/llvm/IR/PassManagerInternal.h
+9-9llvm/include/llvm/Analysis/CGSCCPassManager.h
+9-9llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
+5-5llvm/include/llvm/IR/PassManager.h
+3-4llvm/include/llvm/CodeGen/MachinePassManager.h
+109-675 files

LLVM/project add1925llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

[AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 2) (#207199)

This simplifies the logic a bit more, such that the flow of the lowering
is as follows:
* Try to promote if necessary (fp16/bf16 types or src < dst)
* Try to handle natively (satwidth == srcwidth == dstwidth)
* Otherwise use min/max + truncate.
DeltaFile
+68-45llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+68-451 files

LLVM/project 922b1a9llvm/cmake/modules FindDIASDK.cmake

Revert "[cmake] Fix VSINSTALLDIR check in FindDIASDK module (#208524)" (#209137)

This reverts commit 4c5e15667fe384e434961fe44cf5950dc309fdf1.

https://github.com/llvm/llvm-project/pull/208524 fixed a flag which
enabled testing with the DIA SDK. This broke all Windows build bots,
because the SDK is not available in the PATH.
DeltaFile
+1-1llvm/cmake/modules/FindDIASDK.cmake
+1-11 files

LLVM/project 37d488fllvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination induction-condition-in-loop-exit.ll loops-header-tested-pointer-cmps.ll

[ConstraintElim] Look through post-increment in header EQ/NE compare. (#209199)

Extend the header-controlled induction handling to look through a
post-increment `PN + C` (constant C) on the compared value

For now, the new path is limited to deriving unsigned facts.

Alive2 Proof: https://alive2.llvm.org/ce/z/DCNeSr

PR: https://github.com/llvm/llvm-project/pull/209199
DeltaFile
+311-0llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
+37-11llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+2-2llvm/test/Transforms/ConstraintElimination/loops-header-tested-pointer-cmps.ll
+350-133 files

LLVM/project 6a1f23allvm/include/llvm/CodeGen UnreachableBlockElim.h, llvm/include/llvm/Transforms/Scalar StructurizeCFG.h

[NPM] Make few more passes required (#203511)

essentially a port of https://github.com/llvm/llvm-project/pull/148115.
matches legacy behaviour. MachineBlockPlacement is made optional since
it is optional in legacy as well. not sure if there was any reason to
make it required in NPM.
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/include/llvm/CodeGen/UnreachableBlockElim.h
+1-1llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
+1-1llvm/include/llvm/Transforms/Utils/UnifyLoopExits.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.h
+10-1014 files not shown
+24-2420 files

LLVM/project d4568c9mlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp

[mlir][SPIR-V] Collapse TanPattern/TanhPattern into DirectConversionPattern (#203830)
DeltaFile
+3-37mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+3-371 files

LLVM/project cca525dclang/test/OffloadTools/clang-linker-wrapper linker-wrapper.c, clang/tools/clang-linker-wrapper ClangLinkerWrapper.cpp

Revert "clang-linker-wrapper: Use AMDGPU::TargetID for device-image compatibi…"

This reverts commit dc1273beba1c70cb74d03c760958ee625d8aecf5.
DeltaFile
+35-49llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+0-57clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
+0-48llvm/unittests/TargetParser/TargetParserTest.cpp
+22-17llvm/lib/Object/OffloadBinary.cpp
+0-8llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+2-1clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+59-1806 files

LLVM/project 08dbc4dllvm/utils/lit/lit cl_arguments.py

Remove new line.
DeltaFile
+0-1llvm/utils/lit/lit/cl_arguments.py
+0-11 files

LLVM/project 830f878llvm/utils/lit/lit cl_arguments.py, llvm/utils/lit/tests time-tests.py

[review] Improved parsing check.
DeltaFile
+8-6llvm/utils/lit/lit/cl_arguments.py
+6-0llvm/utils/lit/tests/time-tests.py
+14-62 files

LLVM/project 27f1060llvm/utils/lit/lit main.py

[reviews] Revert non-required change.
DeltaFile
+1-1llvm/utils/lit/lit/main.py
+1-11 files

LLVM/project 7904262llvm/docs/CommandGuide lit.rst, llvm/utils/lit/lit cl_arguments.py util.py

[lit] Add configurable slowest-test limit to --time-tests

Bare --time-tests still defaults to 20; --time-tests=N and --time-tests=all optionally control the slowest-test list shown in the histogram.
DeltaFile
+40-6llvm/utils/lit/tests/time-tests.py
+43-2llvm/utils/lit/lit/cl_arguments.py
+9-4llvm/utils/lit/lit/util.py
+7-3llvm/docs/CommandGuide/lit.rst
+4-4llvm/utils/lit/lit/main.py
+1-0llvm/utils/lit/tests/Inputs/time-tests/b.txt
+104-191 files not shown
+105-197 files

LLVM/project d21d602llvm/include/llvm/Analysis ModuleSummaryAnalysis.h, llvm/lib/Analysis StackSafetyAnalysis.cpp ModuleSummaryAnalysis.cpp

[NPM] Port ImmutableModuleSummaryAnalysis to NPM (#203510)

Required in LTO pipelines
DeltaFile
+29-0llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
+5-2llvm/lib/Analysis/StackSafetyAnalysis.cpp
+2-0llvm/lib/Passes/PassRegistry.def
+1-0llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
+37-24 files

LLVM/project a31c941llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU expand-mov-b64-globaladdr.ll expand-mov-b64-globaladdr-hsa.ll

[AMDGPU] Support global address in V/S_MOV_B64 lowering (#203527)

Hit an issue where V_MOV_B64_PSEUDO had a global, which wasn't
previously handled.
Added support for this, and also for the S_MOV_B64_IMM_PSEUDO to make it
symmetrical.

Claude has been used for this commit, primarily assisting creating a
test.
DeltaFile
+95-0llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
+71-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+48-0llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
+27-0llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
+241-24 files

LLVM/project 771c9eallvm/lib/Analysis ScalarEvolutionDivision.cpp

[SCEVDivision] Add assertion to check operand types match
DeltaFile
+2-0llvm/lib/Analysis/ScalarEvolutionDivision.cpp
+2-01 files

LLVM/project b82e75dllvm/lib/Analysis ScalarEvolutionDivision.cpp

[SCEVDivision] Remove unnecessary integer promotion (NFCI)
DeltaFile
+2-7llvm/lib/Analysis/ScalarEvolutionDivision.cpp
+2-71 files

LLVM/project 7c15144llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp SelectionDAGBuilder.h, llvm/test/CodeGen/X86 type-tests-must-be-lowered.ll pr142937.ll

[SDAG] emit error when `llvm.type.checked.load` is not lowered (#208058)

Fixes https://github.com/llvm/llvm-project/issues/164663

In rust we can enable devirtualization and LTO on a build that actually
builds a library and hence LTO does not really run. That means typed
loads are emitted, but they are not lowered (or cleaned up), which made
us hit an ICE. Giving a slightly better error message, analogous to the
existing one for `Intrinsic::type_test`, seems nice.

I'm putting this together based on
https://github.com/llvm/llvm-project/pull/179249 and
https://github.com/llvm/llvm-project/issues/164663#issuecomment-3433581033.
DeltaFile
+46-0llvm/test/CodeGen/X86/type-tests-must-be-lowered.ll
+31-11llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+0-33llvm/test/CodeGen/X86/pr142937.ll
+2-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+79-444 files

LLVM/project 00bf3d6utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc BUILD.bazel

[Bazel] Fixes 1bd4601 (#209377)

This fixes 1bd46015ea4e842091109cd2a491c55c0b455330.

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=1bd46015ea4e842091109cd2a491c55c0b455330

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-2utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
+2-21 files

LLVM/project c9610acllvm/lib/Target/CSKY/MCTargetDesc CSKYTargetStreamer.h

[CSKY] Fix build without PCH (#209405)
DeltaFile
+1-0llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
+1-01 files

LLVM/project 7401694llvm/docs AMDGPUUsage.rst, llvm/lib/IR Verifier.cpp

[AMDGPU] Add threshold for DPP atomic optimizer on LDS atomics (#186762)

Add amdgpu.expected.active.lane metadata which can be applied to operations by a 
compiler front-end.  Do not apply the DPP atomic optimizer to LDS atomics where
less than five active lanes are expected.
This is an empirically derived threshold based on GFX11 and GFX12 testing.

---------

Co-authored-by: YaFan <YaFan.Tao at amd.com>
DeltaFile
+1,147-0llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
+26-6llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
+30-0llvm/test/Verifier/amdgpu-expected-active-lanes.ll
+22-0llvm/docs/AMDGPUUsage.rst
+11-0llvm/lib/IR/Verifier.cpp
+1,236-65 files

LLVM/project d9798b2llvm/docs LangRef.md

More details, as suggested by Ralf

Co-authored-by: Ralf Jung <post at ralfj.de>
DeltaFile
+4-2llvm/docs/LangRef.md
+4-21 files

LLVM/project afac946llvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/test/CodeGen/AArch64/GlobalISel combine-insert-vec-elt.mir

[GlobalISel] Fix crash in matchCombineInsertVecElts with INLINEASM-de… (#208225)

…fined base

matchCombineInsertVecElts walks the G_INSERT_VECTOR_ELT chain by
following operand 0 of the source-defining instruction. When the base
vector is defined by INLINEASM, operand 0 is the asm string (not a
register), so calling getReg() triggers an assertion:

  Assertion `isReg() && "This is not a register operand!"' failed.

Fix by using the mi_match overload that takes a MachineInstr instead of
a Register, which checks the instruction opcode before accessing any
operands.
DeltaFile
+25-0llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
+1-1llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+26-12 files

LLVM/project 5566c87clang/lib/CodeGen CGBuiltin.cpp, clang/test/CodeGen builtins.c

[Clang] Fix boolean vector bit counting on big-endian targets (#209146)

`__builtin_ctzg` and `__builtin_clzg` (count leading/trailing zeroes)
can accept boolean vectors as arguments. In this case, they operate in
logical vector lane order. However, `EmitBitCountExpr`, used to generate
the argument to those builtins, bitcasts boolean vectors directly to
integer bitfields, whose bit order is reversed on big-endian targets.

This caused libc's SIMD `find_first_set` and `find_last_set` helpers to
count lanes from the wrong end in big-endian mode. But the issue was
general and could affect any user.

This patch normalizes the integer representation with `llvm.bitreverse`
on big-endian targets before emitting bit-count intrinsics. On top of
that, the codegen test has been refactored to run on more targets and to
cover big-endian mode as well.

As a side effect of this change, and because of the way the code is
structured, the bit reverse operation also happens for

    [7 lines not shown]
DeltaFile
+277-241clang/test/CodeGen/builtins.c
+8-0clang/lib/CodeGen/CGBuiltin.cpp
+285-2412 files

LLVM/project dad3e30llvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Fix incorrect rematerialization rollback order (#197576)

This fixes an issue in the rematerializer's rollbacker wherein adjacent
MIs that were deleted through rematerializations would
sometimes---depending on the exact order in which they were
deleted---not be re-created in their original pre-rematerialization
order. While this does not impact correctness (i.e., use-def relations
are always honored), this goes against the rollbacker's intent to
re-create the MIR exactly as it was pre-rematerializations (up to slot
index changes).
DeltaFile
+128-23llvm/unittests/CodeGen/RematerializerTest.cpp
+96-50llvm/lib/CodeGen/Rematerializer.cpp
+60-37llvm/include/llvm/CodeGen/Rematerializer.h
+284-1103 files

LLVM/project f195f4dlldb/bindings/interface SBTargetDocstrings.i, lldb/docs/use tutorial.md

[lldb] Add comma separator in watchpoint description (#209176)

I find it easier to read this way, especially the last "state = enabled type = m" which looks like "enabled type = m" at a glance:
Watchpoint 1: addr = 0xaaaaaaab1018 size = 20 state = enabled type = m

With commas:
Watchpoint 1: addr = 0xaaaaaaab1018, size = 20, state = enabled, type = m

Code breakpoints include commas already:
1: name = 'main', locations = 1, resolved = 1, hit count = 1
1.1: where = test.o`main at test.c:13:15, address = 0x0000aaaaaaaa0714, resolved, hit count = 1

Used the regex "Watchpoint [0-9]+:" to find tests and docs that needed
updating.
DeltaFile
+4-4lldb/test/Shell/Register/x86-db-read.test
+3-3lldb/docs/use/tutorial.md
+1-1lldb/source/Breakpoint/Watchpoint.cpp
+1-1lldb/bindings/interface/SBTargetDocstrings.i
+9-94 files

LLVM/project 534f037llvm/docs LangRef.md

[LangRef] State that the memory model is an axiomatic one

Currently, one could read large parts of the memory model without learning for
sure whether it is meant as an operational model that describes how individual
operations change some notion of state or if it is an axiomatic model (like the
C++ memory model) that lists constraints that a candidate execution must
satisfy to be allowed.

While the description of what a read returns sounds somewhat operational,
aspects like the definition of fence instructions, the monotonic modification
order, and the total order of sequentially consistent operations place it in
the realm of axiomatic models.

This is an attempt to make the nature of the model more explicit (and maybe a
place to discuss the nature of the model), as suggested by RalfJung in the
reviews for #204329.
DeltaFile
+2-0llvm/docs/LangRef.md
+2-01 files

LLVM/project e635600clang/include/clang/Basic DiagnosticSemaKinds.td Attr.td, clang/lib/Sema SemaAMDGPU.cpp SemaDeclCXX.cpp

Use C++ standard layout instead
DeltaFile
+60-38clang/lib/Sema/SemaAMDGPU.cpp
+38-10clang/test/SemaHIP/amdgpu-barrier.hip
+37-10clang/test/SemaCXX/amdgpu-barrier.cpp
+0-13clang/lib/Sema/SemaDeclCXX.cpp
+7-4clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-1clang/include/clang/Basic/Attr.td
+143-761 files not shown
+144-777 files

LLVM/project d1aa304clang/lib/AST Type.cpp TypePrinter.cpp, clang/lib/Basic/Targets SPIR.h

Address Comments
DeltaFile
+4-3clang/lib/AST/Type.cpp
+3-2clang/test/SemaOpenCL/amdgpu-barrier.cl
+1-4clang/lib/CodeGen/CodeGenModule.cpp
+2-2clang/lib/Basic/Targets/SPIR.h
+4-0clang/test/SemaCXX/amdgpu-barrier.cpp
+2-2clang/lib/AST/TypePrinter.cpp
+16-1311 files not shown
+29-2317 files

LLVM/project d6c5e95clang/lib/AST Type.cpp, clang/lib/CodeGen CodeGenModule.cpp

[clang][AMDGPU] Clean-up handling of named barrier type

- Do not allow the type in struct fields. This is more like a handle/resource than a real type. It does not follow the traditional C++ object model, and using it in a struct field can do some weird things if you instantiate too many of them.
- Use a `hip_barrier` LangAS for this type that currently maps to the local AS. This allows easy switching to the barrier AS in a future patch.

Alternative to #195612, see also #195613
DeltaFile
+23-14clang/test/CodeGenHIP/amdgpu-barrier-type.hip
+13-1clang/lib/AST/Type.cpp
+9-1clang/lib/Sema/SemaDecl.cpp
+6-0clang/lib/CodeGen/CodeGenModule.cpp
+5-0clang/test/SemaOpenCL/amdgpu-barrier.cl
+5-0clang/test/SemaHIP/amdgpu-barrier.hip
+61-1616 files not shown
+89-2022 files

LLVM/project 52244d5clang/test/SemaCXX amdgpu-barrier.cpp, clang/test/SemaOpenCL amdgpu-barrier.cl

Add RUN lines to check Sema check works if AMDGCN is aux target
DeltaFile
+1-0clang/test/SemaOpenCL/amdgpu-barrier.cl
+1-0clang/test/SemaCXX/amdgpu-barrier.cpp
+2-02 files