LLVM/project edff199 — llvm/lib/Transforms/IPO IPOOptions.td Instrumentor.cpp

[IPO] Declare Instrumentor.cpp command line options in TableGen (#240199)
DeltaFile
+11-21llvm/lib/Transforms/IPO/Instrumentor.cpp
+6-0llvm/lib/Transforms/IPO/IPOOptions.td
+17-212 files

LLVM/project a89b4c5 — llvm/lib/Target/M68k M68kSubtarget.cpp M68kSubtarget.h, llvm/lib/Target/M68k/AsmParser M68kAsmParser.cpp

[M68k] Declare command line options in TableGen (#240195)

Move -m68k-use-base-pointer into M68kOptions.td and
-m68k-register-prefix-optional into MCTargetDesc/M68kMCOptions.td.
M68kTargetMachine holds `const M68kOptions &CLOpts`, and M68kSubtarget
copies it; M68kAsmParser holds `const M68kMCOptions &CLOpts`.

Delete the unused -m68k-ssection-threshold.
DeltaFile
+23-0llvm/lib/Target/M68k/MCTargetDesc/M68kMCOptions.h
+14-0llvm/lib/Target/M68k/M68kOptions.td
+14-0llvm/lib/Target/M68k/MCTargetDesc/M68kMCOptions.td
+6-7llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+6-3llvm/lib/Target/M68k/M68kSubtarget.h
+5-3llvm/lib/Target/M68k/M68kSubtarget.cpp
+68-137 files not shown
+90-2613 files

LLVM/project 932d5ec — llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen TargetLoweringBase.cpp

TargetLowering: Take libcall info from analysis (#240181)

Pass in LibcallLoweringInfo to getDefaultSafeStackPointerLocation
instead of relying on TargetLoweriing's static copy which will
eventually be removed.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+4-4llvm/lib/CodeGen/TargetLoweringBase.cpp
+1-0llvm/include/llvm/CodeGen/TargetLowering.h
+5-42 files

LLVM/project 5878ac4 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU store.ll load.ll

[AMDGPU] Price misaligned flat and LDS accesses with the LDS misaligned bug

In WGP mode on subtargets with the LDS misaligned bug, a flat access is
split into pieces no wider than its alignment and no narrower than 4
bytes, and an LDS access aligned below 4 bytes uses 8-byte pieces as one
aligned to 4 does.
DeltaFile
+121-60llvm/test/Analysis/CostModel/AMDGPU/store.ll
+121-60llvm/test/Analysis/CostModel/AMDGPU/load.ll
+4-1llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+246-1213 files

LLVM/project cb118cf — llvm/lib/Target/AMDGPU AMDGPULowerBufferFatPointers.cpp AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU store.ll load.ll

apply comments
DeltaFile
+354-0llvm/test/Analysis/CostModel/AMDGPU/buffer-fat-pointer-oob-mode.ll
+21-1llvm/test/Analysis/CostModel/AMDGPU/store.ll
+21-1llvm/test/Analysis/CostModel/AMDGPU/load.ll
+8-4llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+3-3llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+407-95 files

LLVM/project 5f73864 — llvm/lib/Target/AMDGPU AMDGPU.h AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU store.ll load.ll

[AMDGPU] Price buffer fat pointer memory operations

Price buffer fat pointer accesses as global accesses, except that an
aligned load is not widened and a vector of odd width elements is not
split element by element. Without relaxed buffer bounds checking, a
vector of elements that are a multiple of 32 bits wide is accessed in
pieces no wider than its alignment and no narrower than 4 bytes, and a
vector of other byte-sized or power of 2 wide elements in pieces of the
largest power of 2 bytes that divides the element size. The width comes
from buffer fat pointer lowering, which now exposes it. When the pointer
is a buffer resource plus a constant offset, the offset and a constant
number of records give the same bounds facts lowering uses to access it
in wider pieces.
DeltaFile
+38-35llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+51-20llvm/test/Analysis/CostModel/AMDGPU/store.ll
+51-20llvm/test/Analysis/CostModel/AMDGPU/load.ll
+56-14llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+9-0llvm/lib/Target/AMDGPU/AMDGPU.h
+205-895 files

LLVM/project d6f5131 — llvm/test/Analysis/CostModel/AMDGPU store.ll load.ll

[NFC][AMDGPU] Precommit buffer fat pointer and gfx1010 memory cost tests
DeltaFile
+294-0llvm/test/Analysis/CostModel/AMDGPU/load.ll
+235-0llvm/test/Analysis/CostModel/AMDGPU/store.ll
+529-02 files

LLVM/project a0ae5f7 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU load.ll

[AMDGPU] Price constant address space memory operations

Price constant address space accesses as global accesses, except for
loads selected to scalar loads of up to 64 bytes. These are loads from
the 32-bit constant address space, and loads from the constant address
space whose pointer is an argument passed in SGPRs or a constant, plus
constant offsets, both aligned to 4 bytes or to their size. A scalar
load is widened as its lowering does. An integer whose size is not a
multiple of 4 bytes is loaded as whole dwords, plus a byte load when its
size is 7 modulo 8, since the last byte of such a remainder is left out
of the scalar load. A type with no legal dword vector equivalent is
split into the largest power of 2 pieces that fit, and once the
remainder fits in the alignment it is widened to a power of 2 piece of
up to the alignment, at most 8 bytes for byte vectors. A 3-dword
remainder of a legal dword vector takes a fourth dword when aligned to 8
on a subtarget without scalar dwordx3 loads.
DeltaFile
+162-37llvm/test/Analysis/CostModel/AMDGPU/load.ll
+121-71llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll
+56-4llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+339-1123 files

LLVM/project 2ad5b0e — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.h AMDGPUTargetTransformInfo.cpp

Use isSourceOfDivergence in hasUniformPointerOperand
DeltaFile
+3-6llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+2-0llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+5-62 files

LLVM/project 865d348 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.h AMDGPUTargetTransformInfo.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

move uniform helper
DeltaFile
+5-22llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+20-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+15-0llvm/test/Analysis/CostModel/AMDGPU/load.ll
+7-5llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+0-2llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+53-296 files

LLVM/project 76be008 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU load.ll

small changes
DeltaFile
+22-12llvm/test/Analysis/CostModel/AMDGPU/load.ll
+16-10llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+38-222 files

LLVM/project c859550 — llvm/include/llvm/Support MemoryBuffer.h, llvm/lib/Support/Unix Path.inc

[Support] Make dontNeedIfMmap actually release pages on Linux (#240071)

https://reviews.llvm.org/D116366 added `dontNeedIfMmap` for lld/ELF LTO
memory saving (used on read-only maps) https://reviews.llvm.org/D116367.
D119856 (b66b3247f598) switched to posix_madvise to fix the Illumos
build, which made `dontNeedIfMmap` a no-op on Linux, both glibc and
musl.

(glibc and musl return 0 for POSIX_MADV_DONTNEED without calling
`madvise`, because POSIX requires posix_madvise not to change the
semantics of memory access, while Linux's MADV_DONTNEED discards data
(which is acceptable for the read-only map use case).

Other systems treat MADV_DONTNEED as a hint. On macOS 26, a 512 MiB
read-only file mapping stays resident after madvise or posix_madvise;
only the next access is slower.

Call madvise on Linux only, restoring the RSS reduction. Make
dontNeedIfMmap a no-op elsewhere.
DeltaFile
+4-5llvm/lib/Support/Unix/Path.inc
+1-1llvm/include/llvm/Support/MemoryBuffer.h
+5-62 files

LLVM/project 2121945 — llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/lib/Target/X86 ImmutableGraph.h

[Target][NFC] Remove unneeded typename in type aliases (#239934)

Remove some unneeded `typename` keywords in type aliases.
Similar to #166087.
DeltaFile
+2-2llvm/lib/Target/X86/ImmutableGraph.h
+1-1llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+3-32 files

LLVM/project 1076b0b — llvm/lib/Transforms/Vectorize VPlanUtils.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize outer-loop-bitextract.ll bitextract-bitinsert.ll

[LV] Widen `bitextract` and `bitinsert`
DeltaFile
+306-0llvm/test/Transforms/LoopVectorize/bitextract-bitinsert.ll
+134-0llvm/test/Transforms/LoopVectorize/X86/bitextract-bitinsert-cost.ll
+95-0llvm/test/Transforms/LoopVectorize/outer-loop-bitextract.ll
+42-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+18-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+2-0llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+597-16 files

LLVM/project 6adf1ba — llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlan.h

[VPlan] Share the result-type helper of `VPReplicateRecipe` with `VPWidenRecipe` (NFC)
DeltaFile
+29-20llvm/lib/Transforms/Vectorize/VPlan.h
+2-2llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+31-222 files

LLVM/project 6bcf765 — llvm/include/llvm/Analysis TargetTransformInfo.h TargetTransformInfoImpl.h, llvm/include/llvm/CodeGen BasicTTIImpl.h

[TTI] Cost `bitinsert` and `bitextract` by their lowering
DeltaFile
+26-26llvm/test/Analysis/CostModel/X86/bitinsert-bitextract.ll
+43-0llvm/include/llvm/CodeGen/BasicTTIImpl.h
+20-0llvm/lib/Analysis/TargetTransformInfo.cpp
+20-0llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+12-0llvm/include/llvm/Analysis/TargetTransformInfo.h
+121-265 files

LLVM/project 4d73964 — llvm/test/Analysis/CostModel/X86 bitinsert-bitextract.ll

[TTI] Pre-commit tests for `bitinsert` and `bitextract` costs
DeltaFile
+74-0llvm/test/Analysis/CostModel/X86/bitinsert-bitextract.ll
+74-01 files

LLVM/project 27dd673 — llvm/test/Transforms/InstSimplify bitinsert-bitextract.ll

[InstSimplify] Pre-commit tests for vector `bitinsert` and `bitextract` with out-of-range offsets
DeltaFile
+31-11llvm/test/Transforms/InstSimplify/bitinsert-bitextract.ll
+31-111 files

LLVM/project d5ca915 — llvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstSimplify bitinsert-bitextract.ll

[InstSimplify] Simplify vector `bitinsert` and `bitextract` with out-of-range offsets
DeltaFile
+23-5llvm/lib/Analysis/InstructionSimplify.cpp
+2-4llvm/test/Transforms/InstSimplify/bitinsert-bitextract.ll
+25-92 files

LLVM/project 478e293 — llvm/lib/Analysis ConstantFolding.cpp, llvm/test/Transforms/InstSimplify bitcast-vector-fold.ll

[ConstantFolding] Fold constant vector `bitcast`s to scalar bytes
DeltaFile
+20-8llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
+20-5llvm/lib/Analysis/ConstantFolding.cpp
+2-4llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+42-173 files

LLVM/project aecfd0c — llvm/test/Transforms/InstSimplify bitcast-vector-fold.ll, llvm/test/Transforms/InstSimplify/ConstProp bitinsert-bitextract.ll

[ConstantFolding] Pre-commit tests for constant vector `bitcast`s to scalar bytes
DeltaFile
+72-0llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
+20-0llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+92-02 files

LLVM/project d860fec — llvm/lib/Analysis ConstantFolding.cpp, llvm/test/Transforms/InstSimplify/ConstProp bitinsert-bitextract.ll

[ConstantFolding] Fold vector `bitinsert` and `bitextract`
DeltaFile
+65-6llvm/lib/Analysis/ConstantFolding.cpp
+10-23llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+75-292 files

LLVM/project 75b4220 — llvm/test/Transforms/InstSimplify/ConstProp bitinsert-bitextract.ll

[ConstantFolding] Pre-commit tests for vector `bitinsert` and `bitextract`
DeltaFile
+74-0llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+74-01 files

LLVM/project 9c85844 — llvm/lib/CodeGen/GlobalISel IRTranslator.cpp, llvm/test/CodeGen/AArch64 bitinsert-bitextract-vector.ll

[GlobalISel] Lower vector `bitinsert` and `bitextract`
DeltaFile
+65-0llvm/test/CodeGen/AArch64/bitinsert-bitextract-vector.ll
+14-12llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+79-122 files

LLVM/project 9cc4e15 — llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/AArch64 sve-bitinsert-bitextract.ll bitinsert-bitextract-vector.ll

[SelectionDAG] Lower vector `bitinsert` and `bitextract`
DeltaFile
+277-0llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-vector.ll
+183-0llvm/test/CodeGen/X86/bitinsert-bitextract-vector.ll
+145-0llvm/test/CodeGen/RISCV/rvv/bitinsert-bitextract.ll
+94-0llvm/test/CodeGen/AArch64/bitinsert-bitextract-vector.ll
+27-0llvm/test/CodeGen/AArch64/sve-bitinsert-bitextract.ll
+2-2llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+728-26 files

LLVM/project 19655f7 — llvm/test/tools/llubi bitinsert_bitextract_le.ll bitinsert_bitextract_be.ll, llvm/tools/llubi/lib Interpreter.cpp

[llubi] Add support for vector `bitinsert` and `bitextract`
DeltaFile
+26-22llvm/tools/llubi/lib/Interpreter.cpp
+28-0llvm/test/tools/llubi/bitinsert_bitextract_le.ll
+28-0llvm/test/tools/llubi/bitinsert_bitextract_be.ll
+82-223 files

LLVM/project eb04b18 — llvm/test/Transforms/InstCombine bitinsert-bitextract.ll, llvm/test/Transforms/InstSimplify bitinsert-bitextract.ll

[InstSimplify][InstCombine] Add vector tests for `bitinsert` and `bitextract`
DeltaFile
+140-0llvm/test/Transforms/InstSimplify/bitinsert-bitextract.ll
+93-0llvm/test/Transforms/InstCombine/bitinsert-bitextract.ll
+16-0llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+249-03 files

LLVM/project ba18349 — llvm/lib/Target/AArch64 AArch64MacroFusion.cpp, llvm/test/CodeGen/AArch64 misched-fusion-fmin-fmax.ll misched-fusion-fmin-fmax-pre-ra.mir

[AArch64] Don't mix FMIN/FMAX kinds in a cluster (#239162)
DeltaFile
+19-0llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir
+10-8llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+18-0llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
+16-0llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax.ll
+63-84 files

LLVM/project cd67cba — llvm/test/CodeGen/ARM/GlobalISel arm-legalize-divmod.mir arm-legalize-binops.mir

[ARM][GISel] Enable extended LLT (#191830)

This adds the basic enablement for extended LLT for Arm GISel. This is
relatively basic, with no direct use of fp16/bf16 yet. Most of the
changes involved updating the tests and some minor updates to handle
bitcast and merge/unmerge correctly.
DeltaFile
+5,423-1,527llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+534-327llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+227-227llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+210-210llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
+205-205llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir
+178-178llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
+6,777-2,67457 files not shown
+8,582-4,10563 files

LLVM/project 1a6a2a9 — llvm/lib/Transforms/IPO MemProfContextDisambiguation.cpp, llvm/test/Transforms/MemProfContextDisambiguation inlined-callsite-edge-alloc-type.ll

[MemProf] Update edge alloc types when moving context ids to a new node (#239879)

When an inlined callsite is matched to a sequence of stack nodes, the
context ids matched to it are moved from the original edges to a new
node. The alloc types of the original edges that kept some context ids
were not updated, so an edge left with only not cold contexts could
still be marked cold. Since the ambiguous attribute handling now relies
on the alloc types after cloning, an allocation reached through such an
edge was marked ambiguous instead of not cold.

Recompute the alloc type of any edge that keeps context ids, both in
connectNewNode and for the edges between the matched stack nodes.

Assisted-by: Gemini
DeltaFile
+80-0llvm/test/Transforms/MemProfContextDisambiguation/inlined-callsite-edge-alloc-type.ll
+5-1llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
+85-12 files