LLVM/project ea2c207cmake/Modules NormalizeTriple.cmake, llvm/cmake/modules LLVMExternalProjectUtils.cmake

Use clang to canonicalize the triple
DeltaFile
+34-0cmake/Modules/NormalizeTriple.cmake
+21-10llvm/cmake/modules/LLVMExternalProjectUtils.cmake
+2-16runtimes/CMakeLists.txt
+57-263 files

LLVM/project 1becec5mlir/lib/Target/LLVMIR ModuleTranslation.cpp, mlir/lib/Target/LLVMIR/Dialect/LLVMIR LLVMToLLVMIRTranslation.cpp

fix: add braces to metadata translation conditionals
DeltaFile
+6-3mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+2-1mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
+8-42 files

LLVM/project bd6c6famlir/include/mlir/IR EnumAttr.td, mlir/test/mlir-tblgen gen-dialect-doc.td

[mlir-tblgen] Render enum keyword alternatives in generated attr/type docs

When mlir-tblgen generates documentation for AttrDefs/TypeDefs that have
EnumParameter fields, it previously rendered the raw C++ type (e.g.
`::mlir::ns::MyEnum`) in the syntax block. This was unhelpful for
users who need to know the valid keyword values.

This patch:
1. Adds an `EnumInfo enum = enumInfo;` field to the `EnumParameter`
   TableGen class, persisting the enum record for tooling to inspect.
2. Modifies `emitAttrOrTypeDefAssemblyFormat` in OpDocGen.cpp to detect
   EnumParameter fields and render their cases as backtick-quoted
   alternatives (e.g. `` `read` | `read_write` ``).
3. Adds a test case to gen-dialect-doc.td verifying the new behavior.

Before:
  #my_dialect.my_attr<
    int32_t,   # index
    ::mlir::ns::MyEnum,   # access

    [9 lines not shown]
DeltaFile
+25-0mlir/test/mlir-tblgen/gen-dialect-doc.td
+23-1mlir/tools/mlir-tblgen/OpDocGen.cpp
+3-0mlir/include/mlir/IR/EnumAttr.td
+51-13 files

LLVM/project b76803blibcxx/include __locale, libcxx/src locale.cpp

[libc++] LWG3767: `codecvt<charN_t, char8_t, mbstate_t>` incorrectly added to locale (#201749)

Implement it as a DR against C++20, patching P0482R6.
DeltaFile
+26-0libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/codecvt_byname_char16_t_char8_t.depr_in_cxx20.verify.cpp
+26-0libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt.byname/codecvt_byname_char32_t_char8_t.depr_in_cxx20.verify.cpp
+26-0libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/codecvt_char16_t_char8_t.depr_in_cxx20.verify.cpp
+26-0libcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/codecvt_char32_t_char8_t.depr_in_cxx20.verify.cpp
+10-6libcxx/include/__locale
+8-6libcxx/src/locale.cpp
+122-1221 files not shown
+203-1327 files

LLVM/project 58c0dacorc-rt/include/orc-rt-c Error.h Compiler.h, orc-rt/lib/executor Error.cpp

[orc-rt] Add ORC_RT_C_NOTHROW and apply it to the Error C API. (#203674)

Adds an ORC_RT_C_NOTHROW macro that expands to `noexcept` in C++ mode,
and `__attribute__((nothrow))` where that attribute is supported.

Also applies the new ORC_RT_C_NOTHROW macro to orc-rt-c/Error.h (and
adds `noexcept` to the corresponding C++ implementation in
lib/executor/Error.cpp).
DeltaFile
+11-7orc-rt/lib/executor/Error.cpp
+10-7orc-rt/include/orc-rt-c/Error.h
+9-0orc-rt/include/orc-rt-c/Compiler.h
+30-143 files

LLVM/project 2b32f3fclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVMIR.cpp, clang/test/CIR/CodeGenOpenCL kernel-arg-info.cl kernel-arg-info-single-as.cl

[CIR][OpenCL] Lower kernel argument metadata to LLVM IR

Translate CIR OpenCL kernel argument metadata into the LLVM IR kernel_arg_* metadata attached to kernel functions. Preserve optional argument names so -cl-kernel-arg-info controls the LLVM metadata surface through the CIR attribute.
DeltaFile
+74-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
+60-0clang/test/CIR/CodeGenOpenCL/kernel-arg-info.cl
+12-0clang/test/CIR/CodeGenOpenCL/kernel-arg-info-single-as.cl
+12-0clang/test/CIR/CodeGenOpenCL/kernel-arg-metadata.cl
+158-14 files

LLVM/project d0b8992orc-rt/include/orc-rt-c Compiler.h ExternC.h

[orc-rt] Merge ExternC.h and Visibility.h into Compiler.h. (#203673)

This mirrors the combined orc-rt/Compiler.h header on the C++ side, and
provides a natural home for future decoration macros when they're added.
DeltaFile
+51-0orc-rt/include/orc-rt-c/Compiler.h
+0-41orc-rt/include/orc-rt-c/ExternC.h
+0-30orc-rt/include/orc-rt-c/Visibility.h
+1-2orc-rt/include/orc-rt-c/Error.h
+1-1orc-rt/include/orc-rt-c/WrapperFunction.h
+1-1orc-rt/include/orc-rt-c/CoreTypes.h
+54-751 files not shown
+55-767 files

LLVM/project 285b6e3clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenModule.h, clang/test/CIR/CodeGenOpenCL kernel-arg-info.cl kernel-arg-info-single-as.cl

[CIR][OpenCL] Attach kernel argument metadata to CIR functions

Emit the CIR OpenCL kernel argument metadata attribute for kernel functions. Preserve CIR language address-space kinds until lowering and include argument names only when `-cl-kernel-arg-info` is enabled.
DeltaFile
+152-0clang/test/CIR/CodeGenOpenCL/kernel-arg-info.cl
+91-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+19-0clang/test/CIR/CodeGenOpenCL/kernel-arg-info-single-as.cl
+12-0clang/test/CIR/CodeGenOpenCL/kernel-arg-metadata.cl
+5-0clang/test/CIR/CodeGenOpenCL/invalid-kernel-arg-metadata-target-address-space.cl
+4-0clang/lib/CIR/CodeGen/CIRGenModule.h
+283-01 files not shown
+286-07 files

LLVM/project af4839allvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel srem.i64.ll udiv.i64.ll

Updated tests because of liveins/liveouts seeding.
DeltaFile
+11,260-11,217llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,067-2,168llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+249-249llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+220-220llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+220-220llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+191-190llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
+14,207-14,26420 files not shown
+14,998-15,08026 files

LLVM/project e8b43f2llvm/test/CodeGen/AMDGPU agpr-copy-no-free-registers.ll regpressure_printer.mir

Regenerated tests after rebasing.
DeltaFile
+140-44llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+15-15llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
+155-592 files

LLVM/project 1143639llvm/test/CodeGen/AMDGPU schedule-amdgpu-tracker-physreg.ll

[AMDGPU] Adjusted GCN tracker option after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
+1-11 files

LLVM/project 6949ca2llvm/test/CodeGen/AMDGPU bf16.ll minimumnum.bf16.ll

[AMDGPU] Regenerated tests after rebasing.
DeltaFile
+8,626-9,213llvm/test/CodeGen/AMDGPU/bf16.ll
+2,364-2,564llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,314-2,514llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+1,340-1,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,244-1,250llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+1,109-1,102llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+16,997-17,98660 files not shown
+26,853-27,93166 files

LLVM/project 16b4a6allvm/test/CodeGen/AMDGPU call-argument-types.ll amdgcn.bitcast.768bit.ll

[AMDGPU] Regenerated tests after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.
DeltaFile
+284-572llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+227-225llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+180-196llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+171-143llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+131-80llvm/test/CodeGen/AMDGPU/bf16.ll
+88-94llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+1,081-1,3109 files not shown
+1,477-1,70115 files

LLVM/project 8b0466cllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Enabled GCN trackers (amdgpu-use-amdgpu-trackers) by default.

The LIT tests have been generally updated in one of the following ways:
(1) If the above option was not present and the test was auto-generated,
the test has now been auto-generated.
(2) If the above option was not present and the test was not
auto-generated, added the option -amdgpu-use-amdgpu-trackers=0 so as to
preserve any specific attributes the test was already checking.
(3) If the above option was present in a test, then its value has been
updated to reflect the change in the default.

Currently, there are 4 tests in category (2). They are:
CodeGen/AMDGPU/
  addrspacecast.ll
  schedule-regpressure-limit.ll
  schedule-regpressure-limit2.ll
  sema-v-unsched-bundle.ll

There are 8 tests in category (3). They are:

    [15 lines not shown]
DeltaFile
+77,782-77,355llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+13,255-13,280llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,928-9,400llvm/test/CodeGen/AMDGPU/bf16.ll
+4,484-4,395llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+3,842-3,812llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+3,802-3,690llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+113,093-111,932155 files not shown
+169,016-166,668161 files

LLVM/project 7063751llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNRegPressure.h

clang-format.
DeltaFile
+11-11llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+10-11llvm/lib/Target/AMDGPU/GCNRegPressure.h
+5-7llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+26-293 files

LLVM/project 7327c74llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel srem.i64.ll udiv.i64.ll

Updated tests because of liveins/liveouts seeding.
DeltaFile
+11,260-11,217llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,067-2,168llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+249-249llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+220-220llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+220-220llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+191-190llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
+14,207-14,26420 files not shown
+14,998-15,08026 files

LLVM/project 6afb1c4llvm/test/CodeGen/AMDGPU bf16.ll minimumnum.bf16.ll

[AMDGPU] Regenerated tests after rebasing.
DeltaFile
+8,626-9,213llvm/test/CodeGen/AMDGPU/bf16.ll
+2,364-2,564llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,314-2,514llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+1,340-1,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,244-1,250llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+1,109-1,102llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+16,997-17,98660 files not shown
+26,853-27,93166 files

LLVM/project 46ce87allvm/test/CodeGen/AMDGPU agpr-copy-no-free-registers.ll regpressure_printer.mir

Regenerated tests after rebasing.
DeltaFile
+140-44llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+15-15llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
+155-592 files

LLVM/project 62dd26cllvm/test/CodeGen/AMDGPU call-argument-types.ll amdgcn.bitcast.768bit.ll

[AMDGPU] Regenerated tests after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.
DeltaFile
+284-572llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+227-225llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+180-196llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+171-143llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+131-80llvm/test/CodeGen/AMDGPU/bf16.ll
+88-94llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
+1,081-1,3109 files not shown
+1,477-1,70115 files

LLVM/project bf19781llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Enabled GCN trackers (amdgpu-use-amdgpu-trackers) by default.

The LIT tests have been generally updated in one of the following ways:
(1) If the above option was not present and the test was auto-generated,
the test has now been auto-generated.
(2) If the above option was not present and the test was not
auto-generated, added the option -amdgpu-use-amdgpu-trackers=0 so as to
preserve any specific attributes the test was already checking.
(3) If the above option was present in a test, then its value has been
updated to reflect the change in the default.

Currently, there are 4 tests in category (2). They are:
CodeGen/AMDGPU/
  addrspacecast.ll
  schedule-regpressure-limit.ll
  schedule-regpressure-limit2.ll
  sema-v-unsched-bundle.ll

There are 8 tests in category (3). They are:

    [15 lines not shown]
DeltaFile
+77,782-77,355llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+13,255-13,280llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,928-9,400llvm/test/CodeGen/AMDGPU/bf16.ll
+4,484-4,395llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+3,842-3,812llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+3,802-3,690llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+113,093-111,932155 files not shown
+169,016-166,668161 files

LLVM/project a13cc69llvm/test/CodeGen/AMDGPU schedule-amdgpu-tracker-physreg.ll

[AMDGPU] Adjusted GCN tracker option after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
+1-11 files

LLVM/project f0524b8llvm/test/CodeGen/AMDGPU sched-physreg-liveouts.mir

Added a test to capture physical register liveouts.
DeltaFile
+84-0llvm/test/CodeGen/AMDGPU/sched-physreg-liveouts.mir
+84-01 files

LLVM/project e5afb8ellvm/lib/Target/X86 X86Subtarget.cpp, llvm/test/CodeGen/X86 call-imm.ll

[X86] Disallow immediate address calls when position independent (#202370)

Causes problems with mold linker, and was determined to be a compiler
bug. See:
See https://github.com/rui314/mold/pull/1601#issuecomment-4628653209
DeltaFile
+2-0llvm/test/CodeGen/X86/call-imm.ll
+1-1llvm/lib/Target/X86/X86Subtarget.cpp
+3-12 files

LLVM/project caf9864clang/include/clang/CIR/Dialect/IR CIROpenCLAttrs.td CIRAttrConstraints.td, clang/lib/CIR/Dialect/IR CIROpenCLAttrs.cpp

[CIR][OpenCL] Add kernel argument metadata attribute (#199530)

Add a CIR attribute that carries OpenCL kernel argument metadata in
source argument order. Verify that each metadata field has the expected
element type and that all present arrays describe the same number of
arguments.
DeltaFile
+78-0clang/test/CIR/IR/invalid-opencl-kernel-arg-metadata.cir
+71-0clang/test/CIR/IR/opencl-kernel-arg-metadata.cir
+46-0clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
+38-0clang/lib/CIR/Dialect/IR/CIROpenCLAttrs.cpp
+25-6clang/include/clang/CIR/Dialect/IR/CIRAttrConstraints.td
+8-2clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+266-88 files not shown
+279-1014 files

LLVM/project e602cd1llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU wmma-coexecution-valu-hazards.mir wmma-hazards-gfx1250-w32.mir

[AMDGPU] Add a few wmma co-execution hazard checks, NFC (#203658)

This is to reflect the gfx1251 update regarding wmma*8f6f4 with
 matrix format as F4.

  Also fix a comment in GCNHazardRecognizer.cpp
DeltaFile
+362-0llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
+87-0llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
+1-1llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+450-13 files

LLVM/project 24faf90clang/include/clang/Basic AttrDocs.td Attr.td, clang/test/AST undocumented-attrs.cpp

[Clang] Add AttrDocs entry for OverflowBehavior (#203392)

These docs were previously missing.

Fixes: #203322

Signed-off-by: Justin Stitt <justinstitt at google.com>
DeltaFile
+45-0clang/include/clang/Basic/AttrDocs.td
+1-2clang/test/AST/undocumented-attrs.cpp
+1-1clang/include/clang/Basic/Attr.td
+47-33 files

LLVM/project e63cd40llvm/lib/Target/NVPTX NVPTXISelLowering.cpp NVPTXAsmPrinter.cpp

[NVPTX] Rip out vestigial variadic support (NFC) (#202385)
DeltaFile
+65-231llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+11-21llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+4-9llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+0-8llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+80-2694 files

LLVM/project 18a4c90libcxx/include optional, libcxx/test/std/utilities/optional/optional.monadic and_then.pass.cpp transform.pass.cpp

[libc++] Fix bug where `optional<T&>` couldn't be constructed from `transform()` (#203462)

- Add the proper from monadic base constructor
- Fix the constraint so it allows references.
- Add tests
DeltaFile
+35-2libcxx/test/std/utilities/optional/optional.monadic/and_then.pass.cpp
+26-5libcxx/include/optional
+17-4libcxx/test/std/utilities/optional/optional.monadic/transform.pass.cpp
+9-0libcxx/test/std/utilities/optional/optional.monadic/or_else.pass.cpp
+87-114 files

LLVM/project 44cc797libcxx/include/__memory uninitialized_algorithms.h ranges_uninitialized_algorithms.h, libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default ranges_uninitialized_default_construct.pass.cpp uninitialized_default_construct_n.pass.cpp

[libc++] P3369R0: constexpr for `uninitialized_default_construct` (#200163)

Remarks:
- Tests also verify that `uninitialized_default_construct(_n)`
algorithms do not initialize trivially default-constructible elements
(`int` in these tests) to determined values during constant evaluation.
DeltaFile
+179-0libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/ranges_uninitialized_default_construct.pass.cpp
+110-1libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/uninitialized_default_construct_n.pass.cpp
+108-1libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/uninitialized_default_construct.pass.cpp
+109-0libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.construct.default/ranges_uninitialized_default_construct_n.pass.cpp
+7-4libcxx/include/__memory/uninitialized_algorithms.h
+5-3libcxx/include/__memory/ranges_uninitialized_algorithms.h
+518-97 files not shown
+531-1613 files

LLVM/project 08e6e14llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/RISCV/GlobalISel rv64zbb.ll

[GlobalISel] Fix sign-extended byte mask in lowerBswap (#199387)

The per-byte mask in `LegalizerHelper::lowerBswap` was constructed via

```
APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
```

where `0xFF << (i * 8)` is evaluated as a signed `int`. For `i*8 >= 24`
(byte-3 mask of an s64 G_BSWAP) the value `0xFF000000` does not fit in a
positive 32-bit `int`; the conversion to signed `int` is
implementation-defined under C++17 (UB under C++11, fully defined under
C++20) and on two's-complement targets produces `-16777216`. The modular
conversion to `uint64_t` in the `APInt` constructor then materializes
that negative `int` as `0xFFFFFFFFFF000000` — the intended mask was
`0x00000000FF000000`. The over-wide mask preserved bytes 4-7 of the
source where only byte 3 was intended, and the spurious bytes propagated
through the subsequent shift/OR chain.


    [3 lines not shown]
DeltaFile
+28-0llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+13-12llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+1-1llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+1-1llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
+44-155 files