LLVM/project 0ab6a63llvm/docs LangRef.rst, llvm/include/llvm/IR DataLayout.h

[LLVM][IR] Add support for address space names in DataLayout (#170559)

Add support for specifying the names of address spaces when specifying
pointer properties for an address space. Update LLVM's AsmPrinter and
LLParser to print and read these symbolic address space name.
DeltaFile
+87-20llvm/lib/IR/DataLayout.cpp
+47-29llvm/lib/IR/AsmWriter.cpp
+73-0llvm/test/Assembler/symbolic-addrspace-datalayout.ll
+33-1llvm/unittests/IR/DataLayoutTest.cpp
+15-4llvm/include/llvm/IR/DataLayout.h
+6-2llvm/docs/LangRef.rst
+261-561 files not shown
+265-577 files

LLVM/project 05ef57f.github/workflows libcxx-build-and-test.yaml

[libc++][Github] Bump Runners to Next Group (#168122)

To start using the more recently built containers.
DeltaFile
+8-8.github/workflows/libcxx-build-and-test.yaml
+8-81 files

LLVM/project 16fbbacllvm/test/CodeGen/X86 shift-i512.ll

[X86] shift-i512.ll - add load test coverage (#171642)

DeltaFile
+825-0llvm/test/CodeGen/X86/shift-i512.ll
+825-01 files

LLVM/project 5aee752llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPUGlobalISelUtils.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES

Move G_UNMERGE_VALUES handling to AMDGPURegBankLegalizeRules.cpp.
Fix sgpr S16 unmerge by lowering using shift and using S32.
Previously sgpr S16 unmerge was selected using _lo16 and _hi16 subreg
indexes which are exclusive to vgpr register classes.
For remaing cases we do trivial mapping, assigns same reg bank
to all operands, vgpr or sgpr.
DeltaFile
+60-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+36-0llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
+16-0llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+11-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+8-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+4-0llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
+135-11 files not shown
+137-37 files

LLVM/project 5c98163lldb/source/Plugins/Process/gdb-remote ProcessGDBRemote.cpp

[lldb] Log when we use fallback register information

These fallback layouts are essentially guesses. Used when there is
no other way to query register information from the debug server.

Therefore there is a risk that LLDB and the debug server disagree,
which can produce strange effects.

I have added a log message here so we have a clue when triaging
these problems.

Note that it's not wrong to assume a layout in some situations.
It's how some debug servers were built. However if you end up
using the fallback when the server expected you to use XML,
you're likely going to have a bad time.
DeltaFile
+6-1lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+6-11 files

LLVM/project 9728db7llvm/test/tools/llvm-mca/AArch64/Neoverse V3AE-neon-instructions.s V3-neon-instructions.s

Merge branch 'main' into users/bwendling/negative-counted-by
DeltaFile
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s
+5,340-7,2931,356 files not shown
+40,179-29,3541,362 files

LLVM/project 7e69283clang/test/CodeGen attr-counted-by.c

Add testcases.
DeltaFile
+85-1clang/test/CodeGen/attr-counted-by.c
+85-11 files

LLVM/project d162afallvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fpext.ll regbankselect-fpext.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPEXT (#171483)

DeltaFile
+263-0llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+6-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
+7-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+276-23 files

LLVM/project 2ecbb3eflang/lib/Frontend FrontendActions.cpp, flang/test/Lower memory-intrinsics-expansion.F90

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+33-0flang/test/Lower/memory-intrinsics-expansion.F90
+13-0flang/lib/Frontend/FrontendActions.cpp
+46-02 files

LLVM/project 8adcf0amlir/lib/Conversion/XeGPUToXeVM XeGPUToXeVM.cpp, mlir/test/Conversion/XeGPUToXeVM loadstore_matrix.mlir loadstoreprefetch.mlir

[MLIR][XeGPU] Support subview memref: handling the base address during xegpu to xevm type conversion (#170541)

During the XeGPU-to-XeVM type conversion, a memref is lowered to its
base address. This PR extends the conversion to correctly handle memrefs
that include an offset, such as those generated by memref.subview.
DeltaFile
+131-55mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir
+62-8mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
+25-0mlir/test/Conversion/XeGPUToXeVM/loadstoreprefetch.mlir
+2-2mlir/test/Conversion/XeGPUToXeVM/create_nd_tdesc.mlir
+220-654 files

LLVM/project 3a0c006flang/lib/Lower/OpenMP OpenMP.cpp, flang/test/Integration/OpenMP do-simd-firstprivate-lastprivate-runtime.f90

Revert "[flang][OpenMP] Fix firstprivate not working with lastprivate in DO SIMD" (#171646)

Reverts llvm/llvm-project#170163

Regression in fujitsu test suite
DeltaFile
+0-89flang/test/Lower/OpenMP/do-simd-firstprivate-lastprivate.f90
+0-48flang/test/Integration/OpenMP/do-simd-firstprivate-lastprivate-runtime.f90
+12-8flang/lib/Lower/OpenMP/OpenMP.cpp
+7-2flang/test/Lower/OpenMP/wsloop-simd.f90
+4-4flang/test/Lower/OpenMP/order-clause.f90
+23-1515 files

LLVM/project 8f1c593llvm/lib/Target/RISCV RISCVISelLowering.cpp

[RISCV] Reduce code duplication. NFC (#171577)

This code was only different in the opcodes of the nodes it created.
DeltaFile
+6-11llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+6-111 files

LLVM/project f692ca1llvm/lib/Target/RISCV RISCVInstrInfoXSfmm.td, llvm/test/CodeGen/RISCV/rvv sifive-xsfmm-vset-insert.mir

[RISCV] Use 'sew' insead of ixlenimm in Xsfmm pseudos. (#171570)

DeltaFile
+35-35llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir
+9-9llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
+44-442 files

LLVM/project 9848c03llvm/runtimes CMakeLists.txt

[cmake] LLVM_BUILTINS_TARGET='default' should bootstrap builtins without compiler-rt (#171536)

DeltaFile
+7-0llvm/runtimes/CMakeLists.txt
+7-01 files

LLVM/project 580219ellvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.h

address review
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+2-21 files

LLVM/project 53a07b2llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU insert_vector_dynelt.ll extract_vector_dynelt.ll

[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST

Before, instruction selection would fail to select extract/insert
elements for i32/float vectors of sizes 3, 5, 6 and 7 when -O0 was used.

This patch adds the missing SI_INDIRECT_SRC/DST cases for those sizes.
DeltaFile
+5,501-2llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+2,950-6llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+16-0llvm/lib/Target/AMDGPU/SIInstructions.td
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8,475-84 files

LLVM/project 33ceb53llvm/test/CodeGen/AMDGPU insert_vector_dynelt.ll extract_vector_dynelt.ll

Pre commit test: Add <(3, 5, 6, 7) x 32-bit> test cases for insert/extract element with a dynamic index
DeltaFile
+462-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+364-0llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+826-02 files

LLVM/project 6e54034llvm/test/CodeGen/AMDGPU extract_vector_dynelt.ll insert_vector_dynelt.ll

Add llc -O0 line that triggers instruction selection failure
DeltaFile
+2-0llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+2-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+4-02 files

LLVM/project bf81bdemlir/include/mlir/Dialect/OpenACC/Analysis OpenACCSupport.h, mlir/lib/Dialect/OpenACC/Analysis OpenACCSupport.cpp

[mlir][acc] Add isValidValueUse to OpenACCSupport (#171538)

Add a new API `isValidValueUse ` to OpenACCSupport. This is used in
ACCImplicitData to check value that are already legal in the OpenACC
region and do not require implicit clause to be generated. An example
would be a CUDA Fortran device variable that is already on the GPU.
DeltaFile
+24-0mlir/include/mlir/Dialect/OpenACC/Analysis/OpenACCSupport.h
+16-7mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
+6-0mlir/lib/Dialect/OpenACC/Analysis/OpenACCSupport.cpp
+46-73 files

LLVM/project 9239749lldb/test/API/tools/lldb-dap/runInTerminal TestDAP_runInTerminal.py

[lldb-dap] enable run-in-terminal test on linux arm. (#171598)

follow up to
https://github.com/llvm/llvm-project/pull/144954#issuecomment-2990767363
DeltaFile
+0-8lldb/test/API/tools/lldb-dap/runInTerminal/TestDAP_runInTerminal.py
+0-81 files

LLVM/project fc518f7llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp

[AArch64][GlobalISel] Refactored Legaliser Changes

Early returns implemented where possible, in order to reduce
indentation.
DeltaFile
+68-69llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+68-691 files

LLVM/project 54b4bd5flang/include/flang/Optimizer/Analysis AliasAnalysis.h, flang/include/flang/Optimizer/Dialect FortranVariableInterface.td

[flang][AliasAnalysis] Cray pointers/pointees might alias with anything (#170900)

The LOC intrinsic allows a cray pointer to alias with ordinary variables
with no other attribute. See the new test for an example.

This is not enabled by default. The functionality can be used with
`-mmlir -funsafe-cray-pointers`.

First part of the un-revert of #169544. That will handle TBAA.
DeltaFile
+60-0flang/test/Analysis/AliasAnalysis/alias-analysis-cray-pointers.fir
+29-29flang/test/Lower/HLFIR/cray-pointers.f90
+31-0flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+14-0flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td
+10-1flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
+5-5flang/test/Lower/OpenMP/cray-pointers01.f90
+149-355 files not shown
+169-4211 files

LLVM/project f8580c9clang-tools-extra/clang-tidy/readability RedundantControlFlowCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Make `readability-redundant-control-flow` not suggest deleting unrelated lines (#171287)

Closes #171200.
DeltaFile
+50-0clang-tools-extra/test/clang-tidy/checkers/readability/redundant-control-flow.cpp
+5-13clang-tools-extra/clang-tidy/readability/RedundantControlFlowCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+60-133 files

LLVM/project feef80cclang/lib/Tooling/Transformer SourceCode.cpp, clang/unittests/Tooling SourceCodeTest.cpp

[clang][tooling] Fix `getFileRange` false negative (#171555)

When an expression is in a single macro argument but also contains a
macro, `getFileRange` would incorrectly reject that expression,
concluding that it came from two different macro arguments because they
came from two different expansions.

We adjust the logic to look at the full path of macro argument expansion
locations instead, tracking that if our traversal up the macro
expansions continues all the way through macro arguments all the way to
the top. This is similar to the technique used by `makeFileCharRange`.

We also add some test cases to ensure we don't introduce any false
positives.
DeltaFile
+38-13clang/unittests/Tooling/SourceCodeTest.cpp
+13-10clang/lib/Tooling/Transformer/SourceCode.cpp
+51-232 files

LLVM/project c4ff1f3clang/include/clang/CIR/Dialect/IR CIROps.td CIRTypeConstraints.td, clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp

[CIR] Implement builtin extractf (#170427)

Implement builtin extractf, tests are from
clang/test/CodeGen/X86/avx512f-builtins.c.

Added a new type constraint "element or vector of element" since
LLVMIR also has said constraint. The new getBoolMaskValue is because the
existing SelectOp already accepts only a boolean condition; it'd make
more sense for it to accept a vector of boolean instead of a vector of
i32.
DeltaFile
+178-0clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
+61-1clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+39-6clang/include/clang/CIR/Dialect/IR/CIROps.td
+21-0clang/test/CIR/IR/select.cir
+19-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+7-4clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
+325-116 files

LLVM/project 835aa48utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Port c9c4e6eb58c070d65abca68b77b783720de1d5d9 (#171632)

Was missing a dep on the bazel side.
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project 02a908coffload/include/Shared Debug.h, offload/libomptarget omptarget.cpp interface.cpp

[OpenMP][Offload] Continue to update libomptarget debug messages (#170425)

* Add support to use lambdas to output debug messages (like LDBG_OS)
* Update messages for interface.cpp and omptarget.cpp
DeltaFile
+238-213offload/libomptarget/omptarget.cpp
+45-40offload/libomptarget/interface.cpp
+53-0offload/include/Shared/Debug.h
+336-2533 files

LLVM/project 130fa98llvm/include/llvm/ADT StringExtras.h, llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU][NFC] dump Waitcnt using an ostream operator (#171251)

DeltaFile
+24-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+2-2llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+2-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+1-0llvm/include/llvm/ADT/StringExtras.h
+29-24 files

LLVM/project fec0a64mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td, mlir/test/Dialect/LLVMIR rocdl.mlir

[ROCDL] Added global/flag data prefetch ops (#171449)

This PR brings data prefetch ops to ROCDL for gfx1250 architecture.
Extended all necessary rocdl tests
DeltaFile
+25-0mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+14-0mlir/test/Dialect/LLVMIR/rocdl.mlir
+14-0mlir/test/Target/LLVMIR/rocdl.mlir
+53-03 files

LLVM/project 2acefcdclang/lib/CIR/CodeGen CIRGenExprScalar.cpp CIRGenModule.cpp, clang/test/CIR/CodeGen source-loc.cpp

[CIR] Add support for SourceLocExpr (#171492)

Add support for the SourceLocExpr
DeltaFile
+58-0clang/test/CIR/CodeGen/source-loc.cpp
+9-2clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+5-1clang/lib/CIR/CodeGen/CIRGenModule.cpp
+72-33 files