LLVM/project af795ffllvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/CodeGen/AMDGPU fptosi-sat-vector.ll fptosi-sat-scalar.ll

[AMDGPU] Fix pre-GFX11 llvm.fptosi.sat.i16.f32 lowering (#211703)
DeltaFile
+8-8llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+6-6llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+1-1llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+15-153 files

LLVM/project ba42905llvm/test/CodeGen/AArch64 sign-return-address-pauth-lr.ll

[llvm][AArch64] Add a test for -aarch64-cfi-llvm-set-ra-sign-state='s default (#211791)
DeltaFile
+5-3llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
+5-31 files

LLVM/project 1ada304mlir/lib/Dialect/OpenACC/Transforms ACCCGToGPU.cpp

[mlir][OpenACC] Keep ThreadY active for inner-combine-fed worker reductions (#211696)

Example:
```fortran
res = 0
!$cuf kernel do(2) <<< *, (32,8) >>> reduce(+:res)
do j2 = 1, n2
  do j1 = 1, n1
    res = res + a(j1, j2)
  end do
end do
```
In this code the reduction accumulator is per-(block_y, thread_y): each
worker row's shared slot is filled by an inner block-scoped combine, so
the rows hold distinct partials. The final combine into the result was
classified as not "worker-private" (block_y+thread_y into a global
dest), so it fell back to the ThreadY row-zero path and dropped every
worker but row 0 — a 2D SUM returned -1 instead of -4.
Fix: keep ThreadY active for a block_y+thread_y accumulator that is fed

    [3 lines not shown]
DeltaFile
+34-0mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+34-01 files

LLVM/project 42176dallvm/lib/Target/AArch64 AArch64PointerAuth.cpp, llvm/test/CodeGen/AArch64 pauth-lr-tail-call-fpdiff.ll swifttail-ptrauth.ll

[llvm][AArch64] Fix the location of PAuth_LR AUT CFI (#211702)

Unlike PAC CFI, we do not have the same unwinder constraint on PAuth_LR
CFI occurring before the PAC instruction. For AUT CFI, like other CFI
opcodes, these should always occur after the instruciton that they
reference.
DeltaFile
+24-24llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
+9-9llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
+4-6llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+37-393 files

LLVM/project fdbbcbamlir/include/mlir/Dialect/Affine/IR AffineOps.td, mlir/lib/Dialect/Affine/IR AffineOps.cpp

[mlir][affine] Add affine.for verifier and move arguments check earlier (#206685)

Fixes #206628 crash by adding an earlier body argument verifier for
`affine.for`. This crash is caused because `LoopLikeOpInterface`
verifier would call `getRegionIterArgs()` and assumed induction var of
`affine.for` exists.
DeltaFile
+9-7mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+10-0mlir/test/Dialect/Affine/invalid.mlir
+1-0mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
+20-73 files

LLVM/project dd1f975llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/X86 shuffletoidentity-infinite-loop.ll

[VectorCombine] Fix infinite loop in foldShuffleToIdentity (#211717)

PR #211508 ("foldShuffleToIdentity - ensure we push any created
instructions to the WorkList") started re-queueing every instruction
created by generateNewInstTree onto the VectorCombine worklist. When the
regenerated tree contains a bitcast, re-queueing the bitcast's operand
lets foldBitcastShuffle sink the bitcast back into a shuffle(bitcast),
which foldShuffleToIdentity then re-matches as the same superfluous
identity. On a widen/concat shuffle chain feeding a bitcast the two
folds
ping-pong and the pass never reaches a fixed point (observed as an opt
-O3 hang/timeout).

Keep the WorkList threading from PR #211508 (it enables further folds,
e.g. the improved intrinsics_minmax and two_concats cases) but don't
re-queue the operand of a regenerated bitcast, which is the only push
that feeds the foldBitcastShuffle <-> foldShuffleToIdentity loop.

Add an X86 regression test that previously looped and now terminates.

    [3 lines not shown]
DeltaFile
+32-0llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-infinite-loop.ll
+6-1llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+38-12 files

LLVM/project 697f0f3llvm/test/Transforms/LoopVectorize/AArch64 scalable-strict-fadd.ll

[NFC] Regenerate CHECK lines in scalable-strict-fadd.ll (#211573)
DeltaFile
+899-899llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+899-8991 files

LLVM/project adff031llvm/docs AMDGPUUsage.rst

Comments
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

LLVM/project 4d4abe0llvm/lib/Target/AMDGPU SIDefines.h AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll

Comments
DeltaFile
+4-3llvm/lib/Target/AMDGPU/SIDefines.h
+1-3llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+9-106 files

LLVM/project 9806900llvm/docs AMDGPUUsage.rst

Update docs
DeltaFile
+20-13llvm/docs/AMDGPUUsage.rst
+20-131 files

LLVM/project 31f9faallvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp

[AMDGPU] Add synthetic apertures and use them for barriers

Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
DeltaFile
+72-87llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+44-5llvm/docs/AMDGPUUsage.rst
+21-23llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+18-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-0llvm/lib/Target/AMDGPU/SIDefines.h
+9-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+176-1324 files not shown
+186-13710 files

LLVM/project 9705ccdllvm/lib/IR AutoUpgrade.cpp, llvm/unittests/Bitcode DataLayoutUpgradeTest.cpp

Add reserved AS to autoupgrade
DeltaFile
+31-19llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+4-2llvm/lib/IR/AutoUpgrade.cpp
+35-212 files

LLVM/project 62b809a.github/workflows libcxx-pr-benchmark.yml libcxx-benchmark-commit.yml

[libc++] Consistently install Python and dependencies across macOS CI jobs (#211659)

On the macOS self-hosted runners, we need to install dependencies via
Homebrew and pinning the Xcode version is good for reproducibility. This
applies the guidelines documented in #211622 to libc++'s CI jobs.
DeltaFile
+20-8.github/workflows/libcxx-pr-benchmark.yml
+14-8.github/workflows/libcxx-benchmark-commit.yml
+7-6.github/workflows/libcxx-build-and-test.yaml
+41-223 files

LLVM/project 82488f0bolt/lib/Core BinarySection.cpp, bolt/lib/Rewrite RewriteInstance.cpp MachORewriteInstance.cpp

[BOLT] Fix pwrite assertion failure via a new safePWrite wrapper (#198569)

Background: Currently, BOLT seems to implicitly assume that the .dynsym
section is located at a low offset within the binary, calling pwrite()
directly to update it.

Issue: In scenarios where the binary has been modified by tools like
patchelf, sections like .dynsym may be moved to a high offset area. This
can lead to a violation of the Offset + Size <= Pos assertion in
pwrite(). A typical scenario is when the previous eh_frame_header update
moves the stream cursor (pos) back to a low
offset([code](https://github.com/llvm/llvm-project/blob/llvmorg-23-init/bolt/lib/Rewrite/RewriteInstance.cpp#L6387)).

Fix: This patch resolves the pwrite assertion failure via a new
safePWrite wrapper, which introduces a defensive check that verifies and
conditionally adjusts the stream position. A corresponding test case has
also been added.
DeltaFile
+89-0bolt/test/X86/dynsym-pwrite.test
+17-20bolt/lib/Rewrite/RewriteInstance.cpp
+22-9bolt/unittests/Core/BinaryContext.cpp
+22-0bolt/lib/Utils/Utils.cpp
+7-7bolt/lib/Rewrite/MachORewriteInstance.cpp
+6-6bolt/lib/Core/BinarySection.cpp
+163-423 files not shown
+168-459 files

LLVM/project b9782d1lldb/docs dil-expr-lang.ebnf, lldb/include/lldb/ValueObject DILAST.h

[lldb] Add sizeof operator to DIL
DeltaFile
+72-0lldb/test/API/commands/frame/var-dil/expr/SizeOf/TestFrameVarDILExprSizeOf.py
+35-0lldb/source/ValueObject/DILEval.cpp
+33-0lldb/test/API/commands/frame/var-dil/expr/SizeOf/main.cpp
+26-0lldb/include/lldb/ValueObject/DILAST.h
+17-1lldb/source/ValueObject/DILParser.cpp
+3-1lldb/docs/dil-expr-lang.ebnf
+186-23 files not shown
+194-29 files

LLVM/project 81cedf1llvm/lib/Transforms/Vectorize VPlan.cpp, llvm/test/Transforms/LoopVectorize/X86 invoke-in-preheader.ll

[VPlan] Fix sentinel assertion when broadcasting invoke results (#210464)

VPTransformState::get broadcasts a scalar value by inserting after the
last scalarized instruction using
std::next(BasicBlock::iterator(LastInst)). When LastInst is a terminator
like invoke, std::next advances past the end of the block, hitting the
!isKnownSentinel() assertion.

Use Instruction::getInsertionPointAfterDef which correctly handles PHIs,
invokes, and regular instructions, matching the pattern already used in
VectorCombine.cpp.

Fixes #210342
DeltaFile
+93-0llvm/test/Transforms/LoopVectorize/X86/invoke-in-preheader.ll
+5-6llvm/lib/Transforms/Vectorize/VPlan.cpp
+98-62 files

LLVM/project 2c36989llvm/lib/Target/AMDGPU GCNProcessors.td

AMDGPU: Use ProcessorAlias for legacy arch names

Older targets have aliasing names which were previously implemented
by defining a second copy of the processor, identical except for the name
Use the recently improved tablegen mechanism for defining name-only aliases.
This dedupliates some redundant table entries, like the sched model.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+18-60llvm/lib/Target/AMDGPU/GCNProcessors.td
+18-601 files

LLVM/project 0e7006fllvm/include/llvm/MC MCSubtargetInfo.h, llvm/include/llvm/Target Target.td

TableGen: Add first class support for processor aliases

Previously isCPUStringValid was virtual so TableGen could emit an
AArch64 specific hack for recognizing cpu aliases. Teach tablegen
about aliases, and insert each alias into the CPU subtype table as its
own entry (sorted by name, carrying the canonical processor's features
and scheduling model).

There is further opportunity for code sharing improvements. AArch64's
aliases are consumed by ARMTargetDefEmitter to emit a custom inc file
in TargetParser which should be universalized.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+54-43llvm/utils/TableGen/SubtargetEmitter.cpp
+34-0llvm/test/TableGen/ProcessorAliasErrors.td
+24-0llvm/test/TableGen/ProcessorAlias.td
+7-0llvm/include/llvm/Target/Target.td
+0-6llvm/lib/Target/AArch64/AArch64Processors.td
+1-1llvm/include/llvm/MC/MCSubtargetInfo.h
+120-506 files

LLVM/project b82563allvm/include/llvm/Frontend/OpenMP OMP.h

[OpenMP] Fix build error after 19857baa71 (#211771)

Some builders using older versions of gcc encounter this issue:

```
llvm/include/llvm/Frontend/OpenMP/OMP.h:138:14: error: ‘Base’ has not been declared
  138 |   assert(Set.Base::test(At));
      |              ^~~~
```

E.g. https://lab.llvm.org/buildbot/#/builders/10/builds/32524
DeltaFile
+2-1llvm/include/llvm/Frontend/OpenMP/OMP.h
+2-11 files

LLVM/project 51ba87clldb/docs dil-expr-lang.ebnf, lldb/include/lldb/ValueObject DILAST.h

[lldb] Add sizeof operator to DIL
DeltaFile
+63-0lldb/test/API/commands/frame/var-dil/expr/SizeOf/TestFrameVarDILExprSizeOf.py
+35-0lldb/source/ValueObject/DILEval.cpp
+27-0lldb/test/API/commands/frame/var-dil/expr/SizeOf/main.cpp
+26-0lldb/include/lldb/ValueObject/DILAST.h
+17-1lldb/source/ValueObject/DILParser.cpp
+3-1lldb/docs/dil-expr-lang.ebnf
+171-23 files not shown
+179-29 files

LLVM/project 98195e0mlir/include/mlir-c IR.h, mlir/lib/Bindings/Python IRCore.cpp

[MLIR][Python] Make Python-defined dialect loading context-aware (#210501)

Python-defined dialect loading currently relies on
`Dialect._mlir_module` to infer whether a dialect has already been
loaded. This state belongs to the Python dialect class rather than an
MLIR context.

Consequently, loading the same dialect after switching contexts requires
`reload=True`, while reloading it in a context where it is already
present can hit the operation registration assertion reported in
#210053.

This patch adds `mlirContextGetLoadedDialect` (following
https://github.com/llvm/lighthouse/pull/228#discussion_r3589792891) to
the C API and exposes it as `Context.is_dialect_loaded`.
`Dialect.load()` now queries the active context:
- loading a dialect more than once in the same context raises a
`RuntimeError`;
- loading the same Python-defined dialect in another context succeeds

    [8 lines not shown]
DeltaFile
+75-0mlir/test/python/dialects/ext.py
+17-17mlir/python/mlir/dialects/ext.py
+11-3mlir/lib/Bindings/Python/IRCore.cpp
+7-0mlir/include/mlir-c/IR.h
+5-0mlir/lib/CAPI/IR/IR.cpp
+1-1mlir/test/python/dialects/transform_pattern_descriptor_op_interface.py
+116-211 files not shown
+117-227 files

LLVM/project 9c75661llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanHelpers.h

[LV] Simplify VPCostContext ctor by using VFSelectionContext (NFC). (#211765)

VFSelectionContext provides most fields needed. Pass it directly and
access its fields.
DeltaFile
+11-9llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-6llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+7-0llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+21-153 files

LLVM/project 5ae98c1llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/lib/Transforms/Scalar ExpandMemCmp.cpp

[ExpandMemCmp] Check misaligned access per overlapping/tail load (#210707)

Overlapping loads place a power-of-two load at an offset that need not be
a multiple of its size, so the access can be misaligned even when the base
pointers are aligned. Rather than have each target gate
`AllowOverlappingLoads` on unaligned support, give `MemCmpExpansion`
the target info and check the overlapping load against its actual alignment
`(commonAlignment(baseAlign, offset))` via
`TargetTransformInfo::allowsMisalignedMemoryAccesses`. It is only formed when
the target can access it; otherwise the expansion falls back to the greedy
(naturally aligned) sequence.

Tail expansions are different: they merge already-legal adjacent loads
covering the same bytes, and the backend always legalizes the merged
(possibly non-power-of-two) load into aligned power-of-two pieces, so
they need no alignment gate. The one real constraint is size: a merged load
wider than `MaxLoadSize` can only be emitted when it is the sole load
(`getMemCmpOneBlock`). In a multi-block expansion, `emitLoadCompareBlock`
and the result-block phis are sized to `MaxLoadSize` and assume every

    [6 lines not shown]
DeltaFile
+326-0llvm/test/Transforms/ExpandMemCmp/RISCV/memcmp-misaligned-access.ll
+84-39llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
+3-14llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+413-533 files

LLVM/project f8ad1cdllvm/lib/Target/AArch64 AArch64MacroFusion.cpp AArch64Features.td, llvm/test/CodeGen/AArch64 misched-fusion-apple-sme-compute.mir

[AArch64] Add Apple SME compute clustering macro-fusion (#211483)

This patch adds a subtarget feature that controls scheduling SME compute
instructions back to back. Enabled on Apple CPU.
DeltaFile
+181-0llvm/test/CodeGen/AArch64/misched-fusion-apple-sme-compute.mir
+72-0llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+5-0llvm/lib/Target/AArch64/AArch64Features.td
+3-1llvm/lib/Target/AArch64/AArch64Processors.td
+1-1llvm/lib/Target/AArch64/AArch64Subtarget.h
+2-0llvm/test/TableGen/aarch64-apple-tuning-features.td
+264-26 files

LLVM/project 2e272fbllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 fmsubadd-combine.ll fmaddsub-combine.ll

[X86] Match (FM)ADDSUB patterns from target shuffles as well as ISD::VECTOR_SHUFFLE (#211764)

Allows us to match X86ISD::ADDSUB/FMSUBADD/FMADDSUB after shuffle lowering
DeltaFile
+17-17llvm/lib/Target/X86/X86ISelLowering.cpp
+14-19llvm/test/CodeGen/X86/fmsubadd-combine.ll
+3-9llvm/test/CodeGen/X86/fmaddsub-combine.ll
+34-453 files

LLVM/project 3d69acellvm/lib/Frontend/OpenMP OMPIRBuilder.cpp, mlir/test/Target/LLVMIR omptarget-debug-reduc-fn-loc.mlir

Reland [OMPIRBuilder] Don't use invalid debug loc in reduction fn. (#211566)

This fixes https://github.com/llvm/llvm-project/issues/211385. This was
initially landed in https://github.com/llvm/llvm-project/pull/148284.

We have this pattern of code in OMPIRBuilder for many functions that are
used in reduction operations.

 ```
 Function *LtGRFunc = Function::Create
  BasicBlock *EntryBlock = BasicBlock::Create(Ctx, "entry", LtGRFunc);
  Builder.SetInsertPoint(EntryBlock);
```

The insertion point is moved to the new function but the debug location
is not updated. This means that reduction function will use the debug
location that points to another function. This problem gets hidden
because these functions gets inlined but the potential for failure
exists.

    [8 lines not shown]
DeltaFile
+71-0mlir/test/Target/LLVMIR/omptarget-debug-reduc-fn-loc.mlir
+18-12llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+89-122 files

LLVM/project 862a390flang/lib/Semantics check-omp-structure.cpp check-omp-structure.h, llvm/include/llvm/Frontend/OpenMP OMP.td

[flang][OpenMP] Switch TableGen generation to use llvm::EnumSet (#211327)

Replace the remaining uses of the common::EnumSet-based OmpClauseSet to
llvm::omp::ClauseSet.
DeltaFile
+20-19flang/lib/Semantics/check-omp-structure.cpp
+4-9flang/lib/Semantics/check-omp-structure.h
+1-1llvm/include/llvm/Frontend/OpenMP/OMP.td
+25-293 files

LLVM/project 49c3970flang/lib/Semantics check-directive-structure.h check-acc-structure.cpp

[flang] Provide "clause set" type as parameter to DirectiveStructureChecker (#211326)

This will remove the hardcoded dependence of DirectiveStructureChecker
on
the common::EnumSet class. Both consumers of it will be able to use
their
own type for the clause set.

The only complication was the ClauseSetToString member function, whose
implementation depended on the specifics of common::EnumSet, namely the
IterateOverMembers member function. It was moved out of the class, and
turned into a function template to make it possible to provide different
specializations for common::EnumSet and llvm::EnumSet.
DeltaFile
+66-67flang/lib/Semantics/check-directive-structure.h
+6-0flang/lib/Semantics/check-acc-structure.cpp
+5-1flang/lib/Semantics/check-acc-structure.h
+6-0flang/lib/Semantics/check-omp-structure.cpp
+5-1flang/lib/Semantics/check-omp-structure.h
+88-695 files

LLVM/project c9ef522flang/include/flang/Semantics openmp-directive-sets.h, flang/lib/Lower/OpenMP OpenMP.cpp

[flang][OpenMP] Use llvm::omp::DirectiveSet instead of common::EnumSet (#211325)

Replace uses of OmpDirectiveSet (defined in terms of common::EnumSet)
with the common llvm::omp::DirectiveSet (defined via llvm::EnumSet).

The llvm::omp::DirectiveSet class will also be used in openmp-parsers,
where OmpDirectiveSet was an instance of llvm::Bitset.
DeltaFile
+58-60flang/include/flang/Semantics/openmp-directive-sets.h
+21-23flang/lib/Parser/openmp-parsers.cpp
+21-18flang/lib/Lower/OpenMP/OpenMP.cpp
+10-9flang/lib/Semantics/check-omp-structure.cpp
+2-2flang/lib/Semantics/check-omp-structure.h
+1-1flang/lib/Semantics/check-omp-loop.cpp
+113-1131 files not shown
+115-1137 files

LLVM/project 6c7fc0cflang/include/flang/Semantics symbol.h, flang/lib/Semantics resolve-directives.cpp check-omp-structure.h

[flang][OpenMP] Use llvm::omp::ClauseSet instead of common::EnumSet (#211324)

Replace uses of OmpClauseSet (defined in terms of common::EnumSet)
with the common llvm::omp::ClauseSet (defined via llvm::EnumSet).
DeltaFile
+18-19flang/lib/Semantics/resolve-directives.cpp
+17-14flang/include/flang/Semantics/symbol.h
+10-9flang/lib/Semantics/check-omp-structure.h
+8-9flang/lib/Semantics/symbol.cpp
+5-5flang/lib/Semantics/mod-file.cpp
+3-3flang/lib/Semantics/check-omp-structure.cpp
+61-593 files not shown
+66-619 files