LLVM/project ddd770dlibcxx/include/__exception operations.h, libcxx/include/__system_error error_category.h error_code.h

[libc++] Applied `[[nodiscard]]` to `<exception>`, `<stdexcept>` and `<system_error>` (#170837)

[[nodiscard]] should be applied to functions where discarding the return
value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html
DeltaFile
+108-0libcxx/test/libcxx/diagnostics/syserr/nodiscard.verify.cpp
+40-1libcxx/test/libcxx/language.support/nodiscard.verify.cpp
+7-7libcxx/include/__system_error/error_category.h
+5-5libcxx/include/__system_error/error_code.h
+5-5libcxx/include/__exception/operations.h
+4-4libcxx/include/__system_error/error_condition.h
+169-224 files not shown
+178-2910 files

LLVM/project 6bb7863clang/include/clang/CIR/Dialect/IR CIROps.td, clang/test/CIR/IR catch-param.cir

[CIR] Add structured CatchParamOp (#165110)

Upstream, the structured CatchParamOp as a prerequisite for implementing
exception handlers

Issue https://github.com/llvm/llvm-project/issues/154992
DeltaFile
+32-0clang/test/CIR/IR/catch-param.cir
+28-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+60-02 files

LLVM/project 9031544libcxx/include bitset __bit_reference, libcxx/test/libcxx/utilities/template.bitset nodiscard.verify.cpp

[libc++][bitset] Applied `[[nodiscard]]` (#170623)

`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/bitset
DeltaFile
+61-0libcxx/test/libcxx/utilities/template.bitset/nodiscard.verify.cpp
+33-22libcxx/include/bitset
+1-1libcxx/include/__bit_reference
+95-233 files

LLVM/project 0831165.github/workflows release-binaries.yml

fix attestation
DeltaFile
+1-1.github/workflows/release-binaries.yml
+1-11 files

LLVM/project ba836dcllvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize vplan-printing.ll

[VPlan] Remove stray space before ops when printing vector-ptr (NFC)
DeltaFile
+22-22llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+1-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+23-232 files

LLVM/project f927fb9lldb/source/Commands CommandObjectBreakpoint.cpp, llvm/test/CodeGen/AMDGPU atomicrmw_usub_sat.ll atomicrmw_usub_cond.ll

Rebase

Created using spr 1.3.5-bogner
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+4,091-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
+1,277-73lldb/source/Commands/CommandObjectBreakpoint.cpp
+1,315-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
+0-1,298openmp/runtime/src/include/omp_lib.h.var
+1,298-0openmp/module/omp_lib.h.var
+25,503-22,144966 files not shown
+65,151-35,735972 files

LLVM/project 4b1113allvm/include/llvm-c Core.h, llvm/include/llvm/IR Instructions.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+76-0llvm/test/Transforms/SimplifyCFG/switch-dedup.ll
+22-13llvm/include/llvm/IR/Instructions.h
+18-15llvm/lib/IR/Instructions.cpp
+24-0llvm/include/llvm-c/Core.h
+23-0llvm/unittests/IR/InstructionsTest.cpp
+10-10llvm/lib/IR/User.cpp
+173-3810 files not shown
+236-5916 files

LLVM/project 6d38c87clang/docs ReleaseNotes.rst, clang/lib/CodeGen CGCall.cpp

Revert "[clang] Limit lifetimes of temporaries to the full expression (#170517)"

This reverts commit 5daad5bf45b3c7280f7b06979fb580f70e2c4fd0.

That commit caused broken compilation for some cases, see
https://github.com/llvm/llvm-project/pull/170517#issuecomment-3620079591.
DeltaFile
+0-98clang/test/CodeGen/lifetime-call-temp.c
+0-50clang/test/CodeGen/lifetime-invoke-c.c
+0-47clang/test/CodeGenCXX/aggregate-lifetime-invoke.cpp
+1-21clang/lib/CodeGen/CGCall.cpp
+0-19clang/test/CodeGenCXX/amdgcn-call-with-aggarg.cc
+0-9clang/docs/ReleaseNotes.rst
+1-2444 files not shown
+1-26110 files

LLVM/project 404a903clang-tools-extra/clang-tidy/tool check_alphabetical_order.py check_alphabetical_order_test.py

[clang-tidy] Show descriptive error message when check_alphabetical_order.py fails (#170975)

Now we give clearer instructions on how to interpret the output of the
script to fix issues it reported
DeltaFile
+16-7clang-tools-extra/clang-tidy/tool/check_alphabetical_order.py
+10-3clang-tools-extra/clang-tidy/tool/check_alphabetical_order_test.py
+26-102 files

LLVM/project 830ef4eopenmp/cmake/modules LibompUtils.cmake, openmp/module omp_lib.h.var omp_lib.F90.var

[openmp][NFCI] Move .mod code out of runtimes subdir (#169909)

Extracted out of #169638. The motivation is that we want to build
Fortran module files for device triples (amdgpu-amd-amdhsa and
nvptx64-nvidia-cuda) as well, but the runtimes/ directory is only
included for host devices.

This PR itself should not change anything, including that omp_lib.mod is
only built on host devices triple. Some dependencies used for building
omp_lib.mod are hoisted out of runtimes/ as well. IMHO they all make
sense to hoist, e.g. LIBOMP_VERSION_MAJOR/LIBOMP_VERSION_MINOR should be
usable in the entire OpenMP subproject.
DeltaFile
+0-1,298openmp/runtime/src/include/omp_lib.h.var
+1,298-0openmp/module/omp_lib.h.var
+0-1,183openmp/runtime/src/include/omp_lib.F90.var
+1,183-0openmp/module/omp_lib.F90.var
+0-210openmp/runtime/cmake/LibompUtils.cmake
+210-0openmp/cmake/modules/LibompUtils.cmake
+2,691-2,69110 files not shown
+3,019-2,99916 files

LLVM/project 423af42utils/bazel/llvm-project-overlay/lldb BUILD.bazel, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix bazel build for 979462c876c96c3023c0b5e42c8eda88323fd745
DeltaFile
+0-13utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-3utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
+4-162 files

LLVM/project 728f906llvm/include/llvm/Passes PassPlugin.h

Fix Clang warning

Created using spr 1.3.5-bogner
DeltaFile
+8-0llvm/include/llvm/Passes/PassPlugin.h
+8-01 files

LLVM/project 5cd1aa0

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]
DeltaFile
+0-00 files

LLVM/project af27159clang-tools-extra/test/clang-tidy/infrastructure alphabetical-order.test

[clang-tidy] Show correct diff instructions when check_alphabetical_order.py fails (#170971)

Before the change, when given such incorrect ordering:
```
   :doc:`modernize-use-designated-initializers <modernize/use-designated-initializers>`, "Yes"
   :doc:`modernize-use-equals-default <modernize/use-equals-default>`, "Yes"
   :doc:`modernize-use-emplace <modernize/use-emplace>`, "Yes"
   :doc:`modernize-use-equals-delete <modernize/use-equals-delete>`, "Yes"
   :doc:`modernize-use-integer-sign-comparison <modernize/use-integer-sign-comparison>`, "Yes"
```
Script output suggested removing `modernize-use-equals-default` line
that came after `modernize-use-emplace` but in my actual file, we can
see that current ordering is different (same as 2nd part of the diff):
```
# |      :doc:`modernize-use-constraints <modernize/use-constraints>`, "Yes"
# |      :doc:`modernize-use-default-member-init <modernize/use-default-member-init>`, "Yes"
# |      :doc:`modernize-use-designated-initializers <modernize/use-designated-initializers>`, "Yes"
# |      :doc:`modernize-use-emplace <modernize/use-emplace>`, "Yes"
# | -    :doc:`modernize-use-equals-default <modernize/use-equals-default>`, "Yes"

    [13 lines not shown]
DeltaFile
+2-2clang-tools-extra/test/clang-tidy/infrastructure/alphabetical-order.test
+2-21 files

LLVM/project dda0486mlir/docs LangRef.md

[MLIR] Update broken link in LangRef.md (#170938)

Noticed the link was dead when reading the docs. According to the
wayback machine, it was a link to "Revisiting Out-of-SSA Translation for
Correctness, Code Quality, and Efficiency" by Boissinot et al., so
providing a more permanent link.
DeltaFile
+1-1mlir/docs/LangRef.md
+1-11 files

LLVM/project 9dc8caeutils/bazel/llvm-project-overlay/llvm BUILD.bazel

[bazel] Port 979462c876c96c3023c0b5e42c8eda88323fd745
DeltaFile
+0-13utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+0-131 files

LLVM/project 979462cllvm/lib/Target/AMDGPU InstCombineTables.td AMDGPUSearchableTables.td, llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU BUILD.gn

[AMDGPU] Eliminate InstCombineTables.td. NFC. (#170857)

This also eliminates the generated file InstCombineTables.inc which was
99% identical to the existing AMDGPUGenSearchableTables.inc.
DeltaFile
+0-10llvm/lib/Target/AMDGPU/InstCombineTables.td
+9-0llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+0-6llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
+0-4llvm/lib/Target/AMDGPU/CMakeLists.txt
+1-1llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+10-215 files

LLVM/project fa2eabdclang/test/Headers __clang_hip_math.hip, llvm/lib/Transforms/Utils SimplifyCFG.cpp

[SimplifyCFG] Hoist common code for switch multi-case destinations (#165700)

Previously, hoistCommonCodeFromSuccessors did not support hoisting
common code for multi-case destinations of `switch`.

However, if all the predecessors of a given Succ are the same (i.e.,
multi-case destination), it is safe to hoist the common code from Succ
to Pred, which is what this PR does.

See discussion
https://github.com/llvm/llvm-project/pull/165570#discussion_r2473290327.
Alive2 proof: https://alive2.llvm.org/ce/z/cYuczq
Optimization Impact:
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/3003
DeltaFile
+180-201clang/test/Headers/__clang_hip_math.hip
+27-17llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+35-5llvm/test/Transforms/SimplifyCFG/hoist-common-code.ll
+242-2233 files

LLVM/project 5fc8e87mlir/include/mlir/Dialect/XeGPU/IR XeGPUOps.td, mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp

[MLIR][XeGPU] Retain anchor op layouts for XeGPU nD ops (#170934)

This PR adds support to retain the anchor op layouts (after dropping
what's not required) for xegpu nD ops during workgroup to subgroup &
unroll transformation
DeltaFile
+12-3mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
+9-6mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+12-3mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+13-0mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+8-4mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+6-3mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+60-192 files not shown
+64-228 files

LLVM/project 8fe38c4clang/lib/AST/ByteCode Pointer.cpp Interp.h

[clang][bytecode] Allocate InitMaps via Program/InterpState allocators (#170272)

Save them as a pointer intead of using a shared_ptr. This we we can use
the pointer integer value to differentiate the "no initmap yet" and "all
values initialzed" cases.

This regresses one test case in const-eval.c, but as it turns out, that
only worked coincidentally before.
DeltaFile
+57-67clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+20-38clang/lib/AST/ByteCode/Descriptor.cpp
+20-19clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+26-6clang/lib/AST/ByteCode/Descriptor.h
+11-9clang/lib/AST/ByteCode/Pointer.h
+165-1706 files not shown
+185-18812 files

LLVM/project 75aa7bdcompiler-rt/test/asan/TestCases scariness_score_test.cpp

[ASan] Disable another test on Darwin due to ulimit stack issues

Similar to #170786.
DeltaFile
+4-0compiler-rt/test/asan/TestCases/scariness_score_test.cpp
+4-01 files

LLVM/project 9e9e64aclang/lib/CodeGen CGOpenMPRuntime.cpp, clang/test/OpenMP target_firstprivate_pointer_codegen.cpp target_defaultmap_codegen_01.cpp

[OpenMP] Fix defaultmap(firstprivate:pointer) handling  (#169622)

This fixes a bug where pointers from defaultmap(firstprivate:pointer)
were incorrectly treated as firstprivate literals, causing
OMP_MAP_LITERAL to be set. This prevented the runtime from performing
device address lookup.
Realted PR https://github.com/llvm/llvm-project/pull/167879

Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net>
DeltaFile
+169-0clang/test/OpenMP/target_firstprivate_pointer_codegen.cpp
+65-12clang/lib/CodeGen/CGOpenMPRuntime.cpp
+2-2clang/test/OpenMP/target_defaultmap_codegen_01.cpp
+1-1clang/test/OpenMP/target_map_codegen_26.cpp
+237-154 files

LLVM/project 58b319bclang/lib/CIR/Analysis FallThroughWarning.cpp, clang/lib/Frontend CompilerInvocation.cpp

[CIR][Analyzer] Revamping codebase and switch implementation
DeltaFile
+159-63clang/lib/CIR/Analysis/FallThroughWarning.cpp
+141-0clang/test/CIR/Analysis/fallthrough_2.cir
+6-0clang/lib/Frontend/CompilerInvocation.cpp
+3-2clang/test/CIR/Analysis/fallthrough_switch.c
+3-0clang/lib/Sema/SemaDecl.cpp
+1-1clang/test/CIR/Analysis/fallthrough_1.c
+313-662 files not shown
+316-678 files

LLVM/project b889df3llvm/lib/Transforms/Instrumentation MemProfUse.cpp, llvm/test/Transforms/PGOProfile memprof-dump-matched-alloc-site.ll

[MemProf] Add option to print function GUIDs during matching (#170946)

For debugging, add -memprof-print-function-guids option that will cause
memprof matching to emit the computed function GUID for every function
definition in the module to stderr. This is helpful because the profile
only contains the function GUID and not the names.
DeltaFile
+8-0llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
+5-2llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
+13-22 files

LLVM/project 06f9deellvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,628 files not shown
+211,870-242,6594,634 files

LLVM/project 367ebafllvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,626 files not shown
+211,867-242,6564,632 files

LLVM/project e5397f1mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp, mlir/test/Dialect/XeGPU subgroup-distribute-unit.mlir subgroup-distribute.mlir

add unit tests and fix bugs
DeltaFile
+40-28mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+65-0mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
+1-1mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
+106-293 files

LLVM/project 23591c3llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,626 files not shown
+211,867-242,6564,632 files

LLVM/project 9e98712llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,625 files not shown
+211,863-242,6524,631 files

LLVM/project 58c6006llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,998-11,093llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,981-11,098llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,734-0llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+1,529-1,529llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+46,489-44,4934,625 files not shown
+211,863-242,6524,631 files