LLVM/project 2045520llvm/lib/Target/AArch64 AArch64InstrGISel.td, llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp AArch64RegisterBankInfo.cpp

[GlobalISel][AArch64] Added support for sli intrinsic

sli intrinsic now lowers correctly for all vector types.
DeltaFile
+0-10llvm/test/CodeGen/AArch64/arm64-vshift.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrGISel.td
+6-1llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+2-0llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+15-114 files

LLVM/project fe68fb6llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 atomic-ops.ll

[AArch64] Make the list of LSE supported operations explicit (#171126)

Similar to #167760 this makes the list of LSE atomics explicit in case
new operations are added in the future. UIncWrap, UDecWrap, USubCond and
USubSat are excluded.

Fixes #170450
DeltaFile
+1,590-468llvm/test/CodeGen/AArch64/atomic-ops.ll
+19-5llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1,609-4732 files

LLVM/project d478baallvm/include/llvm-c Core.h, llvm/include/llvm/CAS ObjectStore.h ActionCache.h

Add more missing `LLVM_ABI` annotations (#168765)

This patch updates various LLVM headers to properly add the `LLVM_ABI`
and `LLVM_ABI_FOR_TEST` annotations ot build LLVM as a DLL on Windows.

This effort is tracked in #109483.
DeltaFile
+22-22llvm/lib/Transforms/Vectorize/VPlan.h
+8-6llvm/include/llvm-c/Core.h
+3-3llvm/include/llvm/IR/RuntimeLibcalls.h
+2-2llvm/include/llvm/SandboxIR/Instruction.h
+2-1llvm/include/llvm/CAS/ObjectStore.h
+1-1llvm/include/llvm/CAS/ActionCache.h
+38-351 files not shown
+39-357 files

LLVM/project 95e6edcmlir/lib/Dialect/NVGPU/TransformOps NVGPUTransformOps.cpp

[MLIR] Apply clang-tidy fixes for performance-unnecessary-copy-initialization in NVGPUTransformOps.cpp (NFC)
DeltaFile
+1-1mlir/lib/Dialect/NVGPU/TransformOps/NVGPUTransformOps.cpp
+1-11 files

LLVM/project 257417emlir/tools/mlir-irdl-to-cpp mlir-irdl-to-cpp.cpp

[MLIR] Apply clang-tidy fixes for readability-container-size-empty in mlir-irdl-to-cpp.cpp (NFC)
DeltaFile
+1-1mlir/tools/mlir-irdl-to-cpp/mlir-irdl-to-cpp.cpp
+1-11 files

LLVM/project e3cf462mlir/lib/Dialect/Linalg/TransformOps LinalgTransformOps.cpp

[MLIR] Apply clang-tidy fixes for llvm-else-after-return in LinalgTransformOps.cpp (NFC)
DeltaFile
+2-1mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
+2-11 files

LLVM/project 7f6c907mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir] Fix -Wparentheses warning [NFC]

Without this gcc warned
 ../../mlir/lib/Dialect/SCF/IR/SCF.cpp:3748:70: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
DeltaFile
+3-3mlir/lib/Dialect/SCF/IR/SCF.cpp
+3-31 files

LLVM/project f90fe01llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[OpenMP] Fix -Wparentheses warning [NFC]

Without this gcc warned
 ../lib/Frontend/OpenMP/OMPIRBuilder.cpp:5082:45: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
DeltaFile
+1-1llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+1-11 files

LLVM/project 4572f4fllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU lds-dma-waits.ll

Revert "[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)"

Fails on https://lab.llvm.org/buildbot/#/builders/123/builds/31922

This reverts commit bf9344099c63549b2f19f8ede29f883669b0baca.
DeltaFile
+280-309llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+4-4llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
+284-3132 files

LLVM/project 2766002llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 arm64-cvt-simd-round-rint-strictfp.ll arm64-cvt-simd-round-rint.ll

[AArch64]SIMD fpcvt codegen for rounding nodes (#165546)

This is followup patch to
https://github.com/llvm/llvm-project/pull/157680, which allows simd
fpcvt instructions to be generated from l/llround and l/llrint nodes.
DeltaFile
+286-0llvm/test/CodeGen/AArch64/arm64-cvt-simd-round-rint-strictfp.ll
+286-0llvm/test/CodeGen/AArch64/arm64-cvt-simd-round-rint.ll
+43-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+615-03 files

LLVM/project 1b82c16clang/lib/Sema SemaARM.cpp, clang/test/AST attr-target-version.c

[FMV][AArch64] Allow user to override version priority. (#150267)

Implements https://github.com/ARM-software/acle/pull/404

This allows the user to specify "featA+featB;priority=[1-255]" where
priority=255 means highest priority. If the explicit priority string is
omitted then the priority of "featA+featB" is implied, which is lower
than priority=1.

Internally this gets expanded using special FMV features P0 ... P7 which
can encode up to 256-1 priority levels (excluding all zeros). Those do
not have corresponding detection bit at pos FEAT_#enum so I made this
field optional in FMVInfo. Also they don't affect the codegen or name
mangling of versioned functions.
DeltaFile
+204-0clang/test/CodeGen/AArch64/fmv-explicit-priority.c
+71-1llvm/test/Transforms/GlobalOpt/resolve-fmv-ifunc.ll
+57-8clang/lib/Sema/SemaARM.cpp
+20-11llvm/lib/TargetParser/AArch64TargetParser.cpp
+26-4clang/test/AST/attr-target-version.c
+14-3llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+392-2718 files not shown
+509-4924 files

LLVM/project d300eb6utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy BUILD.bazel

Fix bazel build for ff59ecd8856f5501ba90850baa4b0f0d4d309bad
DeltaFile
+1-0utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
+1-01 files

LLVM/project ec4cc34bolt/include/bolt/Core BinaryBasicBlock.h, bolt/test/AArch64 long-jmp-bti.s long-jmp-bti-ignored.s

[BOLT] Updates

- fix format
- add comments
DeltaFile
+11-11bolt/test/AArch64/long-jmp-bti.s
+3-0bolt/test/AArch64/long-jmp-bti-ignored.s
+1-1bolt/include/bolt/Core/BinaryBasicBlock.h
+15-123 files

LLVM/project 719d079mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc TosaOps.td, mlir/test/Dialect/Tosa tosa-validation-version-1p1-valid.mlir invalid_extension.mlir

[mlir][tosa] Remove EXT_MXFP support for cast (#167301)

This was removed in the specification by:
https://github.com/arm/tosa-specification/pull/11
DeltaFile
+0-16mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+1-9mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+0-7mlir/test/Dialect/Tosa/invalid_extension.mlir
+1-1mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+1-1mlir/test/Dialect/Tosa/availability.mlir
+3-345 files

LLVM/project bb8cf7aclang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files

LLVM/project 4e5c83bllvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,111-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,098-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+80-19llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,291-194 files

LLVM/project e163cb4llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

[AMDGPU] Add wave reduce intrinsics for double types - 1

Supported Ops: `min`, `max`
DeltaFile
+1,280-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+1,280-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+65-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,627-14 files

LLVM/project 1cbed4fllvm/lib/Target/AMDGPU VOP3PInstructions.td

[NFC][AMDGPU] Remove unused TableGen generated enum (#171170)

This GenericEnum was just adding separate values for VOP3P_Pseudo
opcodes in the same namespace as existing opcodes that did not match.
They were defined in AMDGPUGenSearchableTables.inc by tablegen emitter
but were guarded out by #ifdef. Because of that, they were never
included in the code, so the compiler never reported the naming
conflict and the bug never had a chance to surface.
DeltaFile
+0-6llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+0-61 files

LLVM/project 4c1d189bolt/test/runtime/AArch64 pacret-synchronous-unwind.cpp

Update bolt/test/runtime/AArch64/pacret-synchronous-unwind.cpp
DeltaFile
+1-1bolt/test/runtime/AArch64/pacret-synchronous-unwind.cpp
+1-11 files

LLVM/project bf93440llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU lds-dma-waits.ll

[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)

The pass was already "reinventing" the concept just to deal with 16 bit
registers. Clean up the entire tracking logic to only use register
units.

There are no test changes because functionality didn't change, except:
- We can now track more LDS DMA IDs if we need it (up to `1 << 16`)
- The debug prints also changed a bit because we now talk in terms of
register units.

This also changes the tracking to use a DenseMap instead of a massive
fixed size table. This trades a bit of access speed for a smaller memory
footprint. Allocating and memsetting a huge table to zero caused a
non-negligible performance impact (I've observed up to 50% of the time
in the pass spent in the `memcpy` built-in on a big test file).

I also think we don't access these often enough to really justify using
a vector. We do a few accesses per instruction, but not much more. In a
huge 120MB LL file, I can barely see the trace of the DenseMap accesses.
DeltaFile
+309-280llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+4-4llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
+313-2842 files

LLVM/project b1ef2dblldb/docs/use/tutorials script-driven-debugging.md writing-custom-commands.md

[lldb][docs] Fix header level warnings in a few documents

All these are using H1 for the main heading but H3 for the
rest, Sphinx warns about this:
WARNING: Non-consecutive header level increase; H1 to H3 [myst.header]
DeltaFile
+11-11lldb/docs/use/tutorials/script-driven-debugging.md
+6-6lldb/docs/use/tutorials/writing-custom-commands.md
+5-5lldb/docs/use/tutorials/implementing-standalone-scripts.md
+4-4lldb/docs/use/tutorials/creating-custom-breakpoints.md
+26-264 files

LLVM/project afb3852lldb/docs/use variable.rst

[lldb][docs] Fix title formatting in Variable document
DeltaFile
+1-1lldb/docs/use/variable.rst
+1-11 files

LLVM/project 2cb8e52lldb/docs/resources contributing.rst

[lldb][docs] Fix plain text markers in Contributing

RST tries to resolve things in single backticks to a reference,
which is not the intention here. Double backticks indicates
plain text formatting.

Fixes warnings in the docs build:
contributing.rst:92: WARNING: 'any' reference target not found: A1
contributing.rst:92: WARNING: 'any' reference target not found: B1
contributing.rst:92: WARNING: 'any' reference target not found: B2
contributing.rst:92: WARNING: 'any' reference target not found: A2
contributing.rst:95: WARNING: 'any' reference target not found: A1->B1
contributing.rst:95: WARNING: 'any' reference target not found: B2->C2
contributing.rst:95: WARNING: 'any' reference target not found: C3->A3
contributing.rst:100: WARNING: 'any' reference target not found: LLDB_ACCEPTABLE_PLUGIN_DEPENDENCIES
contributing.rst:100: WARNING: 'any' reference target not found: LLDB_TOLERATED_PLUGIN_DEPENDENCIES
DeltaFile
+5-5lldb/docs/resources/contributing.rst
+5-51 files

LLVM/project 95bd878llvm/test/tools/llvm-mca/AArch64/Neoverse V3AE-neon-instructions.s V3-neon-instructions.s

[llvm-mca][AArch64] Merge Neoverse NEON tests (NFC) (#170881)

Follow-on from #170324 to also refactor the NEON tests to reuse the
input assembly across all Neoverse cores.

The approach is as follows:

- Inputs for Neoverse N1/N2/N3 NEON tests are already identical, so
  first combine those.
- Inputs for V2/V3/V3AE NEON tests are also already identical, but
  differ from N-cores, so combine those separately.
- Most significantly, input for V1 differs from all other cores
  primarily because of 24f0901 (#128892).
- Split out features that are not supported across all cores.
  - Split out FEAT_I8MM, FEAT_FHM, FEAT_FCMA. N1 doesn't have this
    feature but all other Neoverse cores do. Also adds coverage for
    N2/N3 since they were missing tests.
  - Split out FEAT_BF16. V1 doesn't have this feature but all other
    Neoverse cores do. Also adds coverage for N1/N2/N3 since they were

    [23 lines not shown]
DeltaFile
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s
+5,340-7,29336 files not shown
+8,764-8,94542 files

LLVM/project 870aa89lldb/docs/use/tutorials custom-frame-recognizers.md script-driven-debugging.md

[lldb][docs] Remove syntax hint from some output blocks

This tries to parse the block as that language but in these
cases fails because they aren't purely that language. This
falls back to a permissive mode which is fine, but highlights
the invalid tokens like errors which isn't great.

Instead don't try to highlight these blocks. This fixes 4
warnings seen in the docs build:
lldb/docs/use/tutorials/custom-frame-recognizers.md:43: WARNING: Lexing literal_block <...> as "c++" resulted in an error at token: '#'. Retrying in relaxed mode.
lldb/docs/use/tutorials/script-driven-debugging.md:175: WARNING: Lexing literal_block <...> as "c++" resulted in an error at token: '#'. Retrying in relaxed mode.
lldb/docs/use/tutorials/script-driven-debugging.md:426: WARNING: Lexing literal_block <...> as "c++" resulted in an error at token: '#'. Retrying in relaxed mode.
lldb/docs/use/tutorials/writing-custom-commands.md:416: WARNING: Lexing literal_block <...> as "python3" resulted in an error at token: '$'. Retrying in relaxed mode.
DeltaFile
+2-2lldb/docs/use/tutorials/custom-frame-recognizers.md
+2-2lldb/docs/use/tutorials/script-driven-debugging.md
+1-1lldb/docs/use/tutorials/writing-custom-commands.md
+5-53 files

LLVM/project 4e94198clang-tools-extra/clangd SemanticSelection.cpp SemanticSelection.h, clang-tools-extra/clangd/unittests SemanticSelectionTests.cpp

[clangd] Remove the unused AST-based code folding Implementation. (#166189)

In clangd, we use the non-ast version one.
DeltaFile
+0-78clang-tools-extra/clangd/SemanticSelection.cpp
+0-70clang-tools-extra/clangd/unittests/SemanticSelectionTests.cpp
+0-4clang-tools-extra/clangd/SemanticSelection.h
+0-1523 files

LLVM/project 31c03c9lldb/docs/use variable.rst

[lldb][docs] Fix plaintext marker in variables doc

Single backtick tries to make a reference to something
and if that fails, renders as plain text.

These 3 weren't finding a reference and so produced
a warning:
variable.rst:975: WARNING: 'any' reference target not found: max_children
DeltaFile
+3-3lldb/docs/use/variable.rst
+3-31 files

LLVM/project 9a971ccllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 fp-to-int-to-fp.ll

[DAGCombiner] Relax nsz constraint with fp->int->fp optimizations
DeltaFile
+18-124llvm/test/CodeGen/X86/setoeq.ll
+21-0llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
+2-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+41-1253 files

LLVM/project 9c83428clang-tools-extra/clang-tidy/google CMakeLists.txt

[clang-tidy] Add missing Modernize module to Google module link libs (#171427)

Fixes failures in
https://github.com/llvm/llvm-project/pull/171058#issuecomment-3631809933
DeltaFile
+1-0clang-tools-extra/clang-tidy/google/CMakeLists.txt
+1-01 files

LLVM/project 43d71eellvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 fp-to-int-to-fp.ll

[DAGCombiner] Relax nsz constraint with fp->int->fp optimizations
DeltaFile
+18-124llvm/test/CodeGen/X86/setoeq.ll
+21-0llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
+2-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+41-1253 files