LLVM/project 77c27bdllvm/lib/Passes RunCodeGen.cpp

fix

Created using spr 1.3.7
DeltaFile
+10-2llvm/lib/Passes/RunCodeGen.cpp
+10-21 files

LLVM/project d821765clang/docs ReleaseNotes.md, clang/lib/AST ASTContext.cpp

[Clang] Fix BitInt padding clearing on big-endian targets (#215809)

This patch fixes the padding clearing logic of `_BitInt`s.

Before this patch, the clearing logic assumed little endian. But the
memory layout of BitInts differs between little and big endian:

- In LE, the occupied bits start from the lowest address and go on
contiguously up until the BitInt's declared size. The padding bits then
start from that point and go contiguously until the end of the storage
unit.
- In BE, since the byte order is reversed, the occupied bit interval is
not contiguous if the storage unit is larger than the BitInt's size.

Therefore, the logic must tell the two cases apart and perform the
calculations accordingly.
DeltaFile
+81-0clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+81-0clang/test/CodeGen/builtin-clear-padding-codegen.c
+46-0clang/lib/AST/ASTContext.cpp
+2-0clang/docs/ReleaseNotes.md
+210-04 files

LLVM/project 57998a6flang/include/flang/Optimizer/Analysis AliasAnalysis.h, flang/lib/Optimizer/Analysis AliasAnalysis.cpp

[flang][AliasAnalysis] Relax AliasAnalysis for host associated allocatables (#220826)

Relax AliasAnalysis for host associated allocatables.

FIR alias analysis conservatively returns MayAlias for values with
distinct host-associated origins because their storage may overlap
through EQUIVALENCE.

This change utilizes the fact that an equivalence object cannot be an
allocatable and relaxes the analysis for them. Specifically, if two
values have distinct host associated origin, neither is a pointer or a
target and at least one of them is an allocatable, we can safely declare
them NoAlias. Otherwise, we continue to conservatiely declare them
MayAlias.

Assisted-by: Codex
DeltaFile
+65-0flang/test/Analysis/AliasAnalysis/alias-analysis-host-assoc.fir
+23-1flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+4-0flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
+92-13 files

LLVM/project 8da3092clang/test/OpenMP interchange_codegen.cpp, llvm/lib/Target/Hexagon HexagonDepMask.h

Merge branch 'main' into users/adams381/cir-callconv-byval-noalias
DeltaFile
+17,282-3,458llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-sve-instructions.s
+7,983-1,591llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-neon-instructions.s
+1,738-2,433clang/test/OpenMP/interchange_codegen.cpp
+3,312-825llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+2,226-1,164llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+0-2,819llvm/lib/Target/Hexagon/HexagonDepMask.h
+32,541-12,2901,701 files not shown
+111,917-46,0611,707 files

LLVM/project b77f97allvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

[AMDGPU] PromoteAlloca: split scalar accesses that span several elements

promoteAllocaToVector already splits a *vector* access across several
elements when it is a multiple of the element size, but a *scalar* access
had to be bitcastable to the element type, so an i64 load from an alloca
promoted to <8 x i32> was rejected as "not a supported access type" and
the object stayed in scratch.

Accept a scalar access that is a whole multiple of the element size and
route it through the existing subvector path, which already builds the
value from consecutive elements and bitcasts. Accesses with padding are
still rejected, since splitting those would put the pieces at the wrong
offsets, as are non-integer non-float types.
DeltaFile
+78-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+28-4llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+106-42 files

LLVM/project 58fc73dllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Refactor to enable scalars inline instead of seperate helper function
DeltaFile
+23-38llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+50-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+73-382 files

LLVM/project ebaf9d9llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Testing updates per PR feedback, add some new test cases
DeltaFile
+87-6llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+87-61 files

LLVM/project 90d81acclang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/CodeGen call-conv-lowering-x86_64-empty.cpp

[CIR] Fix CIR tests after recent ABI change (#220749)

A recent change to unnamed bitfield classification for X86 targets
(https://github.com/llvm/llvm-project/pull/216777) broke several CIR
tests.

This change updates two of the failing tests to reflect the current
state. Further cleanup is needed in CIR after the ABI backward
compatibility issues are handled.

A third test was failing with an assertion because the unnamed bitfield
classification change exposed a problem in CIR's type mapper. We were
modeling unnamed zero-length bitfields as having the width of their
declared type rather than zero width. This triggered an assertion in the
ABI library after such bitfields were no longer skipped. This change now
reports zero width for such fields.
DeltaFile
+12-6clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+6-3clang/test/CIR/CodeGen/call-conv-lowering-x86_64-empty.cpp
+4-3clang/test/CIR/Transforms/abi-lowering/x86_64-struct-padded.cir
+22-123 files

LLVM/project 2e1201fflang/lib/Lower/OpenMP OpenMP.cpp, mlir/include/mlir/Dialect/OpenMP OpenMPOpsInterfaces.td

[MLIR][OpenMP] DeclareTargetInterface and DeclareTargetAttr cleanup

The changes introduced by this patch are intended to avoid triggering
multiple by name lookups to the "omp.declare_target" attribute every
time any data from the `DeclareTargetInterface` is queried, remove the
need for keeping multiple default values for the same data, clean up
the assembly format and generally improve the usage of the interface.

List of changes:
- `DeclareTargetInterface` only provides `setDeclareTarget` and
  `getDeclareTarget` methods to handle the "omp.declare_target"
  attribute, maintaining a single canonical way of accessing it.
- `DeclareTargetAttr` provides direct access to the capture clause and
  device type enums, rather than wrapping them into an `Attribute`.
  These are now mandatory as well. Both changes together make accessing
  them more straightforward and simplify the attribute representation.
DeltaFile
+15-61mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
+25-19mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+10-6mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
+8-5flang/lib/Lower/OpenMP/OpenMP.cpp
+4-4mlir/test/Dialect/OpenMP/invalid-interface.mlir
+5-3mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
+67-9812 files not shown
+103-12518 files

LLVM/project 5c9830cflang/lib/Lower ConvertVariable.cpp, flang/test/Fir/OpenACC acc-declare-gpu-module-insertion.fir

[flang][OpenACC] Emit module PARAMETERs as initialized linkonce_odr globals (#220666)

Emit an initialized linkonce_odr global from the module-file value in
each compilation unit that needs a module PARAMETER (follow USE
association so the initializer is not lost). Separately compiled uses
under OpenACC default(present) then keep the constant on the device
instead of treating a bodyless external as data that must already be
present.

Keep external linkage when the PARAMETER has an explicit !$acc declare
or a CUDA data attribute, which need a single shared device symbol
rather than a per-unit copy.
DeltaFile
+90-0flang/test/Lower/module-parameter-linkonce-odr.f90
+57-11flang/test/Fir/OpenACC/acc-declare-gpu-module-insertion.fir
+46-0flang/test/Transforms/OpenACC/acc-implicit-declare-module-parameter.fir
+23-2flang/lib/Lower/ConvertVariable.cpp
+2-1flang/test/Integration/function-sections.f90
+1-1flang/test/Lower/dense-attributed-array.f90
+219-156 files

LLVM/project df9e068openmp/device CMakeLists.txt

[OpenMP][CMake] Fix the device runtime build with LLVM_USE_SPLIT_DWARF (#220322)

Building with LLVM_USE_SPLIT_DWARF fails in the GPU runtimes:

  ld.lld: error: -r and --gdb-index may not be used together

HandleLLVMOptions appends -Wl,--gdb-index to CMAKE_EXE_LINKER_FLAGS, and
libompdevice is an add_executable, so it inherits the flag. Its link is
not a real link at all: -flto -r -Wl,--lto-emit-llvm merges the objects
into a single bitcode file, for which a gdb index is meaningless.

Fix is to turn it off for the target.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+6-1openmp/device/CMakeLists.txt
+6-11 files

LLVM/project 16a644dflang/include/flang/Semantics openmp-modifiers.h, flang/lib/Semantics check-omp-structure.h check-omp-variant.cpp

[flang][OpenMP] Remove now unused OmpVerifyModifiers

Its functionality has been subsumed by VerifyModifiers.
DeltaFile
+164-269flang/lib/Semantics/check-omp-structure.cpp
+44-49flang/lib/Semantics/check-omp-loop.cpp
+0-6flang/include/flang/Semantics/openmp-modifiers.h
+1-3flang/lib/Semantics/check-omp-variant.cpp
+0-2flang/lib/Semantics/check-omp-structure.h
+209-3295 files

LLVM/project f330760flang/lib/Semantics check-omp-structure.h check-omp-syntax.cpp, llvm/include/llvm/Frontend/OpenMP OMPDescriptors.h.inc OMPDescriptors.h

[flang][OpenMP] Implement modifier set and modifier group verification

Introduce modifier set and group definitions, and include that information
in clause descriptors.

Extend the verification of syntactic properties to handle sets and groups.
DeltaFile
+676-590llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+133-27flang/lib/Semantics/check-omp-syntax.cpp
+47-0llvm/include/llvm/Frontend/OpenMP/OMPDescriptors.h
+32-1llvm/lib/Frontend/OpenMP/OMPDescriptors.cpp
+17-0llvm/include/llvm/Frontend/OpenMP/OMPDescriptors.h.inc
+6-4flang/lib/Semantics/check-omp-structure.h
+911-6221 files not shown
+912-6227 files

LLVM/project 7e4c96dflang/lib/Semantics check-omp-structure.cpp, flang/test/Semantics/OpenMP ordered01.f90

Restore checks on cross-clause SOURCE/SINK
DeltaFile
+35-2flang/lib/Semantics/check-omp-structure.cpp
+3-0flang/test/Semantics/OpenMP/ordered01.f90
+38-22 files

LLVM/project 72066b7flang/test/Semantics/OpenMP ordered01.f90

Restore original order of checks
DeltaFile
+1-1flang/test/Semantics/OpenMP/ordered01.f90
+1-11 files

LLVM/project eeb9bb7flang/include/flang/Parser parse-tree.h, flang/include/flang/Semantics openmp-modifiers.h

[flang][OpenMP] Replace modifier verification with a generic one

Implement verification of syntactic properties (i.e. required, unique,
exclusive, ultimate) in a generic way, agnostic of the kind of element
to which these properties are applied. The goal here is to reuse it
for verifying clause properties in the future.

Refactor the existing modifier verification code to use it. Modify
the previous implementation (OmpVerifyModifiers) to always succeed
to reduce the amount of necessary changes.
DeltaFile
+439-0flang/lib/Semantics/check-omp-syntax.cpp
+2-366flang/include/flang/Semantics/openmp-modifiers.h
+19-44flang/lib/Semantics/check-omp-structure.cpp
+50-9flang/include/flang/Parser/parse-tree.h
+20-34flang/test/Parser/OpenMP/dims-modifier.f90
+32-1flang/lib/Semantics/check-omp-structure.h
+562-4547 files not shown
+580-45913 files

LLVM/project c440d9cllvm/lib/Transforms/Scalar GVN.cpp

[fixup] Do not use the heavy WeakVH for observing  Else-block barriers
DeltaFile
+31-6llvm/lib/Transforms/Scalar/GVN.cpp
+31-61 files

LLVM/project 0a3955cflang/test/Driver fveclib.f90

[flang][test] Expect a single -rpath in fveclib.f90 ArmPL check (#220969)

Fixes a `check-flang` failure on main: `Flang :: Driver/fveclib.f90`.

#220697 consolidated `tools::addArchSpecificRPath()` down to a single
call site — it was removed from `ToolChain::addFlangRTLibPath()` and
from the `-fveclib=ArmPL` block in `tools::AddLinkerInputs()`, and one
unconditional call was hoisted to the end of `AddLinkerInputs()`. A link
line can therefore emit each candidate rpath at most once, so
`CHECK-RPATH-ARMPL` fails on its second `-rpath` match:

```
flang/test/Driver/fveclib.f90:59:27: error: CHECK-RPATH-ARMPL-SAME: expected string not found in input
! CHECK-RPATH-ARMPL-SAME: "-rpath"
                          ^
```

The two matches only ever passed because `addArchSpecificRPath()` is a
pure function of the toolchain and the argument list, so the two former

    [10 lines not shown]
DeltaFile
+0-2flang/test/Driver/fveclib.f90
+0-21 files

LLVM/project 35f6bd6offload/plugins-nextgen/level_zero/dynamic_l0 L0DynWrapper.cpp, offload/plugins-nextgen/level_zero/dynamic_l0/level_zero ze_api.h

[offload][l0] Report actual driver version through OL_DEVICE_INFO_DRIVER_VERSION (#218412)

The Level Zero plugin currently reports the Level Zero API version as
the driver version. Moreover, as the lookup table only includes API
versions up to `1.12`, newer versions (e.g. `1.15`) end up being
reported as Unknown.

Report the actual driver version instead:

- If the `zeIntelGetDriverVersionString` extension is available, use it.
This string may be more detailed than what `zeDriverGetProperties`
provides (e.g. hotfix suffix)
- If the above is not available, use
`zeDriverGetProperties().driverVersion`, an U32 value whose octets make
up major, minor & build numbers.
- The driver version is fetched once per context and stored in an
`std::string` inside of the `L0ContextTy`.

This is intended to match the behavior of Intel's Unified Runtime.

    [5 lines not shown]
DeltaFile
+38-0offload/plugins-nextgen/level_zero/src/L0Context.cpp
+16-1offload/plugins-nextgen/level_zero/dynamic_l0/level_zero/ze_api.h
+2-12offload/plugins-nextgen/level_zero/src/L0Device.cpp
+9-0offload/plugins-nextgen/level_zero/include/L0Context.h
+4-0offload/plugins-nextgen/level_zero/include/L0Compat.h
+1-0offload/plugins-nextgen/level_zero/dynamic_l0/L0DynWrapper.cpp
+70-136 files

LLVM/project 97c8facclang/test/CIR/Transforms/abi-lowering x86_64-struct-direct-offset.cir

[CIR][NFC] Use the CIR check prefix in the direct-offset test

Assisted-by: Cursor / claude-opus-5
DeltaFile
+45-45clang/test/CIR/Transforms/abi-lowering/x86_64-struct-direct-offset.cir
+45-451 files

LLVM/project 0434d8flibsycl/src/detail platform_impl.hpp platform_impl.cpp, libsycl/src/detail/offload offload_topology.cpp offload_topology.hpp

[offload][sycl] Introduce `DRIVER_ID` device property (#217562)

Prior to the introduction of liboffload contexts, Level Zero devices
under different driver instances used to each receive their own
`L0ContextTy`s.

https://github.com/llvm/llvm-project/pull/209144 introduced contexts,
which are designed to map to a single `ze_context` on L0.
`olCreateContext` accepts a user-defined device list and is restricted
to accept devices within a single platform. This restriction is
insufficient for L0 - passing devices from different driver instances is
allowed under this contract, but does not make sense on L0 as
`zeContextCreate` needs a concrete driver instance as a parameter.

Introduce a `DRIVER_ID` device property. On CUDA and AMD, it is always
equal to 0. On L0, it is a distinct integer for each driver instance. A
set of devices can be used to create a context if and only if they all
belong to the same platform and have the same DRIVER_ID.


    [4 lines not shown]
DeltaFile
+139-0libsycl/unittests/platform/get_platforms.cpp
+21-37libsycl/src/detail/offload/offload_topology.cpp
+22-36libsycl/src/detail/offload/offload_topology.hpp
+14-38libsycl/src/detail/platform_impl.cpp
+4-18libsycl/src/detail/platform_impl.hpp
+7-5libsycl/unittests/common/unittests_helper.hpp
+207-13414 files not shown
+275-14020 files

LLVM/project 9e8a0fellvm/include/llvm/IR Instruction.h, llvm/lib/IR Instruction.cpp

[VectorCombine] Check call targets when folding deinterleave/interleave pairs (#219116)

Instruction::isSameOperationAs() intentionally compares operation shape
and
special state without requiring operand identity. For CallBase
instructions,
this means calls to different targets with otherwise compatible
signatures can
compare as equivalent.

This caused VectorCombine::foldDeinterleaveInterleavePair() to treat
same-signature intrinsics such as llvm.smax and llvm.smin as the same
operation
and incorrectly fold them into a single widened call.

Add an opt-in Instruction::CompareCallTargets operation-equivalence
flag. When
requested, isSameOperationAs() additionally requires
CallBase::getCalledOperand() to match. Existing callers retain the

    [9 lines not shown]
DeltaFile
+74-0llvm/unittests/IR/InstructionsTest.cpp
+35-0llvm/test/Transforms/VectorCombine/deinterleave-interleave-pairs.ll
+7-5llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+6-0llvm/lib/IR/Instruction.cpp
+2-0llvm/include/llvm/IR/Instruction.h
+124-55 files

LLVM/project 90edec1llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64RegisterInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

Remove isArtificial and isAllocatable, and use RegisterTuples
DeltaFile
+4-12llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+10-3llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+2-2llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+0-3llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1-1llvm/test/TableGen/aarch64-register-info-stats.td
+1-1llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+18-226 files

LLVM/project 6db90c8clang/docs ReleaseNotes.md, clang/lib/CodeGen CGStmtOpenMP.cpp

[Clang][OpenMP] Lower assume directive's holds clause to llvm.assume (#220688)

Emit `@llvm.assume` for the OpenMP 5.1 `assume` directive's `holds()`
clause, enabling downstream optimizations. Previously the clause was
parsed but its condition discarded without effect. Side-effectful
conditions are skipped with a warning, matching the existing
`[[assume]]`/`__builtin_assume` behavior.
DeltaFile
+50-0clang/test/OpenMP/assume_holds_codegen.cpp
+32-0clang/test/OpenMP/assume_holds_side_effects.cpp
+6-0clang/lib/CodeGen/CGStmtOpenMP.cpp
+3-0clang/lib/Sema/SemaOpenMP.cpp
+3-0clang/docs/ReleaseNotes.md
+94-05 files

LLVM/project a44ec49llvm/include/llvm/CodeGen MachORelocation.h, llvm/include/llvm/DebugInfo/CodeView TypeSymbolEmitter.h FunctionId.h

[llvm] Remove dead headers (NFC) (#220832)

None of these headers are referenced anywhere in the repository.
DeltaFile
+0-2,819llvm/lib/Target/Hexagon/HexagonDepMask.h
+0-58llvm/include/llvm/WindowsResource/ResourceScriptToken.h
+0-55llvm/include/llvm/DebugInfo/CodeView/FunctionId.h
+0-55llvm/include/llvm/CodeGen/MachORelocation.h
+0-50llvm/include/llvm/WindowsResource/ResourceProcessor.h
+0-35llvm/include/llvm/DebugInfo/CodeView/TypeSymbolEmitter.h
+0-3,0721 files not shown
+0-3,0957 files

LLVM/project d7a7dbfllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Refactor to enable scalars inline instead of seperate helper function
DeltaFile
+23-38llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+50-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+73-382 files

LLVM/project 814d6c9llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Testing updates per PR feedback, add some new test cases
DeltaFile
+87-6llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+87-61 files

LLVM/project 430ae16llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

[AMDGPU] PromoteAlloca: split scalar accesses that span several elements

promoteAllocaToVector already splits a *vector* access across several
elements when it is a multiple of the element size, but a *scalar* access
had to be bitcastable to the element type, so an i64 load from an alloca
promoted to <8 x i32> was rejected as "not a supported access type" and
the object stayed in scratch.

Accept a scalar access that is a whole multiple of the element size and
route it through the existing subvector path, which already builds the
value from consecutive elements and bitcasts. Accesses with padding are
still rejected, since splitting those would put the pieces at the wrong
offsets, as are non-integer non-float types.
DeltaFile
+78-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+28-4llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+106-42 files

LLVM/project de7b1d5llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-select.ll promote-alloca-homogeneous-struct.ll

[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors (#217055)

getVectorTypeForAlloca() peeled nested ArrayType and one inner
FixedVectorType, but stopped at any StructType. An alloca of an array of
structs was therefore rejected with "Cannot convert type to vector" and
fell back to scratch, even when the struct was a trivial wrapper around
a scalar.

Peel structs too, but only when every field has the same type and the
struct has no padding, so flattened elements keep the byte offsets the
surrounding index arithmetic assumes. Structs with differing field types
or with padding are left alone.
DeltaFile
+152-0llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+23-6llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+6-1llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+181-73 files

LLVM/project 1d7070dllvm/lib/Passes RunCodeGen.cpp

fix

Created using spr 1.3.7
DeltaFile
+1-0llvm/lib/Passes/RunCodeGen.cpp
+1-01 files