LLVM/project 3078eaaoffload/plugins-nextgen/level_zero/src L0Program.cpp L0Kernel.cpp

[offload] fix invalid symbol handling in l0 plugin (#189442)
DeltaFile
+2-2offload/plugins-nextgen/level_zero/src/L0Program.cpp
+4-0offload/plugins-nextgen/level_zero/src/L0Kernel.cpp
+6-22 files

LLVM/project 7fb61f5clang-tools-extra/clang-tidy/misc UseInternalLinkageCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Make `misc-use-internal-linkage` not diagnose symbols in importable module units (#188679)

Fixes #187884.
DeltaFile
+31-0clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-module-implementation.cpp
+15-7clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
+16-3clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-module.cpp
+10-0clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-module-partition.cpp
+6-0clang-tools-extra/docs/ReleaseNotes.rst
+78-105 files

LLVM/project cb1d614clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Use UnitProp for comdat, constant, dso_local (#190518)
DeltaFile
+3-3clang/include/clang/CIR/Dialect/IR/CIROps.td
+2-3clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+5-62 files

LLVM/project cfdd8bcclang-tools-extra/clang-tidy/bugprone AssignmentInSelectionStatementCheck.cpp AssignmentInSelectionStatementCheck.h, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Add check 'bugprone-assignment-in-selection-statement' (#180219)
DeltaFile
+144-0clang-tools-extra/clang-tidy/bugprone/AssignmentInSelectionStatementCheck.cpp
+131-0clang-tools-extra/test/clang-tidy/checkers/bugprone/assignment-in-selection-statement.c
+63-0clang-tools-extra/docs/clang-tidy/checks/bugprone/assignment-in-selection-statement.rst
+41-0clang-tools-extra/test/clang-tidy/checkers/bugprone/assignment-in-selection-statement.cpp
+30-0clang-tools-extra/clang-tidy/bugprone/AssignmentInSelectionStatementCheck.h
+9-0clang-tools-extra/docs/ReleaseNotes.rst
+418-05 files not shown
+435-011 files

LLVM/project 8944608llvm/include/llvm/IR Instruction.h

[IR] Remove HasMetadata bit from instructions (#190651)

We were reserving one bit for a HasMetadata flag. However, this flag has
long since been moved into Value itself, prior to being removed from
there as well recently.
DeltaFile
+3-16llvm/include/llvm/IR/Instruction.h
+3-161 files

LLVM/project dcd58a8llvm/lib/Analysis InlineCost.cpp, llvm/test/Transforms/Inline attributes.ll

[Inline] Allow inlining with null_pointer_is_valid mismatch (#190510)

If the callee has null_pointer_is_valid but the caller does not, we
should still inline and add null_pointer_is_valid to the caller (which
is handled by an already existing inline adjustment rule).

This does mean that optimizations in the caller may be reduced by
unnecessarily preserving null checks, but that's still better than not
inlining at all. In particular, this check causes issues with LTO in the
Linux kernel, as the C portions are compiled with null_pointer_is_valid,
but the Rust portions are not.

The test is modified to show that the previous alwaysinline behavior now
always holds.
DeltaFile
+8-28llvm/test/Transforms/Inline/attributes.ll
+0-5llvm/lib/Analysis/InlineCost.cpp
+8-332 files

LLVM/project 774ac31llvm/test/CodeGen/AMDGPU llvm.amdgcn.ds.gws.barrier.ll llvm.amdgcn.ds.gws.barrier-bundle.ll

[AMDGPU][NFC] Split and auto-generate ds.gws.barrier test checks (#190680)

Split MIR checks into a separate test file.
DeltaFile
+733-127llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
+172-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
+905-1272 files

LLVM/project 39e5034clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 bf16-getset-intrinsics.c

[CIR][AArch64] Implement vget_lane_bf16 and vgetq_lane_bf16 builtins (#186866)

Implements vget_lane_bf16 and vgetq_lane_bf16 builtins. Updates test
with CIR test.
Part of #185382
DeltaFile
+44-0clang/test/CodeGen/AArch64/neon/bf16-getset.c
+0-36clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
+9-18clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+53-543 files

LLVM/project 4c2e49dclang/lib/AST StmtProfile.cpp, clang/test/Modules callable-require-clause-merge.cppm polluted-operator.cppm

[C++20] [Modules] Don't profiling the callee of CXXFoldExpr (#190732)

Close https://github.com/llvm/llvm-project/issues/190333

For the test case, the root cause of the problem is, the compiler
thought the declaration of `operator &&` in consumer.cpp may change the
meaning of '&&' in the requrie clause of `F::operator()`. But it doesn't
make sense. Here we skip profiling the callee to solve the problem. Note
that we've already record the kind of the operator. So '&&' and '||'
won't be confused.
DeltaFile
+35-0clang/test/Modules/callable-require-clause-merge.cppm
+29-1clang/lib/AST/StmtProfile.cpp
+0-7clang/test/Modules/polluted-operator.cppm
+64-83 files

LLVM/project 8460cb9clang-tools-extra/clang-tidy ClangTidy.cpp, clang-tools-extra/test lit.cfg.py

[clang-tidy] [Modules] Skip checking decls in clang-tidy (#145630) (#190733)

Close https://github.com/llvm/llvm-project/issues/145628

Note that I am not sure if this is the proper fix. On the one hand, the
fix lives in ASTMachers instead of clang-tidy. On the other hand, I feel
this may be a more general fix.
DeltaFile
+29-0clang-tools-extra/test/clang-tidy/infrastructure/cxx20-modules.cppm
+4-0clang/lib/ASTMatchers/ASTMatchFinder.cpp
+3-0clang-tools-extra/clang-tidy/ClangTidy.cpp
+2-0clang/include/clang/ASTMatchers/ASTMatchFinder.h
+1-0clang-tools-extra/test/lit.cfg.py
+39-05 files

LLVM/project aed3c80llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/include/llvm/Transforms/Scalar LoopStrengthReduce.h

[NPM] Make LoopStrengthReduce function pass
DeltaFile
+40-7llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+9-8llvm/include/llvm/Passes/CodeGenPassBuilder.h
+4-4llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+4-4llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-2llvm/include/llvm/Transforms/Scalar/LoopStrengthReduce.h
+1-1llvm/test/Transforms/LoopStrengthReduce/callbr-critical-edge-splitting2.ll
+59-2612 files not shown
+71-3818 files

LLVM/project a89f174clang/lib/Sema SemaDecl.cpp, clang/test/SemaTemplate GH187909.cpp

[clang] Fix crash on invalid out-of-line enum definition with template parameters (#188246)

clang crashes when an invalid out-of-line enum definition is provided
with template parameters. In these cases, clang produces a dependent
type within a non-dependent context, violating internal invariants.

The fix is to fallback the underlying type of the enum to `int` during
error recovery in `Sema::ActOnTag` when `Invalid` is true, making it
safe for downstream processing while still preserving the invalid
declaration in the AST.


Fixes #187909
DeltaFile
+10-0clang/test/SemaTemplate/GH187909.cpp
+2-1clang/lib/Sema/SemaDecl.cpp
+12-12 files

LLVM/project d55122eclang/lib/Rewrite Rewriter.cpp, clang/unittests/Rewrite RewriterTest.cpp

[clang][Rewriter] Adjust end offset before RewriteBuffer::getMappedOffset() call (#187374)

Without this patch, only cases when a token length increased were
supported.
If a token length decreased, we returned a larger string than expected
(e.g. in the added tests, "xretur " would be returned instead of
"xretur")
DeltaFile
+8-0clang/unittests/Rewrite/RewriterTest.cpp
+4-4clang/lib/Rewrite/Rewriter.cpp
+12-42 files

LLVM/project d8391e4llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/include/llvm/Transforms/Scalar LoopStrengthReduce.h

[NPM] Make LoopStrengthReduce function pass
DeltaFile
+40-7llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+10-8llvm/include/llvm/Passes/CodeGenPassBuilder.h
+4-4llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+4-4llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-2llvm/include/llvm/Transforms/Scalar/LoopStrengthReduce.h
+1-1llvm/test/Transforms/LoopStrengthReduce/depth-limit-overrun.ll
+60-2612 files not shown
+72-3818 files

LLVM/project a485f1cllvm/lib/Target/AMDGPU SILowerSGPRSpills.cpp, llvm/test/CodeGen/AMDGPU si-lower-sgpr-spills-cycle-header.ll si-lower-sgpr-spills-multi-entry-cycle.mir

[AMDGPU][SILowerSGPRSpills] Correct insertion of IMPLICIT_DEF in cycles (#186348)

si-lower-sgpr spills was observed inserting IMPLICIT_DEF for lane VGPR
restores in the cycle header. The virtual VGPR is therefore not live-in
to the header and wwm regallocfast does not insert a restore. This
results in the vgpr being clobbered after each backedge.

Correct this by inserting the IMPLICIT_DEF in a block that dominates
all entries.

Assisted by Claude.
DeltaFile
+206-0llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.ll
+149-0llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
+114-0llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
+66-21llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+72-0llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
+63-0llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
+670-214 files not shown
+687-2510 files

LLVM/project b6759f1lldb/source/Host/aix Host.cpp, lldb/source/Plugins/ObjectFile/XCOFF ObjectFileXCOFF.cpp ObjectFileXCOFF.h

[lldb][AIX] Extract CPU type and set up process architecture accordingly (#189910)

This PR is in reference to porting LLDB on AIX. Ref discusssions: [llvm
discourse](https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640) and
[#101657](https://github.com/llvm/llvm-project/issues/101657).
Complete changes together in this draft:
- [Extending LLDB to work on AIX
#102601](https://github.com/llvm/llvm-project/pull/102601)

Description:
The process architecture was previously initialized using a hardcoded
TCPU_PPC64 CPU type.

The logic has been updated to determine the CPU type dynamically by
inspecting the magic bytes and the XCOFF header. Based on this
information, the appropriate CPU type (TCPU_PPC or TCPU_PPC64) is
selected and used when constructing and setting the ArchSpec.

This change ensures that the process architecture correctly reflects the
underlying binary format.
DeltaFile
+20-29lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp
+37-3lldb/source/Host/aix/Host.cpp
+3-2lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.h
+1-1lldb/source/Utility/ArchSpec.cpp
+1-1lldb/test/Shell/ObjectFile/XCOFF/basic-info32.yaml
+62-365 files

LLVM/project 9e72ab6clang/lib/Sema SemaChecking.cpp, clang/test/Analysis bstring.c

[Clang][Sema] Add fortify warnings for bcopy and bzero  (#168965) (#186522)

Add fortify warnings for bcopy and bzero as part of
[llvm#142230](https://github.com/llvm/llvm-project/issues/142230)
DeltaFile
+12-0clang/test/Sema/warn-fortify-source.c
+9-0clang/lib/Sema/SemaChecking.cpp
+2-1clang/test/Analysis/bstring.c
+23-13 files

LLVM/project 45494d9llvm/lib/Target/RISCV RISCVInstrInfoZa.td

[RISCV] Fix address type in Zacas seq_cst atomic pattern (#190729)

The seq_cst pattern in AMOCASPat used (vt GPR:$addr) for the address
operand, while all other patterns (monotonic, acquire, release, acq_rel)
consistently use (XLenVT GPR:$addr). This would produce a wrong type for
the address when vt differs from XLenVT (e.g., amocas.d on RV32 where
vt=i64).

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
+1-11 files

LLVM/project cab7d1emlir/lib/Reducer ReductionTreePass.cpp, mlir/test/mlir-reduce test.sh false.sh

[mlir][reducer] Repalce module.emitWarning with module.emitError in ReductionTree pass (#190584)

This PR fixes the diagnostic message for mlir-reduce's reduction-tree
pass when the input module is not "interesting". Previously, running
with the warning pass would fail silently, and enabling debug options
would only show a generic "pass manager run failed" message without any
useful diagnostic information.
DeltaFile
+0-6mlir/test/mlir-reduce/test.sh
+6-0mlir/test/mlir-reduce/false.sh
+6-0mlir/test/mlir-reduce/true.sh
+4-1mlir/test/mlir-reduce/invalid.mlir
+2-2mlir/lib/Reducer/ReductionTreePass.cpp
+1-1mlir/test/mlir-reduce/simple-test.mlir
+19-106 files

LLVM/project d6d7d0aclang/lib/Driver/ToolChains Flang.cpp, flang/lib/Optimizer/Transforms FunctionAttr.cpp

[Flang][Driver] Add support for '-fprofile-sample-use' option (#188697)

When the `-fprofile-sample-use=sample.prof` option is passed, the
compiler records the profile file path in `SampleProfileFile` . This
value is later used by the `SampleProfileLoaderPass`, which loads the
sample profile and injects the corresponding profiling metadata in the
LLVM IR.
DeltaFile
+38-0flang/test/Driver/fprofile-sample-use.f90
+35-0clang/lib/Driver/ToolChains/Flang.cpp
+34-0flang/test/Integration/profile-sample-use.f90
+9-0mlir/test/Target/LLVMIR/Import/use-sample-profile.ll
+7-0mlir/test/Target/LLVMIR/use-sample-profile.mlir
+6-0flang/lib/Optimizer/Transforms/FunctionAttr.cpp
+129-012 files not shown
+164-618 files

LLVM/project 150783emlir/include/mlir/Dialect/ControlFlow/IR ControlFlowOps.td, mlir/include/mlir/Interfaces ControlFlowInterfaces.td

Revert "Reland "[mlir][reducer] Add eraseRedundantBlocksInRegion and getSuccessorForwardOperands API to BranchOpInterface"" (#190727)

To decouple the BranchOpInterface implementation from the reduction-tree
changes. Reverts llvm/llvm-project#189253,
DeltaFile
+0-114mlir/lib/Reducer/ReductionTreePass.cpp
+0-65mlir/test/mlir-reduce/reduction-tree.mlir
+0-24mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
+4-6mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
+0-10mlir/lib/Reducer/ReductionNode.cpp
+0-9mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+4-2282 files not shown
+4-2328 files

LLVM/project 7349977mlir/lib/Transforms CSE.cpp

[mlir][CSE] Fix CSE markAnalysesPreserved<DominanceInfo, PostDominanceInfo> comment (#190471)

The original comment claimed that DominanceInfo and PostDominanceInfo
could be preserved because region operations are not removed. However,
the real reason was that the original CSE only deleted redundant
operations without moving any operation to a different block, leaving
the dominance tree structure unchanged. Part of
https://github.com/llvm/llvm-project/pull/180556.
DeltaFile
+3-2mlir/lib/Transforms/CSE.cpp
+3-21 files

LLVM/project 0a13e4dmlir/include/mlir/Dialect/ControlFlow/IR ControlFlowOps.td, mlir/include/mlir/Interfaces ControlFlowInterfaces.td

Revert "Reland "[mlir][reducer] Add eraseRedundantBlocksInRegion and getSucce…"

This reverts commit ce1a9fd76640929fe340c5c5d1bb493ea09ca9bc.
DeltaFile
+0-114mlir/lib/Reducer/ReductionTreePass.cpp
+0-65mlir/test/mlir-reduce/reduction-tree.mlir
+0-24mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
+0-10mlir/lib/Reducer/ReductionNode.cpp
+4-6mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
+0-9mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+4-2282 files not shown
+4-2328 files

LLVM/project 97ed648libcxx/docs/Status Cxx2cIssues.csv Cxx2cPapers.csv

[libc++][docs] Update paper and LWG issue lists after 2026-03 meeting (#189901)

[P3726R2](https://wg21.link/P3726R2) is a Core paper but adds
`std::start_lifetime`, so it needs to be listed in libc++'s
documentation.

For LWG issues, see [P4145R0](https://wg21.link/P4145R0) and
[P4146R0](https://wg21.link/P4146R0).
DeltaFile
+82-0libcxx/docs/Status/Cxx2cIssues.csv
+38-0libcxx/docs/Status/Cxx2cPapers.csv
+120-02 files

LLVM/project 6870ebcllvm/include/llvm/Support FileSystem.h, llvm/lib/CAS MappedFileRegionArena.cpp

[CAS] Give Windows file mappings names to better ensure same mappings are used (#190692)
DeltaFile
+52-0llvm/unittests/Support/Path.cpp
+12-5llvm/lib/Support/Windows/Path.inc
+10-1llvm/lib/CAS/MappedFileRegionArena.cpp
+5-4llvm/lib/Support/Unix/Path.inc
+3-2llvm/include/llvm/Support/FileSystem.h
+82-125 files

LLVM/project e80f32fllvm/lib/CodeGen CodeGenPrepare.cpp

[CodeGenPrepare] Use Instruction::comesBefore instead of manual ordering (#190485)

After #172329, we noticed that some sources compiled with MSan take
1000x longer to compile. This is caused by quadratic complexity in
tryToSinkFreeOperands, which can be called on a significant number
of instructions within huge basic blocks.

This inefficiency was introduced in 9cfa9b4, which manually iterates
and creates a DenseMap of entire basic blocks for each interesting
instruction.

This patch avoids the manual ordering by using
Instruction::comesBefore(), which provides the exact same
ordering much more efficiently.
DeltaFile
+1-6llvm/lib/CodeGen/CodeGenPrepare.cpp
+1-61 files

LLVM/project 49093c4clang-tools-extra/clang-tidy/performance TriviallyDestructibleCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix performance-trivially-destructible with C++20 modules (#178471)

When a class definition is seen through both a header include and a
C++20 module import, destructors may appear multiple times in the AST's
redeclaration chain. The original matcher used `isFirstDecl()` which
fails in this scenario because the same declaration can appear as both
first and non-first depending on the view.

Replace `unless(isFirstDecl())` with `isOutOfLine()` which correctly
identifies out-of-line definitions by checking whether the lexical
context differs from the semantic context.

Also update clang-tools-extra's lit.cfg.py to call `use_clang()` instead
of `clang_setup()` to make the `%clang` substitution available for
tests.

Fixes #178102

Co-authored-by: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
DeltaFile
+61-0clang-tools-extra/test/clang-tidy/checkers/performance/trivially-destructible-module.cpp
+7-3clang-tools-extra/clang-tidy/performance/TriviallyDestructibleCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+2-2clang-tools-extra/test/lit.cfg.py
+3-0clang-tools-extra/test/CMakeLists.txt
+78-55 files

LLVM/project 613c5b4flang/lib/Semantics tools.cpp, flang/test/Lower/CUDA cuda-program-global.cuf

[flang][cuda] Lower unified variables as cuf.alloc in main program scope (#190713)

Remove the unified exception from CanCUDASymbolBeGlobal so unified
variables follow the same cuf.alloc lowering path as other CUDA data
attributes.
DeltaFile
+1-3flang/lib/Semantics/tools.cpp
+2-1flang/test/Lower/CUDA/cuda-program-global.cuf
+3-42 files

LLVM/project f9adee2llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU asyncmark-gfx12plus.ll asyncmark-err.ll

[AMDGPU] asyncmark support for ASYNC_CNT (#185813)

The ASYNC_CNT is used to track the progress of asynchronous copies
between global and LDS memories. By including it in asyncmark, the
compiler can now assist the programmer in generating waits for
ASYNC_CNT.

Assisted-By: Claude Sonnet 4.5

This is part of a stack:

- #185813
- #185810 

Fixes: LCOMPILER-332
DeltaFile
+359-0llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
+14-7llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+0-19llvm/test/CodeGen/AMDGPU/asyncmark-err.ll
+1-2llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+3-0llvm/lib/Target/AMDGPU/AMDGPU.td
+1-1llvm/lib/Target/AMDGPU/SOPInstructions.td
+378-291 files not shown
+380-297 files

LLVM/project 5567b34llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU vgpr-setreg-mode-swar.mir hazard-setreg-vgpr-msb-gfx1250.mir

[AMDGPU] Fix setreg handling in the VGPR MSB lowering

There are multiple issues with it:

1. It can skip inserting S_SET_VGPR_MSB if we set the mode via
   piggybacking. We are now relying on the HW bug for correct
   behavior. If/when the bug is fixed lowering will be incorrect.
2. We should just unconditionally update MSBs if immediate allows it.
   We shall set correct bits and keep the rest of the immediate
   (that is done). There is no reasonable way for an user to change
   MSBs nor does it do anything good to set it with SETREG and then
   immediately overwrite with S_SET_VGPR_MSB.
3. We can always update immediate if Offset is zero.
4. Redundant mode changes created as seen in the
   hazard-setreg-vgpr-msb-gfx1250.mir.

With unconditional immediate update most of time and not relying on
the SETREG for setting MSBs there is no good reason to complicate
handling by supporting SETREG as a piggybacking target. Moreover,

    [10 lines not shown]
DeltaFile
+209-47llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
+20-39llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+12-18llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir
+241-1043 files