LLVM/project bbece4blibc/src/__support/File file.cpp

[libc] replace for loops with a call to memcpy in File (#165219)

Addresses `TODO`s in file.cpp by replacing data copies via for loops
with calls to inline_memcpy.

Signed-off-by: Shreeyash Pandey <shreeyash335 at gmail.com>
DeltaFile
+5-11libc/src/__support/File/file.cpp
+5-111 files

LLVM/project 05e94c9llvm/lib/Target/Xtensa XtensaISelLowering.h XtensaISelLowering.cpp

[Xtensa] TableGen-erate SDNode descriptions (#166253)

Part of #119709.
DeltaFile
+0-63llvm/lib/Target/Xtensa/XtensaISelLowering.h
+1-52llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+28-0llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h
+19-0llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp
+10-1llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
+5-5llvm/lib/Target/Xtensa/XtensaSubtarget.h
+63-1212 files not shown
+66-1218 files

LLVM/project 3f0ef27mlir/include/mlir/Target/LLVMIR ModuleImport.h, mlir/lib/Target/LLVMIR ModuleImport.cpp ConvertFromLLVMIR.cpp

[MLIR][LLVM] Debug info: import debug records directly (#167812)

Effectively means we don't need to call into
`llvmModule->convertFromNewDbgValues()` anymore. Added a flag to allow
users to access the old behavior.
DeltaFile
+191-69mlir/lib/Target/LLVMIR/ModuleImport.cpp
+87-0mlir/test/Target/LLVMIR/Import/debug-info-records.ll
+27-3mlir/include/mlir/Target/LLVMIR/ModuleImport.h
+12-2mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+317-744 files

LLVM/project 8e4209allvm/utils/lit/lit run.py

[utils] don't warn when setting rlimit fails on Solaris (#167921)

Solaris doesn't define RLIMIT_NPROC, so this is expected to fail there.
This fixes a test failure in llvm/utils/lit/tests/verbosity.py on
Solaris due to this unexpected warning being included in the lit output.
DeltaFile
+2-1llvm/utils/lit/lit/run.py
+2-11 files

LLVM/project 52f2a94clang/test/CodeGen/SystemZ encoding.c, llvm/lib/Support VirtualOutputBackends.cpp

[Support] Prevent loss of file type flags when creating temporary (#167939)

Non-binary output files from the compiler need the `OF_Text` flag set
for encoding conversion to be performed correctly on z/OS.

---------

Co-authored-by: Tony Tao <tonytao at ca.ibm.com>
DeltaFile
+17-8llvm/lib/Support/VirtualOutputBackends.cpp
+9-0clang/test/CodeGen/SystemZ/encoding.c
+26-82 files

LLVM/project 420d56alldb/tools/debugserver/source/MacOSX MachTask.mm MachTask.h

Clean up MachTask.mm's handling of m_exception_thread. (#167994)

This was getting joined in ShutDownExcecptionThread (sic) but not
cleared. So this function was not safe to call twice, since you aren't
supposed to join a thread twice. Sadly, this was called in
MachTask::Clear and MachProcess::Destroy, which are both called when you
tell debugserver to detach.

This didn't seem to cause problems IRL, but the most recent ASAN detects
this as an error and calls ASAN::Die, which was causing all the tests
that ran detach to fail.

I fixed that by moving the clear & test for m_exception_thread to
ShutDownExceptionThread. I also fixed the spelling of that routine. And
that routine was claiming to return a kern_return_t which no one was
checking. It actually returns a kern_return_t if there was a Mach
failure and a Posix error if there was a join failure. Since there's
really nothing you can do but exit if this fails, which is always what
you are in the process of doing when you call this, and since we have
already done all the useful logging in ShutDownExceptionThread, I just
removed the return value.
DeltaFile
+8-5lldb/tools/debugserver/source/MacOSX/MachTask.mm
+1-1lldb/tools/debugserver/source/MacOSX/MachTask.h
+1-1lldb/tools/debugserver/source/MacOSX/MachProcess.mm
+10-73 files

LLVM/project 306f49allvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU gfx10_asm_ds_err.s gfx11_asm_ds_err.s

[AMDGPU][MC] Disallow nogds in ds_gws_* instructions (#166873)

The ds_gws_* instructions require gds as an operand. However, when nogds
is given, it is treated the same as gds. This patch fixes this to
disallow nogds.
DeltaFile
+38-0llvm/test/MC/AMDGPU/gfx10_asm_ds_err.s
+37-0llvm/test/MC/AMDGPU/gfx11_asm_ds_err.s
+37-0llvm/test/MC/AMDGPU/gfx7_asm_ds_err.s
+37-0llvm/test/MC/AMDGPU/gfx8_asm_ds_err.s
+37-0llvm/test/MC/AMDGPU/gfx9_asm_ds_err.s
+6-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+192-06 files

LLVM/project 739a5a4flang/lib/Semantics resolve-directives.cpp, flang/test/Semantics/OpenMP defaultmap-clause-none.f90

[Flang][OpenMP] Fix defaultmap(none) being overly aggressive with symbol checks (#167806)

Currently we're picking up and complaining about builtin (and procedure)
symbols like null() when defaultmap(none) is set, so I've relaxed the
restriction a bit to allow for procedures and named constants to bypass
the restriction. It might be the case that we want to tighten it up
again in certain aspects in the future.
DeltaFile
+37-0flang/test/Semantics/OpenMP/defaultmap-clause-none.f90
+7-2flang/lib/Semantics/resolve-directives.cpp
+44-22 files

LLVM/project 249055boffload/include omptarget.h

Fix comment
DeltaFile
+1-1offload/include/omptarget.h
+1-11 files

LLVM/project ebc0e07llvm/lib/Target/AMDGPU AMDGPUArgumentUsageInfo.h SIMachineFunctionInfo.h

[AMDGPU] Use std::variant in ArgDescriptor. (#167992)

This replaces the 2 bool flags and the anonymous union. This also
removes an implicit conversion from Register to unsigned and a call to
MCRegister::id().

The ArgDescriptor constructor was always assigning the union through the
MCRegister field even for stack offsets.

The change to SIMachineFunctionInfo.h fixes a case where getRegister was
being called on an unset ArgDescriptor. Since it was only this case, it
seemed cleaner to fix it at the caller. The other option would be to
make getRegister() return MCRegister() for an unset ArgDescriptor.
DeltaFile
+17-27llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
+3-1llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+20-282 files

LLVM/project b2f1233llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU mfma-loop.ll waterfall-call-target-av-register-failure.ll

AMDGPU: Fix verifier error when waterfall call target is in AV register (#168017)

DeltaFile
+862-668llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+141-0llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
+26-18llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+16-12llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+8-9llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
+1-1llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
+1,054-7086 files

LLVM/project 4d3ed10compiler-rt/lib/asan asan_mapping.h, compiler-rt/lib/sanitizer_common sanitizer_platform.h

[compiler-rt] [Darwin] Strip MTE tags from ASAN and TSAN (#166453)

ASAN and TSAN need to strip tags in order to compute the correct shadow
addresses.

rdar://163518624
DeltaFile
+8-3compiler-rt/lib/tsan/rtl/tsan_platform.h
+7-0compiler-rt/lib/sanitizer_common/sanitizer_platform.h
+3-1compiler-rt/lib/asan/asan_mapping.h
+18-43 files

LLVM/project 518b38cclang/lib/CIR/CodeGen CIRGenFunction.cpp, clang/test/CIR/CodeGen defaultarg.cpp

[CIR] Upstream handling for C++ default argument l-values (#167999)

This adds handling emitting C++ default arguments as l-values.
DeltaFile
+32-0clang/test/CIR/CodeGen/defaultarg.cpp
+5-0clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+37-02 files

LLVM/project 48c758dllvm/lib/Transforms/Scalar MemCpyOptimizer.cpp, llvm/test/Transforms/MemCpyOpt memset-memcpy-dbgloc.ll

[MemCpyOpt][profcheck] Set `unknown` branch weights for certain selects
DeltaFile
+5-3llvm/test/Transforms/MemCpyOpt/memset-memcpy-dbgloc.ll
+5-0llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+10-32 files

LLVM/project 0a5be0fllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 minbw-node-used-twice.ll non-schedulable-parent-multi-copyables.ll

[SLP]Enable Sub as a base instruction in copyables

Patch adds support for sub instructions as main instruction in copyables
elements. Also, adds a check if the base instruction is not profitable
for the selection if at least one instruction with the main opcode is
  used as an immediate operand.

Reviewers: RKSimon, hiraditya

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/163231
DeltaFile
+87-27llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-9llvm/test/Transforms/SLPVectorizer/X86/minbw-node-used-twice.ll
+6-1llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
+1-1llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
+96-384 files

LLVM/project 2bcb3f8.github/workflows libcxx-build-and-test.yaml

[libcxx][Github] Move from next runner set (#168089)

This will allow us to actually bump the runner set.
DeltaFile
+8-8.github/workflows/libcxx-build-and-test.yaml
+8-81 files

LLVM/project 9ac84a6llvm/include/llvm/IR ProfDataUtils.h, llvm/lib/IR ProfDataUtils.cpp

[MergeICmp][profcheck] Propagate profile info (#167594)

Propagate branch weights in `mergeComparisons`​ : the probability of reaching the common "exit" BB (`bb_phi`​ in the description in `processPhi`​)doesn't change, and is a disjunction over the probabilities of doing that from the blocks performing comparisons which are now being merged  
  
Issue #147390
DeltaFile
+41-3llvm/lib/Transforms/Scalar/MergeICmps.cpp
+25-12llvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll
+20-7llvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll
+3-0llvm/include/llvm/IR/ProfDataUtils.h
+1-1llvm/lib/IR/ProfDataUtils.cpp
+90-235 files

LLVM/project cfc74ddllvm/lib/Target/AMDGPU SIFixSGPRCopies.cpp, llvm/test/CodeGen/AMDGPU si-fix-sgpr-copies-av-constrain.mir fix-sgpr-copies-readfirstlane-av-register-regression.ll

AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)

Fixes another verifier error after introducing AV registers.
Also fixes not clearing the subregister index if there was
one.
DeltaFile
+18-4llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+19-0llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
+16-1llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-readfirstlane-av-register-regression.ll
+53-53 files

LLVM/project 1122581flang/test/Lower derived-types-bindc.f90

[flang][AIX] add use of the variables (NFC) (#168073)

After
https://github.com/llvm/llvm-project/commit/bf3b704c60cc521b79ec54bd57fcf72368178a52,
the type definition is no longer generated without using the variables.
This patch is to add the use of the derived type variables.
DeltaFile
+6-0flang/test/Lower/derived-types-bindc.f90
+6-01 files

LLVM/project 9398eafllvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU mfma-loop.ll waterfall-call-target-av-register-failure.ll

AMDGPU: Fix verifier error when waterfall call target is in AV register

This isn't an ideal fix; technically this should be an optimization path
we shouldn't need to go down. The base path where a copy will be inserted
is still broken.

The lit test changes are mostly regressions to be fixed later.
DeltaFile
+862-668llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+141-0llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
+26-18llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+16-12llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+8-9llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
+1-1llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
+1,054-7086 files

LLVM/project ab51862llvm/lib/Target/AMDGPU SIFixSGPRCopies.cpp, llvm/test/CodeGen/AMDGPU si-fix-sgpr-copies-av-constrain.mir fix-sgpr-copies-readfirstlane-av-register-regression.ll

AMDGPU: Constrain readfirstlane operand when writing to m0

Fixes another verifier error after introducing AV registers.
Also fixes not clearing the subregister index if there was
one.
DeltaFile
+18-4llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+19-0llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
+16-1llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-readfirstlane-av-register-regression.ll
+53-53 files

LLVM/project c6ee2d9llvm/lib/Target/AMDGPU SIFixSGPRCopies.cpp, llvm/test/CodeGen/AMDGPU si-fix-sgpr-copies-av-constrain.mir fix-sgpr-copies-readfirstlane-av-register-regression.ll

AMDGPU: Constrain readfirstlane operand to vgpr_32 (#168001)

DeltaFile
+92-0llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
+52-0llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-readfirstlane-av-register-regression.ll
+14-3llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+158-33 files

LLVM/project 71eaf14llvm/include/llvm/TableGen TableGenBackend.h Main.h, llvm/lib/TableGen Main.cpp TableGenBackend.cpp

[TableGen] Split *GenRegisterInfo.inc. (#167700)

Reduces memory usage compiling backend sources, most notably for
AMDGPU by ~98 MB per source on average.

AMDGPUGenRegisterInfo.inc is tens of megabytes in size now, and
is even larger downstream. At the same time, it is included in
nearly all backend sources, typically just for a small portion of
its content, resulting in compilation being unnecessarily
memory-hungry, which in turn stresses buildbots and wastes their
resources.

Splitting .inc files also helps avoiding extra ccache misses
where changes in .td files don't cause changes in all parts of
what previously was a single .inc file.

It is thought that rather than building on top of the current
single-output-file design of TableGen, e.g., using `split-file`,
it would be more preferable to recognise the need for multi-file
outputs and give it a proper first-class support directly in
TableGen.
DeltaFile
+55-31llvm/utils/TableGen/RegisterInfoEmitter.cpp
+52-24llvm/lib/TableGen/Main.cpp
+40-3llvm/include/llvm/TableGen/TableGenBackend.h
+14-5llvm/lib/TableGen/TableGenBackend.cpp
+16-1llvm/include/llvm/TableGen/Main.h
+8-1mlir/lib/Tools/mlir-tblgen/MlirTblgenMain.cpp
+185-658 files not shown
+201-7314 files

LLVM/project e170fb5clang/lib/Sema SemaOpenMP.cpp, clang/test/OpenMP parallel_default_variableCategory_codegen.cpp

Revert "[Clang][OpenMP] Bug fix Default clause variable category (#165276)"

This reverts commit 39774f9cafeb8d68acae73c1bf8493343732ebdd.
DeltaFile
+0-92clang/test/OpenMP/parallel_default_variableCategory_codegen.cpp
+3-3clang/lib/Sema/SemaOpenMP.cpp
+3-952 files

LLVM/project 0e1152ellvm/lib/Target/AArch64 AArch64RegisterInfo.cpp AArch64RegisterInfo.h

AArch64: rewrite the CSR compuation (#167967)

Rather than having a separate path for Darwin, and then a partial
handling for Windows, and then the remainder using its own path, unify
the three paths. Use a switch over the calling convention to avoid
having to check and handle the calling convention in a variety of
places. This simplifies the logic and avoids accidnetally missing a
calling convention (such as we had done with PreserveMost, PreserveAll
on Windows).
DeltaFile
+86-108llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+0-1llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+86-1092 files

LLVM/project e06fabclldb/include/lldb/Core Disassembler.h, lldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

[lldb][nfc] Simplify instruction iteration in UnwindAssemblyInstEmulation (#167914)
DeltaFile
+7-9lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+4-0lldb/include/lldb/Core/Disassembler.h
+11-92 files

LLVM/project f26f27clldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp UnwindAssemblyInstEmulation.h

[lldb][nfc] Initialize m_initial_sp in ctor for UnwindAssemblyInstEmulation (#167914)

Also rename the "sp" suffix (originally intended to mean "Stack
Pointer") to "cfa", as "sp" generally means Shared Pointer.
DeltaFile
+6-12lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+6-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h
+12-142 files

LLVM/project 1f93400lldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

[lldb][nfc] Reduce indentation in UnwindAssemblyInstruction (#167914)
DeltaFile
+107-100lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+107-1001 files

LLVM/project 0b5543alldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

[lldb][nfc] Fix comment in UnwindAssemblyInstruction (#167914)
DeltaFile
+1-1lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+1-11 files

LLVM/project 81a73dclldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

[lldb][nfc] Reduce scope of loop variable in UnwindAssemblyInstEmulation (#167914)
DeltaFile
+3-3lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+3-31 files