LLVM/project 6c81859llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AArch64/GlobalISel knownbits-sadde.mir knownbits-uadde.mir

[GlobalISel] Implement G_UADDO/G_UADDE/G_SADDO/G_SADDE for computeKnownBits (#165497)

Addressing the carry out cases Matt mentioned in #159202.

Note: G_[US]SUB[OE] will be implemented in a different PR.
DeltaFile
+275-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
+275-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
+163-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
+163-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
+31-1llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+1-5llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
+908-61 files not shown
+909-117 files

LLVM/project 18155c6flang/include/flang/Runtime freestanding-tools.h

[flang][cuda] Fix device compilation after #172913 (#174031)

DeltaFile
+2-1flang/include/flang/Runtime/freestanding-tools.h
+2-11 files

LLVM/project 0bd5975llvm/include/llvm/CodeGen SelectionDAGISel.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

[SelectionDAG] Use uint8_t instead of unsigned char for isel MatcherTable. (#174014)

These are really the same type, but uint8_t is more accurate since we
make assumptions that a table element is 8 bits when we emit VBRs.
DeltaFile
+21-25llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+1-1llvm/include/llvm/CodeGen/SelectionDAGISel.h
+1-1llvm/test/TableGen/CPtrWildcard.td
+1-1llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+24-284 files

LLVM/project 0bc6491clang/lib/CodeGen CGBuiltin.cpp, clang/test/CodeGen builtin_clrsb.c

[Clang] Add NUW to the Sub in __builtin_clrsb expansion. (#174010)

The ctlz will produce a value in the range [1..bitwidth]. It can't
produce 0. This means the subtract of 1 will not have unsigned wrap.

It also has no signed wrap, but the optimizer can figure that out on its
own.

It's very likely InstCombine will just drop the NUW when it
canonicalizes to Add, but maybe it will be helpful in some case.
DeltaFile
+2-2clang/test/CodeGen/builtin_clrsb.c
+2-1clang/lib/CodeGen/CGBuiltin.cpp
+4-32 files

LLVM/project 6f6fca1llvm/lib/Transforms/Vectorize VPlanRecipes.cpp

[VPlan] Re-use common cast cost logic for VPReplicateRecipe (NFCI).

Move the logic to compute cast costs to getCostForRecipeWithOpcode and
use for VPReplicateRecipe.

This should match the costs computed by the legacy cost model for scalar
casts.
DeltaFile
+94-59llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+94-591 files

LLVM/project 746ecedllvm/test/Transforms/LoopVectorize/AArch64 load-cast-context.ll pr46950-load-cast-context-crash.ll, llvm/test/Transforms/LoopVectorize/X86 cost-model.ll

[LV] Add extra tests for computing replicating cast costs (NFC)
DeltaFile
+315-314llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+198-0llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
+0-25llvm/test/Transforms/LoopVectorize/AArch64/pr46950-load-cast-context-crash.ll
+513-3393 files

LLVM/project 35040a0flang/include/flang/Evaluate tools.h, flang/test/Lower/CUDA cuda-data-transfer.cuf

[flang][cuda] Make copy to managed variable on host (#174012)

When the LHS has multiple symbols with the managed attribute, still
perform the copy on the host.
DeltaFile
+19-0flang/test/Lower/CUDA/cuda-data-transfer.cuf
+3-3flang/include/flang/Evaluate/tools.h
+22-32 files

LLVM/project c16480dllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-minimumnum.ll simplify-demanded-fpclass-maximumnum.ll

InstCombine: Handle minimumnum/maximumnum in SimplifyDemandedFPClass
DeltaFile
+36-59llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+34-55llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+64-12llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+134-1263 files

LLVM/project 10f04e1llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximum.ll simplify-demanded-fpclass-minimum.ll

InstCombine: Introduce nsz flag on minimum/maximum in SimplifyDemandedFPClass

Alive isn't particularly happy with this in the case where
one of the inputs could be zero, but I think
it's wrong: https://alive2.llvm.org/ce/z/dF7V6k

nsz shouldn't permit introducing a -0 result where
there wasn't one in the input here.
DeltaFile
+46-46llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+46-46llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+18-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+110-943 files

LLVM/project 7669370llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Implement SimplifyDemandedFPClass for sqrt
DeltaFile
+31-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+10-19llvm/lib/Analysis/ValueTracking.cpp
+24-0llvm/lib/Support/KnownFPClass.cpp
+7-11llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
+4-0llvm/include/llvm/Support/KnownFPClass.h
+76-305 files

LLVM/project 731dc7dllvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximumnum.ll simplify-demanded-fpclass-minimumnum.ll

InstCombine: Add baseline minimumnum/maximumnum SimplifyDemandedFPClass tests
DeltaFile
+1,625-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+1,625-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+3,250-02 files

LLVM/project 9744178llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Handle minimum/maximum in SimplifyDemandedFPClass
DeltaFile
+51-80llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+49-76llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+26-87llvm/lib/Analysis/ValueTracking.cpp
+94-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+92-0llvm/lib/Support/KnownFPClass.cpp
+14-0llvm/include/llvm/Support/KnownFPClass.h
+326-2446 files

LLVM/project dd4394bllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fmul.ll

InstCombine: Consider not-inf/nan context when simplifying fmul

Consider if the result can be nan, or if the inputs cannot
be infinity from the flag when trying to simplify fmul into
copysign.
DeltaFile
+18-12llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
+18-6llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+36-182 files

LLVM/project eb783bbllvm/test/Transforms/InstCombine simplify-demanded-fpclass-sqrt.ll

InstCombine: Add baseline tests for sqrt SimplifyDemandedFPClass
DeltaFile
+206-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
+206-01 files

LLVM/project eb1e33allvm/include/llvm/ADT FloatingPointMode.h, llvm/include/llvm/Support KnownFPClass.h

InstCombine: Handle log/log2/log10 in SimplifyDemandedFPClass
DeltaFile
+16-30llvm/lib/Analysis/ValueTracking.cpp
+37-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+9-18llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll
+17-0llvm/lib/Support/KnownFPClass.cpp
+5-0llvm/include/llvm/ADT/FloatingPointMode.h
+4-0llvm/include/llvm/Support/KnownFPClass.h
+88-486 files

LLVM/project ff4c662llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fmul.ll

InstCombine: Handle fmul by -0 case in SimplifyDemandedFPClass

The fmul visitor handles this case as copysign and fneg.
DeltaFile
+18-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+4-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
+22-42 files

LLVM/project c3b27f9llvm/test/Transforms/InstCombine simplify-demanded-fpclass-log.ll

InstCombine: Add baseline test for SimplifyDemandedFPClass log handling
DeltaFile
+268-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll
+268-01 files

LLVM/project 260c6e7llvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximum.ll simplify-demanded-fpclass-minimum.ll

InstCombine: Add baseline tests for minimum/maximum SimplifyDemandedFPClass handling
DeltaFile
+1,625-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+1,625-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+3,250-02 files

LLVM/project 171dd91llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Handle fmul in SimplifyDemandedFPClass
DeltaFile
+123-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+58-49llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
+18-63llvm/lib/Analysis/ValueTracking.cpp
+59-0llvm/lib/Support/KnownFPClass.cpp
+29-0llvm/include/llvm/Support/KnownFPClass.h
+1-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+288-1156 files

LLVM/project 75fc190llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fmul.ll

InstCombine: Add baseline tests for fmul SimplifyDemandedFPClass handling
DeltaFile
+1,198-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
+1,198-01 files

LLVM/project 4a83caf

Merge branch 'users/abhinavgaba/udp-fallback-3' into users/abhinavgaba/udp-fallback-4
DeltaFile
+0-00 files

LLVM/project fdfa6edoffload/test/mapping/use_device_ptr target_data_use_device_ptr_class_member_fallback_nullify.cpp target_data_use_device_ptr_class_member_ref_fallback_nullify.cpp

Clang-format changed its mind.
DeltaFile
+1-1offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_fallback_nullify.cpp
+1-1offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_ref_fallback_nullify.cpp
+2-22 files

LLVM/project 82ef720libc/fuzzing/stdio printf_float_conv_fuzz.cpp

[libc][fuzzing] Delete test buffs for asan checks (#174018)

I'm currently getting "Detected memory leaks" errors due to this. This
change should always delete the buffers after use.
DeltaFile
+5-6libc/fuzzing/stdio/printf_float_conv_fuzz.cpp
+5-61 files

LLVM/project ecf73ccflang/lib/Semantics check-call.cpp resolve-names.cpp, flang/test/Lower/CUDA cuda-data-transfer.cuf

Revert "[flang][cuda] Emit error when a device actual argument is used in host intrinsic" (#174019)

Reverts llvm/llvm-project#172914
DeltaFile
+0-36flang/lib/Semantics/check-call.cpp
+1-11flang/test/Lower/CUDA/cuda-data-transfer.cuf
+0-12flang/lib/Semantics/resolve-names.cpp
+0-7flang/test/Semantics/cuf23.cuf
+1-664 files

LLVM/project 0f3a9f6llvm/test/Transforms/LoopVectorize fmax-without-fast-math-flags-interleave.ll

[LV] Add tail-folded test for fmax reductions without fast-math flags.

Adds missing tail-folding test.
DeltaFile
+160-2llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
+160-21 files

LLVM/project 292c9e3llvm/test/CodeGen/SPARC 2011-01-19-DelaySlot.ll

[SPARC] Change delay slot test to use autogenerated code (#173442)

DeltaFile
+435-59llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+435-591 files

LLVM/project 4fe4824llvm/test/tools/UpdateTestChecks/update_mc_test_checks riscv-show-inst.test, llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs riscv_show_inst.s.expected riscv_show_inst.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+23-21llvm/utils/update_mc_test_checks.py
+8-0llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s.expected
+5-0llvm/test/tools/UpdateTestChecks/update_mc_test_checks/riscv-show-inst.test
+2-0llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s
+38-214 files

LLVM/project f00575ellvm/test/tools/UpdateTestChecks lit.local.cfg

[UpdateTestChecks] Fix %update_mc_test_checks substitution

We need to explicitly pass --llvm-mc-binary to avoid picking up llvm-mc
from somewhere else in $PATH. Noticed this because test lines were being
generated that didn't include my latest changes to update_mc_test_checks.py

Pull Request: https://github.com/llvm/llvm-project/pull/172230
DeltaFile
+2-1llvm/test/tools/UpdateTestChecks/lit.local.cfg
+2-11 files

LLVM/project 0b46cf7llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize vector-loop-backedge-elimination-early-exit.ll

[VPlan] Handle BranchOnTwoConds in simplifyBranchCondition.

This fixes a crash after introducing BranchOnTwoConds (524b1788,
https://github.com/llvm/llvm-project/pull/172750) when trying to
replace BranchOnTwoConds with a VPBranchOnCond, without dissolving the
region.

In that case, we need to update the appropriate condition operand.
DeltaFile
+122-0llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
+7-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+129-02 files

LLVM/project 16a8055llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Implement SimplifyDemandedFPClass for sqrt
DeltaFile
+31-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+10-19llvm/lib/Analysis/ValueTracking.cpp
+24-0llvm/lib/Support/KnownFPClass.cpp
+7-11llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
+4-0llvm/include/llvm/Support/KnownFPClass.h
+76-305 files