LLVM/project 17406f7libsycl/include/sycl/__impl/detail default_async_handler.hpp, libsycl/include/sycl/__impl/info event.hpp

[libsycl] implement methods of synchronization in event and queue classes (#205860)

Extends libsycl’s sycl::event API by adding default-constructed event
semantics, wait-list exposure and async exceptions handling. Async
exceptions handling is generic for event and queue APIs and though added
to sycl::queue API as well.

Introduces async-exception aggregation/flush infrastructure (global
associative container).
Adds/adjusts unit tests and unifies test binary registration utilities
(Scoped*Registration, namespace cleanup).

This PR was assisted by GH Copilot.

Signed-off-by: Tikhomirova, Kseniya
[kseniya.tikhomirova at intel.com](mailto:kseniya.tikhomirova at intel.com)
DeltaFile
+152-0libsycl/unittests/event/async_handler.cpp
+139-0libsycl/unittests/event/event.cpp
+64-0libsycl/unittests/common/scoped_binary_registration.hpp
+0-55libsycl/include/sycl/__impl/detail/default_async_handler.hpp
+53-0libsycl/include/sycl/__impl/info/event.hpp
+47-0libsycl/src/detail/spinlock.hpp
+455-5523 files not shown
+774-16229 files

LLVM/project f48b09bclang/lib/Driver/ToolChains Clang.cpp, llvm/lib/Target/DirectX DXILTranslateMetadata.cpp DXContainerGlobals.cpp

[Driver][DirectX] Add `/Qsource_in_debug_module` flag (#204415)

Adds a flag that embeds the source code info into `dx.source` nodes in
bitcode, for both main DXContainer and PDB file output. For the PDB
file, it also removes the `SRCI` part from the output.
DeltaFile
+109-0llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Strip.ll
+15-9llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
+7-4llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
+4-0llvm/test/CodeGen/DirectX/embed-ildb.ll
+4-0clang/lib/Driver/ToolChains/Clang.cpp
+2-1llvm/lib/Target/DirectX/DXContainerGlobals.cpp
+141-142 files not shown
+146-148 files

LLVM/project a208080llvm/lib/Target/AMDGPU SIDefines.h, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUInstPrinter.cpp AMDGPUMCCodeEmitter.cpp

[NFC][AMDGPU] Use SIInstrFlags predicates in MC layer (#206766)

Replace raw TSFlags accesses with SIInstrFlags predicate calls in
AMDGPUInstPrinter and AMDGPUMCCodeEmitter.

Part of a series following the introduction of SIInstrFlags predicates.
DeltaFile
+16-25llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+6-9llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+3-0llvm/lib/Target/AMDGPU/SIDefines.h
+25-343 files

LLVM/project 3485d85clang/lib/Parse ParseDeclCXX.cpp, clang/test/SemaCXX constexpr-late-instantiation.cpp

[Clang] Ensure correct template parameter depth for abbreviated templates (#209693)

This fixes another case of member functions where we overlooked template
depths when only abbreviated template parameters are involved.

This mirrors previous fix cfb25203c25f, but I don't intend to put it in
ParseTrailingRequiresClause because we might want the similar fix for
e.g. noexcept expressions, so let's keep it inline for future refactor.

The example comes from #205557.
DeltaFile
+32-2clang/test/SemaCXX/constexpr-late-instantiation.cpp
+6-0clang/lib/Parse/ParseDeclCXX.cpp
+38-22 files

LLVM/project 4b455a9clang/docs ReleaseNotes.md, clang/lib/Sema SemaBoundsSafety.cpp

[BoundsSafety][Sema] Allow `sized_by`/`sized_by_or_null` on pointers to structs with a flexible array member (#209603)

`Sema::CheckCountedByAttrOnField()` in `SemaBoundsSafety.cpp` rejects
the `counted_by` family of attributes when the pointee is a struct that
contains a flexible array member (FAM). For example:

```
struct has_unannotated_fam {
  int count;
  int buffer[];
};

struct on_member_pointer_struct_with_fam {
  int size;
  struct has_unannotated_fam *objects __counted_by(size);
};
```

This restriction makes sense for `counted_by`/`counted_by_or_null`

    [33 lines not shown]
DeltaFile
+7-0clang/docs/ReleaseNotes.md
+0-4clang/test/Sema/attr-sized-by-or-null-struct-ptrs.c
+0-4clang/test/Sema/attr-sized-by-struct-ptrs.c
+2-1clang/lib/Sema/SemaBoundsSafety.cpp
+0-2clang/test/Sema/attr-sized-by-or-null-late-parsed-struct-ptrs.c
+0-2clang/test/Sema/attr-sized-by-late-parsed-struct-ptrs.c
+9-136 files

LLVM/project 94ef4fclibc/test/UnitTest ConstraintHandlerCheckingTest.h CMakeLists.txt

[libc] Annex K: Add constraint handler unit test class (#197707)

This unit test class will be useful for the tests related to Annex K.
The functions in Annex K may call a constraint handler, so this new unit
test class will facilitate the checks that the constraint handling
mechanism is working as expected.
DeltaFile
+53-0libc/test/UnitTest/ConstraintHandlerCheckingTest.h
+10-0libc/test/UnitTest/CMakeLists.txt
+63-02 files

LLVM/project 9e1b9dbclang/lib/Driver Driver.cpp

clang: Remove unnecessary cstdlib include

The comment says it's needed for getenv, but this file does
not directly use getenv; it uses sys::Process::GetEnv.
DeltaFile
+0-1clang/lib/Driver/Driver.cpp
+0-11 files

LLVM/project 4aa1590clang/docs ReleaseNotes.md, clang/lib/StaticAnalyzer/Checkers DeadStoresChecker.cpp

[analyzer] Ignoring `T v=v;` idiom for uninitialized variable checker and dead store checker (#187530)

Closing #173210

The self-assignment initialization `Type var = var;` is an idiom in C
code. The analyzer is expected to suppress the uninitialized assignment
reports and dead store reports for this idiom. Variables that are really
uninitialized will be reported until they are actually used. Since GCC
will not generate assembly code for such usage, even if under -O0
optimization (but Clang will), this patch resolves this problem by
ignoring such self-assigned `DeclStmt`s in the `ExprEngine`, as well as
in the `DeadStoreObs` of the dead store checker.

This ignorance will be applied to C variables and non-reference C++
variables. For record types in C++, since the constructors will always
be invoked, they will not be affected by this change.
DeltaFile
+111-0clang/test/Analysis/issue-173210-self-assign-init.c
+21-0clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
+6-0clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
+5-0clang/docs/ReleaseNotes.md
+143-04 files

LLVM/project 0e877fdllvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/lib/Transforms/Utils SimplifyLibCalls.cpp

Reland "[InstCombine] Combine llvm.sin/llvm.cos libcall pairs into llvm.sincos" (#194616)

This reland #184760

Fixed https://lab.llvm.org/buildbot/#/builders/123/builds/39337

The root cause is new created llvm.sincos is inserted into the right
after of the sin/cos's argument, however we didn't check if it's PHI, it
may cause it inserted into the middle of PHIs, and then fail the
verification.

Teach InstCombine to recognize pairs of `llvm.sin(x)` and `llvm.cos(x)`
intrinsic calls that share the same argument and replace them with a
single `llvm.sincos(x)` call, extracting the individual results.

The optimization works in two phases:

1. **SimplifyLibCalls**: Convert `sin`/`cos` C library calls (e.g.
   `sinf`, `cosf`, `sin`, `cos`, `sinl`, `cosl`) into `llvm.sin` /

    [10 lines not shown]
DeltaFile
+472-0llvm/test/Transforms/InstCombine/sincos.ll
+77-0llvm/test/Transforms/InstCombine/sincos-fpmath.ll
+73-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+32-18llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
+29-11llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
+20-2llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+703-314 files not shown
+719-5610 files

LLVM/project 3e4160fllvm/lib/Target/X86 X86LowerTileCopy.cpp, llvm/test/CodeGen/X86/AMX pr209512.ll

[X86] Skip debug instructions in tile copy lowering (#209640)

X86LowerTileCopy iterates over instructions in reverse to track live
registers, calling LiveRegUnits::stepBackward on every instruction
unconditionally. Since commit 16b2ef32 added an assertion that
stepBackward must not receive debug instructions, functions containing
debug info hit the assertion during tile copy lowering.
This patch skips debug instructions early in the loop, matching the
guard pattern used in RegisterScavenging.cpp and X86FixupBWInsts.cpp.

Fixes #209512
DeltaFile
+28-0llvm/test/CodeGen/X86/AMX/pr209512.ll
+2-0llvm/lib/Target/X86/X86LowerTileCopy.cpp
+30-02 files

LLVM/project 1a0ddbdllvm/include/llvm/CodeGen/GlobalISel Combiner.h, llvm/lib/CodeGen/GlobalISel Combiner.cpp

[GlobalISel] Filter combiner worklists (#197693)

This follows on from #196017 which added an opcode predicate for GICombiner
matchers and used it to return from tryCombineAll before executing the match
table.

The better approach is to not add opcodes with no combines to the worklist in
the first place. This is a further -0.35% CTMark geomean improvement on
aarch64-O0-g, sqlite is -0.67%.

https://llvm-compile-time-tracker.com/compare.php?from=35f5d7ea802eae78b26a5fb2a46f072acd15f49d&to=c356bec46b68b59f37b26347f93676c9102d810c&stat=instructions%3Au

I also measured O3 locally and it's positive:

```
stage1-aarch64-O3 -fglobal-isel
                 instructions:u                 diff
                            old           new
7zip               203863583445  203865335443  0.00%

    [15 lines not shown]
DeltaFile
+7-4llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+1-3llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
+2-1llvm/lib/CodeGen/GlobalISel/Combiner.cpp
+2-0llvm/include/llvm/CodeGen/GlobalISel/Combiner.h
+12-84 files

LLVM/project b9c1e15clang/test/Driver msvc-link.c

[clang][test] Avoid relying on `-fuse-ld=ld` default value for marm64x test (#209597)

Test case added in #209324

(cherry picked from commit 0b908e100f3d88232aa3b0190e23e41ca327edf1)
DeltaFile
+4-4clang/test/Driver/msvc-link.c
+4-41 files

LLVM/project ba9f8e4clang/lib/StaticAnalyzer/Checkers UndefinedAssignmentChecker.cpp, clang/test/Analysis operator-calls.cpp

[clang][analyzer] Improved message in uninitialized.Assign at default assignment (#208173)
DeltaFile
+18-6clang/test/Analysis/operator-calls.cpp
+15-0clang/lib/StaticAnalyzer/Checkers/UndefinedAssignmentChecker.cpp
+33-62 files

LLVM/project 0d33149llvm/test/CodeGen/AMDGPU unsupported-image-sample.ll uaddsat.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (35) (#209599)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
+6-6llvm/test/CodeGen/AMDGPU/uaddsat.ll
+6-6llvm/test/CodeGen/AMDGPU/trap-abis.ll
+6-6llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
+6-6llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
+5-5llvm/test/CodeGen/AMDGPU/unsupported-code-object-version.ll
+36-3688 files not shown
+198-19894 files

LLVM/project 67dabeeclang/lib/AST/ByteCode Interp.cpp, clang/test/AST/ByteCode cxx11.cpp

[clang][bytecode] Fix "declared here" location of ... (#209696)

... "read outside its lifetime" diagnostics.

We should be pointing to the first decl.
DeltaFile
+7-0clang/test/AST/ByteCode/cxx11.cpp
+2-3clang/lib/AST/ByteCode/Interp.cpp
+9-32 files

LLVM/project 13bdd50llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 scalable_masked_interleaved_stores.ll

[AArch64][ISel] Enable masked interleaved stores for splat values (#207950)

Enable masked interleaved store combine to recognise splat values and
split them into SVE component vectors. This allows the existing stN
lowering path to handle masked stores where the stored value is a splat
rather than an explicit vector.interleave result.
DeltaFile
+51-8llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+56-0llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
+107-82 files

LLVM/project 38e1487llvm/test/CodeGen/SystemZ zos-ppa2.ll

Fix test that had a check embedded which depended on the current LLVM version number. (#209530)

When the test was refactored, it embedded the current LLVM version
number in one of the check strings so that when I bumped the LLVM
version to 24, the test failed since it was expecting 23 but the
compiler was now generating 23.

Fix this issue by changing the check to a regex so it doesn't need
updating after every LLVM version change.

(cherry picked from commit 1a072b5f008321f22e61f744b7474fe52f0ee48c)
DeltaFile
+2-1llvm/test/CodeGen/SystemZ/zos-ppa2.ll
+2-11 files

LLVM/project 06bf4bfllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-6.ll vector-interleaved-store-i8-stride-6.ll

[X86] combineINSERT_SUBVECTOR - enable shuffle combining of concat(extractsub(shuffle),extractsub(shuffle)) patterns (#209510)

Reuse the peekThroughBitcastsAndExtracts helper that we already use for insertsub(shuffle,extractsub(shuffle)) patterns
DeltaFile
+590-590llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+166-166llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+10-9llvm/lib/Target/X86/X86ISelLowering.cpp
+2-5llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
+768-7704 files

LLVM/project 22aefbclldb/packages/Python/lldbsuite/test/tools/lldb_dap dap_types.py, llvm/test/CodeGen/AMDGPU amdgpu-codegenprepare-idiv.ll vector-reduce-fminimum.ll

Merge branch 'main' into users/ssahasra/av-metadata-clang
DeltaFile
+23,904-12llvm/test/CodeGen/RISCV/clmul.ll
+1,419-2,129llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+1,640-1,695llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+1,482-1,543llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+2,262-0llvm/test/Transforms/SLPVectorizer/X86/idiv-by-const.ll
+0-2,026lldb/packages/Python/lldbsuite/test/tools/lldb_dap/dap_types.py
+30,707-7,4054,234 files not shown
+100,103-40,5274,240 files

LLVM/project 2af345alldb/include/lldb/Target MemoryRegionInfo.h, lldb/source/Plugins/Process/Utility LinuxProcMaps.cpp

[lldb-server] Add type info for qMemoryinfo reponse (#209235)

Use the name of the memory region to report the known cases where an
address points to stack/heap: "[stack]" or "[heap"].

According to [1], the "[stack]" name is the main thread's stack region:
```
  [stack]
                     The initial process's (also known as the main
                     thread's) stack.
```

For other threads, we can't know their stack region because this field
got removed in newer kernels:

```
 [stack:tid] (from Linux 3.4 to Linux 4.4)
        A thread's stack (where the tid is a thread ID).  It
        corresponds to the /proc/pid/task/tid/ path.  This

    [9 lines not shown]
DeltaFile
+12-1lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
+10-1lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
+4-1lldb/include/lldb/Target/MemoryRegionInfo.h
+4-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+30-34 files

LLVM/project b3bb0d1llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/SPIRV SPIRVLegalizePointerCast.cpp

Merge branch 'main' into users/arsenm/llvm/amdgpu-migrate-tests-subarch-34
DeltaFile
+131-18llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+73-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+45-0llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll
+41-4llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+24-11llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+34-0llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizePointerCast.ll
+348-3383 files not shown
+539-20589 files

LLVM/project bdd15ffllvm/test/CodeGen/AMDGPU strict_fsub.f16.ll strict_fmul.f16.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (34) (#209598)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+12-12llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
+12-12llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
+10-10llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
+8-8llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
+8-8llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
+62-6288 files not shown
+307-30794 files

LLVM/project 396a2d7llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-insert-subvector.ll

[RISCV][P-ext] Fold packed insert-into-zero to zero-extend (#208006)

An insert_subvector of a 32-bit packed type (v4i8/v2i16) into a zero-filled
64-bit packed vector at index 0 is a zero-extend. Fold it so RV64 emits a
single zext.w instead of scalarizing into a byte-wise repack; RV32
concatenates with a zero half into the GPRPair.
DeltaFile
+45-0llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll
+30-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+75-02 files

LLVM/project 046acffllvm/include/llvm/IR IntrinsicsRISCV.td, llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoP.td

[RISCV][P-ext] Add packed saturating rounding shift codegen (#208630)

Add codegen for `pssha`, `psshar`, `psshl`, and `psshlr` on RV32 and
RV64.
DeltaFile
+131-18llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+41-4llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+43-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+15-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+10-0llvm/include/llvm/IR/IntrinsicsRISCV.td
+240-225 files

LLVM/project 5b345aellvm/docs ReleaseNotes.md, llvm/lib/Target/RISCV RISCVInstrInfoZilx.td RISCVFeatures.td

Add release note

Created using spr 1.3.6-beta.1
DeltaFile
+16-16llvm/test/MC/RISCV/zilx-valid-rv64.s
+8-8llvm/test/MC/RISCV/zilx-valid-rv32.s
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+2-2llvm/lib/Target/RISCV/RISCVFeatures.td
+2-1llvm/docs/ReleaseNotes.md
+1-1llvm/test/CodeGen/RISCV/features-info.ll
+31-301 files not shown
+32-317 files

LLVM/project 60139c4llvm/docs ReleaseNotes.md, llvm/lib/Target/RISCV RISCVFeatures.td RISCVInstrInfoZilx.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+16-16llvm/test/MC/RISCV/zilx-valid-rv64.s
+8-8llvm/test/MC/RISCV/zilx-valid-rv32.s
+2-2llvm/lib/Target/RISCV/RISCVFeatures.td
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+1-1llvm/docs/ReleaseNotes.md
+1-1llvm/test/CodeGen/RISCV/features-info.ll
+30-301 files not shown
+31-317 files

LLVM/project 771d152llvm/lib/Target/SPIRV SPIRVLegalizePointerCast.cpp, llvm/test/CodeGen/SPIRV/passes SPIRVLegalizePointerCast.ll

[SPIR-V] Preserve offset alignment in pointer cast legalization (#209251)

Splitting a load/store into per-element accesses reused the original
alignment for every element, which could wrongly strengthen or discard
alignment

Compute each split access alignment via commonAlignment with its
DataLayout derived byte offset matching SPIRVLegalizerInfo.cpp
DeltaFile
+24-11llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+34-0llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizePointerCast.ll
+58-112 files

LLVM/project b78a0acllvm/lib/Target/SPIRV SPIRVUtils.cpp

[SPIR-V] Unify duplicated named MDNode lookup helper (#209376)
DeltaFile
+16-18llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+16-181 files

LLVM/project af84127llvm/lib/Target/SPIRV SPIRVCallLowering.cpp

[SPIR-V] Remove dead typed pointer check in getArgSPIRVType (#209515)

Arg->getType() can never be a TypedPointerType since opaque pointers are
now the only pointer representation in LLVM IR
DeltaFile
+0-5llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+0-51 files

LLVM/project a9d4741clang/test/Driver print-supported-extensions-riscv.c, llvm/lib/Target/RISCV RISCVInstrInfoZilx.td RISCVFeatures.td

Change the expanded name of Zilx

Created using spr 1.3.6-beta.1
DeltaFile
+16-16llvm/test/MC/RISCV/zilx-valid-rv64.s
+8-8llvm/test/MC/RISCV/zilx-valid-rv32.s
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+2-2llvm/lib/Target/RISCV/RISCVFeatures.td
+1-1llvm/test/CodeGen/RISCV/features-info.ll
+1-1clang/test/Driver/print-supported-extensions-riscv.c
+30-301 files not shown
+31-317 files