LLVM/project 09b607allvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-usabs.ll

Add comment
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+3-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-usabs.ll
+3-01 files

LLVM/project 99e6632clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c poly64.c

[CIR][AArch64] Upstream vector-shift-right-and-insert NEON builtins (#196776)

Related to https://github.com/llvm/llvm-project/issues/185382

CIR lowering for vector-shift-right-and-insert intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-insert)

Port tests from clang/test/CodeGen/AArch64/neon_intrinsics.c and
clang/test/CodeGen/AArch64/poly64.c to
clang/test/CodeGen/AArch64/neon/intrinsics.c
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+0-282clang/test/CodeGen/AArch64/neon-intrinsics.c
+83-9clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+0-28clang/test/CodeGen/AArch64/poly64.c
+398-3194 files

LLVM/project b186960llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll fixed-vectors-shuffle-int-interleave.ll

Revert "[RISCV][CodeGen] Use vzip.vv for e64 interleave shuffles with Zvzip (…"

This reverts commit a4b1361f33139e7a0a02edee1a1b012740951e01.
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+20-6llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+17-8llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+4-9llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+41-233 files

LLVM/project c94e5f3llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp

AMDGPU/GlobalISel: Move executeInWaterfallLoop call from lower (#199701)

WFI is an argument to applyMappingSrc and lower,
move executeInWaterfallLoop after these two return.
Also set insert point in executeInWaterfallLoop to
avoid need to set insert point before calling it.
DeltaFile
+6-5llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+6-51 files

LLVM/project 698d44bclang/lib/CodeGen CGBuiltin.cpp, clang/lib/Sema SemaChecking.cpp

[clang] Add builtin to clear padding bytes (prework for P0528R3) (#75371)

Add builtin to clear padding bytes. This is the pre-work to implement
`std::atomic::compare_exchange_[weak/strong]` that ignores padding bits.
PR draft here: https://github.com/llvm/llvm-project/pull/76180

This PR picked up this patch from 3 years ago
https://reviews.llvm.org/D87974

The above patch no longer works as things changed quite a lot. I've made
some changes on top of the above patch:


it handles:
- struct
- builtin types with paddings (like `long double` and types with
`__attribute__((ext_vector_type(N)))`
- _Complex long double
- constant array

    [7 lines not shown]
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+886-0libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
+344-0clang/lib/CodeGen/CGBuiltin.cpp
+98-0clang/test/SemaCXX/builtin-clear-padding.cpp
+64-0clang/lib/Sema/SemaChecking.cpp
+3,906-03 files not shown
+3,968-09 files

LLVM/project 19d2965llvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

update perf_test

Created using spr 1.3.8-beta.1
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+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,723 files not shown
+68,398-29,5951,729 files

LLVM/project 72795dbllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
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+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
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+68,396-29,5941,728 files

LLVM/project d63f996bolt/test merge-fdata-no-lbr-event-multi.test merge-fdata-no-lbr-event.test, bolt/tools/merge-fdata merge-fdata.cpp

[BOLT][merge-fdata] Preserve event names



Test Plan: added merge-fdata-no-lbr-event*.test

Reviewers:
maksfb, paschalis-mpeis, yozhu, yota9, yavtuk, rafaelauler, ayermolo

Reviewed By: rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/199323
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+21-2bolt/tools/merge-fdata/merge-fdata.cpp
+22-0bolt/test/merge-fdata-no-lbr-event-multi.test
+18-0bolt/test/merge-fdata-no-lbr-event.test
+61-23 files

LLVM/project 7a93152clang/include/clang/Basic riscv_vector.td, clang/lib/CodeGen/TargetBuiltins RISCV.cpp

Merge commit '853d532794be83adc97d51c9ff8c9095ce32631b' into users/chenshanzhi/AArch64-TTI-getTgtMemIntrinsic
DeltaFile
+178-267llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+71-67llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+49-43clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+32-27clang/include/clang/Basic/riscv_vector.td
+21-18clang/utils/TableGen/RISCVVEmitter.cpp
+10-12clang/lib/Support/RISCVVIntrinsicUtils.cpp
+361-4343 files not shown
+371-4389 files

LLVM/project 3e0c818clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp CIRGenTypes.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-image.hip

[CIR][AMDGPU] Adds lowering for amdgcn image load/store builtins (#198184)

Support for lowering of amdgcn_image_load/store for AMDGPU builtins to
clangIR.
Followed similar lowering from clang->llvmir:
`clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp`.

Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/2058
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+73-12clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+17-0clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+556-123 files

LLVM/project 4c9296dbolt/tools/driver llvm-bolt.cpp

[BOLT][NFC] Unify perf data setting

Combine opts::PerfData handling into one place per driver (llvm-bolt and
heatmap).
* Allow using perf data directly after DataAggregator/DataReader
  unification in #195986.
* Drop redundant perf data checks in perf2boltMode done by setProfile.

Test Plan: NFC

Reviewers:
ritter-x2a, david-salinas, grypp, Pierre-vh, dcaballe, aartbik, adam-smnk, fabianmcg, yota9, JDevlieghere, banach-space, xlauko, nikic, #reviewers-libcxx, rafaelauler, Moxinilian, nicolasvasilache, yozhu, ayermolo, paschalis-mpeis, lamb-j, andykaylor, #reviewers-libc, vangthao95, bcardosolopes, yavtuk, aaronmondal, rupprecht, matthias-springer, keith, maksfb, lanza, Jianhui-Li, charithaintc

Reviewed By: yozhu, rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/199322
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+3-221 files

LLVM/project c797b79clang/test/CodeGen builtin-masked.c, clang/test/Sema warn-lifetime-safety.cpp

Merge branch 'main' into users/chenshanzhi/AArch64-TTI-getTgtMemIntrinsic
DeltaFile
+178-267llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+416-0mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
+109-109clang/test/Sema/warn-lifetime-safety.cpp
+195-0clang/test/CodeGen/builtin-masked.c
+71-67llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+127-0mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaOps.cpp
+1,096-44355 files not shown
+1,620-77761 files

LLVM/project b926cf7mlir/include/mlir/Conversion/TosaToSPIRVTosa TosaToSPIRVTosa.h, mlir/lib/Conversion/TosaToSPIRVTosa TosaToSPIRVTosaOps.cpp CMakeLists.txt

[mlir][tosa][spirv] Lower TOSA elementwise ops to SPIR-V TOSA (#199505)

Add conversion patterns for simple TOSA elementwise operations to the
SPIR-V TOSA dialect.

The lowering covers unary and binary elementwise ops with shared pattern
templates, plus min/max handling for NaN propagation mode.

Add focused conversion tests that check the generated SPIR-V TOSA ops.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+416-0mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
+127-0mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaOps.cpp
+2-0mlir/include/mlir/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.h
+1-0mlir/lib/Conversion/TosaToSPIRVTosa/CMakeLists.txt
+1-0mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
+547-05 files

LLVM/project 9923871bolt/include/bolt/Profile DataAggregator.h, bolt/lib/Profile DataAggregator.cpp

[BOLT][NFC] Split out DataAggregator::parseInput



Test Plan: NFC

Reviewers:
paschalis-mpeis, maksfb, ayermolo, yavtuk, yozhu, rafaelauler, yota9

Reviewed By: yozhu, rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/199321
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+12-7bolt/lib/Profile/DataAggregator.cpp
+4-1bolt/include/bolt/Profile/DataAggregator.h
+16-82 files

LLVM/project 66bafd4mlir/lib/Support TypeID.cpp

[MLIR] Improve TypeID anonymous namespace check to handle GCC's __PRETTY_FUNCTION__ format (#199634)

The anonymous namespace detection in
`FallbackTypeIDResolver::registerImplicitTypeID` only checked for
Clang's `(anonymous namespace)` and MSVC's `anonymous-namespace`
formats. GCC produces `{anonymous}` in `__PRETTY_FUNCTION__`, silently
bypassing the check.
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+7-5mlir/lib/Support/TypeID.cpp
+7-51 files

LLVM/project f5bda2bclang/test/Sema warn-lifetime-safety.cpp

[LifetimeSafety] Change new tests' warnings to new ones  (#199887)

cc: @usx95
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+3-3clang/test/Sema/warn-lifetime-safety.cpp
+3-31 files

LLVM/project a4b1361llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll fixed-vectors-shuffle-int-interleave.ll

[RISCV][CodeGen] Use vzip.vv for e64 interleave shuffles with Zvzip (#199512)

Allow e64 interleave shuffles to use the standard Zvzip `vzip.vv`
lowering when the operand type is legal for Zvzip, just the same as what
XrivosVizip already does.
DeltaFile
+6-20llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+8-17llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+9-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+23-413 files

LLVM/project 6de9a33llvm/docs/CommandGuide llvm-debuginfo-analyzer.rst, llvm/include/llvm/DebugInfo/LogicalView/Readers LVIRReader.h

Revert "[llvm-debuginfo-analyzer] Add support for LLVM IR format. (#135440)" (#199890)

This reverts commit 6bbbf743ae49736ba438e9dbd14a5bd0f4166382.

There are link issues with some buildbots.
DeltaFile
+0-2,630llvm/lib/DebugInfo/LogicalView/Readers/LVIRReader.cpp
+0-362llvm/unittests/DebugInfo/LogicalView/IRReaderTest.cpp
+0-302llvm/include/llvm/DebugInfo/LogicalView/Readers/LVIRReader.h
+134-87llvm/docs/CommandGuide/llvm-debuginfo-analyzer.rst
+0-168llvm/test/tools/llvm-debuginfo-analyzer/IR/08-ir-multiple-compile-units.test
+0-151llvm/test/tools/llvm-debuginfo-analyzer/IR/01-ir-select-logical-elements.test
+134-3,70035 files not shown
+152-5,40641 files

LLVM/project 685c27fllvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

actually cover all values in the enum scope
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+3-0llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+3-01 files

LLVM/project 2634949utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] Fixes 532940b (#199874)

This fixes 532940bdee66bf5f36a70578698aab66f16919af.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
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+3-01 files

LLVM/project 77d3da6clang/lib/Sema SemaChecking.cpp, clang/test/CodeGen builtin-masked.c

[Clang] Accept gnu vectors in __builtin_masked* (#198248)

There doesn't seem to be a good reason to reject gnu vectors in these
builtins. The error messages for that case are also rather bizzare,
which doesn't help with figuring out what's going wrong.
DeltaFile
+195-0clang/test/CodeGen/builtin-masked.c
+16-11clang/lib/Sema/SemaChecking.cpp
+211-112 files

LLVM/project 2b28679mlir/include/mlir/IR MLIRContext.h, mlir/lib/IR MLIRContext.cpp

[MLIR] Add a non-const ActionHandler getter to MLIRContext (#199652)

#197230 added a getter for the ActionHandler, but only returns a const
ref with a non-const accessor.
Instead provide both variants: a const accessor returning a const ref
and non-const one returning a mutable ref.
DeltaFile
+5-1mlir/lib/IR/MLIRContext.cpp
+3-1mlir/include/mlir/IR/MLIRContext.h
+8-22 files

LLVM/project f5517e2clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip

[CIR][AMDGPU] Implement lowering for __builtin_amdgcn_dispatch_ptr
DeltaFile
+29-6clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+37-62 files

LLVM/project bcb555dlldb/test/API lit.cfg.py, llvm/utils/lit/lit TestingConfig.py main.py

Revert "[lit] Move maxIndividualTestTime from global to test suite config (#1…"

This reverts commit 4ee7e900f321c78271c87da47f1d7bd4263f3e7c.
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+0-16llvm/utils/lit/lit/TestingConfig.py
+12-1llvm/utils/lit/lit/main.py
+4-4llvm/utils/lit/lit/TestRunner.py
+1-4llvm/utils/lit/lit/LitConfig.py
+2-2llvm/utils/lit/lit/formats/googletest.py
+1-1lldb/test/API/lit.cfg.py
+20-285 files not shown
+25-3311 files

LLVM/project 6bbbf74llvm/docs/CommandGuide llvm-debuginfo-analyzer.rst, llvm/include/llvm/DebugInfo/LogicalView/Readers LVIRReader.h

[llvm-debuginfo-analyzer] Add support for LLVM IR format. (#135440)

llvm-debuginfo-analyzer is a command line tool that processes debug
info contained in a binary file and produces a debug information
format agnostic “Logical View”, which is a high-level semantic
representation of the debug info, independent of the low-level format.

Add support for the LLVM IR format and be able to generate logical
views. Both textual representation (.ll) and bitcode (.bc) formats
are supported.
DeltaFile
+2,630-0llvm/lib/DebugInfo/LogicalView/Readers/LVIRReader.cpp
+362-0llvm/unittests/DebugInfo/LogicalView/IRReaderTest.cpp
+302-0llvm/include/llvm/DebugInfo/LogicalView/Readers/LVIRReader.h
+87-134llvm/docs/CommandGuide/llvm-debuginfo-analyzer.rst
+168-0llvm/test/tools/llvm-debuginfo-analyzer/IR/08-ir-multiple-compile-units.test
+151-0llvm/test/tools/llvm-debuginfo-analyzer/IR/01-ir-select-logical-elements.test
+3,700-13435 files not shown
+5,406-15241 files

LLVM/project a3adb54clang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeSafety.h, clang/include/clang/Basic DiagnosticSemaKinds.td

[LifetimeSafety] Add details for `-Wlifetime-safety-return-stack-addr` diagnostic (#199432)

Most of the diagnostic's wording was taken from `-Wreturn-stack-address`
with exceptions such as:
- We do not special-case `[[clang::musttail]]`
- We do not special-case `CompoundLiteralExpr` as it is mostly a C
thing.

This patch does not add any new tests, it only updates already existing
test warnings to follow the new wording.

Comes as part of completing #186002
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+106-106clang/test/Sema/warn-lifetime-safety.cpp
+44-44clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
+29-6clang/lib/Sema/SemaLifetimeSafety.h
+13-11clang/test/Sema/warn-lifetime-safety-suggestions.cpp
+9-10clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-2clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
+202-1791 files not shown
+203-1807 files

LLVM/project 505a611.github new-issues-labeler.yml

Auto-label LifetimeSafety issues with `clang:temporal-safety` (#199522)

cc: @usx95
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+3-0.github/new-issues-labeler.yml
+3-01 files

LLVM/project 034ba70clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip

[CIR][AMDGPU] Implement lowering for __builtin_amdgcn_dispatch_ptr
DeltaFile
+23-6clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+31-62 files

LLVM/project d16d14fllvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.av.load.b128.ll accvgpr-spill-scc-clobber.mir

Merge branch 'main' into users/el-ev/_itaniumdemangle_fix_template_args_subst
DeltaFile
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+8,633-8,584llvm/test/CodeGen/Thumb2/mve-clmul.ll
+12,365-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
+1,243-8,768llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
+3,436-2,769llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+55,118-41,0446,730 files not shown
+369,552-189,0656,736 files

LLVM/project 5954e21llvm/utils/lit/tests lit-config-readonly.py, llvm/utils/lit/tests/Inputs/lit-config-readonly lit.cfg dummy.txt

feedback addressed

Created using spr 1.3.7
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+1-1llvm/utils/lit/tests/lit-config-readonly.py
+0-1llvm/utils/lit/tests/Inputs/lit-config-readonly/lit.cfg
+0-1llvm/utils/lit/tests/Inputs/lit-config-readonly/dummy.txt
+1-33 files