LLVM/project 63dd996orc-rt/include/orc-rt SimpleNativeMemoryMap.h, orc-rt/lib/executor SimpleNativeMemoryMap.cpp

[orc-rt] Capture a Session& in SimpleNativeMemoryMap, fix TODOs. (#187200)

SimpleNativeMemoryMap now captures a reference to the Session that it
was constructed for. This is used to fix some outstanding TODOs: using
the real page size for the process, and reporting errors that were
previously discarded.
DeltaFile
+83-0orc-rt/unittests/SimpleNativeMemoryMapTest.cpp
+4-7orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
+2-1orc-rt/include/orc-rt/SimpleNativeMemoryMap.h
+89-83 files

LLVM/project 3515017llvm/include/llvm/CodeGen TargetLowering.h BasicTTIImpl.h, llvm/lib/CodeGen CodeGenPrepare.cpp

[CodeGen] Improve `getLoadExtAction` and friends (#181104)

Alternative approach to the same goals as #162407

This takes `TargetLoweringBase::getLoadExtAction`, renames it to
`TargetLoweringBase::getLoadAction`, merges `getAtomicLoadExtAction`
into it, and adds more inputs for relavent information (alignment,
address space).

The `isLoadExtLegal[OrCustom]` helpers are also modified in a matching
manner.

This is fully backwards compatible, with the existing `setLoadExtAction`
working as before. But this allows targets to override a new hook to
allow the query to make more use of the information. The hook
`getCustomLoadAction` is called with all the parameters whenever the
table lookup yields `LegalizeAction::Custom`, and can return any other
action it wants.
DeltaFile
+157-110llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+50-36llvm/include/llvm/CodeGen/TargetLowering.h
+28-5llvm/include/llvm/CodeGen/BasicTTIImpl.h
+22-9llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+7-6llvm/lib/CodeGen/CodeGenPrepare.cpp
+5-3llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+269-1693 files not shown
+275-1729 files

LLVM/project 9a2f23ellvm/include/llvm/CodeGen MachineFunction.h MachineBasicBlock.h, llvm/lib/CodeGen MachineBlockPlacement.cpp BranchRelaxation.cpp

[CodeGen] Use separate MBB number for analyses (#187086)

Block numbers are updated too frequently, which makes it difficult to
keep analyses up to date. Therefore, introduce a second number per basic
block that is used for analyses and is renumbered less often. This frees
analyses from providing somewhat efficient facilities for dealing with
changed block numbers, making it simpler to implement in e.g. LoopInfo
or CycleInfo.

(Currently, "less often" means not at all, but we might want to renumber
after certain passes if the numbering gets too sparse and no analyses
are preserved anyway.)

When we introduced a more general use of block numbers some time ago,
using the existing numbers seemed to be a somewhat obvious choice, but I
now think that this was a bad decision, as it conflates a number that is
used for ordering with a number that should be more stable.

MachineBasicBlock isn't particularly size-optimized and there's a fair

    [2 lines not shown]
DeltaFile
+22-15llvm/include/llvm/CodeGen/MachineFunction.h
+15-8llvm/include/llvm/CodeGen/MachineBasicBlock.h
+0-10llvm/lib/CodeGen/MachineBlockPlacement.cpp
+1-9llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+0-8llvm/lib/CodeGen/BranchRelaxation.cpp
+0-7llvm/lib/CodeGen/BasicBlockSections.cpp
+38-579 files not shown
+40-8315 files

LLVM/project 72a8273clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVMIR.cpp

remove redundant returns
DeltaFile
+0-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
+0-21 files

LLVM/project 14b4233orc-rt/include/orc-rt SimpleNativeMemoryMap.h SimpleSymbolTable.h, orc-rt/lib/executor SimpleNativeMemoryMap.cpp

[orc-rt] Publish controller interface from SimpleNativeMemoryMap ctor. (#187198)

Add named constructors to SimpleNativeMemoryMap to publish
SimpleNativeMemoryMap's controller interface when an instance is
constructed.

This supports correct setup by construction, since API clients can't
forget to publish the interface that the controller will need to
interact with the SimpleNativeMemoryMap object.
DeltaFile
+34-18orc-rt/unittests/SimpleNativeMemoryMapTest.cpp
+27-0orc-rt/include/orc-rt/SimpleNativeMemoryMap.h
+22-0orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
+5-1orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
+3-0orc-rt/include/orc-rt/SimpleSymbolTable.h
+91-195 files

LLVM/project 51fd033bolt/lib/RuntimeLibs InstrumentationRuntimeLibrary.cpp, bolt/runtime instr.cpp

[BOLT] Enable compatibility of instrumentation-file-append-pid with instrumentation-sleep-time (#183919)

This commit enables compatibility of instrumentation-file-append-pid and
instrumentation-sleep-time options. It also requires keeping the
counters mapping between the watcher process and the instrumented binary
process in shared mode. This is useful when we instrument a shared
library that is used by several tasks running on the target system. In
case when we cannot wait for every task to complete, we must use the
sleep-time option. Without append-pid option, we would overwrite the
profile at the same path but collected from different tasks, leading to
unexpected or suboptimal optimization effects.

Co-authored-by: Vasily Leonenko <vasily.leonenko at huawei.com>
DeltaFile
+5-7bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp
+1-1bolt/runtime/instr.cpp
+6-82 files

LLVM/project faf9cc2clang/lib/CIR/CodeGen CIRGenCall.cpp CIRGenModule.cpp, clang/test/CIR/CodeGen arg-attrs.cpp invoke-attrs.cpp

[CIR] Fix reference alignment to use pointee type

getNaturalTypeAlignment on a reference type returned pointer alignment
instead of pointee alignment. Pass the pointee type with
forPointeeType=true to match traditional codegen's
getNaturalPointeeTypeAlignment behavior. Fix applies to both argument
and return type attribute construction paths.
DeltaFile
+27-4clang/test/CIR/CodeGen/arg-attrs.cpp
+9-7clang/lib/CIR/CodeGen/CIRGenCall.cpp
+7-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+3-3clang/test/CIR/CodeGen/invoke-attrs.cpp
+2-4clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+3-0clang/lib/CIR/CodeGen/CIRGenModule.h
+51-186 files

LLVM/project b5ddd3aclang/test/CodeGenHIP builtins-amdgcn-buffer-format.hip

[Clang][AMDGPU][test] Added -O1 to map builtin:intrinsic map and removed extra allocas in CHECK lines
DeltaFile
+21-149clang/test/CodeGenHIP/builtins-amdgcn-buffer-format.hip
+21-1491 files

LLVM/project 9502925orc-rt/unittests SessionTest.cpp CommonTestUtils.h

[orc-rt] De-duplicate some test helper APIs. (#187187)

Moves noErrors, mockExecutorProcessInfo, and NoDispatcher into
CommonTestUtils.h where they can be re-used between tests.
DeltaFile
+2-16orc-rt/unittests/SessionTest.cpp
+17-0orc-rt/unittests/CommonTestUtils.h
+2-14orc-rt/unittests/BootstrapInfoTest.cpp
+21-303 files

LLVM/project 9d43029clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVMIR.cpp, clang/test/CIR/CodeGenHIP amdgpu-module-flags.hip

Fix amendFunction and amendModule returns
DeltaFile
+19-10clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
+1-5clang/test/CIR/CodeGenHIP/amdgpu-module-flags.hip
+20-152 files

LLVM/project dc8fd02clang/test/CXX/drs cwg2947.cpp cwg14xx.cpp

[clang] Reshuffle compiler options in C++ DR tests

This patch changes the order of compiler options on RUN lines so that options that differ in length (like -verify with its multiple prefixes) are at the end. This way it's much easier to see what is common and what is different between RUN lines
DeltaFile
+27-27clang/test/CXX/drs/cwg2947.cpp
+14-14clang/test/CXX/drs/cwg14xx.cpp
+7-7clang/test/CXX/drs/cwg12xx.cpp
+7-7clang/test/CXX/drs/cwg13xx.cpp
+7-7clang/test/CXX/drs/cwg158.cpp
+7-7clang/test/CXX/drs/cwg15xx.cpp
+69-6935 files not shown
+311-31141 files

LLVM/project ee0ac74mlir/include/mlir/Dialect/X86 Transforms.h, mlir/include/mlir/Dialect/X86/TransformOps X86TransformOps.td

[mlir][x86] Lower packed type vector.contract to AMX dot-product (#182810)

A transform pass to lower `vector.contract` operation to (a)
`amx.tile_mulf` for BF16, or (b) `amx.tile_muli` for Int8 packed types.
DeltaFile
+1,034-0mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
+675-0mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
+11-0mlir/include/mlir/Dialect/X86/TransformOps/X86TransformOps.td
+6-0mlir/include/mlir/Dialect/X86/Transforms.h
+5-0mlir/lib/Dialect/X86/TransformOps/X86TransformOps.cpp
+1-0mlir/lib/Dialect/X86/Transforms/CMakeLists.txt
+1,732-06 files

LLVM/project 37d1e3dflang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP declare-simd.f90

[flang][mlir][OpenMP] Add linear modifier (val, ref, uval)

Add support for OpenMP linear modifiers `val`, `ref`, and `uval`
as defined in OpenMP 5.2 (5.4.6).
DeltaFile
+106-23mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+75-0mlir/test/Dialect/OpenMP/invalid.mlir
+71-0mlir/test/Dialect/OpenMP/ops.mlir
+54-6flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+43-2flang/test/Lower/OpenMP/declare-simd.f90
+16-0mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td
+365-318 files not shown
+409-5914 files

LLVM/project f4e64fdlld/ELF Writer.cpp, lld/test/ELF/linkerscript symbol-only-align.test nobits-offset.s

[ELF] Orphan placement: remove hasInputSections condition

https://reviews.llvm.org/D60131 (Change default output section type to
SHT_PROGBITS) caused a orphan placement regression for Fuchsia
`zircon.elf`: #40998 The orphan section `code_patch_table` was placed
before the first output section description `.text.boot0`, breaking the
address requirement.

https://reviews.llvm.org/D61197 (Fix getRankProximity to "ignore" not
live sections) fixed the regression by adding a `Live` condition (which
later became `hasInputSections`).

This condition added complexity, which turns out to be unneeded after

* 3bdc90e3ff4c9a18caeb3e6ad40fa5d15bbf9d5e ("[ELF] adjustOutputSections: update sortRank. NFC")
* 747d670baef35f0615b32652e93c97a2ff8dba18 ("[ELF] Make .interp/SHT_NOTE not special")
* #94099

The new orphan placement rule is slightly different (orphans can be

    [12 lines not shown]
DeltaFile
+5-11lld/ELF/Writer.cpp
+6-5lld/test/ELF/linkerscript/symbol-only-align.test
+1-1lld/test/ELF/linkerscript/nobits-offset.s
+1-1lld/test/ELF/linkerscript/tls-nobits-offset.s
+13-184 files

LLVM/project 2890f98offload/plugins-nextgen/level_zero/include L0Trace.h, offload/plugins-nextgen/level_zero/src L0Device.cpp

[OFFLOAD] Improve handling of synchronization errors in L0 plugin and reenable tests (#186927)

This change improves handling of errors during synchronization in Level
Zero plugin by ensuring cleanup of queues and events in case of an
synchronization error. As a result multiple tests stopped hanging.

---------

Co-authored-by: Duran, Alex <alejandro.duran at intel.com>
DeltaFile
+14-8offload/plugins-nextgen/level_zero/src/L0Device.cpp
+11-0offload/plugins-nextgen/level_zero/include/L0Trace.h
+1-2offload/test/api/omp_host_call.c
+1-2offload/test/sanitizer/ptr_outside_alloc_1.c
+1-2offload/test/sanitizer/ptr_outside_alloc_2.c
+1-2offload/test/libc/malloc_parallel.c
+29-1633 files not shown
+59-7439 files

LLVM/project 038c8d3llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-large-btc.ll weak-zero-siv-overflow.ll

[DA] Rewrite formula in the Weak Zero SIV tests (#183738)

This patch rewrites the formula in the Weak Zero SIV tests to match the
one used in the Strong SIV test that was updated in #179665. In this
form, `ConstantRange` is used so we don't need to pay attention to any
corner cases such as overflow.

Fix some test cases that were added in the past PRs to represent the
edge cases.
DeltaFile
+18-14llvm/lib/Analysis/DependenceAnalysis.cpp
+8-8llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll
+2-6llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-overflow.ll
+28-283 files

LLVM/project ce7fe20llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.umax.ll llvm.amdgcn.reduce.umin.ll

Rebase main + Remove compiler warning.
DeltaFile
+28-28llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+28-28llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+0-8llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+56-643 files

LLVM/project c909370llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.max.ll

Refactor Code:
Logical error in the code, was using the wrong register
to calculate some values.
DeltaFile
+34-34llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+114-1145 files not shown
+181-17111 files

LLVM/project 70933d1llvm/lib/Target/AMDGPU SIISelLowering.cpp

Add compiler warning
DeltaFile
+13-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+13-31 files

LLVM/project d063bd1llvm/lib/Target/AMDGPU SIISelLowering.cpp

Review comments and code cleanup.
DeltaFile
+18-27llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+18-271 files

LLVM/project 96b63c5llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

Overload `getVALUOp` to accept Opcodes as well.
DeltaFile
+26-26llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+26-26llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+2-26llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-8llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+67-865 files

LLVM/project bdd6039llvm/test/CodeGen/AMDGPU dynamic_stackalloc.ll llvm.amdgcn.reduce.sub.ll

[AMDGPU] DPP implementations for Wave Reduction

Adding DPP reduction support for i32 types.
Supported Ops: `umin`, `min`, `umax`, `max`,
`add`, `sub`, `and`, `or`, `xor`.
DeltaFile
+2,113-1,374llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+1,096-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,047-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+986-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+894-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+894-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+7,030-2,0108 files not shown
+11,269-2,82214 files

LLVM/project 5f6cd9bllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis strong-siv-overflow.ll strong-siv-large-btc.ll

[DA] Fix overflow in symbolic RDIV test (#185805)

The symbolic RDIV test relies on computing the extremes of affine
expressions (e.g., `A1*N1` and `A2*N2`) to disprove dependencies. These
calculations were previously done using `SE->getMulExpr` and
`SE->getMinusSCEV` without guarding against signed integer overflow. If
large coefficients or loop bounds cause a wrap, `isKnownPredicate`
evaluates the wrapped values, potentially disproving a valid dependence
and leading to miscompilations.

This patch reimplements symbolicRDIVtest using `ConstantRange` to work
around overflows.

---------

Signed-off-by: Ruoyu Qiu <cabbaken at outlook.com>
Co-authored-by: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
DeltaFile
+11-102llvm/lib/Analysis/DependenceAnalysis.cpp
+10-18llvm/test/Analysis/DependenceAnalysis/strong-siv-overflow.ll
+10-17llvm/test/Analysis/DependenceAnalysis/strong-siv-large-btc.ll
+8-14llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-overflow.ll
+6-7llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
+3-6llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-addrec-wrap.ll
+48-1645 files not shown
+60-17911 files

LLVM/project 709ef15llvm/test/CodeGen/PowerPC bswap64.ll

[NFC][PowerPC] Pre-commit to optimize bswap64 builtin for power8 (#181776)

The current codegen (for power 8 targets specifically) does not make use
of the parallelism and does most of the operations sequentially.
This will be optimized in a future patch which will follow this NFC PR.
It will enhance the performance and also save us instructions.

---------

Co-authored-by: himadhith <himadhith.v at ibm.com>
DeltaFile
+41-0llvm/test/CodeGen/PowerPC/bswap64.ll
+41-01 files

LLVM/project 19c1eedmlir/include/mlir/Bindings/Python Globals.h, mlir/lib/Bindings/Python Globals.cpp

format
DeltaFile
+5-5mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
+1-2mlir/include/mlir/Bindings/Python/Globals.h
+2-1mlir/lib/Bindings/Python/Globals.cpp
+1-2mlir/python/mlir/ir.py
+0-1mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
+9-115 files

LLVM/project 3a75683clang/bindings/python/clang cindex.py, clang/docs ReleaseNotes.rst

[libclang/python] Add type annotations to the TranslationUnit class (#180876)

This adds type annotations to the `TranslationUnit` class, enough to
pass a strict typecheck. This resolves 19 strict typing errors as the
next step towards https://github.com/llvm/llvm-project/issues/76664
DeltaFile
+67-31clang/bindings/python/clang/cindex.py
+2-0clang/docs/ReleaseNotes.rst
+69-312 files

LLVM/project 0f74f10mlir/include/mlir/Bindings/Python Globals.h, mlir/lib/Bindings/Python Globals.cpp IRCore.cpp

[mlir-python] Fix duplicate EnumAttr builder registration across dialects.

When multiple dialects share .td includes (e.g. affine includes arith),
each dialect's _*_enum_gen.py file registered attribute builders under
the same keys, causing "already registered" errors on the second import.

Two-pronged fix:

1. Add `allow_existing=True` to `register_attribute_builder` (and the
   underlying C++ `registerAttributeBuilder`). When set, silently skips
   registration if the key already exists (first-wins semantics). This
   handles EnumInfo-based builders (e.g. `AtomicRMWKindAttr`,
   `Arith_CmpFPredicateAttr`) that are emitted by every dialect whose
   .td file includes the defining file.

2. Filter EnumAttr-loop builders by `-bind-dialect` in
   `EnumPythonBindingGen.cpp` and register them under dialect-qualified
   keys (`"dialect.AttrName"`). Update `OpPythonBindingGen.cpp` to look
   up the same qualified keys for EnumAttr-typed op attributes (detected

    [5 lines not shown]
DeltaFile
+23-6mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
+18-2mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
+10-6mlir/lib/Bindings/Python/Globals.cpp
+5-5mlir/test/mlir-tblgen/enums-python-bindings.td
+6-2mlir/include/mlir/Bindings/Python/Globals.h
+4-2mlir/lib/Bindings/Python/IRCore.cpp
+66-234 files not shown
+74-2910 files

LLVM/project 70665c6clang/test/CXX/drs cwg2947.cpp, clang/www cxx_dr_status.html

[clang] Update C++ DR status page
DeltaFile
+74-18clang/www/cxx_dr_status.html
+1-1clang/test/CXX/drs/cwg2947.cpp
+75-192 files

LLVM/project 8187875clang/lib/Driver/ToolChains Darwin.cpp, clang/test/Driver xcselect.c darwin-ld-platform-version-macos-nosdk.c

[clang][Driver][Darwin] Use `xcselect` for `*-apple-darwin*` targets too (#186683)

This is a follow-up to #119670. There, we introduced a CMake option
`CLANG_USE_XCSELECT`, which, when enabled, uses `libxcselect` to find
the right SDK to inject as an `-isysroot` flag when targeting
`*-apple-macos*`.

We intentionally left out `*-apple-darwin*` targets because it broke
many tests. This is unfortunate because `*-apple-darwin*` is the default
triple when building LLVM on macOS, so one isn't able to take advantage
of `xcselect` without an explicit `-target` flag or a change to the
toolchain's default target.

We fix this in two ways.

First, we move the injection of the `-isysroot` flag using `xcselect`
later, until after we are sure that we are targeting macOS. This avoids
confusing the earlier deployment target detection code when we inject
the macOS SDK but actually intended to target non-macOS.

    [3 lines not shown]
DeltaFile
+21-12clang/lib/Driver/ToolChains/Darwin.cpp
+30-3clang/test/Driver/xcselect.c
+0-17clang/test/Driver/darwin-ld-platform-version-macos-nosdk.c
+13-0clang/test/Driver/darwin-ld-platform-version-macos.c
+2-1clang/test/Driver/fsanitize-ignorelist.c
+2-1clang/test/Driver/darwin-builtin-modules.c
+68-341 files not shown
+70-347 files

LLVM/project a21c414clang/test/OpenMP target_teams_distribute_parallel_for_simd_schedule_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp, libc/AOR_v20.02/math/test/traces sincosf.txt exp.txt

Merge branch 'main' into users/kasuga-fj/da-rewrite-weak-zero-siv-formula
DeltaFile
+0-31,999libc/AOR_v20.02/math/test/traces/sincosf.txt
+0-16,000libc/AOR_v20.02/math/test/traces/exp.txt
+5,294-4,814clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+5,238-4,758clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+4,350-4,098clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+4,004-3,524clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
+18,886-65,1934,105 files not shown
+247,605-244,4514,111 files