LLVM/project 8915dd8llvm/include/llvm/CodeGen TargetPassConfig.h, llvm/lib/CodeGen TargetPassConfig.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+2-3llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
+0-4llvm/lib/CodeGen/TargetPassConfig.cpp
+0-4llvm/include/llvm/CodeGen/TargetPassConfig.h
+1-1llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+3-124 files

LLVM/project 8584442llvm/include/llvm/CodeGen TargetPassConfig.h, llvm/include/llvm/CodeGen/GlobalISel IRTranslator.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+265-207llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+46-13llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+2-3llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
+0-4llvm/lib/CodeGen/TargetPassConfig.cpp
+0-4llvm/include/llvm/CodeGen/TargetPassConfig.h
+3-0llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
+316-23115 files not shown
+331-24521 files

LLVM/project 4b1a5d5llvm/include/llvm/CodeGen TargetPassConfig.h, llvm/lib/CodeGen TargetPassConfig.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+2-3llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
+0-4llvm/lib/CodeGen/TargetPassConfig.cpp
+0-4llvm/include/llvm/CodeGen/TargetPassConfig.h
+1-1llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+3-124 files

LLVM/project f3bc580clang/lib/AST/ByteCode Pointer.h InterpBuiltin.cpp

[clang][bytecode] Add `Pointer::getRootExpr()` (#216706)

Similarly to `getRootVarDecl()`, returns the expression of the base of
the pointer, if there is such an expression.
DeltaFile
+5-7clang/lib/AST/ByteCode/Interp.h
+4-4clang/lib/AST/ByteCode/Interp.cpp
+6-0clang/lib/AST/ByteCode/Pointer.cpp
+2-2clang/lib/AST/ByteCode/InterpBuiltin.cpp
+1-0clang/lib/AST/ByteCode/Pointer.h
+18-135 files

LLVM/project 5eeda72llvm/lib/Target/RISCV RISCVInstrInfoXCV.td RISCVInstrInfoXAndes.td

[RISCV] Use PatLeaf to simplify XAndes and XCV select patterns. NFC (#216839)
DeltaFile
+14-15llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+6-5llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+20-202 files

LLVM/project fcce921clang/lib/AST/ByteCode Pointer.cpp, clang/test/AST/ByteCode cxx23.cpp

[clang][bytecode] Check for invalid RecordDecls in Pointer::toAPValue() (#216537)

We can't pass forward declarations to ASTContext::getRecordLayout().
DeltaFile
+21-8clang/lib/AST/ByteCode/Pointer.cpp
+22-0clang/test/AST/ByteCode/cxx23.cpp
+43-82 files

LLVM/project 8488a83llvm/docs LFI.md, llvm/lib/MC MCELFStreamer.cpp MCLFI.cpp

[LFI][X86] Enable bundling for the LFI target (#214111)

This enables 32-byte bundling for the LFI x86-64 target, and uses bundle
grouping for existing rewrites where appropriate.
DeltaFile
+24-0llvm/docs/LFI.md
+10-0llvm/lib/MC/MCLFI.cpp
+7-0llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+5-0llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
+3-1llvm/test/MC/X86/LFI/syscall.s
+2-0llvm/lib/MC/MCELFStreamer.cpp
+51-11 files not shown
+53-17 files

LLVM/project b1550b1llvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp-samesign-canonicalize.ll icmp-samesign-known-bits.ll

[InstCombine] Use samesign constraints in unsigned known-bits folds (#209675)

Extracted from #209097 during review.

For a non-poison unsigned `icmp samesign`, both operands have the same
sign bit. Propagate a known sign bit between the temporary `KnownBits`
values in `foldICmpUsingKnownBits()` so the existing range folds can use
this constraint.

This enables endpoint folds in both signed halves of the integer range,
for example:

```
icmp samesign ugt i8 %x, 126 -> icmp eq i8 %x, 127
icmp samesign ult i8 %x, 127 -> icmp ne i8 %x, 127
icmp samesign ugt i8 %x, -2  -> icmp eq i8 %x, -1
```

-------------------------------

    [34 lines not shown]
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+51-0llvm/test/Transforms/InstCombine/icmp-samesign-known-bits.ll
+16-0llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+3-5llvm/test/Transforms/InstCombine/icmp-samesign-canonicalize.ll
+70-53 files

LLVM/project d7d525eclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c

[CIR][AArch64] Lower NEON Saturating substract intrinsics (#207189)

### Summary

part of : https://github.com/llvm/llvm-project/issues/185382

Lower intrinsics with out SISD in :
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#saturating-subtract

- Vector forms (vqsub{q}_{s,u}{8,16,32,64} - 16): added vqsub_v/vqsubq_v
to the existing vshl_v intrinsic-call block in
emitCommonNeonBuiltinExpr; signedness picks sqsub/uqsub via the
UnsignedAlts alternates.

Assisted by : Claude Opus4.8
DeltaFile
+0-234clang/test/CodeGen/AArch64/neon-intrinsics.c
+181-2clang/test/CodeGen/AArch64/neon/subtraction.c
+2-0clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+183-2363 files

LLVM/project fe17ff6llvm/lib/Target/NVPTX CMakeLists.txt, llvm/utils/gn/secondary/llvm/lib/Target/NVPTX BUILD.gn

[NVPTX] Fix link error when building LLVM with dylib (#216898)
DeltaFile
+2-0llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
+2-0llvm/lib/Target/NVPTX/CMakeLists.txt
+4-02 files

LLVM/project da9c024llvm/lib/Support FoldingSet.cpp

[Support] Remove duplicate comments in FoldingSet.cpp (NFC) (#216833)

This patch removes duplicate comments in FoldingSet.cpp.
Corresponding declarations are already documented in FoldingSet.h.

Note that LLVM Coding Standards state:

  Don't duplicate the documentation comment in the header file and in
  the implementation file. Put the documentation comments for public
  APIs into the header file.
DeltaFile
+0-27llvm/lib/Support/FoldingSet.cpp
+0-271 files

LLVM/project 703f0aellvm/include/llvm/ADT FoldingSet.h

[ADT] Remove CRTP from FoldingSet and ContextualFoldingSet (NFC) (#216830)

This patch simplifies FoldingSet by removing CRTP from FoldingSet and
ContextualFoldingSet.

Without this patch, FoldingSetImpl uses CRTP to get FoldingSetInfo, a
custom "vtable", from FoldingSet and ContextualFoldingSet.

With this patch, we put ContextStorage as the base class of
FoldingSetImpl.  FoldingSetImpl directly takes FoldingSetTrait as a
template parameter.  This allows us to:

- populate FoldingSetInfo for both FoldingSet and
  ContextualFoldingSet as a static constexpr variable.

- rely on the empty base optimization (EBO) on ContextStorage so that
  FoldingSet incurs no memory overhead.

- turn FoldingSet and ContextualFoldingSet into simple type aliases of

    [2 lines not shown]
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+59-104llvm/include/llvm/ADT/FoldingSet.h
+59-1041 files

LLVM/project 7299aafclang/docs UsersManual.md

Fix text color in dark mode
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+1-1clang/docs/UsersManual.md
+1-11 files

LLVM/project 2aa7480clang/docs conf.py, clang/docs/_static custom.css

[docs] Restore project-specific Furo CSS
DeltaFile
+0-140utils/docs/llvm_sphinx/_static/furo-common.css
+71-0llvm/docs/_static/custom.css
+60-0clang/docs/_static/custom.css
+8-0utils/docs/llvm_sphinx/__init__.py
+2-1llvm/docs/conf.py
+3-0clang/docs/conf.py
+144-1414 files not shown
+147-14210 files

LLVM/project 9089be3flang/include/flang/Optimizer/CodeGen CodeGen.h CGPasses.td, flang/lib/Optimizer/CodeGen CodeGen.cpp

[flang][cuda] Add support for custom descriptor allocator in codegen (#216881)

Simlar to https://github.com/llvm/llvm-project/pull/216841 but for
CodeGen pass usage.
DeltaFile
+49-29flang/lib/Optimizer/CodeGen/CodeGen.cpp
+6-1flang/include/flang/Optimizer/CodeGen/CGPasses.td
+6-0flang/include/flang/Optimizer/CodeGen/CodeGen.h
+5-0flang/test/Fir/CUDA/cuda-code-gen.mlir
+66-304 files

LLVM/project b84b33dflang/include/flang/Optimizer/Transforms Passes.td, flang/include/flang/Optimizer/Transforms/CUDA CUFAllocationConversion.h

[flang][cuda] Add option to emit different function name for alloc/free of descriptors (#216841)

This allow to call specialized functions instead of the upstream ones.
DeltaFile
+52-10flang/lib/Optimizer/Transforms/CUDA/CUFAllocationConversion.cpp
+12-0flang/include/flang/Optimizer/Transforms/Passes.td
+7-1flang/include/flang/Optimizer/Transforms/CUDA/CUFAllocationConversion.h
+7-0flang/test/Fir/CUDA/cuda-allocate.fir
+78-114 files

LLVM/project 7a12952llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h, llvm/lib/Analysis BlockFrequencyInfoImpl.cpp

[BFI] Solve irreducible SCCs instead of splitting their headers (#215170)

c5a3139ebd0d (2014) approximates irreducible control flow by modelling
an SCC as a loop with multiple headers, and
http://reviews.llvm.org/D10348 re-distributes the loop mass across those
headers in proportion to the backedge mass each one received -- one step
of a power iteration, from an assumed split.

Package the SCC with a single representative and solve it instead.
`solveIrreducibleMass` iterates the SCC's internal chain towards its
dominant eigenvector and reads the member masses, the exits and the
circulating mass off that, so the entries' relative frequencies come out
of the solve.  Power iteration rather than a relaxation of `f = e +
f*P`: the mass `e` entering the SCC is unknown here, so there is no
fixed point to relax towards, only a direction.  NumHeaders, the
per-header BackedgeMass, getHeaderIndex, the isHeader binary search and
adjustLoopHeaderMass go away with the split.

Relative error against an exact rational solve has improved.

    [29 lines not shown]
DeltaFile
+148-164llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+25-89llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
+19-19llvm/test/CodeGen/AArch64/late-taildup-computed-goto.ll
+22-14llvm/test/CodeGen/X86/pr38795.ll
+26-1llvm/test/Analysis/BlockFrequencyInfo/irreducible_pgo.ll
+13-13llvm/test/Analysis/BlockFrequencyInfo/irreducible.ll
+253-3005 files not shown
+275-32011 files

LLVM/project 763aec0lldb/source/Host/common NativeProcessProtocol.cpp, lldb/source/Plugins/Process/elf-core ProcessElfCore.cpp

[lldb] Adopt ProcessAddress in the read memory APIs (NFC) (#214088)

Relevant RFC:
https://discourse.llvm.org/t/rfc-address-spaces-support-in-lldb/91222/

Previous PR  #206370  adding the AddressSpace definitions. 


- switches the read memory virtuals from lldb::addr_t to const
ProcessAddress & and updates every override. No behavior change
expected.
 

**Test Plan**
- Depending on the buildbots for all other platforms.
DeltaFile
+10-7lldb/unittests/Target/MemoryTest.cpp
+6-4lldb/source/Target/ProcessTrace.cpp
+6-4lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
+6-4lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
+6-4lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
+6-4lldb/source/Host/common/NativeProcessProtocol.cpp
+40-2742 files not shown
+143-10748 files

LLVM/project 23b24afllvm/lib/Target/WebAssembly WebAssemblyInstrSIMD.td, llvm/test/CodeGen/WebAssembly f16-intrinsics.ll

[WebAssembly] Add v8f16 select instruction patterns (#213280)

I see the following 

```
 anutosh491 at Anutoshs-MacBook-Air llvm-project % cat /private/tmp/wasm-f16-select.ll
define <8 x half> @select_v8f16(i1 %cond, <8 x half> %a, <8 x half> %b) {
  %result = select i1 %cond, <8 x half> %a, <8 x half> %b
  ret <8 x half> %result
}
```
```

 anutosh491 at Anutoshs-MacBook-Air llvm-project % build-assert/bin/llc \             
  -mtriple=wasm32-unknown-unknown \
  -mattr=+simd128,+fp16 \
  -o /dev/null \
  /private/tmp/wasm-f16-select.ll
LLVM ERROR: Cannot select: t8: v8f16 = select t12, t4, t6

    [33 lines not shown]
DeltaFile
+33-0llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+2-2llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+35-22 files

LLVM/project 0207706orc-rt/include/orc-rt NativeDylibManager.h

[orc-rt] Add missing `#include <optional>` (#216894)
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+2-0orc-rt/include/orc-rt/NativeDylibManager.h
+2-01 files

LLVM/project 93030c3llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 abdu.ll

[SDAG] Fix invalid sign bit condition for abs(sub) -> abdu fold (#215548)

The fold here for (abs (sub x y)) -> (abdu x y) was proven in Alive,
assuming that both operands had a sign bit of zero. However, the code
was checking if x had a sign bit of zero and y had a sign bit of 1

Fixes https://github.com/llvm/llvm-project/issues/214942

Original Alive proof from
https://github.com/llvm/llvm-project/pull/186659 :
https://alive2.llvm.org/ce/z/HfPF5q
A variant that's explicitly (abs (sub x y)):
https://alive2.llvm.org/ce/z/QEgDaa
And changing the range to 32770 or higher there will break the
transformation
DeltaFile
+30-0llvm/test/CodeGen/X86/abdu.ll
+2-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+32-22 files

LLVM/project 7b2a985lldb/source/Expression DWARFExpression.cpp, lldb/unittests/Expression DWARFExpressionTest.cpp

[lldb] Keep DW_OP_fbreg results address-sized (#216641)

DW_OP_fbreg adds its signed displacement as an int64_t, which can widen
a 32-bit frame-base Scalar to 64 bits. Canonicalize the pushed result
using the evaluator's existing generic conversion so subsequent
arithmetic uses the target address width.

Add an i386 regression test that checks 32-bit wrapping and the
resulting APSInt width.

Fixes #211007
DeltaFile
+36-0lldb/unittests/Expression/DWARFExpressionTest.cpp
+2-0lldb/source/Expression/DWARFExpression.cpp
+38-02 files

LLVM/project fc04134llvm/lib/Target/NVPTX CMakeLists.txt, llvm/utils/gn/secondary/llvm/lib/Target/NVPTX BUILD.gn

[NVPTX] Fix link error when building LLVM with dylib
DeltaFile
+2-0llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
+2-0llvm/lib/Target/NVPTX/CMakeLists.txt
+4-02 files

LLVM/project 2e5c3f6llvm/test/Transforms/PGOProfile memprof.ll

don't test on windows
DeltaFile
+2-0llvm/test/Transforms/PGOProfile/memprof.ll
+2-01 files

LLVM/project ccef5b7llvm/test/CodeGen/AMDGPU flat-saddr-atomics.ll llvm.amdgcn.wmma.imm.gfx1250.w32.ll

[AMDGPU] Improve the sequence for initial unclaused VMEM

Fixes LCOMPILER-2619.
DeltaFile
+250-250llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+232-232llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+196-196llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+183-183llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+174-174llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+166-166llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+1,201-1,201204 files not shown
+6,524-6,326210 files

LLVM/project 9b2118cbolt/include/bolt/Core BinaryContext.h, bolt/include/bolt/Passes LongJmp.h

[BOLT][AArch64] Add call relaxation pass (#173952)

Add a function call relaxation pass that groups functions into clusters,
each with a maximum size of 128MB. This pass is enabled using the
`--relax-exp` option.

* Within each cluster: function calls do not require relaxation.

* Between clusters: thunks are created at the cluster boundaries to
handle inter-cluster calls. These thunks can be either short or long,
depending on the proximity of the thunk destination. When possible, a
long thunk may be shared by both adjacent clusters.

* Hot functions: if all hot functions (after reordering) fit within a
single cluster (under 128MB), no thunks are needed on the hot path, as
determined by the profile.

* PLT behavior: for the Procedure Linkage Table (PLT), it is currently
assumed that the hottest cluster will be placed adjacent to the PLT, so

    [8 lines not shown]
DeltaFile
+316-2bolt/lib/Passes/LongJmp.cpp
+78-0bolt/test/AArch64/relax-exp.s
+41-0bolt/include/bolt/Passes/LongJmp.h
+11-1bolt/include/bolt/Core/BinaryContext.h
+8-2bolt/lib/Core/BinaryContext.cpp
+5-3bolt/lib/Passes/BinaryPasses.cpp
+459-81 files not shown
+462-87 files

LLVM/project 9f05d1fllvm/test/Transforms/PGOProfile memprof-inline-call-stacks.ll

Remove unneeded lines
DeltaFile
+0-94llvm/test/Transforms/PGOProfile/memprof-inline-call-stacks.ll
+0-941 files

LLVM/project ecdcdf0llvm/test/CodeGen/AMDGPU rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir

[AMDGPU] Fix MIR test by adding stackPtrOffsetReg (#216866)

Otherwise, the test fails with expensive_checks.
DeltaFile
+2-0llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir
+2-01 files

LLVM/project 85e76ecclang/lib/Frontend CompilerInvocation.cpp, clang/test/Driver lto.c

[Driver] Treat -O4 as -O3 in clang::getOptimizationLevel, which is called when building LTO link command (#216450)

#169762 (commit e60a69ab8a9e7) replaced the -O option handling in
`tools::addLTOOptions` with `getOptimizationLevel()`, but
`getOptimizationLevel` doesn't expect -O4, while `addLTOOptions` used to
accept and without diagnostics. Teach `getOptimizationLevel` about -O4
and don't diagnose to revert to the old behavior.

---------

Co-authored-by: Wael Yehia <wyehia at ca.ibm.com>
DeltaFile
+2-1clang/lib/Frontend/CompilerInvocation.cpp
+2-0clang/test/Driver/lto.c
+4-12 files

LLVM/project dbf0a16llvm/test/Transforms/PGOProfile memprof.ll, llvm/test/Transforms/PGOProfile/Inputs memprof.nocolinfo.memprofraw memprof.nocolinfo.exe

[NFC][MemProf] Replace memprofraw with YAML in memprof.ll test
DeltaFile
+205-49llvm/test/Transforms/PGOProfile/memprof.ll
+0-96llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
+0-60llvm/test/Transforms/PGOProfile/Inputs/memprof_pgo.proftext
+0-0llvm/test/Transforms/PGOProfile/Inputs/memprof.nocolinfo.memprofraw
+0-0llvm/test/Transforms/PGOProfile/Inputs/memprof.nocolinfo.exe
+0-0llvm/test/Transforms/PGOProfile/Inputs/memprof.memprofraw
+205-2056 files