LLVM/project c0a8d9fclang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaExprCXX.cpp SemaDeclCXX.cpp

[clang][P2719] Relax requirements for matching operator new and delete

The most recent revision of P2719 introduced very strict rules about
matching parameter sets between type aware operators new and delete.

The intention was to resolve the classic "no matching operator delete
has been found so the object will silently leak" problem. The strict
rules however made deleting objects that had a placement new
"impossible".

I missed this however as all of our large scale tests involved
projects that were already using manually implemented allocators
(often trying to support type isolation). The problem with this from
a validation point of view is simple: all of these projects had
existing class scoped operators, and the untyped delete was silently
selected, avoiding the need for a non-placement type-aware delete
that would conflict with the placement cleanup delete.

The next revision of P2719 resolves this by removing the exact type

    [6 lines not shown]
DeltaFile
+60-42clang/lib/Sema/SemaExprCXX.cpp
+52-33clang/test/SemaCXX/type-aware-class-scoped-mismatched-constraints.cpp
+59-17clang/test/SemaCXX/type-aware-new-delete-basic-resolution.cpp
+38-27clang/lib/Sema/SemaDeclCXX.cpp
+7-4clang/include/clang/Basic/DiagnosticSemaKinds.td
+0-6clang/test/SemaCXX/type-aware-coroutines.cpp
+216-1292 files not shown
+218-1318 files

LLVM/project c9d713allvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[GlobalISel] Fast-path single reg loads and stores in IRTranslator (#195245)

IRTranslator::translateLoad is hot in compile-time profiles of sqlite on
aarch64-O0-g. Aggregates are flattened into multiple vregs with offsets.
Most loads and stores lower to a single register so this offset
materialization can be avoided.

Small -0.07% geomean improvement on aarch64-O0-g with -0.24% for sqlite.

https://llvm-compile-time-tracker.com/compare.php?from=a7a2dc59616a8cb1198d933bcdf55ebdbd78894c&to=e535e96fd0952cfa646d48ef84cf5948c0a8a2ab&stat=instructions%3Au
DeltaFile
+34-17llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+34-171 files

LLVM/project d30d5fellvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[GlobalISel] Fast-path single vreg values in getOrCreateVRegs (#195244)

IRTranslator::translateLoad is hot in compile-time profiles of sqlite on
aarch64-O0-g. Aggregates are flattened into multiple vregs with offsets.
Avoiding this path for single vregs is a small -0.11% compile-time win.

https://llvm-compile-time-tracker.com/compare.php?from=a7a2dc59616a8cb1198d933bcdf55ebdbd78894c&to=96fcfe733947db64effd5e1d1413697981cbe357&stat=instructions%3Au
DeltaFile
+25-20llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+25-201 files

LLVM/project 36b95famlir/include/mlir/Dialect/SPIRV/IR SPIRVBase.td, mlir/lib/Dialect/SPIRV/Transforms UpdateVCEPass.cpp

[mlir][SPIR-V] Add Weak linkage type and SPV_AMD_weak_linkage extension (#195660)

- add 'Weak' linkage type (SPV_AMD_weak_linkage)
- deduce the Linkage capability and linkage-type extension from
linkage_attributes in UpdateVCE pass

---------

Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
DeltaFile
+45-0mlir/test/Target/SPIRV/linkage-types.mlir
+28-0mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
+28-0mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
+9-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+110-24 files

LLVM/project edb9645flang/include/flang/Lower OpenMP.h AbstractConverter.h, flang/lib/Lower Bridge.cpp

support device_type groupprivate lowering
DeltaFile
+22-3flang/lib/Lower/OpenMP/OpenMP.cpp
+22-0flang/test/Lower/OpenMP/groupprivate.f90
+11-0flang/lib/Lower/Bridge.cpp
+11-0flang/include/flang/Lower/OpenMP.h
+11-0flang/include/flang/Lower/AbstractConverter.h
+77-35 files

LLVM/project 58d9781llvm/lib/Transforms/Utils CallPromotionUtils.cpp, llvm/test/Transforms/SampleProfile icp_target_feature.ll

[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features (#192142)

Profile-driven indirect call promotion was promoting indirect calls to
functions requiring advanced CPU features (e.g., AVX512) even when the
caller function did not support those features. When these promoted
calls were subsequently inlined, it could lead to invalid IR and
backend crashes during instruction selection because the target CPU
could not handle the advanced instructions.

This patch addresses the issue by adding a target feature
compatibility check to `llvm::isLegalToPromote` in
`CallPromotionUtils.cpp`. If the callee requires target features
(prefixed with `+`) that are not present in the caller's target
features, the promotion is skipped.  By centralizing this check in
`isLegalToPromote`, we protect all passes relying on this utility
(such as `SampleProfileLoader` and `IndirectCallPromotion`) from
promoting to incompatible targets. This also prevents incorrect
inlining of `always_inline` functions that would otherwise be promoted
via indirect calls and then inlined.

    [3 lines not shown]
DeltaFile
+61-0llvm/test/Transforms/SampleProfile/icp_target_feature.ll
+21-0llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
+82-02 files

LLVM/project b907c14clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][NFC] Rename SignBitOp to CIR_SignBitOp (#195477)

Align with the CIR_ prefix naming convention used by other op
definitions in CIROps.td.
DeltaFile
+1-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-11 files

LLVM/project 81bdba1mlir/docs/Traits _index.md, mlir/include/mlir/IR OpDefinition.h OpBase.td

[MLIR] Add HasAncestor op trait (#195447)

Add HasAncestor/AncestorOneOf traits that verify an operation has a
specific ancestor anywhere in the parent chain, unlike HasParent which
only checks the immediate parent.
DeltaFile
+79-0mlir/test/IR/traits.mlir
+26-0mlir/include/mlir/IR/OpDefinition.h
+10-0mlir/docs/Traits/_index.md
+9-0mlir/test/lib/Dialect/Test/TestOps.td
+8-0mlir/include/mlir/IR/OpBase.td
+132-05 files

LLVM/project 00562c5mlir/lib/CAPI/Interfaces CMakeLists.txt

fix libMLIRCAPIInterfaces after #195505 (#195789)

https://github.com/llvm/llvm-project/pull/195505 missed
`MLIRSideEffectInterfaces` in the CMakeLists.txt.
DeltaFile
+2-1mlir/lib/CAPI/Interfaces/CMakeLists.txt
+2-11 files

LLVM/project 2d5abf3orc-rt/lib/executor/sps-ci MemoryAccessSPSCI.cpp SimpleNativeMemoryMapSPSCI.cpp, orc-rt/unittests MemoryAccessSPSCITest.cpp SimpleNativeMemoryMapSPSCITest.cpp

[orc-rt] Change SPS controller-interface naming conventions. (#195614)

This commit makes two changes to the naming conventions for SPS CI
symbols:

1. The orc_rt_sps_ci_ prefix is replaced with orc_rt_ci_sps_ (for SPS
wrapper functions) and orc_rt_ci_ (without the "sps_" suffix) for data
symbols.

2. The _sps_wrapper suffix is dropped from wrapper functions, since the
prefix now distinguishes between SPS-wrappers and data symbols.
DeltaFile
+28-28orc-rt/lib/executor/sps-ci/MemoryAccessSPSCI.cpp
+26-26orc-rt/unittests/MemoryAccessSPSCITest.cpp
+16-21orc-rt/lib/executor/sps-ci/SimpleNativeMemoryMapSPSCI.cpp
+8-13orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
+8-9orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
+6-6orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
+92-1033 files not shown
+102-1139 files

LLVM/project 23b330dclang/include/clang/Options Options.td, flang/test/Driver print-file-name.f90

Enable -print-file-name for flang
DeltaFile
+13-0flang/test/Driver/print-file-name.f90
+1-1clang/include/clang/Options/Options.td
+0-0flang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-unknown-linux-gnu/libflang_rt.runtime.a
+0-0flang/test/Driver/Inputs/resource_dir/share/asan_ignorelist.txt
+14-14 files

LLVM/project 227c3e4libcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,931 files not shown
+72,117-31,8281,937 files

LLVM/project 808b2dblibcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,932 files not shown
+72,119-31,8301,938 files

LLVM/project 3975cdblibcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,932 files not shown
+72,119-31,8301,938 files

LLVM/project 85c92d4libcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,925 files not shown
+72,039-31,8241,931 files

LLVM/project 4059891lld/ELF/Arch TargetImpl.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+1-1lld/ELF/Arch/TargetImpl.h
+1-11 files

LLVM/project 4448636llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer BUILD.gn

[gn build] Port cb2a64e7e5af



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/195783
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn
+2-02 files

LLVM/project 8c8e053llvm/lib/CodeGen TargetInstrInfo.cpp, llvm/lib/Target/RISCV RISCVInstrInfo.h

[X86][APX] Add VirtRegMap to non stack foldMemoryOperand too (#193423)

We need to query mapped physical register through VirtRegMap.

Fixes: https://godbolt.org/z/1KGj3aYeP
DeltaFile
+270-0llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll
+6-5llvm/lib/Target/X86/X86InstrInfo.h
+6-5llvm/lib/Target/RISCV/RISCVInstrInfo.h
+5-6llvm/lib/CodeGen/TargetInstrInfo.cpp
+6-5llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+6-4llvm/lib/Target/X86/X86InstrInfo.cpp
+299-256 files not shown
+311-3412 files

LLVM/project 7c2c06cmlir/include/mlir-c Interfaces.h, mlir/lib/Bindings/Python IRInterfaces.cpp

[MLIR][Python] Add `ConditionallySpeculatable` interface and `Pure` specifier (#195505)

This PR brings two features: the `ConditionallySpeculatable` op
interface and the `Pure` specifier for Python-defined ops.

The result is that you can mark an op as pure like:
```python
class PureOp(
    TestPure.Operation,
    name="pure",
    traits=[Pure]  # just like in the ODS!
):
    a: Operand[IntegerType[32]]
    b: Operand[IntegerType[32]]
    res: Result[IntegerType[32]] = infer_result()
```

Then this op is both `NoMemoryEffect` and `AlwaysSpeculatable`.

Assisted-by: Copilot/GPT5.4
DeltaFile
+116-0mlir/test/python/dialects/ext.py
+99-0mlir/test/CAPI/ir.c
+97-0mlir/lib/CAPI/Interfaces/Interfaces.cpp
+77-1mlir/lib/Bindings/Python/IRInterfaces.cpp
+43-0mlir/include/mlir-c/Interfaces.h
+20-0mlir/python/mlir/dialects/ext.py
+452-11 files not shown
+453-17 files

LLVM/project 040c2b2llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port f7329e61ad4b



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/195782
DeltaFile
+0-1llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+0-11 files

LLVM/project 852dd0dllvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port be8e0842a103



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/195781
DeltaFile
+0-1llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+0-11 files

LLVM/project 239ca8dllvm/docs LangRef.rst, llvm/lib/AsmParser LLParser.cpp

[IR] Add elementwise modifier to atomicrmw (#189517)

This PR implements the IR side modifications of [[RFC] Add elementwise
modifier to atomicrmw](https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomicrmw/90134).

Design Decisions:

- In the IR, the current atomicrmw record layout looks like: [ptrty,
ptr, valty, val, operation, vol, ordering, syncscope, align]. To encode
elementwise, I decided to pack it into the operation field, which also
contains the math op (i.e. fadd, fmin, add etc...). I could have changed
the record structure, but that would be slightly more complicated.
- elementwise vector atomics can be vectors of integers because we can always scalarize legally
- elementwise vector atomics need to have power of 2 size. We can potentially remove this restriction later.

Assisted by AI.
DeltaFile
+101-1llvm/unittests/IR/VerifierTest.cpp
+69-27llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+31-18llvm/lib/AsmParser/LLParser.cpp
+33-0llvm/test/Assembler/invalid-atomicrmw-elementwise.ll
+11-9llvm/docs/LangRef.rst
+14-4llvm/lib/IR/Verifier.cpp
+259-5913 files not shown
+334-7619 files

LLVM/project a80d2a7llvm/lib/Passes PassBuilderPipelines.cpp, llvm/test/Other new-pm-defaults.ll new-pm-thinlto-postlink-pgo-defaults.ll

Reapply "[JTS][Passes] Enable JTS By Default" (#193409)" (#195776)

This reverts commit c74951c6c3074be23fd7b12843e1187ca98e98af.

The ASan issues on the buildbot should be fixed by
b5f4f16fd98cb57a13a96b7d7faa89326636c5bc.
DeltaFile
+1-5llvm/test/Other/new-pm-defaults.ll
+2-2llvm/lib/Passes/PassBuilderPipelines.cpp
+1-0llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
+7-72 files not shown
+9-78 files

LLVM/project e37ca02compiler-rt/test/asan/TestCases asan_and_llvm_coverage_test.cpp

[compiler-rt] Add MSVC CRT flags to ASan coverage test (#195719)

The ASan coverage test also links clang_rt.profile because it uses
-coverage. On Windows MSVC, this can fail if the test is linked with the
static CRT but clang_rt.profile was built with the dynamic CRT.

For example, a profile runtime that uses /MD may reference DLL CRT
symbols
such as __imp_* symbols. Add the same dynamic CRT flags directly to this
one test on Windows MSVC so it keeps linking when clang_rt.profile
changes.
DeltaFile
+5-1compiler-rt/test/asan/TestCases/asan_and_llvm_coverage_test.cpp
+5-11 files

LLVM/project f81445ellvm/lib/Analysis InlineOrder.cpp

[InlineOrder] Remove unused InlineHistoryMap (#195769)

This patch removes InlineHistoryMap, an unused variable.  The last
use was removed by:

  commit 3af427539bc6b85a9fe3334b9a0b43d347ea29ac
  Author: Arthur Eubanks <aeubanks at google.com>
  Date:   Wed Apr 8 09:34:52 2026 -0700
DeltaFile
+0-1llvm/lib/Analysis/InlineOrder.cpp
+0-11 files

LLVM/project 9701e73clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaDeclCXX.cpp SemaExprCXX.cpp

[clang][P2719] Relax requirements for matching operator new and delete

The most recent revision of P2719 introduced very strict rules about
matching parameter sets between type aware operators new and delete.

The intention was to resolve the classic "no matching operator delete
has been found so the object will silently leak" problem. The strict
rules however made deleting objects that had a placement new
"impossible".

I missed this however as all of our large scale tests involved
projects that were already using manually implemented allocators
(often trying to support type isolation). The problem with this from
a validation point of view is simple: all of these projects had
existing class scoped operators, and the untyped delete was silently
selected, avoiding the need for a non-placement type-aware delete
that would conflict with the placement cleanup delete.

The next revision of P2719 resolves this by removing the exact type

    [6 lines not shown]
DeltaFile
+57-21clang/test/SemaCXX/type-aware-new-delete-basic-resolution.cpp
+38-27clang/lib/Sema/SemaDeclCXX.cpp
+21-37clang/lib/Sema/SemaExprCXX.cpp
+33-9clang/test/SemaCXX/type-aware-class-scoped-mismatched-constraints.cpp
+4-4clang/include/clang/Basic/DiagnosticSemaKinds.td
+3-3clang/test/SemaCXX/type-aware-coroutines.cpp
+156-1011 files not shown
+157-1027 files

LLVM/project 94b475dlibunwind/src Registers.hpp, libunwind/test aarch64_za_unwind.pass.cpp

[libunwind] Add SME detection for Apple platforms (#193630)

Copy SME detection sysctl code from ZA test. Also fix a
logic issue in the original code while being reviewed.
DeltaFile
+12-1libunwind/src/Registers.hpp
+1-1libunwind/test/aarch64_za_unwind.pass.cpp
+13-22 files

LLVM/project b5f4f16libcxx/include string, libcxx/test/libcxx/strings/basic.string asan_vector_integration.pass.cpp asan_deque_integration.pass.cpp

[libcxx] Remove ASan container overflow checks for SSO strings (#194208)

Essentially a revert of #79536, although manual given how much the code
has changed.

Doing container overflow checks on SSO strings is fundamentally unsound
due to how they interact with compiler optimizations within LLVM, which
assume that the entire object is dereferencable when it is live. LLVM
can sometimes insert speculative loads that will create false positives
when they try and load a partially filled SSO buffer. This was
previously prevented using inline asm barriers within std::string
itself. However, this can also manifest in other ways, with the
motivating example for the revert being GlobalOpt inserting a
speculative load of a std::variant containing a SSO std::string, causing
an ASan failure.
DeltaFile
+0-182libcxx/test/libcxx/strings/basic.string/asan_vector_integration.pass.cpp
+0-182libcxx/test/libcxx/strings/basic.string/asan_deque_integration.pass.cpp
+0-56libcxx/test/libcxx/strings/basic.string/asan_short.pass.cpp
+2-33libcxx/include/string
+24-5libcxx/test/support/asan_testing.h
+26-4585 files

LLVM/project e7ea34eclang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll atomic-rmw.ll

rebase

Created using spr 1.3.7
DeltaFile
+652-9,343clang/test/AST/ast-dump-templates.cpp
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+4,652-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+2,420-2,120llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,940-1,458llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,936-1,457llvm/test/CodeGen/X86/vector-reduce-smax.ll
+18,661-18,5406,136 files not shown
+265,686-136,6696,142 files

LLVM/project 7c17a1dmlir/lib/Dialect/Transform/IR Utils.cpp

[MLIR][Transform] Don't error when a structurally inlinable call exists
DeltaFile
+30-2mlir/lib/Dialect/Transform/IR/Utils.cpp
+30-21 files