LLVM/project 4883f11mlir/lib/Dialect/Affine/IR AffineOps.cpp

[mlir][affine] Add early exit to getLowerBound/getUpperBound function (NFC) (#212047)

When an AffineExpr is an AffineConstantExpr, its bound can be directly
returned without computing the lower/upper bounds for all operand
values. This avoids redundant bound evaluations on operands and speeds
up static bound computation.
DeltaFile
+9-12mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+9-121 files

LLVM/project 3fac469llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.ubfe.ll

[AMDGPU] Fix BFE_U32 fold to check known zero bits instead of sign bits (#216310)
DeltaFile
+101-28llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
+7-6llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+108-342 files

LLVM/project 367b306llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination shl.ll uge.ll

[ConstraintElimination] Fix trivially true compares with no variables. (#216392)

getConstraintForSolving handles 'X uge 0' and '0 ule X' directly,
returning a constraint that is trivially true. The returned row was sized
Value2Index.size(), which is 0 if the unsigned system does not have any
variables yet, e.g. in a function without arguments. An empty row means
the condition could not be decomposed, so the fast path was discarded and
the compare not simplified.

Size the row to include the entry for the constant part, so it is never
empty.

PR: https://github.com/llvm/llvm-project/pull/216392
DeltaFile
+26-0llvm/test/Transforms/ConstraintElimination/uge.ll
+2-4llvm/test/Transforms/ConstraintElimination/shl.ll
+2-2llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+30-63 files

LLVM/project 3ee35aellvm/lib/Transforms/InstCombine InstCombineAddSub.cpp, llvm/test/Transforms/InstCombine add.ll

[InstCombine] support zext in ceiling division fold (#216470)

Proof https://alive2.llvm.org/ce/z/vxRGV7
DeltaFile
+44-0llvm/test/Transforms/InstCombine/add.ll
+14-8llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+58-82 files

LLVM/project e45f256clang/unittests/Analysis IntervalPartitionTest.cpp

IntervalPartitionTest.cpp: Suppress a warning. [-Wunused-template] (#215564)

I think it'd be fair just to suppress since this is just a test.
DeltaFile
+1-1clang/unittests/Analysis/IntervalPartitionTest.cpp
+1-11 files

LLVM/project 7afbf0fclang/unittests/Analysis/FlowSensitive SignAnalysisTest.cpp

SignAnalysisTest.cpp: Suppress a warning. [-Wunused-template] (#215563)
DeltaFile
+1-0clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp
+1-01 files

LLVM/project af15d15clang/lib/Format UnwrappedLineParser.cpp, clang/unittests/Format TokenAnnotatorTest.cpp

[clang-format] Harden star and amp annotation (#212856)

At this point we can't (or won't) decide wether this is a template
argument or just an expression, opt out of the specialized (and in the
test cases wrong) assignment.

Fixes #212622
DeltaFile
+18-3clang/lib/Format/UnwrappedLineParser.cpp
+12-0clang/unittests/Format/TokenAnnotatorTest.cpp
+30-32 files

LLVM/project 1ebbabeclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR][NFC] Remove unnecessary casts in LowerToLLVM (#216395)

Remove unnecessary casts for Op with TypeConstraints and known type for
operands in the LowerToLLVM
DeltaFile
+8-11clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+8-111 files

LLVM/project c15928ellvm/include/llvm/Target/GlobalISel Combine.td, llvm/test/CodeGen/AArch64 vec-combine-trunc-dup-ext.ll select_cc.ll

[GlobalISel] Add G_SEXT_INREG(G_ZEXT) -> G_SEXT combine. (#213606)

This converts a G_ZEXT or G_ANYEXT to a G_SEXT if we will G_SEXT_INREG
the bits away.
DeltaFile
+139-0llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-inreg.mir
+12-28llvm/test/CodeGen/AArch64/fcmp.ll
+16-2llvm/include/llvm/Target/GlobalISel/Combine.td
+4-6llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
+1-3llvm/test/CodeGen/AArch64/vec-combine-trunc-dup-ext.ll
+1-3llvm/test/CodeGen/AArch64/select_cc.ll
+173-422 files not shown
+175-458 files

LLVM/project 4c6ec79mlir/include/mlir/Dialect/LLVMIR LLVMOps.td, mlir/include/mlir/Interfaces ControlFlowInterfaces.td

[mlir][Interfaces] Use `areTypesCompatible` instead of `mayForwardTypeToSuccessor`
DeltaFile
+10-10mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+3-16mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+2-3mlir/lib/Transforms/Utils/RegionUtils.cpp
+15-293 files

LLVM/project 500afbdllvm/include/llvm/ExecutionEngine/JITLink ppc64.h, llvm/lib/ExecutionEngine/JITLink JITLink.cpp

[JITLink][ORC] Add ppc64 to generic stub API; use it in DLLImportDefinitionGenerator (#207968)

`getAnonymousPointerCreator` and `getPointerJumpStubCreator` provide
arch-neutral factory functions for pointer slots and PLT jump stubs, but
ppc64/ppc64le were missing from both switch tables.

Add ppc64 support: `createAnonymousPointer` maps directly, while
`createAnonymousPointerJumpStub` requires a lambda wrapper to fix the
endianness template parameter and supply _LongBranchSaveR2_ as the stub
kind (the correct default for external calls that must preserve the TOC
pointer). Callers needing a different stub kind can construct a
`PointerJumpStubCreator` lambda directly. Update
`DLLImportDefinitionGenerator::createStubsGraph` to use these
arch-neutral factories instead of calling jitlink::x86_64:: directly,
completing part of the work tracked in issue
https://github.com/llvm/llvm-project/issues/57162
DeltaFile
+21-9llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
+13-0llvm/include/llvm/ExecutionEngine/JITLink/ppc64.h
+9-0llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
+43-93 files

LLVM/project 3eeed35llvm/include/llvm/ADT APInt.h, llvm/lib/Support APInt.cpp

[ADT] Mark deprecated APInt constructor deleted (#216371)

Mark deprecated APInt constructor, taking uint64_t[] deleted instead of
removing it as the comment suggests.
DeltaFile
+5-9llvm/include/llvm/ADT/APInt.h
+0-5llvm/lib/Support/APInt.cpp
+5-142 files

LLVM/project bbff70cllvm/test/CodeGen/NVPTX tcgen05-mma-collector-b.ll tcgen05-mma-sp-disable-output-lane-collector-b.ll

[NVPTX] Add tcgen05.mma kind::ti16 for sm_107f + mxf4{nvf4} for sm_107a (#215624)

Extend NVPTX `tcgen05.mma*` with `kind::ti16` for `sm_107f`.
DeltaFile
+692-0llvm/test/CodeGen/NVPTX/tcgen05-mma-ti16-kind.ll
+572-0llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-mxf4-mxf4nvf4-kind.ll
+309-0llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-collector-b.ll
+217-0llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-collector-b.ll
+212-0llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-disable-output-lane-collector-b.ll
+151-0llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b.ll
+2,153-011 files not shown
+2,320-11017 files

LLVM/project 585178dllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 intrinsic-vector-match-sve2.ll

[AArch64] Remove search size limit in VECTOR_MATCH lowering (#215786)

Any legal (64/128-bits) needle vector can be lowered to `match`.
DeltaFile
+29-0llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
+0-8llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+29-82 files

LLVM/project 23e0cbelldb/source/Expression DWARFExpression.cpp, lldb/unittests/Expression DWARFExpressionTest.cpp

[LLDB] fix lldb breg adress width (#216291)

`DW_OP_breg0..31` and `DW_OP_bregx` preserved the scalar width supplied
by the register backend and added their displacement as a `uint64_t`. On
32-bit targets this could leave a 64-bit value on the expression stack,
so later generic address arithmetic did not wrap at the target address
size.

Perform the register-plus-offset calculation using the evaluator's
address-sized generic representation. This keeps `DW_OP_breg*` results
at the target address width without changing shared register reading or
the generic
operand compatibility rule.

Add unit tests for both compact and extended breg opcodes. They cover a
32-bit register value, a backend-provided 64-bit register value on i386,
a negative displacement, and modulo-32-bit overflow.

Fixes #209728
DeltaFile
+31-0lldb/unittests/Expression/DWARFExpressionTest.cpp
+4-2lldb/source/Expression/DWARFExpression.cpp
+35-22 files

LLVM/project d0bc528llvm/tools/llvm-nm llvm-nm.cpp

Address review comments on the parameter.
DeltaFile
+2-3llvm/tools/llvm-nm/llvm-nm.cpp
+2-31 files

LLVM/project 04956d9llvm/include/llvm/Analysis DXILResource.h, llvm/include/llvm/IR IntrinsicsDirectX.td

[DirectX] Add support for heap resources to `DXILResourceMap`.

- `DXILResourceMap` now handles a new `llvm.dx.resource.handlefromheap` intrisics
  and adds the heap resources to the resource map.

- A new member `HeapResourceID` has been added to `ResourceInfo` to distinguish
  between heap resource instances created from different indices. The `HeapResourceID`
  is unique for each heap index `Value*`, so multiple handle creation calls using
  the same index `Value*` resolve to the same resource.

- Heap resources do not have register bindings, so the `Binding` member
  on `ResourceInfo` is now optional.

- All places that were always expecting binding are updated to handle
  heap resources. In most cases that means skipping them, such as when
  generating DXIL resource metadata, creating PSV resource entries or
  pretty-printing the resource table comment for the module disassembly
  output.


    [2 lines not shown]
DeltaFile
+174-0llvm/test/Analysis/DXILResource/buffer-fromheap.ll
+50-14llvm/lib/Analysis/DXILResource.cpp
+24-7llvm/include/llvm/Analysis/DXILResource.h
+9-5llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
+12-0llvm/test/CodeGen/DirectX/resource_from_heap_counter_error.ll
+10-0llvm/include/llvm/IR/IntrinsicsDirectX.td
+279-262 files not shown
+289-268 files

LLVM/project 22eba47lld/ELF SyntheticSections.cpp, lld/test/ELF eh-frame-hdr-oscillation.s

[ELF] Prevent .eh_frame_hdr size oscillation in address assignment (#216248)

When .eh_frame_hdr size shifts, section addresses can change whether
FDEs evaluate to identical PC-relative offsets, causing FDE
deduplication count to toggle and section size to oscillate infinitely
between passes.

Prevent .eh_frame_hdr from shrinking during iterative address assignment
passes (matching .relr.dyn) to ensure monotonic convergence.
DeltaFile
+51-0lld/test/ELF/eh-frame-hdr-oscillation.s
+6-0lld/ELF/SyntheticSections.cpp
+57-02 files

LLVM/project 05ed268llvm/include/llvm/Analysis DXILResource.h, llvm/lib/Analysis DXILResource.cpp

[NFC][DirectX] Rename ResourceInfo::RecordID to BindingID (#216376)

Rename `ResourceInfo::RecordID` to `BindingID` to better reflect its
purpose. This field is set only for resources with an associated
binding. This also clarifies the distinction from the upcoming
`HeapResourceID` member, which will identify resources originating from
a heap. The existing `RecordID` name could be ambiguous once both
identifiers are present.

The change also removes the `RecordID` argument from the `ResourceIfo`
constructor because it has always been called with `0` value. The
`BindingID` is set later via `setBindingID` after all resource instances
are collected.
DeltaFile
+32-34llvm/unittests/Analysis/DXILResourceTest.cpp
+10-10llvm/test/Analysis/DXILResource/buffer-frombinding.ll
+10-10llvm/include/llvm/Analysis/DXILResource.h
+4-5llvm/lib/Analysis/DXILResource.cpp
+3-3llvm/test/Analysis/DXILResource/has-atomic64-use.ll
+2-2llvm/test/Analysis/DXILResource/buffer-frombinding-unbounded.ll
+61-642 files not shown
+63-668 files

LLVM/project 25e6e73llvm/lib/Target/AMDGPU SIInstrInfo.td, llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.cpp

[AMDGPU][MC] Fix a crash when invalid SDWA encoding is used

Fixes #215006.
DeltaFile
+16-0llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+14-0llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
+4-1llvm/lib/Target/AMDGPU/SIInstrInfo.td
+34-13 files

LLVM/project 0cd9f45llvm/lib/Target/AMDGPU SIInstrInfo.td, llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.cpp

[AMDGPU][MC] Fix a crash when invalid SDWA encoding is used

Fixes #215006.
DeltaFile
+16-0llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+14-0llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
+4-1llvm/lib/Target/AMDGPU/SIInstrInfo.td
+34-13 files

LLVM/project b43c56bclang-tools-extra/clangd Diagnostics.cpp, clang-tools-extra/clangd/unittests DiagnosticsTests.cpp

[clangd][clang-tidy] Factor out mergeFixits() logic and reuse it in clangd (#208682)

This patch extracts `mergeFixits()` from `DiagnosticRenderer` to
`clang::edit` and reuses it in clangd. This prevents syntax errors
caused by token merging when applying clang-tidy fixits via clangd.

Fixes #207618
DeltaFile
+56-6clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
+54-0clang/lib/Edit/EditedSource.cpp
+1-51clang/lib/Frontend/DiagnosticRenderer.cpp
+11-3clang-tools-extra/clangd/Diagnostics.cpp
+9-0clang/include/clang/Edit/EditedSource.h
+2-0clang-tools-extra/docs/ReleaseNotes.md
+133-601 files not shown
+134-607 files

LLVM/project 125c8d3llvm/lib/DWARFLinker/Parallel AcceleratorRecordsSaver.cpp, llvm/test/tools/dsymutil/AArch64 lit.local.cfg debug-names-accel-table-types.ll

[DWARFLinker] Index Swift mangled type names in the parallel linker (#216429)

Swift records a type's mangled name in DW_AT_linkage_name. The classic
linker indexes it as a type accelerator entry alongside the short
DW_AT_name, but the parallel linker indexed only the short name.

Port the DW_LANG_Swift block added to the classic linker in 8234f8ae2685
to the parallel linker's type case.
DeltaFile
+213-0llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/debug-names-swift-mangled-type.s
+35-14llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.cpp
+3-3llvm/test/tools/dsymutil/AArch64/debug-names-accel-table-types.ll
+1-1llvm/test/tools/dsymutil/AArch64/lit.local.cfg
+252-184 files

LLVM/project 34cce43llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

Revert "[SLP]Recalculate copyable-element deps after tree reordering"

This reverts commit 8024076c7591b6477d23c3519652a7c6487d97d3 to fix
buildbot https://lab.llvm.org/buildbot/#/builders/210/builds/12275

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/216444
DeltaFile
+0-188llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+0-50llvm/test/Transforms/SLPVectorizer/RISCV/recalc-copyable-deps-on-reorder.ll
+2-34llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-2723 files

LLVM/project 101a9b5llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-188llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+0-50llvm/test/Transforms/SLPVectorizer/RISCV/recalc-copyable-deps-on-reorder.ll
+2-34llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-2723 files

LLVM/project 8024076llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

[SLP]Recalculate copyable-element deps after tree reordering

Reordering permutes the operand columns of the entries and may move an
operand between copyable-covered and plain edges, making the computed
dependency counts stale and tripping the unscheduled-deps assertion.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/216442
DeltaFile
+188-0llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+50-0llvm/test/Transforms/SLPVectorizer/RISCV/recalc-copyable-deps-on-reorder.ll
+34-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+272-23 files

LLVM/project ef3a908clang/docs/analyzer checkers.md, clang/docs/analyzer/developer-docs InitializerLists.md

[docs][clang] Finish MyST migration for analyzer docs
DeltaFile
+210-198clang/docs/analyzer/user-docs/Annotations.md
+32-33clang/docs/analyzer/developer-docs/InitializerLists.md
+21-22clang/docs/analyzer/user-docs/CommandLineUsage.md
+15-16clang/docs/analyzer/user-docs/CrossTranslationUnit.md
+12-13clang/docs/analyzer/checkers.md
+5-6clang/docs/analyzer/user-docs/UsingWithXCode.md
+295-2889 files not shown
+312-31415 files

LLVM/project 7dc88ccllvm/lib/Target/RISCV RISCVInstrInfoSFB.td RISCVFeatures.td, llvm/test/CodeGen/RISCV short-forward-branch-opt-zibi.ll sfb-merge-base-offset.ll

[RISCV] Remove short-forward-branch-imm. (#216401)

Just use short-forward-branch-ialu. I hope implentations that implement
short-forward-branch, do it equally for all branch types. Doing anything
else would create complex tradeoffs.

I'm planning to add conditional c.mv fusion support for Zibi and I don't
want to add an immediate version flag there.

The patterns that checked NoShortForwardBranchImm were not checking that
an immediate branch ISA was enabled. So I've changed them to
NoVendorXqcibiOrNoShortForwardBranch.
DeltaFile
+7-7llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+2-7llvm/lib/Target/RISCV/RISCVFeatures.td
+3-3llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll
+2-2llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
+1-2llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+17-2313 files not shown
+29-3619 files

LLVM/project 47aa7b9llvm/test/Transforms/SLPVectorizer/AMDGPU elementwise-fma-operand1.ll

[NFC][SLP] Add a test for fma fusion with the fmul on operand 1 (#216428)

canConvertToFMA only looks at operand 0 of the fadd, so the accumulator
shape fadd c, a * b is never recognised, and the fmul it does find is
priced with the target's fusion discount already applied. The threshold
puts the decision right at the cost boundary so the checks record which
way SLP goes today.
DeltaFile
+114-0llvm/test/Transforms/SLPVectorizer/AMDGPU/elementwise-fma-operand1.ll
+114-01 files

LLVM/project 8a6a59allvm/include/llvm/DWARFLinker AddressesMap.h, llvm/lib/DWARFLinker/Classic DWARFLinker.cpp

[DWARFLinker] Constrain a function's high_pc to its own symbol (#216432)

Mach-O objects built with .subsections_via_symbols make every symbol an
independently placeable atom, and the linker packs atoms without
preserving the spacing they had in the object file.

I have an example where the compiler describes such a subprogram as
extending past its own atom. While it's debatable whether that's a good
idea, it's not invalid in the object file. However, once linked, it is
invalid.

We can make dsymutil resilient against this by looking at the size of
the symbol in the debug map and adjusting the end_pc. I'm doing so
conservatively so that only a collision is repaired. Already
overlapping/invalid ranges remain untouched.

rdar://184768778
DeltaFile
+88-0llvm/test/tools/dsymutil/subprogram-high-pc-past-symbol.test
+76-0llvm/test/tools/dsymutil/Inputs/subprogram-high-pc-past-symbol.s
+72-0llvm/test/tools/dsymutil/Inputs/subprogram-high-pc-past-symbol-dwarf2.s
+38-8llvm/include/llvm/DWARFLinker/AddressesMap.h
+34-2llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
+24-6llvm/tools/dsymutil/DwarfLinkerForBinary.h
+332-163 files not shown
+371-209 files