1,107,040 commits found in 87 milliseconds
[mlir] Reuse the MLIRIR PCH through dependencies (NFC)
Track whether an MLIR library's link closure reaches MLIRIR and reuse the
MLIRIR PCH for those libraries. Preserve higher-priority local PCHs and add an
explicit opt-out for targets whose sources are incompatible with reuse.
Relative to the core and LLVM dialect PCH parent, clean Release builds of LLVM
and MLIR with Ninja -j16 pinned to CPUs 16-31 improved as follows:
wall: 398.79s -> 386.47s (-3.09%)
user: 5789.14s -> 5624.02s (-2.85%)
system: 455.05s -> 438.45s (-3.65%)
Assisted-by: Codex
LLVM /project 707c032 — mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/test/Dialect/Tosa ops.mlir invalid_extension.mlir [mlir][tosa] Add support for MXFP SCATTER (#222288)
Tosa specification changes in
https://github.com/arm/tosa-specification/pull/78 [mlir][LLVM] Reuse a PCH for MLIRLLVMDialect (NFC)
Build a private precompiled header from the LLVM dialect and LLVM IR headers
and use it for MLIRLLVMDialect. Build dialect libraries before conversions so
the PCH is available early and repeated parsing is avoided.
Relative to the MLIRIR PCH parent, clean Release builds of LLVM and MLIR with
Ninja -j16 pinned to CPUs 16-31 improved as follows:
wall: 420.41s -> 398.79s (-5.14%)
user: 6125.97s -> 5789.14s (-5.50%)
system: 481.88s -> 455.05s (-5.57%)
Assisted-by: Codex
[gn] port eb5cd179549d68 (#222476) [mlir] Reuse a precompiled header for MLIRIR (NFC)
Build a private precompiled header from the common MLIR IR headers and use it
for MLIRIR. Build Support and IR first so the PCH is available early, and
qualify the LLVM LSP Location name that the broader header surface exposes.
On current main, clean Release builds of LLVM and MLIR with Ninja -j16 pinned
to CPUs 16-31 improved as follows:
wall: 535.99s -> 420.41s (-21.56%)
user: 7550.29s -> 6125.97s (-18.86%)
system: 569.85s -> 481.88s (-15.44%)
Assisted-by: Codex
LLVM /project 265bb9f — clang/lib/Basic/Targets AMDGPU.cpp AMDGPU.h, llvm/include/llvm/TargetParser AMDGPUTargetParser.h AMDGPU: Migrate R600 onto generated TargetParser bitset (#222461)
Follow the new amdgcn system so we don't have to carry 2 different
forms of this infrastructure.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com> LLVM /project 70e79a0 — llvm/lib/Target/X86/AsmParser X86AsmParser.cpp, llvm/test/MC/X86 x86_errors.s [X86] Reject a register where a memory operand displacement belongs (#216068)
Fixes #61438 [ProfCheck] Removing passing tests from xfail list (#222473)
These tests appear to be passing/deleted as of 9/9/26. LLVM /project f1b62b8 — clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl First attempt implementing InterlockedCompareExchangeFloatBitwise
LLVM /project f861da9 — clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl First attempt implementing InterlockedCompareStoreFloatBitwise
LLVM /project 31a16a5 — clang/lib/Sema SemaHLSL.cpp HLSLExternalSemaSource.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl RWByteAddressBuffer-InterlockedCompareExchange.hlsl First attempt implementing InterlockedCompareExchange
LLVM /project 92e630b — clang/test/AST/HLSL Textures-vector-AST.hlsl Textures-scalar-AST.hlsl, clang/test/CodeGenHLSL/resources Textures-Sample.hlsl Textures-Mips.hlsl [HLSL] Add Texture3D and RWTexture3D types (#220438)
Fixes https://github.com/llvm/llvm-project/issues/194739 and fixes
https://github.com/llvm/llvm-project/issues/194743
This PR implements Texture3D and RWTexture3D and adds+modifies tests for
the two types.
Assisted by: Claude Opus 5
---------
Co-authored-by: Finn Plummer <mail at inbelic.dev> LLVM /project 3cff976 — clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Sema HLSLExternalSemaSource.cpp First attempt implementing InterlockedCompareStore
LLVM /project ff2b4c2 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll Count the intrinsics that really become calls when refusing promotion
LLVM /project d35391e — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll Do not add a second lifetime start when allocating VGPRs again
LLVM /project 1f7b3e5 — llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll Promote private objects into the VGPR address space via flag
LLVM /project 5bab363 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll Carry null operands and intrinsic names across when promoting to VGPRs
LLVM /project f940596 — llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-private-object-vgprs.mir Propagate object liveness to every changed successor, not only back edges
LLVM /project ebb7ec3 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-budget.ll Diagnose an object that does not fit the function's register budget
LLVM /project cc91d70 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll Refuse promotion only when the object is live across a call
LLVM /project 929d2a7 — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll Treat a sub-dword VGPR-memory load as divergent too
LLVM /project 3d934eb — llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll Diagnose inline asm that clobbers a VGPR-memory object's registers
LLVM /project 0bc0c41 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-across-call.ll as-vgpr-private-object-vgprs.mir Allocate and reserve registers for address space 13 objects
Pin the width guard that keeps sub-dword accesses out of aliasing decisions
LLVM /project fe6a59b — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-index-demanded-bits.ll Regenerate the demanded-bits expectations for the gfx1250 entry sequence
LLVM /project 8c6abb8 — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits-encoding.ll as-vgpr-bits.ll Regenerate the sub-dword expectations for the M0 setup change
LLVM /project f2fb95b — llvm/lib/Target/AMDGPU AMDGPULowerIdxOps.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir as-vgpr-verifier.mir Check the encodings of the sub-dword VGPR-memory accesses
LLVM /project 9b3c2fc — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp Document the sub-dword access rules for the VGPR address space
LLVM /project 2a1620d — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll as-vgpr-index-demanded-bits.ll Fix tests
LLVM /project 6871e98 — llvm/lib/Target/AMDGPU SIInstructions.td SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir Inherit the M0 operand when expanding the sub-dword VGPR-memory pseudos
