LLVM/project f214ce6utils/bazel/llvm-project-overlay/libc BUILD.bazel, utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet BUILD.bazel

[libc][bazel] Add missing arpa/inet functions and tests (#210310)

Add bazel build targets for the remaining arpa/inet functions
(inet_addr, inet_aton, inet_ntoa, and inet_ntop) along with their unit
tests and supporting targets (__support_net_address, headers, and proxy
types).

Assisted by Gemini.
DeltaFile
+110-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+43-0utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
+153-02 files

LLVM/project a4ca7f3libc/hdr CMakeLists.txt

[libc][cmake] Remove proxy header XXX_macros -> XXX.h deps (#210008)

In the full build mode, these headers do not include the main XXX.h
header, which makes sense, because they exist to allow us only to expose
a part of it. They do include it in the overlay mode, but in this case,
they are referring to the header from the libc being overlaid, which
exists outside of the build system.

Also fix float_macros by moving
libc.include.llvm-libc-macros.float_macros from DEPENDS to
FULL_BUILD_DEPENDS, as llvm-libc-macros/float-macros.h is only included
under LIBC_FULL_BUILD.
DeltaFile
+1-37libc/hdr/CMakeLists.txt
+1-371 files

LLVM/project 751fca6clang/test/Driver freebsd-mips-as.c freebsd.c

[Driver][test] Unwrap freebsd-mips-as.c RUN lines (#210658)

Collapse 3-line RUN blocks to 2 lines and move -### immediately after
%clang, matching the prevailing style for new tests.
DeltaFile
+34-51clang/test/Driver/freebsd-mips-as.c
+14-23clang/test/Driver/freebsd.c
+48-742 files

LLVM/project f9a440bllvm/test/TableGen RuntimeLibcallEmitter-predicate-dag.td, llvm/utils/TableGen/Basic PredicateExpanderDag.cpp PredicateExpanderDag.h

Only apply parens to not
DeltaFile
+4-4llvm/test/TableGen/RuntimeLibcallEmitter-predicate-dag.td
+5-3llvm/utils/TableGen/Basic/PredicateExpanderDag.cpp
+2-3llvm/utils/TableGen/Basic/PredicateExpanderDag.h
+1-1llvm/utils/TableGen/Basic/RuntimeLibcalls.cpp
+12-114 files

LLVM/project 92aded9flang/lib/Lower PFTBuilder.cpp Bridge.cpp, flang/test/Lower do_loop_execute_region_wrap.f90 do_loop_unstructured.f90

[flang][PFT-to-MLIR] Wrap unstructured Fortran constructs in scf.execute_region (#208635)

Extend the PFT-to-MLIR (HLFIR/FIR) lowering so unstructured DO and IF
constructs are emitted inside scf.execute_region, hiding their
multi-block CFG behind a single op. OpenACC lowerings that reject
multi-block content (e.g. the "unstructured do loop in combined acc
construct" TODO in OpenACC.cpp) now see a structured op instead.

The main goal is to prevent propagating the "unstructured" property up
the evaluation tree just because one nested evaluation is unstructured;
which is the current behavior.

Flag: -mmlir --wrap-unstructured-constructs-in-execute-region (default
on).

An evaluation is wrappable iff all of the following hold:

  * wrap flag on
  * eval is parser::DoConstruct or parser::IfConstruct

    [37 lines not shown]
DeltaFile
+227-4flang/lib/Lower/PFTBuilder.cpp
+103-102flang/test/Lower/OpenMP/unstructured.f90
+177-24flang/test/Lower/OpenACC/acc-unstructured.f90
+171-0flang/test/Lower/do_loop_execute_region_wrap.f90
+144-4flang/lib/Lower/Bridge.cpp
+38-87flang/test/Lower/do_loop_unstructured.f90
+860-22122 files not shown
+1,181-52128 files

LLVM/project ba9a115llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 vselect-masked-shift.ll

[AArch64] Fold vector shifts guarded against oversized amounts into USHL (#207628)

`select(icmp ult(amt, EltSize), shl(x, amt), 0)`, where EltSize is the
{8, 16, 32, 64} lane size, is the usual way to guard a variable vector
shift against shl poison. On AArch64 the guard is unnecessary because
USHL already returns zero once the shift amount reaches the lane size.

For v4i32:

Before:
```
        movi    v2.4s, #63
        movi    v3.4s, #32
        and     v1.16b, v1.16b, v2.16b
        ushl    v0.4s, v0.4s, v1.4s
        cmhi    v1.4s, v3.4s, v1.4s
        and     v0.16b, v1.16b, v0.16b
```
After:

    [22 lines not shown]
DeltaFile
+277-0llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
+81-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+358-02 files

LLVM/project 9e2e9b3libc/cmake/modules LLVMLibCTestRules.cmake, libc/test/UnitTest ExecuteFunctionUnix.cpp HermeticTestUtils.cpp

[libc] Port process utilities to hermetic mode and enable some tests (#209999)

This is achieved by calling internal libc functions in hermetic mode. In
the overlay mode I keep calling the system functions so that the tests
work even on systems which don't have these implemented.

I also needed to implement the delete operators as both the libc proper
and the test framework uses them nowadays.

This is sufficient to enable all stdlib tests in hermetic mode, except
for one, which actually exposes a bug in the implementation. I'll deal
with that in a separate patch.
DeltaFile
+41-13libc/test/UnitTest/ExecuteFunctionUnix.cpp
+5-14libc/test/UnitTest/HermeticTestUtils.cpp
+13-2libc/test/UnitTest/CMakeLists.txt
+13-0libc/cmake/modules/LLVMLibCTestRules.cmake
+1-11libc/test/src/stdlib/CMakeLists.txt
+2-3libc/test/UnitTest/LibcDeathTestExecutors.cpp
+75-431 files not shown
+76-437 files

LLVM/project 56e13dcllvm/docs LangRef.md

Explicitly restrict the atomic ordering constraints to perfectly overlapping accesses.
DeltaFile
+29-18llvm/docs/LangRef.md
+29-181 files

LLVM/project 99789calibcxx/docs/Status Cxx23Issues.csv, libcxx/test/std/ranges/range.adaptors/range.adjacent.transform helpers.h

[libc++] Add tests for LWG3798 and mark it as Complete (#210640)
DeltaFile
+5-0libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/helpers.h
+4-0libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
+1-1libcxx/docs/Status/Cxx23Issues.csv
+10-13 files

LLVM/project 21d537ellvm/test/Transforms/LoopVectorize iv_outside_user.ll

[LV][Test] Rename conflicting IR values to avoid FileCheck conflicts. nfc (#210293)
DeltaFile
+50-50llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+50-501 files

LLVM/project e2572b8lld/ELF/Arch RISCV.cpp, lld/test/ELF riscv-feature-zicfilp-unlabeled.s

[LLD][RISCV][Zicfilp] Generate unlabeled landing pad-style PLT (#145461)

To support dynamic linking when Zicfilp is enabled, lpad insns are
inserted into PLTs. This patch generates the unlabeled landing pad-style
PLT, in which all the lpads have label `0`, when ZICFILP-unlabeled is
enabled:

--- PLT Header:

```
1:  auipc  t3, %pcrel_hi(.got.plt)
    sub    t1, t1, t2
    l[w|d] t2, %pcrel_lo(1b)(t3)
    addi   t1, t1, -(hdr size + 16)
    addi   t0, t3, %pcrel_lo(1b)
    srli   t1, t1, log2(16/PTRSIZE)
    l[w|d] t0, PTRSIZE(t0)
    jr     t2
```

    [16 lines not shown]
DeltaFile
+59-23lld/ELF/Arch/RISCV.cpp
+32-0lld/test/ELF/riscv-feature-zicfilp-unlabeled.s
+91-232 files

LLVM/project c34d2c3mlir/lib/Dialect/LLVMIR/IR LLVMMemorySlot.cpp, mlir/test/Dialect/LLVMIR mem2reg.mlir

[mlir] Fix mem2reg crash on scalable vector store/load with matching type (#209426)

Fixes #209065

`createInsertAndCast/createExtractAndCast` in `LLVMMemorySlot.cpp`
queried the bit size of the source/target types before checking whether
they were already identical. For scalable vector types (e.g.
`vector<[4]xi1>`), this size query implicitly converts a scalable
TypeSize to a scalar, which aborts. `mem2reg` hits this path for any
store or load whose value type exactly matches the slot's element type,
since `getStored/removeBlockingUses` run even when no cast is needed.

This fix adds an early return when the types are already equal, skipping
the size query, consistent with the existing short-circuit in
`areConversionCompatible/castSameSizedTypes`.
DeltaFile
+14-0mlir/test/Dialect/LLVMIR/mem2reg.mlir
+11-0mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
+25-02 files

LLVM/project 9ddbe1cllvm/lib/Transforms/Coroutines MaterializationUtils.cpp

remove redundant predicate check
DeltaFile
+3-4llvm/lib/Transforms/Coroutines/MaterializationUtils.cpp
+3-41 files

LLVM/project dcb9342llvm/docs LangRef.md

Adapt Ralf's simpler no-tearing formulation.
DeltaFile
+3-4llvm/docs/LangRef.md
+3-41 files

LLVM/project 222d484llvm/docs LangRef.md

Remove vague use of "defined"
DeltaFile
+2-2llvm/docs/LangRef.md
+2-21 files

LLVM/project d8f7ce0llvm/docs LangRef.md

[RFC][LangRef] Specify that the accessed bytes of concurrent atomics must be either disjoint or the same

So far, the LangRef hasn't been clear on the semantics of partially overlapping
concurrent atomics in LLVM IR (specifically: a set of accesses marked as
`atomic` that would be in a data race if they weren't `atomic` and not all of
them access the exact same set of bytes).

What loads read is defined in terms of individual bytes, but the memory
ordering constraints are formulated closely to the C/C++ (and Java for
`unordered`) memory model, where partially overlapping atomics are not
possible. It's not obvious how concepts like C/C++'s per-location total
modification order for `monotonic` accesses map to accesses that can partially
overlap. While C/C++ relies on the modification order to ensure that atomics
cannot tear (i.e., atomic reads return bytes from two or more atomic writes),
our IR semantics (as written) currently does not guarantee this in the presence
of partially overlapping accesses.

This PR proposes a solution to this problem: It specifies that concurrent
overlapping atomics must access the exact same set of bytes to act atomically.

    [7 lines not shown]
DeltaFile
+5-1llvm/docs/LangRef.md
+5-11 files

LLVM/project 29a08b5llvm/docs LangRef.md

"un-simplify" the no-tearing constraint
DeltaFile
+4-2llvm/docs/LangRef.md
+4-21 files

LLVM/project 9d2e7e6llvm/test/Transforms/FixIrreducible switch.ll nested.ll, llvm/test/Transforms/UnifyLoopExits integer_guards.ll restore-ssa.ll

[FixIrreducible][UnifyLoopExits] Support switch statements (#206567)

This builds on #149308, which implemented `callbr` support.

The same approach of splitting multi-branch edges entering irreducible
loops can be used for switches. It does not introduce any new switch
statements, but alleviates the requirement of having to run the
`LowerSwitch` pass first. This makes the pass usable for users other
than AMDGPU, which can handle switch statements (e.g., WebAssembly, see
[here](https://github.com/llvm/llvm-project/pull/181755#issuecomment-3936316307)).

I'm also implementing a flag into the `ControlFlowHub` to support
switches as well, for which I will open a separate PR. Currently the
`ControlFlowHub` creates a branch-sled, mimicking a `switch` (a series
of blocks consisting only of conditional branches, selectively entering
an irreducible loop at a certain point or continuing to the next
potential entry point). If the target can support switches, that should
be the clear goal here, as shown in the image below. This PR implements
the step from (a) to (b), whereas extending the `ControlFlowHub`

    [10 lines not shown]
DeltaFile
+931-25llvm/test/Transforms/FixIrreducible/switch.ll
+800-69llvm/test/Transforms/FixIrreducible/nested.ll
+473-30llvm/test/Transforms/UnifyLoopExits/integer_guards.ll
+260-15llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
+171-0llvm/test/Transforms/UnifyLoopExits/multiedge.ll
+164-4llvm/test/Transforms/UnifyLoopExits/basic.ll
+2,799-14311 files not shown
+3,470-31417 files

LLVM/project 146fb5bllvm/test/TableGen RuntimeLibcallEmitter-predicate-dag.td, llvm/utils/TableGen/Basic PredicateExpanderDag.h RuntimeLibcalls.cpp

TableGen: Parenthesize negated predicate-dag leaves with operators

Allows writing more general expressions in the predicate code. Previously
not ("a == b") would be emitted as !a == b.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+18-6llvm/test/TableGen/RuntimeLibcallEmitter-predicate-dag.td
+3-1llvm/utils/TableGen/Basic/PredicateExpanderDag.h
+1-1llvm/utils/TableGen/Basic/RuntimeLibcalls.cpp
+22-83 files

LLVM/project 2a76dc0llvm/include/llvm/IR RuntimeLibcallsImpl.td, llvm/test/TableGen RuntimeLibcallEmitter-predicate-dag.td RuntimeLibcallEmitter-predicate-dag-errors.td

RuntimeLibcalls: Reuse AssemblerPredicate's operators for libcalls

Allow specifying RuntimeLibcall's availability in terms of individual
triple properties composed with logical operators.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+60-0llvm/test/TableGen/RuntimeLibcallEmitter-predicate-dag.td
+24-35llvm/utils/TableGen/Common/SubtargetFeatureInfo.cpp
+56-0llvm/utils/TableGen/Basic/PredicateExpanderDag.cpp
+42-0llvm/test/TableGen/RuntimeLibcallEmitter-predicate-dag-errors.td
+41-0llvm/utils/TableGen/Basic/PredicateExpanderDag.h
+29-2llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+252-373 files not shown
+291-409 files

LLVM/project d39269allvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

Update some comments and some fix
DeltaFile
+154-112llvm/lib/Analysis/DependenceAnalysis.cpp
+63-0llvm/test/Analysis/DependenceAnalysis/banerjee-symbolic.ll
+2-1llvm/include/llvm/Analysis/DependenceAnalysis.h
+219-1133 files

LLVM/project a64f741llvm/lib/Target/SPIRV SPIRVStructurizer.cpp, llvm/test/CodeGen/SPIRV/structurizer HLSLControlFlowHint-pass-check.ll

[SPIR-V][NewPM] Register SPIRVStructurizer with the new pass manager (#209965)
DeltaFile
+39-31llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
+9-0llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
+48-312 files

LLVM/project d7f7b0cllvm/include/llvm/IR RuntimeLibcalls.td RuntimeLibcallsImpl.td, llvm/test/TableGen RuntimeLibcallEmitter.td RuntimeLibcallEmitter-calling-conv.td

RuntimeLibcalls: Rename RuntimeLibcallPredicate to RuntimeLibcallAvailability

Rename to avoid confusing partial name collisions in future changes.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+79-79llvm/include/llvm/IR/RuntimeLibcalls.td
+10-10llvm/test/TableGen/RuntimeLibcallEmitter.td
+8-8llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+5-5llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td
+3-3llvm/test/TableGen/RuntimeLibcallEmitter-nested-predicates-error.td
+3-3llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td
+108-1083 files not shown
+112-1119 files

LLVM/project 8a11931clang/include/clang/Basic DiagnosticIDs.h

[clang][NFC] Bump the maximum number of Frontend diagnostics (#210345)

The number of Frontend diagnostics in DiagnosticFrontendKinds.td is
close to the DIAG_SIZE_FRONTEND limit of 200 (195 in use), and in-flight
PRs adding frontend diagnostics (e.g. #187986) run into the static
assert in DiagnosticIDs.cpp. Increase the limit to 300, following the
precedent of #200948 which did the same for Sema diagnostics.

Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
DeltaFile
+1-1clang/include/clang/Basic/DiagnosticIDs.h
+1-11 files

LLVM/project c98bd8cllvm/docs NVPTXUsage.rst NVPTXUsage.md, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

Merge branch 'users/aokblast/lldb/fix_auxilary_handle' into users/aokblast/lldb/mmap_fix_for_reexport
DeltaFile
+0-4,767llvm/docs/NVPTXUsage.rst
+2,949-1,487llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,871-1,461llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+4,253-0llvm/docs/NVPTXUsage.md
+3,624-0mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+1,635-849llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+15,332-8,5646,297 files not shown
+150,969-75,9326,303 files

LLVM/project d8a4772llvm/docs NVPTXUsage.rst NVPTXUsage.md, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

Merge branch 'main' into users/aokblast/lldb/fix_auxilary_handle
DeltaFile
+0-4,767llvm/docs/NVPTXUsage.rst
+2,949-1,487llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,871-1,461llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+4,253-0llvm/docs/NVPTXUsage.md
+3,624-0mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+1,635-849llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+15,332-8,5646,297 files not shown
+150,969-75,9326,303 files

LLVM/project 53c6ce1libcxx/include/__utility cmp.h

[libc++][cmp][NFC] Fix: Empty namespaces should be avoided (#210624)

Context: Including `<__utility/cmp.h>` causes:

> cmp.h:25:1: error: Empty namespaces should be avoided. Move any checks
around the namespace instead.
[libcpp-avoid-empty-namespaces,-warnings-as-errors]
DeltaFile
+4-4libcxx/include/__utility/cmp.h
+4-41 files

LLVM/project 5497f46clang/lib/Headers riscv_packed_simd.h, clang/test/CodeGen/RISCV rvp-intrinsics.c

[RISCV][P-ext] Support Packed Narrowing Zip (#210040)
DeltaFile
+266-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+99-0llvm/test/CodeGen/RISCV/rvp-narrowing-zip.ll
+80-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+46-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+43-0clang/lib/Headers/riscv_packed_simd.h
+26-3llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+560-36 files

LLVM/project d417c27clang/include/clang/Basic DiagnosticIDs.h

[clang][NFC] Bump the maximum number of Frontend diagnostics

The number of Frontend diagnostics in DiagnosticFrontendKinds.td is close
to the DIAG_SIZE_FRONTEND limit of 200 (195 in use). Increase the limit
to 300.
DeltaFile
+1-1clang/include/clang/Basic/DiagnosticIDs.h
+1-11 files

LLVM/project 126d90allvm/docs NVPTXUsage.rst NVPTXUsage.md, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

Merge branch 'main' into users/tonykuttai/bump-diag-size-frontend
DeltaFile
+0-4,767llvm/docs/NVPTXUsage.rst
+2,949-1,487llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,871-1,461llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+4,253-0llvm/docs/NVPTXUsage.md
+1,635-849llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+0-1,177llvm/docs/JITLink.rst
+11,708-9,741576 files not shown
+38,248-22,080582 files