[RISCV] Add ABI_IL32PC64E and ABI_CHERIOT to RISCVABI::isRVE. Use in RISCVTargetELFStreamer::finish. NFC
The isRVE function is used in codegen, but as far as I know we don't support
codegen with these ABIs yet so that code isn't reachable.
[SystemZ][Clang] Update Modules and PCH lit tests for z/OS (#238624)
Mark the modules & pch lit tests that are failing on z/OS as xfail or
unsupported.
[AArch64] Combine SVE AND and XOR to BIC for _m form
Add patterns to combine the expressions of the following type to BIC
when possible:
```
return svand_u32_m(svptrue_b32(), a, sveor_u32_x(svptrue_b32(), a, b));
```
Cover symmetric case where result of AND is used by EOR for the above
expression.
Cover cases where the inner node is of _u form like sveor_u32_u or
sveand_u32_u.
Cover cases where the inner node is of _m/_z form under matching
predicates or all-active predicates for the inner node.
Also, cover the case where the inner node is a normal LLVM AND(or XOR)
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[libc++] Provide `optional::iterator` a packed, bounded representation (#203782)
The current situation with `optional::iterator`:
If the ABI switch is on, then `optional`'s iterator type is
`__bounded_iter` as it is a bit stronger, since
`__static_packed_bounded_iter` can only guarantee that a dereference
isn't out of bounds `__bounded_iter` can guard against dereferencing an
uninitialized item in bounds.
Otherwise, if `T` fulfills the alignment requirements for
`__static_packed_bounded_iter`, then the iterator type is that.
Otherwise, it is `__capacity_aware_iterator`.
Due to the implementation of `__static_packed_bounded_iter` which relies
on pointer tagging, `optional::iterator` cannot be constexpr.
[llvm] Remove forward and friend declarations of non-existent types (NFC) (#238694)
This patch removes forward and friend declarations of classes that have
no definitions in the codebase.
Note that llvm::TargetExtType exists in IR, whereas
llvm::sandboxir::TargetExtType has never been defined.
Assisted-by: Antigravity
[clang] Remove forward declarations of non-existent types (NFC) (#238693)
This patch removes forward declarations of classes that have no
definitions in the codebase.
Assisted-by: Antigravity
[AMDGPU][CodeGen] Move rematerialization strategy out of scheduler (NFC)
This un-ties the rematerialization strategy based on the
target-independent `Rematerializer` from the `PreRARematStage`, allowing
its use at different points in the pipeline and making future changes to
the strategy easier thanks to better separation of concerns. The
strategy is moved as-is with no functional changes at the moment.
[SPIR-V] Fix ALTERA write pipe and float-to-int cast opcodes (#238729)
- OpWritePipeBlockingALTERA reused the read opcode, so objects encoded
writes as reads
- OpArbitraryFloatCastToIntALTERA used an invalid opcode
[AMDGPU][CodeGen] Move rematerialization strategy out of scheduler (NFC)
This un-ties the rematerialization strategy based on the
target-independent `Rematerializer` from the `PreRARematStage`, allowing
its use at different points in the pipeline and making future changes to
the strategy easier thanks to better separation of concerns. The
strategy is moved as-is with no functional changes at the moment.
[AArch64] Add patterns to combine SVE AND and XOR to BIC
Add ISel patterns to rewrite the following pattern to BIC:
```
return svand_u32_x(svptrue_b32(), a, sveor_u32_x(svptrue_b32(), a, b));
```
Cover cases where atleast one of AND and XOR node is of _u form or is a
normal LLVM AND/XOR node.
Also, combine sve.and.u and sve.eor(.z) when predicate for sve.and.u
matches that of sve.eor(.z) or the predicate of sve.eor(.z) is an
all-active predicate.
Cover all SVE integer widths and cover the following symmetric case:
```
return sveor_u32_x(svptrue_b32(), a, svand_u32_x(svptrue_b32(), a, b));
```
[Clang][AArch64] Give FPM scale helper declarations C linkage in arm_vector_types.h (#238025)
Fixes 22287cb048390352d95d8a4925dfb9f96835444d.
#227722 defined `__arm_set_fpm_lscale`, `__arm_set_fpm_nscale`, and
`__arm_set_fpm_lscale2` as `TargetLibBuiltin` with `RequireDeclaration`
and replaced their `static __inline__` definitions in
`arm_vector_types.h` with plain declarations.
Because `TargetLibBuiltin` lazily creates an implicit declaration with C
language linkage in C++, including `<arm_neon.h>` inside an explicit
`extern "C++" { ... }` block (commonly hit on Windows ARM64 where UCRT's
`wchar.h` includes `<arm_neon.h>`) fails with `error: declaration of
'__arm_set_fpm_lscale' has a different language linkage`.
This PR wraps the three declarations in `extern "C"` under C++ to match
the builtin linkage (consistent with `arm_acle.h` and `arm_sve.h`). This
is a language linkage issue, separate from the `uint64_t` type mismatch
in #234780.
[AArch64] NFC: Add pre-commit tests for SVE AND-XOR/XOR-AND combining
Add tests for patterns like AND(a, XOR(a, b)) and XOR(a, AND(a, b))
that could be replaced by `BIC(a, b)`.
Cover various cases involving plain LLVM AND/XOR instructions and
sve.and/eor[.u/z] intrinsics.
Add negative test cases where the instruction sequence can't be replaced
by BIC.
[mlir][NFC] Remove includes provided by generated declarations and definitions
#236155 and #238735 made the generated declarations and definitions of
ops, attributes, types and interfaces include the core MLIR headers they
require. Includes that headers and source files only had for the
generated code are therefore redundant. This removes them in MLIR, Flang
and ClangIR.
Includes of headers that the hand-written code uses directly are kept,
even when the generated code includes them as well.
Co-authored-by: Claude <noreply at anthropic.com>
[SPIR-V] Preserve float type of undef operands in G_CONCAT_VECTORS (#238510)
Untyped undef padding fell back to an integer vector, which spirv-val
rejects
[flang][OpenMP] Extract the declare-reduction op naming into helpers
genOpenMPDeclareReductionImpl computed the op name for each listed type with
an 88-line common::visit nested inside its per-type loop, with the inner
visit over the defined-operator alternatives reaching four levels deep.
Lift it out into three file-static helpers: getDeclareReductionOpName
dispatches on the reduction identifier, and getDefinedOperatorOpName and
getProcedureDesignatorOpName handle the two alternatives. The
named-reduction case is now plain straight-line code rather than a lambda
body, and the deepest statements move from roughly column 38 to column 12.
The bodies move verbatim; the comments move with them, re-wrapped to fill 80
columns now that they are no longer indented for a deeply nested lambda.
No functional change.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
