LLVM/project cabb972mlir/include/mlir/Dialect/SPIRV/IR SPIRVTosaOps.td

[mlir][spirv] Mark several SPIR-V TOSA Ext Inst ops as NoMemoryEffects (#191814)

Initially such ops were marked Pure wrongly since they could overflow or
underflow the accumulator and result in undefined behavior.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+16-4mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
+16-41 files

LLVM/project 3fe0bdfllvm/docs LFI.rst, llvm/lib/Target/AArch64 AArch64InstrInfo.cpp

[LFI][AArch64] Add AArch64 LFI rewrites for system instructions (#186896)

This builds on the MCLFIRewriter infrastructure to add the
AArch64-specific LFI rewriter, which rewrites AArch64 instructions for
LFI sandboxing during the assembler step.

The initial rewriter handles system instructions: system calls, thread
pointer accesses, and also rejects modifications to reserved registers.
DeltaFile
+210-0llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
+72-36llvm/docs/LFI.rst
+81-0llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.h
+45-0llvm/test/MC/AArch64/LFI/reserved.s
+25-0llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+13-0llvm/test/MC/AArch64/LFI/tp.s
+446-363 files not shown
+465-369 files

LLVM/project 444ffdellvm/lib/DebugInfo/DWARF DWARFDebugFrame.cpp

[llvm][DebugInfo] formatv in DWARFDebugFrame (#191984)

This relates to #35980.
DeltaFile
+28-20llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
+28-201 files

LLVM/project 90ccb1cllvm/lib/DebugInfo/DWARF DWARFDebugLine.cpp

[llvm][DebugInfo] formatv in DWARFDebugLine (#191986)

This relates to #35980.
DeltaFile
+34-33llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
+34-331 files

LLVM/project 7c3b499llvm/lib/DebugInfo/DWARF DWARFDebugMacro.cpp

[llvm][DebugInfo] formatv in DWARFDebugMacro (#191987)

This relates to #35980.
DeltaFile
+11-7llvm/lib/DebugInfo/DWARF/DWARFDebugMacro.cpp
+11-71 files

LLVM/project 1b804e2clang/include/clang/Analysis/Analyses/LifetimeSafety Facts.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

[LifetimeSafety] Track origins through std::function (#191123)

1. Recognizes `std::function` and `std::move_only_function` as types
that can carry origins from a wrapped lambda's captures, propagating
origins through both construction and assignment.
2. Adds a kill-only mechanism (i.e., a new `KillOriginFact`) to clear
old loans when the RHS has no origins.

Fixes #186009
DeltaFile
+107-0clang/test/Sema/warn-lifetime-safety.cpp
+28-3clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+21-3clang/test/Sema/warn-lifetime-safety-suggestions.cpp
+20-0clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
+14-0clang/test/Sema/Inputs/lifetime-analysis.h
+13-0clang/test/Sema/warn-lifetime-safety-dangling-field.cpp
+203-69 files not shown
+260-615 files

LLVM/project 06c1aa3llvm/docs Coroutines.rst, llvm/include/llvm/Transforms/Coroutines CoroShape.h

[CoroEarly][IR] Clarify semantic of llvm.coro.end (#191752)

We introduced a workaround for the following pattern in #139243:
``` LLVM
define void @fn() presplitcoroutine {
  %__promise = alloca ptr, align 8
  ...

coro.ret:
  call void @llvm.coro.end(ptr null, i1 false, token none)
  store ptr null, ptr %__promise, align 8
  ret void
}
```
where DSE considers `__promise` dead after the return and eliminates the
store, leading to a miscompilation.

However, after #151067, the problematic pattern is gone. And it
currently looks like:

    [17 lines not shown]
DeltaFile
+0-31llvm/test/Transforms/Coroutines/gh105595.ll
+0-31llvm/lib/Transforms/Coroutines/CoroEarly.cpp
+10-8llvm/docs/Coroutines.rst
+2-15llvm/lib/Transforms/Coroutines/Coroutines.cpp
+7-10llvm/test/Transforms/Coroutines/coro-debug.ll
+6-8llvm/include/llvm/Transforms/Coroutines/CoroShape.h
+25-1036 files

LLVM/project a044447llvm/test/CodeGen/SPIRV/hlsl-resources cbuffer.ll

[NFC][SPIR-V] Fix cbuffer.ll test to pass spirv-val validation (#191940)

Mark `main()` function as a compute shader entry point with numthreads
attribute so the test produces valid SPIR-V

related to https://github.com/llvm/llvm-project/issues/190736
DeltaFile
+4-1llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer.ll
+4-11 files

LLVM/project 1a47551mlir/lib/IR BuiltinDialectBytecode.cpp

clang-format
DeltaFile
+5-10mlir/lib/IR/BuiltinDialectBytecode.cpp
+5-101 files

LLVM/project bdec04fllvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-add-sdot-i8-i16.ll partial-reduce-add-sdot-i16-i32.ll

[AArch64] Add new dot insts. to cost model (#189642)

This patch builds on #184659 and #184649 and adds cost modelling for new
dot instructions variants, codegened in those patches.
DeltaFile
+61-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-add-sdot-i8-i16.ll
+12-6llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+5-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-add-sdot-i16-i32.ll
+78-63 files

LLVM/project 8beed11clang/lib/Driver/ToolChains AMDGPU.cpp HIPAMD.cpp

[Driver][HIP] Do not default to `hidden` visibility for AMDGCNSPIRV (#191820)

SPIR-V cannot encode hidden for now, which leads to quirky errors. For
now we deal with this at run time, as part of JIT. Once SPIR-V learns
about `hidden` it'll be revisited.
DeltaFile
+3-1clang/lib/Driver/ToolChains/AMDGPU.cpp
+3-1clang/lib/Driver/ToolChains/HIPAMD.cpp
+6-22 files

LLVM/project fa720e7mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp, mlir/test/Dialect/Tosa canonicalize.mlir

[mlir][tosa] Optimize non-narrowing float casts (#191439)

Extend the existing NonNarrowingCastsOptimization to also cover casts
between floating point types f32, f16, bf16, f8E4M3FN and F8E5M2. Avoid
introducing direct casts between f8 types since those are not allowed in
TOSA.

Also expand the set of cases that are considering non-narrowing by only
checking if the cast we're trying to remove is non-narrowing. Example
i16 -> i32 -> i8 would have been rejected before, but it is now safely
converted to a single i16 -> i8 tosa.cast, since the behaviour should
identical for the entire input space.

Finally disallow the optimization in the case when the cast that we
would remove involves integer types of different signedness.

Signed-off-by: Ian Tayler Lessa <ian.taylerlessa at arm.com>
DeltaFile
+109-0mlir/test/Dialect/Tosa/canonicalize.mlir
+88-13mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+197-132 files

LLVM/project eb9a9b9mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Create and use utility to print shapes (#191774)

Follow up for #191300
DeltaFile
+16-16mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+16-161 files

LLVM/project 272122allvm/lib/Target/LoongArch LoongArchISelDAGToDAG.cpp

Fix a typo
DeltaFile
+1-1llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+1-11 files

LLVM/project 0756e59llvm/test/CodeGen/AArch64 sve-pred-selectop2.ll sve-pred-selectop3.ll

[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)

For some cores it is preferable to choose a destination predicate
register that does not match the governing predicate.

The hint is conservative in that it tries not to pick a callee-save
register if it's not already used/allocated for other purposes, as that
would introduce new spills/fills. Note that this might be preferable if
the instruction is executed in a loop, but it might also be less
preferable for small functions that have an SVE interface (p4-p15 are
caller-preserved).

It is enabled for all cores by default, but it can be disabled by adding
the `disable-distinct-dst-reg-cmp-match` feature. This feature can also
be added to specific cores if this behaviour is undesirable.
DeltaFile
+194-194llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
+130-130llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
+114-114llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
+205-0llvm/test/CodeGen/AArch64/sve-distinct-predicate-dst.ll
+66-66llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
+58-58llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
+767-56269 files not shown
+1,960-1,60575 files

LLVM/project 2332c5dllvm/lib/Transforms/Vectorize LoopVectorize.cpp LoopVectorizationPlanner.h, llvm/test/Transforms/LoopVectorize conditional-assignment.ll

[LV] Remove legacy selectVectorizationFactor and assert (NFCI) (#190838)

Almost all recipes now go through ::computeCost to properly compute
their costs using the VPlan-based cost model. There are currently no
known cases where the VPlan-based cost model returns an incorrect cost
vs the legacy cost model. I check the remaining open issues with reports
of the assertion triggering and in all cases the VPlan-based cost model
is more accurate, which is causing the divergence.

There are still some fall-back paths, mostly via precomputeCosts, but
those cannot be easily removed without triggering the assert, as the
VPlan-based cost model is more accurate for those cases. An example of
this is https://github.com/llvm/llvm-project/pull/187056.

Fixes https://github.com/llvm/llvm-project/issues/38575. 
Fixes https://github.com/llvm/llvm-project/issues/149651. 
Fixes https://github.com/llvm/llvm-project/issues/182646. 
Fixes https://github.com/llvm/llvm-project/issues/183739. 
Fixes https://github.com/llvm/llvm-project/issues/187523.

PR: https://github.com/llvm/llvm-project/pull/190838
DeltaFile
+0-346llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+7-8llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/x86-loopvectorize-costmodel.ll.expected
+0-9llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+3-3llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/loopvectorize-costmodel.test
+0-5llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+1-1llvm/test/Transforms/LoopVectorize/conditional-assignment.ll
+11-3721 files not shown
+12-3737 files

LLVM/project c838322libcxx/docs/Status Cxx2cIssues.csv, libcxx/include mdspan

[libc++] LWG4511: Inconsistency between the deduction guide of `std::mdspan` taking `(data_handle_type, mapping_type, accessor_type)` and the corresponding constructor (#191950)

No functional change; this only removes a redundant const qualifier.

Fixes: #189860
DeltaFile
+6-1libcxx/test/std/containers/views/mdspan/mdspan/deduction.pass.cpp
+1-1libcxx/include/mdspan
+1-1libcxx/include/__mdspan/mdspan.h
+1-1libcxx/docs/Status/Cxx2cIssues.csv
+9-44 files

LLVM/project dd034aellvm/lib/Target/X86 X86CompressEVEX.cpp, llvm/test/CodeGen/X86 evex-to-vex-compress.mir

[X86] Fix VPMOVPattern folding for extended registers (#191760)

Fixes a problem that tryCompressVPMOVPattern incorrectly folds
instruction using extended registers into VEX. Introduced relevant tests
in MIR.

AI Statement: I used AI to write the tests.
Fixes #191304
DeltaFile
+8-0llvm/test/CodeGen/X86/evex-to-vex-compress.mir
+3-0llvm/lib/Target/X86/X86CompressEVEX.cpp
+11-02 files

LLVM/project 08fb464llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 gfni-or-fold.ll

[AVX-512] Fix for disjoint-or-fold (VGF2P8AFFINEQB) (#190896)

Fixes #190502

Added implementation of helper combineOrWithGF2P8AFFINEQB and wired the logic with combineOrXorWithSETCC:

Fold: (GF2P8AFFINEQB(X, Y, Imm) or_disjoint SplatVal) -> GF2P8AFFINEQB(X, Y, Imm ^ SplatVal)

When OR is disjoint (no common bits), the splat constant can be folded directly into the GF2P8AFFINEQB immediate via XOR.
DeltaFile
+81-0llvm/test/CodeGen/X86/gfni-or-fold.ll
+32-0llvm/lib/Target/X86/X86ISelLowering.cpp
+113-02 files

LLVM/project d68e5e9mlir/include/mlir/Dialect/Transform/IR TransformDialect.td, mlir/include/mlir/Dialect/Transform/Interfaces TransformInterfaces.td

[mlir] transform dialect; add pre/post-condition type

Add a transform dialect type denoting additional invariants on payload
IR usable for pre/post-conditions of a transformation. The invariants
are defined as a list of attributes in the type parameter, where the
attribute implements the interface for invariant-checking. This allows
clients to factor out, explicify and deduplicate precondition
verification logic.

This required adding support for Transform dialect extensions injecting
attributes into the dialects similarly to how they already do this for
operations and types.

Co-authored-by: Tim Gymnich <tim at gymni.ch>
Co-authored-by: Martin Lücke <martin.luecke at amd.com>
Assisted-by: Claude Opus 4.3 / Cursor
DeltaFile
+82-0mlir/test/Dialect/Transform/normal-forms.mlir
+46-3mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
+48-0mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
+40-0mlir/lib/Dialect/Transform/IR/TransformTypes.cpp
+33-7mlir/lib/Dialect/Transform/IR/TransformDialect.cpp
+34-0mlir/include/mlir/Dialect/Transform/Interfaces/TransformInterfaces.td
+283-1010 files not shown
+407-1016 files

LLVM/project 4b4aa3bllvm/include/llvm/CodeGen SDPatternMatch.h, llvm/unittests/CodeGen SelectionDAGPatternMatchTest.cpp

[DAG] Add funnel-shift matchers to SDPatternMatch (Fixes #185880) (#186593)

Add new SelectionDAG pattern matchers for funnel shifts:
- m_FShL and m_FShR as ternary wrappers for ISD::FSHL/ISD::FSHR
- m_FShLLike and m_FShRLike to match:
-- direct FSHL/FSHR nodes
-- ROTL/ROTR equivalents (binding both X and Y to the same rotate operand)
-- OR(SHL(X, C), SRL(Y, BW - C)) forms (including commuted OR)

Also add unit tests covering positive and negative cases for:
- direct funnel-shif matching
- rotate equivalence matching
- OR-based funnel-shift-like patterns

Fixes #185880
DeltaFile
+91-0llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+86-0llvm/include/llvm/CodeGen/SDPatternMatch.h
+177-02 files

LLVM/project c61b070clang/lib/AST/ByteCode Compiler.cpp

[clang][bytecode] Use `CopyArray` for primitive ArrayInitLoops (#191956)

This reduces the bytecode output for the copy constructor of a struct
such as:

```c++
struct Buffer {
  struct {
    char D[N];
  } V;

  Buffer() = default;
};
```
from
```
Buffer<5>::(unnamed struct)::(unnamed struct at array.cpp:873:3) 0x7d38d2de3f80
frame size: 104
arg size:   96

    [62 lines not shown]
DeltaFile
+15-4clang/lib/AST/ByteCode/Compiler.cpp
+15-41 files

LLVM/project 6f1a17fllvm/lib/Target/LoongArch LoongArchISelDAGToDAG.cpp LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction add.ll sub.ll

[LoongArch] Select V{ADD,SUB}I for operations with negative splat immediates

Currently, vector add/sub with a negative splat immediate is lowered as a
vector splat followed by a register-register add, e.g.:

```
vrepli.b $vr1, -1
vadd.b   $vr0, $vr0, $vr1
```

This misses the opportunity to use the more efficient V{ADD,SUB}I instruction
with a positive immediate.

This patch introduces `selectVSplatImmNeg` to detect negative splat
immediates whose negated value fits in a 5-bit unsigned immediate. New
patterns `(Pat{Vr,Vr}Nimm5)` are added to match:

```
add v, splat(-imm)  -->  vsubi v, v, imm

    [7 lines not shown]
DeltaFile
+22-0llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+17-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+5-10llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+5-10llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+5-10llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+5-10llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+59-402 files not shown
+74-408 files

LLVM/project 6b778e6llvm/test/CodeGen/LoongArch/lasx/ir-instruction add.ll sub.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction add.ll sub.ll

[LoongArch][NFC] Add tests for add/sub with negative splat immediates
DeltaFile
+66-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+66-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+66-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+66-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+264-04 files

LLVM/project 78cd6c9clang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

[LifetimeSafety] Detect use-after-scope through fields in member calls (#191731)

Add `UseFact`s for field origins when calling instance methods.

Fixes #182945

---------

Co-authored-by: Utkarsh Saxena <usx at google.com>
DeltaFile
+67-0clang/test/Sema/warn-lifetime-safety.cpp
+33-0clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+15-0clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+4-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+119-04 files

LLVM/project 8c9ce12clang/lib/AST/ByteCode Disasm.cpp Program.h

[clang][bytecode] Use qualified name in `Function::dump()` (#191958)
DeltaFile
+8-1clang/lib/AST/ByteCode/Disasm.cpp
+2-0clang/lib/AST/ByteCode/Program.h
+10-12 files

LLVM/project 6a88394clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded vpairo.c vpaire.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded vpairo.c vpaire.c

[RISCV] Add Zvzip intrinsics (#186342)

In the RVV Clang builtins generator, a new prototype descriptor
`d` was added to represent vectors with `2 x LMUL`.

The `.ll` tests were generated by LLM and I have reviewed them.

And the .c tests were generated by
https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/431.
DeltaFile
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
+2,189-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
+2,189-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
+15,270-047 files not shown
+44,143-653 files

LLVM/project 0206ae0mlir/include/mlir/IR BuiltinDialectBytecode.td, mlir/lib/IR BuiltinDialectBytecode.cpp

[mlirbc] Add AffineMap serialization support

Add binary bytecode encoding for AffineMapAttr, replacing the textual fallback.
AffineMap is encoded as numDims, numSymbols, numResults, followed by the result
expressions.  Where each expression, AffineExpr, is encoded as a recursive tree
with a VarInt kind tag followed by kind-specific data.
DeltaFile
+164-3mlir/lib/IR/BuiltinDialectBytecode.cpp
+10-0mlir/include/mlir/IR/BuiltinDialectBytecode.td
+174-32 files

LLVM/project 4ea9b49clang-tools-extra/clangd TidyFastChecks.inc

[clangd] Update TidyFastChecks.inc via TidyFastChecks.py (#191096)

Updated
[TidyFastCheck.inc](https://github.com/llvm/llvm-project/blob/main/clang-tools-extra/clangd/TidyFastChecks.inc#L1)
that has been stale for a while using this
[script](https://github.com/llvm/llvm-project/blob/main/clang-tools-extra/clangd/TidyFastChecks.py),
as discussed in #190531. In the thread, there was some conversation on
the limitations of doing this manually at every new release (adding the
script to the release checklist would definitely help) but it seems like
this is the only low-risk solution for now.
DeltaFile
+401-340clang-tools-extra/clangd/TidyFastChecks.inc
+401-3401 files

LLVM/project b8b5962llvm/lib/CodeGen InsertCodePrefetch.cpp

[NFC] clang-format llvm/lib/CodeGen/InsertCodePrefetch.cpp. (#191959)
DeltaFile
+4-3llvm/lib/CodeGen/InsertCodePrefetch.cpp
+4-31 files