[RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)
This enables MachineVerifier and MachineIR printing support for these
operands.
[compiler-rt] follow-up to 166837, rename COMPILER_RT_FORCE_TEST_BUILTINS_DIR to COMPILER_RT_TEST_BUILTINS_DIR (#171741)
Co-authored-by: David Tenty <daltenty at ibm.com>
[RISC-V][MC] Fix tied operand register class mismatch in P-extension
I have a change to validate the operand classes emitted in the AsmParser
and that caused llvm/test/MC/RISCV/rv32p-valid.s to fail due to the rd_wb
register using a different register class from rd:
`PWADDA_H operand 1 register X6 is not a member of register class GPRPair`
This happens because tablegen's AsmMatcherEmitter emits code to literally
copy over the tied registers and does not feed them through the equivalent
of RISCVAsmParser::validateTargetOperandClass() which would allow adjusting
these operand classes.
Ideally we would handle this in tablegen (or at least add an error), but
the tied operand handling logic is rather complex and I don't understand
it yet. For now just update the rd register class to match rd_wb.
Pull Request: https://github.com/llvm/llvm-project/pull/171738
[TableGen] Replace reachable assertion with error in *ByHwMode
Having duplicate mode entries previously asserted (or silently replaced
the last value with a new one in release builds). Report an error with
a helpful message instead.
Pull Request: https://github.com/llvm/llvm-project/pull/171715
Add a _regexp-break-add and some more tests for the b alias. (#171236)
This commit leaves "b" aliased to the old _regexp-break for now. The two
variants are identical except that `_regexp-break` allows you to say:
`(lldb) b <unrecognized_input>
`
which gets translated to:
`break set <unrecognized_input>
`
So switching people to `_regexp-break-add` would be a surprising
behavior change. It would be wrong for `_regexp_break-add` have one
branch that call `break set`, so to avoid surprise, I'll add the command
and let people who are playing with `break add` instead of `break set`
can set the alias to the new one by hand for now.
[AArch64] Restrict TBI to ignore top 4 bits for Darwin targets.
In order to allow arm64 code to run on MTE environments, we need to make the
compiler only assume the top 4 bits can be ignored as MTE occupies the lower 4.
rdar://164645323
[Clang][counted_by] Correct signed counted_by values (#171260)
If the 'counted_by' value is signed, we will incorrectly allow accesses
when the value is negative. This has obvious bad effects as it will
allow accessing a huge swath of unallocated memory.
Also clarify and rearrange the parameters to make them more
perspicuous.
Fixes: #170987.
[lldb] fix failing tests due to CI diagnostics rendering (#171685)
This patch fixes issues introduced by
https://github.com/llvm/llvm-project/pull/171491 when running tests in
CI.
The shell tests expect certain characters when matching diagnostics.
With https://github.com/llvm/llvm-project/pull/171491, those characters
can either be Unicode specific characters or their ASCII equivalent. The
tests were always expecting the ASCII version. This patch fixes this by
using a regex to match one or the other.
[SelectionDAG] Salvage debuginfo when combining load and sext instrs. (#169779)
SelectionDAG uses the DAGCombiner to fold a load followed by a sext to a
load and sext instruction. For example, in x86 we will see that
```
%1 = load i32, ptr @GlobArr
#dbg_value(i32 %1, !43, !DIExpression(), !52)
%2 = sext i32 %1 to i64, !dbg !53
```
is converted to:
```
%0:gr64_nosp = MOVSX64rm32 $rip, 1, $noreg, @GlobArr, $noreg, debug-instr-number 1, debug-location !51
DBG_VALUE $noreg, $noreg, !"Idx", !DIExpression(), debug-location !52
```
The `DBG_VALUE` needs to be transferred correctly to the new combined
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[mlir][acc] Introduce acc loop tiling pass (#171692)
This pass implements the OpenACC loop tiling transformation for acc.loop
operations that have the tile clause (OpenACC 3.4 spec, section 2.9.8).
The tile clause specifies that the iterations of the associated loops
should be divided into tiles (rectangular blocks). The pass transforms a
single or nested acc.loop with tile clauses into a structure of "tile
loops" (iterating over tiles) containing "element loops" (iterating
within tiles).
For example, tiling a 2-level nested loop with tile(T1, T2):
```
// Before tiling:
acc.loop tile(T1, T2) control(%i, %j) = ...
// After tiling:
acc.loop control(%i) step (s1*T1) { // tile loop 1
acc.loop control(%j) step (s2*T2) { // tile loop 2
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[VPlan] Strip stray whitespace when printing VPWidenSelectRecipe. (NFCI)
printFlags takes care of inserting the correct amount of spaces,
depending on whether there are flags to print or not.
