LLVM/project 8a0c070libcxx/include __hash_table, libcxx/include/ext hash_map

[libc++] Revert recent changes to __hash_table and ext/hash_map (#189427)

This reverts commits 30084d74765c and 5b8c17580482. The second commit
was landed without proper review: not by fault of the submitter, but
because I mistakenly thought this was modifying something else entirely
that is unsupported. The first commit must also be reverted because it
is a breaking change without the second commit.

This corresponds to PRs #183223 and #188660, see those for more details.
DeltaFile
+11-7libcxx/include/ext/hash_map
+0-16libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-16libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+4-12libcxx/include/__hash_table
+1-5libcxx/test/extensions/gnu/hash_map/copy.pass.cpp
+16-565 files

LLVM/project 42cc454lld/ELF SyntheticSections.cpp InputSection.cpp, lld/test/ELF merge-piece-oob.s

[ELF] Optimize binary search in getSectionPiece (#187916)

Two optimizations to make getSectionPiece O(1) for common cases:

1. For non-string fixed-size merge sections, use direct computation
   (offset / entsize) instead of binary search.

2. Pre-resolve piece indices for non-section Defined symbols during
   splitSections. The piece index and intra-piece offset are packed
   into Defined::value as ((pieceIdx+1) << 32) | intraPieceOffset,
   replacing repeated binary searches (MarkLive, includeInSymtab,
   getRelocTargetVA) with a single upfront resolution.

On x86-64, references to mergeable strings use local labels:

    leaq .LC0(%rip), %rax  # R_X86_64_PC32 .LC0-4

The relocations use non-section symbols and benefit from optimization 2.
On many other targets (e.g. AArch64), the addend is 0 and the assembler

    [4 lines not shown]
DeltaFile
+20-0lld/ELF/SyntheticSections.cpp
+12-0lld/ELF/InputSection.cpp
+6-1lld/ELF/InputSection.h
+1-1lld/test/ELF/merge-piece-oob.s
+39-24 files

LLVM/project 1ec7e86lld/test/COFF lto-libcall-archive-bitcode.test, lld/test/ELF/lto libcall-archive-bitcode.test

Revert "[LTO][LLD] Prevent invalid LTO libfunc transforms (#164916)"

This reverts commit 8b21fe60b43fe358321bca904ae307406725c002.

to unblock bot: https://lab.llvm.org/buildbot/#/builders/67/builds/1196
DeltaFile
+19-52llvm/lib/LTO/LTO.cpp
+0-56lld/test/wasm/lto/libcall-archive-bitcode.ll
+0-54lld/test/ELF/lto/libcall-archive-bitcode.test
+0-51lld/test/COFF/lto-libcall-archive-bitcode.test
+0-35llvm/test/LTO/Resolution/X86/libcall-in-thin-link.ll
+0-34llvm/test/LTO/Resolution/X86/libcall-in-tu.ll
+19-28219 files not shown
+52-48825 files

LLVM/project 8e20a6dllvm/docs ReleaseNotes.md, llvm/lib/Target/AArch64 AArch64TargetObjectFile.cpp AArch64TargetObjectFile.h

[AArch64] Support TLS variables in debug info (#146572)

This adds an implementation of getDebugThreadLocalSymbol for AArch64 by
using AArch::S_DTPREL.

Fixes #83466
DeltaFile
+30-5llvm/test/DebugInfo/AArch64/tls-at-location.ll
+11-4llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
+5-0llvm/docs/ReleaseNotes.md
+3-0llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
+49-94 files

LLVM/project 14ce208lld/ELF/Arch AArch64.cpp, lld/test/ELF aarch64-tls-dtprel.s

[LLD][AArch64] Handle R_AARCH64_TLS_DTPREL64 in non-alloc sections (#183962)

Clang plan to emit R_AARCH64_TLS_DTPREL64 in .debug_info (see PR
#146572). LLD currently fails to recognize this relocation.

This prevent the debugger from correctly locating TLS variables when
using the DWARF DW_OP_GNU_push_tls_address or DW_AT_location with DTPREL
offsets.

This patch adds support for R_AARCH64_TLS_DTPREL64, adds its mapping to
R_DTPREL.
DeltaFile
+23-0lld/test/ELF/aarch64-tls-dtprel.s
+5-0lld/ELF/Arch/AArch64.cpp
+28-02 files

LLVM/project e1aef5ellvm/lib/Target/X86 X86CompressEVEX.cpp, llvm/test/CodeGen/X86/apx compress-evex-negative-nf.mir

[X86][APX] Remove NF entries in X86CompressEVEXTable (#189308)

NF (No-Flags) instructions should not compress to non-NF instructions,
as this would incorrectly modify flags behavior. The compression table
is only intended for encoding optimizations that preserve semantics.

This removes the incorrect NF entries that could have led to
miscompilation if the compression logic were applied.
DeltaFile
+123-0llvm/test/CodeGen/X86/apx/compress-evex-negative-nf.mir
+0-24llvm/test/TableGen/x86-instr-mapping.inc
+7-2llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+4-0llvm/lib/Target/X86/X86CompressEVEX.cpp
+134-264 files

LLVM/project 227edfbllvm/lib/CodeGen CodeGenPrepare.cpp, llvm/lib/Transforms/Utils BypassSlowDivision.cpp BreakCriticalEdges.cpp

[CodeGenPrepare][NFC] Reland: Update the dominator tree instead of rebuilding it (#179040)

The original differential revision is https://reviews.llvm.org/D153638

Reverted in
https://github.com/llvm/llvm-project/commit/f5b5a30858f32e237636acd296b6d0f87c1dfe97
because of causing a clang crash.

This patch relands it with the crash fixed. Call `DTU->flush()` in each
iteration of `while (MadeChange)`
loop, flush all awaiting BasicBlocks deletion, and prevent iterator
invalidation.
DeltaFile
+147-110llvm/lib/CodeGen/CodeGenPrepare.cpp
+48-32llvm/test/CodeGen/PowerPC/atomics-regression.ll
+49-19llvm/lib/Transforms/Utils/BypassSlowDivision.cpp
+30-30llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
+30-30llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll
+16-2llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
+320-2234 files not shown
+340-23310 files

LLVM/project 9de3ebdllvm/lib/Target/RISCV RISCVISelLowering.cpp

[RISCV] Avoid creating unnecessary node. Add missing break to switch. NFC (#189511)
DeltaFile
+5-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+5-11 files

LLVM/project ac12b32llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-reduction-formation.ll

[RISCV] Check hasVInstructions() rather than hasStdExtZbb() for UMAX/UMIN/SMAX/SMIN combines. (#189506)

The combines are related to combining min/max with vector reductions. I
don't think it matters if Zbb is enabled.

I did not merge this with other hasVInstructions() because I have a P
extension patch coming after this that will need to separate them.
DeltaFile
+2-2llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
+2-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+4-32 files

LLVM/project 35f8945mlir/include/mlir/Interfaces SideEffectInterfaces.h, mlir/lib/Transforms CSE.cpp

[mlir] Made DefaultResource the root of memory resource hierarchy. (#187423)

DefaultResource is made the root of the memory resource hierarchy,
so now it overlaps with all resources.

RFC:
https://discourse.llvm.org/t/rfc-mlir-memory-region-hierarchy-for-mlir-side-effects/89811/32
DeltaFile
+39-7mlir/test/Transforms/cse.mlir
+19-9mlir/lib/Transforms/CSE.cpp
+23-0mlir/test/Analysis/test-alias-analysis-modref.mlir
+13-8mlir/unittests/Interfaces/SideEffectInterfacesTest.cpp
+16-0mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+10-3mlir/include/mlir/Interfaces/SideEffectInterfaces.h
+120-272 files not shown
+136-278 files

LLVM/project 47e3f42llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes BottomUpVec.cpp

Reapply "[SandboxVec][VecUtils] Lane Enumerator (#188355)"

This reverts commit c93049ef504f942af0f884ce8a5efc21df21d131.
DeltaFile
+58-0llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+31-0llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+2-11llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
+91-113 files

LLVM/project b255e78lldb/include/lldb/Target Process.h

[lldb] Fix copy-paste error in SetPrivateRunLockToRunning (#189322)

SetPrivateRunLockToRunning incorrectly delegated to
SetPrivateRunLockToStopped instead of SetPrivateRunLockToRunning,
causing the private run lock to never transition to the running state on
process resume.

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
DeltaFile
+1-1lldb/include/lldb/Target/Process.h
+1-11 files

LLVM/project 96bd7b6llvm/include/llvm/CodeGen TargetLowering.h BasicTTIImpl.h, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp LegalizeDAG.cpp

[CodeGen] Add additional params to `TargetLoweringBase::getTruncStoreAction` (#187422)

The truncating store analogue of #181104.

Adds `Alignment` and `AddrSpace` parameters to
`TargetLoweringBase::getTruncStoreAction` and dependents, and introduces
a `getCustomTruncStoreAction` hook for targets to customize legalization
behavior using this new information.

This change is fully backwards compatible from the target's point of
view, with `setTruncStoreAction` having identical functionality. The
change is purely additive.
DeltaFile
+41-15llvm/include/llvm/CodeGen/TargetLowering.h
+15-9llvm/lib/Target/X86/X86ISelLowering.cpp
+14-8llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+10-5llvm/include/llvm/CodeGen/BasicTTIImpl.h
+7-4llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+5-3llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+92-448 files not shown
+117-5614 files

LLVM/project c5fc4b2llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+19-29llvm/lib/Target/AArch64/AArch64SystemOperands.td
+5-6llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+6-0llvm/test/MC/AArch64/armv9a-tlbip.s
+30-353 files

LLVM/project 8e20e40llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+19-29llvm/lib/Target/AArch64/AArch64SystemOperands.td
+5-6llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+4-0llvm/test/MC/AArch64/armv9a-tlbip.s
+28-353 files

LLVM/project 12319b3clang/lib/CodeGen CGCall.cpp, clang/test/CodeGenCXX microsoft-vector-deleting-dtors.cpp microsoft-vector-deleting-dtors2.cpp

[Clang] More aggressively mark this* dead_on_return in destructors (#183347)

Now also mark the this pointer dead_on_return for classes with a
non-zero number of base classes. We saw a limited number of failures
internally due to this change, so it doesn't seem like there are too
many problems with real world deployment.
DeltaFile
+45-45clang/test/OpenMP/for_reduction_codegen_UDR.cpp
+8-8clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
+6-6clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
+3-6clang/lib/CodeGen/CGCall.cpp
+4-4clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
+1-1clang/test/CodeGenCXX/destructor-dead-on-return.cpp
+67-701 files not shown
+68-717 files

LLVM/project 0e7f715clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.h, clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.cpp

address comments
DeltaFile
+90-21clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.cpp
+0-96clang/unittests/ScalableStaticAnalysisFramework/Analyses/MockSerialization.h
+30-62clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+6-63clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.h
+126-2424 files

LLVM/project b85492bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.sudot8.ll llvm.amdgcn.sudot4.ll

AMDGPU/GlobalISel: RegBankLegalize rules for sudot4/sudot8 (#189104)
DeltaFile
+14-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
+14-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+32-23 files

LLVM/project b15f94ellvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+19-29llvm/lib/Target/AArch64/AArch64SystemOperands.td
+3-5llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+2-0llvm/test/MC/AArch64/armv9a-tlbip.s
+24-343 files

LLVM/project 9887cd6llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Simplify logic after suggestions from Marian
DeltaFile
+13-10llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+13-101 files

LLVM/project 9306eebllvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

[AArch64][llvm] Gate some `tlbip` insns with +tlbid or +d128

Change the gating of `tlbip` instructions containing `*E1IS*`, `*E1OS*`,
`*E2IS*` or `*E2OS*` to be used with `+tlbid` or `+d128`. This is because
the 2025 Armv9.7-A MemSys specification says:

```
  All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
  that are currently dependent on FEAT_D128 are updated to be dependent
  on FEAT_D128 or FEAT_TLBID
```
DeltaFile
+259-0llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s
+66-66llvm/test/MC/AArch64/armv9a-tlbip.s
+20-0llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+15-5llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+360-714 files

LLVM/project f7d1309llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! More simplification
DeltaFile
+413-443llvm/test/MC/AArch64/armv9a-tlbip.s
+1-15llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+7-9llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+421-4673 files

LLVM/project a425b7cllvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Don't use ExtraRequires. Instead, set a boolean in TLBITableBase
DeltaFile
+27-22llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+17-1llvm/lib/Target/AArch64/AArch64SystemOperands.td
+7-7llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+51-303 files

LLVM/project 9214a07llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! More optimisations
DeltaFile
+10-11llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+7-6llvm/lib/Target/AArch64/AArch64SystemOperands.td
+1-8llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+18-253 files

LLVM/project 68dba8cllvm/test/MC/AArch64 tlbip-tlbid-or-d128.s armv9a-tlbip.s

fixup! Fix using Marian's suggestion
DeltaFile
+0-259llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s
+160-0llvm/test/MC/AArch64/armv9a-tlbip.s
+160-2592 files

LLVM/project 8ca1cb7llvm/lib/Target/AArch64 AArch64SystemOperands.td

[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (part 2) (#189503)

(This is the change message for 306e86be5, which GitHub unhelpfully discarded
when I enabled "auto-merge" when all tests had passed. It merged my change
and didn't merge the detailed commit message which I had carefully written(!)

So this is an NFC change, for those in the future looking for the lost message,
which explains the changes in 306e86be5)

-------------

Correct the `TLBI` system operand definitions so the emitted aliases are
generated from a single data table per feature group. The TLBI data is now
written once as anonymous `TLBI<...>` entries inside a defvar list, and we
iterate over it with a foreach to define those entries.

Hopefully this is clearer and more future-proof, since it is a complex set of
interactions between `tlbi`/`tlbip` with `*nXS` variants, and differing gating.


    [7 lines not shown]
DeltaFile
+1-1llvm/lib/Target/AArch64/AArch64SystemOperands.td
+1-11 files

LLVM/project 89d5d50clang/lib/CIR/CodeGen CIRGenBuiltin.cpp, llvm/include/llvm/IR Intrinsics.h

[NFC][LLVM] Rename `IITDescriptor` fields to confirm to LLVM CS (#189448)

Rename fields of `IITDescriptor` to conform to LLVM coding standards
naming conventions.
DeltaFile
+11-11llvm/include/llvm/IR/Intrinsics.h
+9-10llvm/lib/IR/Intrinsics.cpp
+3-3clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+23-243 files

LLVM/project 7b52dd6libc/src/__support/wchar CMakeLists.txt string_converter.h

[libc][NFC] Add LIBC_INLINE and cleanup wchar internals (#188856)

Some of the functions were missing LIBC_INLINE and some of the variable
names were less descriptive than I liked. This PR fixes both as well as
cleaning up dependencies.
DeltaFile
+10-2libc/src/__support/wchar/CMakeLists.txt
+5-5libc/src/__support/wchar/string_converter.h
+5-5libc/src/__support/wchar/mbrtowc.cpp
+4-6libc/src/__support/wchar/mbsnrtowcs.h
+5-4libc/src/__support/wchar/character_converter.h
+4-4libc/src/__support/wchar/wcrtomb.h
+33-262 files not shown
+36-298 files

LLVM/project 824af5cllvm/lib/Target/AArch64 AArch64SystemOperands.td

[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (part 2)

(This is the change message for 306e86be5, which GitHub unhelpfully lost
when I enabled "auto-merge" when all tests had passed. It merged my change
and didn't merge the commit message. So this is an NFC change, for those
in the future looking for the lost message, which explains the actual change)

-------------

Correct the `TLBI` system operand definitions so the emitted aliases are
generated from a single data table per feature group. The TLBI data is now
written once as anonymous `TLBI<...>` entries inside a defvar list, and we
iterate over it with a foreach to define those entries.

Hopefully this is clearer and more future-proof, since it is a complex set of
interactions between `tlbi`/`tlbip` with `*nXS` variants, and differing gating.

The gating was incorrect before. The gating is now:
  - `FeatureTLB_RMI`, `FeatureRME`, and `FeatureTLBIW` gate only TLBI aliases

    [6 lines not shown]
DeltaFile
+1-1llvm/lib/Target/AArch64/AArch64SystemOperands.td
+1-11 files

LLVM/project 974d663llvm/test/CodeGen/AMDGPU schedule-amdgpu-tracker-physreg.ll

Folded multiple RUN lines into one while maintaining debug msgs.
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
+4-41 files