LLVM/project 2162c16clang-tools-extra/clang-tidy/bugprone UnhandledCodePathsCheck.cpp, clang-tools-extra/clang-tidy/hicpp MultiwayPathsCoveredCheck.cpp

[clang-tidy] Rename hicpp-multiway-paths-covered to bugprone-unhandled-code-paths (#191625)

Part of the work in https://github.com/llvm/llvm-project/issues/183462.

Closes https://github.com/llvm/llvm-project/issues/183464.

Splitting the check into two more focused checks was considered during
discussion, but since clang-tidy does not support one-to-many aliases, a
single name covering both behaviors was chosen instead that is more
clear than `multiway-paths-covered`.

---------

Co-authored-by: Zeyi Xu <mitchell.xu2 at gmail.com>
DeltaFile
+468-0clang-tools-extra/test/clang-tidy/checkers/bugprone/unhandled-code-paths.cpp
+0-468clang-tools-extra/test/clang-tidy/checkers/hicpp/multiway-paths-covered.cpp
+0-175clang-tools-extra/clang-tidy/hicpp/MultiwayPathsCoveredCheck.cpp
+174-0clang-tools-extra/clang-tidy/bugprone/UnhandledCodePathsCheck.cpp
+3-93clang-tools-extra/docs/clang-tidy/checks/hicpp/multiway-paths-covered.rst
+95-0clang-tools-extra/docs/clang-tidy/checks/bugprone/unhandled-code-paths.rst
+740-73610 files not shown
+855-84116 files

LLVM/project 6983aa7llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values (#151372)

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32). This
avoids transferring the value through a GPR when storing.

Also remove the pre-legaliztion early-exit in `combineStoreValueFPToInt`
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 8272f19flang/lib/Semantics rewrite-parse-tree.cpp

[flang] Format rewrite-parse-tree.cpp, NFC

It's a 4-line change that makes the file invariant under clang-format.
DeltaFile
+4-4flang/lib/Semantics/rewrite-parse-tree.cpp
+4-41 files

LLVM/project 7456636flang/include/flang/Parser parse-tree.h, flang/lib/Lower/OpenMP OpenMP.cpp

[flang][OpenMP] Consistent names for non-executable directives, NFC (#196803)

Change
  OpenMPGroupprivate      -> OmpGroupprivateDirective
  OpenMPThreadprivate     -> OmpThreadprivateDirective
  OpenMPRequiresConstruct -> OmpRequiresDirective
  OpenMPUtilityConstruct  -> OmpUtilityDirective
DeltaFile
+13-11flang/include/flang/Parser/parse-tree.h
+10-10flang/lib/Parser/openmp-parsers.cpp
+10-10flang/lib/Semantics/resolve-directives.cpp
+7-7flang/lib/Semantics/check-omp-structure.cpp
+9-4flang/lib/Semantics/unparse-with-symbols.cpp
+6-6flang/lib/Lower/OpenMP/OpenMP.cpp
+55-4814 files not shown
+97-8820 files

LLVM/project 0b98750llvm/utils/gn/secondary/clang/unittests/DependencyScanning BUILD.gn

[gn] Make ClangDependencyScanningTests depend on Testing/Support (#196809)

Needed after ebb9a79cd370c.
DeltaFile
+1-0llvm/utils/gn/secondary/clang/unittests/DependencyScanning/BUILD.gn
+1-01 files

LLVM/project b2f37f4clang/lib/Format ContinuationIndenter.cpp, clang/unittests/Format AlignmentTest.cpp

clang-format: ensure ternary operands are aligned (#196697)

Set ParentState::AlignedTo for ternary operands.
DeltaFile
+16-0clang/lib/Format/ContinuationIndenter.cpp
+10-0clang/unittests/Format/AlignmentTest.cpp
+26-02 files

LLVM/project e7ea212libc/src/__support freetrie.h

[libc] Fix -Wshadow warnings in freetrie.h (#196529)
DeltaFile
+2-2libc/src/__support/freetrie.h
+2-21 files

LLVM/project 2491cc2clang/docs ReleaseNotes.rst, clang/include/clang/Basic Builtins.td

[clang] constexpr `__builtin_elementwise_{max,min}num`
DeltaFile
+42-80clang/lib/AST/ByteCode/InterpBuiltin.cpp
+52-0clang/test/Sema/constant-builtins-vector.cpp
+18-30clang/lib/AST/ExprConstant.cpp
+2-2clang/include/clang/Basic/Builtins.td
+3-0clang/docs/ReleaseNotes.rst
+117-1125 files

LLVM/project ad92988llvm/lib/Target/X86 X86InstrCompiler.td X86ISelLowering.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Cast atomic vectors in IR to support floats

This commit casts floats to ints in an atomic load during AtomicExpand to support
floating point types. It also is required to support 128 bit vectors in SSE/AVX.
DeltaFile
+98-288llvm/test/CodeGen/X86/atomic-load-store.ll
+15-0llvm/lib/Target/X86/X86InstrCompiler.td
+7-0llvm/lib/Target/X86/X86ISelLowering.cpp
+2-0llvm/lib/Target/X86/X86ISelLowering.h
+122-2884 files

LLVM/project a6344c0flang/include/flang/Parser parse-tree.h, flang/lib/Parser openmp-parsers.cpp

[flang][OpenMP] Consistent names for non-executable directives, NFC

Change
  OpenMPGroupprivate      -> OmpGroupprivateDirective
  OpenMPThreadprivate     -> OmpThreadprivateDirective
  OpenMPRequiresConstruct -> OmpRequiresDirective
  OpenMPUtilityConstruct  -> OmpUtilityDirective
DeltaFile
+13-11flang/include/flang/Parser/parse-tree.h
+10-10flang/lib/Parser/openmp-parsers.cpp
+10-10flang/lib/Semantics/resolve-directives.cpp
+7-7flang/lib/Semantics/check-omp-structure.cpp
+9-4flang/lib/Semantics/unparse-with-symbols.cpp
+6-6flang/lib/Semantics/check-omp-structure.h
+55-4814 files not shown
+97-8820 files

LLVM/project 3de25f5clang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeSafety.h, clang/include/clang/Basic DiagnosticGroups.td DiagnosticSemaKinds.td

[LifetimeSafety] Warn on incorrectly placed `[[clang::lifetimebound]]` attributes (#196144)

Adds new warning that is emitted when parameter is marked as
`[[clang::lifetimebound]]` but is not returned in one way or another
(tracked via `OriginEscapeFact`).

Closes #182935
DeltaFile
+89-0clang/test/Sema/warn-lifetime-safety-lifetimebound.cpp
+27-12clang/lib/Sema/SemaLifetimeSafety.h
+24-3clang/lib/Analysis/LifetimeSafety/Checker.cpp
+10-2clang/include/clang/Basic/DiagnosticGroups.td
+5-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+4-0clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
+159-171 files not shown
+160-177 files

LLVM/project 2b26355llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 horizontal-reduce-smax.ll horizontal-reduce-smin.ll

Revert "[VectorCombine] foldShuffleChainsToReduce - add support for partial vector reductions" (#196796)

Reverts llvm/llvm-project#195119 while reported assertions are investigated.
DeltaFile
+0-50llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+6-33llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+134-1156 files

LLVM/project c7ad740clang/docs ReleaseNotes.rst, clang/lib/AST ExprConstant.cpp

[clang] constexpr `__builtin_elementwise_{max,min}num`
DeltaFile
+42-80clang/lib/AST/ByteCode/InterpBuiltin.cpp
+52-0clang/test/Sema/constant-builtins-vector.cpp
+18-30clang/lib/AST/ExprConstant.cpp
+3-0clang/docs/ReleaseNotes.rst
+115-1104 files

LLVM/project 79fa36flldb/source/Plugins/Process/Linux NativeRegisterContextLinux.h, lldb/source/Plugins/Process/Utility NativeRegisterContextRegisterInfo.h

[lldb][Windows] Invalidate cached register values on thread stop (#192430)

Invalidate cached values in register context data structures on every
thread stop.

NativeRegisterContextRegisterInfo::InvalidateAllRegisters performs no
operation by default. Subclasses may override it to clear cached values
within their register context data structures whenever a thread stops.

This change intends to set up the necessary infrastructure to support
caching of the thread context in NativeRegisterContextWindows_arm64,
which will improve read performance. Currently, the thread context is
retrieved for every read or write operation.
DeltaFile
+3-0lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
+0-3lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
+3-0lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h
+6-33 files

LLVM/project af1d9cdllvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 horizontal-reduce-smax.ll horizontal-reduce-smin.ll

Revert "[VectorCombine] foldShuffleChainsToReduce - add support for partial v…"

This reverts commit a2942d472aac907af6f47f8c7658288609b6e1de.
DeltaFile
+0-50llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+6-33llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+134-1156 files

LLVM/project 43ef21fllvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32).
This avoids transferring the value through a GPR when storing.

Also remove the pre-legalization early-exit in combineStoreValueFPToInt
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 53ce9fbllvm/lib/CodeGen/SelectionDAG ExpandMulByConstant.cpp, llvm/test/CodeGen/Lanai constant_multiply.ll

[TargetLowering] Add target-independent mul-by-constant expansion algorithm
DeltaFile
+176-379llvm/test/CodeGen/RISCV/mul-expand.ll
+307-0llvm/lib/CodeGen/SelectionDAG/ExpandMulByConstant.cpp
+130-164llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+88-152llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+73-128llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+82-78llvm/test/CodeGen/Lanai/constant_multiply.ll
+856-90119 files not shown
+1,356-1,40825 files

LLVM/project 9a1da2elibcxx/include algorithm

address review comments
DeltaFile
+4-4libcxx/include/algorithm
+4-41 files

LLVM/project fd89940llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32).
This avoids transferring the value through a GPR when storing.

Also remove the pre-legalization early-exit in combineStoreValueFPToInt
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 6b9b1c2llvm/lib/Transforms/Utils LoopPeel.cpp, llvm/test/Transforms/LoopUnroll peel-last-iteration-load-widening.ll peel-last-iteration-load-widening-be.ll

Address comments 1
DeltaFile
+1,694-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening.ll
+0-616llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+117-79llvm/lib/Transforms/Utils/LoopPeel.cpp
+0-104llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+67-0llvm/test/Transforms/LoopUnroll/PowerPC/peel-last-iteration-load-widening-be.ll
+56-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-disabled.ll
+1,934-7994 files not shown
+1,948-80910 files

LLVM/project 719b58cllvm/include/llvm/Transforms/Utils LoopPeel.h UnrollLoop.h, llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopPeel] Peel last iteration to enable load widening

In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., i32) for
all other N-1 iterations.

Patterns such as:
```
  %a = load i8, ptr %p
  %b = load i8, ptr %p+1
  %c = load i8, ptr %p+2
  ...
  %p.next = getelementptr i8, ptr %p, 3
```

Can be transformed to:
```
  %wide = load i32, ptr %p  ; Read 4 bytes

    [9 lines not shown]
DeltaFile
+616-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+230-1llvm/lib/Transforms/Utils/LoopPeel.cpp
+104-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+19-13llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+7-1llvm/include/llvm/Transforms/Utils/LoopPeel.h
+2-1llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+978-166 files

LLVM/project c522ad0clang-tools-extra/clang-tidy/readability ContainerSizeEmptyCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix FP in readability-container-size-empty with compairing to unrelated type (#190535)

Fixes https://github.com/llvm/llvm-project/issues/162287.
DeltaFile
+74-0clang-tools-extra/test/clang-tidy/checkers/readability/container-size-empty.cpp
+19-9clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
+3-0clang-tools-extra/docs/ReleaseNotes.rst
+96-93 files

LLVM/project d66420cllvm/test/CodeGen/X86 call-range-attr.ll

update test

Co-Authored-By: nikic <github at npopov.com>
DeltaFile
+2-3llvm/test/CodeGen/X86/call-range-attr.ll
+2-31 files

LLVM/project ddfbf5dllvm/test/CodeGen/X86 call-range-attr.ll

add test
DeltaFile
+74-0llvm/test/CodeGen/X86/call-range-attr.ll
+74-01 files

LLVM/project 90c1ba7llvm/test/CodeGen/AMDGPU bit-op-reduce-width-known-bits.ll, llvm/test/CodeGen/X86 argument-range-attr.ll

update test
DeltaFile
+12-14llvm/test/CodeGen/X86/argument-range-attr.ll
+3-3llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
+15-172 files

LLVM/project 0ae088fllvm/test/CodeGen/X86 argument-range-attr.ll

add test
DeltaFile
+123-0llvm/test/CodeGen/X86/argument-range-attr.ll
+123-01 files

LLVM/project ccb3861llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp SelectionDAGBuilder.h

[SelectionDAG] Emit `AssertZext` for function argument range attributes
DeltaFile
+6-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+8-12 files

LLVM/project b3ff86bllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp SelectionDAGBuilder.cpp

[SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt
DeltaFile
+4-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+0-4llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+4-42 files

LLVM/project e535d2fllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 abds.ll

[DAGCombiner] Fix abs(add) to abdu miscompile in foldABSToABD
DeltaFile
+9-9llvm/test/CodeGen/X86/abds.ll
+1-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+10-122 files

LLVM/project 86ba661mlir/docs Tokens.md, mlir/lib/Conversion/AsyncToLLVM AsyncToLLVM.cpp

[mlir][IR] Add builtin `TokenTypeInterface`

type instead of type interface

add bytecode
DeltaFile
+104-0mlir/docs/Tokens.md
+60-0mlir/test/IR/token-type.mlir
+36-24mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
+18-17mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
+30-0mlir/test/lib/Dialect/Test/TestOps.td
+12-12mlir/test/Dialect/SparseTensor/invalid.mlir
+260-5324 files not shown
+365-9530 files