[CIR] Drop the stale callconv opt-out from two CIR tests (#225180)
`bitfields.cpp` was waiting on padded, packed and over-aligned record
shapes. `uncopyable-args.cpp` was waiting on parameters of an empty or
tag class. Both files now compile and check clean with the pass running,
so the `-fno-clangir-call-conv-lowering` opt-out and its TODO header are
removed and the tests exercise the pass as written. Neither file changes
a CHECK directive.
Assisted-by: Cursor / claude-opus-5
[flang][OpenMP] Annotate some directive and clause names
There are some directives that share the same spelling, but have
different functionality. The same is true for clauses. When getting
the upper-case name of such a directive or a clause, optionally
(and by default) add an annotation about the kind of the directive
or clause.
For example, a standalone ORDERED directive will be displayed as
"ORDERED (standalone)". This was already done, for this directive,
but not in all cases.
[AMDGPU] Fold fpround of fadd and fsub into v_mad/fma_mixlo and mixhi
MadFmaMixFP32Pats turns (fadd x, y) into (fma x, 1.0, y) and (fsub x, y)
into (fma (-y), 1.0, x) so the mix instructions absorb the operation along
with the f16 or bf16 source modifiers. MadFmaMixFP16Pats and
MadFmaMixFP16Pats_t16 only did this for fmul, so a rounded result still
needed a separate convert for a rounding the mix instructions perform
themselves.
Unlike the f32 patterns these do not require an operand to be an fpextend
of an f16, since an fpround on the result always removes the convert. The
rewrite is exact because the mix instructions round the f32 result again
when they write the 16-bit destination, so it stays f32_to_f16(fma(x, 1.0,
y)).
Assisted-by: Claude Code Opus 5
[clang][openmp] Avoid generating geometry for Bare kernels (#225185)
Don't use the information from num_teams or thread_limit clauses to
initialize the Kernel Environment of bare kernels. They only support one
single dimension and for NVIDIA (only) we generate a "nnvm.maxntid"
attribute which is incompatible with the multi-dimensional launch that
happens at runtime.
Fixes a regression introduced by #223772
[ORC] Rename ConnectionSpec's fd transport to socket:adopt (#225075)
A ConnectionSpec's transport field says what kind of thing the
descriptor names, and "fd" named a representation rather than a kind. It
also left no room for a pipe transport, which takes two descriptors and
a different server.
The transport becomes "socket", and adopting a handed-over handle
becomes an explicit "adopt" action rather than the absence of one. So
"tcp" names an endpoint to reach while "socket" names a handle already
held, and a spec states how the process came by its channel -- worth
spelling out, since "adopt", "connect" and "listen" do not carry the
same trust.
llvm-jitlink-executor takes "socket:adopt=<fd>" in place of "fd=<fd>"
and rejects any other action for that transport. The spec is an internal
handoff from llvm-jitlink in every in-tree use, so nothing else needed
updating. The class comment is rewritten around the same split and stops
describing transports that do not exist yet.
Matches the scheme the ORC runtime uses for its connector registry.
[ORC] Mangle NativeDylibManager CI names as C (#225096)
Flip the NativeDylibManager descriptors (instance + load/lookup) from
Verbatim to C, so their names carry the target's C mangling. Served by
the in-tree SimpleExecutorDylibManager; controller and executor mangle
the same specs and nothing else defines these names.
Also give the CreateFromExecutionSession test EPC the process triple,
matching the memory-manager fix (its bootstrap symbols were keyed with
the process triple but the EPC had an empty target triple).
[CIR] Regenerate CHECK lines for two callconv opt-out tests (#225189)
Neither `union.c` nor `paren-list-agg-init.cpp` is blocked by the
calling convention lowering pass any more, and both compile clean with
it running. Remove the `-fno-clangir-call-conv-lowering` opt-out and
update their CHECK lines. The coerced parameters and returns they now
pin match classic.
The bodies still differ, since CIR round-trips the record through a
fresh coerce slot, so those fragments move to the `LLVMCIR` and `OGCG`
prefixes the file already declares. Four `define` lines in
`paren-list-agg-init.cpp` wildcarded their return type and now pin it.
Assisted-by: Cursor / claude-opus-5
[AMDGPU][MC] Upstream gfx11/gfx12 true16 assembler test coverage (#223826)
Upstream new assembler test cases, covering true16 .l/.h operands and
op_sel
handling that had no upstream coverage.
[AMDGPU] Remove two VOPD instructions from gfx1250 and gfx13.
V_DUAL_DOT2ACC_F32_F16 and V_DUAL_DOT2ACC_F32_BF16 were removed from both
gfx1250 and gfx13.
Fixes LCOMPILER-2684.
[SLP] Reland: More accurately cost RISCV scalar splats (#224766)
Originally #213104, reverted due to assertion failure in cases of
reordered gather nodes.
Backends may have a fast path for splatting scalar operands (i.e. rather
than generating the splat vector, the vector instruction may be able to
take a scalar operand), for example RISCV `vfoo.vx` instructions. Pass a
hint to the TTI when costing the insert/shuffle sequence in such cases.
Fixes #212413.
Assisted By: Codex
[DebugInfo] Fix overflow in DWARFDebugLine::SectionParser (#224770)
Adding a DWARF64 unit length can overflow and wrap back into the
section, causing an infinite loop. Saturate the addition so an
overflowing offset fails the bounds check.
rdar://186810393
[NVPTX] Preserve volatile on atomic local loads and stores (#224719)
Local loads and stores discard atomic ordering during instruction
selection, but volatile accesses with acquire, release, or seq_cst
ordering also lose the volatile qualifier. Preserve volatile for all
valid load/store orderings when local volatile instructions are
supported. Follow up to #217764.
[WebKit Checkers] Trace through temporaries in tryToFindPtrOrigin (#224877)
RefPtr checking skips temporaries, reporting a path through any
temporary as unsafe. This is mostly correct, but not always. For
example, the following is a false positive:
// makeKey() returns a temporary
RefCountable* p = condition(makeKey()) ? guardian.ptr() : nullptr;
In the upcoming Borrow checker, it's even more important to trace
through temporaries because not tracing an expression can drop a
`lifetimebound` link, resulting in false **negatives**.
This patch adds tracing through temporaries. The logic is:
* In function call arguments, temporaries are lifetime safe because the
full expression does not end until the call returns
* In ranged for loops, temporaries are lifetime safe because lifetime
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[clang][FreeBSD] Enable KASAN and KMSAN for riscv64 (#202288)
enables KASAN and KMSAN for the riscv64 freebsd target in the Clang
driver.
The corresponding FreeBSD kernel runtime support for riscv64 KASAN is
currently under active review.
Depends on: https://reviews.freebsd.org/D57381
Co-authored-by: aokblast <aokblast at FreeBSD.org>
Reland "[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors" (#221058)
This relands #217055
The original commit revealed a latent issue in eliminateFrameIndex in
SIRegisterInfo where SCC can be clobbered before reading it on
gfx900/gfx90a. This change itself has no known issues.
[AMDGPU] Update based on review feedback
Replace the lambda with the check inlined at both sites, and report a fatal
error when neither a free SGPR nor FrameReg is available, rather than
silently falling back to the spilling scavenge.
[AMDGPU] Use the scavenger to test whether SCC is live after MI
The register scavenger is stepped backwards to the liveness state
immediately after MI, so RS->isRegUsed(SCC) already answers "is SCC live
after MI" directly. Replace the hand-rolled test with that query.
[AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering
When SCC is live into a scalar frame index user, the scaling path avoids
SALU ops that write SCC by computing the address in a VGPR and reading it
back with V_READFIRSTLANE_B32. If the destination of that readfirstlane is
scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive
lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead, scavenge
that register with AllowSpill=false.
[NFC][AMDGPU] Add tests for SCC live into a frame index user
Pre-commit tests for the case where SCC is live into a frame index user and
no SGPR is free to hold the V_READFIRSTLANE_B32 result. Scavenging one
emergency-spills an SGPR, and an SGPR spill flips EXEC with S_NOT_B64, so the
EXEC flips land between the S_CMP_EQ_U32 that defines SCC and the read of SCC
that follows, clobbering it in between.
[AMDGPU] Prevent SCC clobber in frame index lowering in scaling path
eliminateFrameIndex has two lowering strategies, but only one has the
proper handling for checking SCC-liveness to prevent clobbering. Unify
them with a helper function to ensure both paths handle the same
