LLVM/project faf140amlir/lib/Dialect/SCF/IR SCF.cpp, mlir/test/Dialect/SCF canonicalize.mlir

Reapply "[mlir][SCF] Fold unused `index_switch` results (#173560)"

This reverts commit 85bfb54f9dfcb323f7a8cbb38a264a596aa1a3d3,
i.e. it reapplies #173560 which was temporarily reverted in
DeltaFile
+51-1mlir/lib/Dialect/SCF/IR/SCF.cpp
+31-0mlir/test/Dialect/SCF/canonicalize.mlir
+82-12 files

LLVM/project f7c2a62llvm/test/CodeGen/AMDGPU combine-scalar-selects-asm.ll

added asm test file
DeltaFile
+268-0llvm/test/CodeGen/AMDGPU/combine-scalar-selects-asm.ll
+268-01 files

LLVM/project 74a8de5llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU agpr-copy-no-free-registers.ll licm-regpressure.mir

[AMDGPU] Take into account amdgpu-waves-per-eu in getRegPressureLimit

The minimum occupancy computed by `getOccupancyWithWorkGroupSizes`
doesn't take into account that the user may have provided a
low-occupancy target through the amdgpu-waves-per-eu attribute.

Bound the minimum-occupancy using the maximum value in
amdgpu-waves-per-eu.

When the user specifies a small amdgpu-waves-per-eu (like "1,1"), this
results in higher vpgr limits.

This patch depends on https://github.com/llvm/llvm-project/pull/168358
to work.
DeltaFile
+34-50llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+7-1llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-2llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
+43-533 files

LLVM/project 3ecf4d2mlir/lib/Dialect/SCF/IR SCF.cpp, mlir/test/Dialect/SCF canonicalize.mlir

Revert "[mlir][scf] Fold away scf.for iter args cycles (#173436)" (#173991)

It causes issues with Triton usage.

Also revert dependent "[mlir][SCF] index_switch results (#173560)".
DeltaFile
+14-150mlir/lib/Dialect/SCF/IR/SCF.cpp
+24-91mlir/test/Dialect/SCF/canonicalize.mlir
+38-2412 files

LLVM/project 7307519llvm/test/CodeGen/AMDGPU licm-regpressure.mir

Pre-commit test: [AMDGPU] Take into account amdgpu-waves-per-eu in getRegPressureLimit
DeltaFile
+154-2llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
+154-21 files

LLVM/project 6ec2ec4llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 gather-buildvector-with-minbitwidth-user.ll

Revert "[SLP]Exclude non-profitable subtrees."

This reverts commit 79472d366591a39a453c186cf031dda874ddf728 to fix
a bug reported in https://github.com/llvm/llvm-project/pull/162018#pullrequestreview-3617073149
DeltaFile
+66-333llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+83-243llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
+26-137llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
+66-67llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
+63-29llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
+48-29llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
+352-83833 files not shown
+677-1,21939 files

LLVM/project 25acd42llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp

Revert "[aarch64] Mix the frame pointer with the stack cookie when protecting the stack (#161114)" (#173987)

This reverts commit b6bfa856860bb4304e635102872a4c994af101b4.

This commit broke Windows on Arm bots.
DeltaFile
+36-69llvm/test/CodeGen/AArch64/mingw-refptr.ll
+0-19llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+0-15llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+6-6llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+0-12llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+5-5llvm/include/llvm/CodeGen/TargetLowering.h
+47-1269 files not shown
+59-15615 files

LLVM/project a5260edllvm/lib/Target/AMDGPU AMDGPULateCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU combine-scalar-selects.ll

Combine scalarized selects back into vector selects
DeltaFile
+638-0llvm/test/CodeGen/AMDGPU/combine-scalar-selects.ll
+149-0llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+787-02 files

LLVM/project 8e86107mlir/include/mlir/IR Block.h, mlir/lib/Dialect/Transform/DebugExtension DebugExtensionOps.cpp

[mlir][IR][NFC] Add `Block::computeBlockNumber` convenience helper (#173475)

Add a helper function to compute the number of a block. Recommended only
for debugging purposes and to print error messages.
DeltaFile
+10-0mlir/include/mlir/IR/Block.h
+2-7mlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
+2-3mlir/lib/Dialect/Transform/DebugExtension/DebugExtensionOps.cpp
+5-0mlir/lib/IR/Block.cpp
+1-3mlir/lib/IR/Unit.cpp
+1-2mlir/test/lib/Analysis/TestAliasAnalysis.cpp
+21-153 files not shown
+24-199 files

LLVM/project 8bd804amlir/include/mlir/IR Block.h, mlir/lib/Dialect/Transform/DebugExtension DebugExtensionOps.cpp

[mlir][IR][NFC] Add `Block::computeBlockNumber` helper
DeltaFile
+10-0mlir/include/mlir/IR/Block.h
+2-7mlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
+2-3mlir/lib/Dialect/Transform/DebugExtension/DebugExtensionOps.cpp
+5-0mlir/lib/IR/Block.cpp
+1-3mlir/lib/IR/Unit.cpp
+1-2mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
+21-153 files not shown
+24-199 files

LLVM/project 6274b6bllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 pr173794.ll

[X86] Ensure we fold pow2 masks with the mask type, not the result type (#173984)

This was missed in #173366 when we relaxed the constraint on the types to just be the same element width

Fixes #173794
DeltaFile
+43-0llvm/test/CodeGen/X86/pr173794.ll
+3-2llvm/lib/Target/X86/X86ISelLowering.cpp
+46-22 files

LLVM/project e4a0e0aclang/test/Headers __clang_hip_math.hip, llvm/lib/IR Instructions.cpp

Revert "Revert 159f1c048e08a8780d92858cfc80e723c90235e3 (#173893)"

This reverts commit 86b9f90b9574b3a7d15d28a91f6316459dcfa046.
DeltaFile
+81-88llvm/test/Transforms/DFAJumpThreading/dfa-unfold-select.ll
+22-22clang/test/Headers/__clang_hip_math.hip
+17-24llvm/lib/IR/Instructions.cpp
+18-18llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
+15-17llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
+12-12llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
+165-18167 files not shown
+316-34373 files

LLVM/project 869163bmlir/include/mlir/Transforms Passes.td Passes.h, mlir/lib/Transforms RemoveDeadValues.cpp

tmp commit

simple test working

draft: do not erase IR, just replace uses
DeltaFile
+184-328mlir/lib/Transforms/RemoveDeadValues.cpp
+110-45mlir/test/Transforms/remove-dead-values.mlir
+10-0mlir/include/mlir/Transforms/Passes.td
+1-0mlir/include/mlir/Transforms/Passes.h
+305-3734 files

LLVM/project 6897234llvm/lib/Transforms/Utils CloneFunction.cpp

fix
DeltaFile
+16-3llvm/lib/Transforms/Utils/CloneFunction.cpp
+16-31 files

LLVM/project b1d47f4mlir/include/mlir/Transforms Passes.td Passes.h, mlir/lib/Transforms RemoveDeadValues.cpp

tmp commit

simple test working

draft: do not erase IR, just replace uses
DeltaFile
+203-311mlir/lib/Transforms/RemoveDeadValues.cpp
+110-45mlir/test/Transforms/remove-dead-values.mlir
+10-0mlir/include/mlir/Transforms/Passes.td
+1-0mlir/include/mlir/Transforms/Passes.h
+324-3564 files

LLVM/project a512318mlir/lib/Analysis SliceWalk.cpp

[mlir][Analysis] Improve `RegionBranchOpInterface` API usage
DeltaFile
+10-50mlir/lib/Analysis/SliceWalk.cpp
+10-501 files

LLVM/project 7da282fllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 pr173924.ll

[X86] combineArithReduction - avoid PSADBW expansion for 128 bit integers and larger (#173979)

Fixes #173924
DeltaFile
+38-0llvm/test/CodeGen/X86/pr173924.ll
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+39-12 files

LLVM/project 2db7110llvm/lib/Target/RISCV RISCVRegisterInfo.cpp, llvm/test/CodeGen/RISCV xqcibm-regalloc-hints.ll

[RISCV] Add regalloc hints for BSETI/BEXTI (#173964)

This patch hints the register allocator to use the same source and
destination registers for the `BEXTI/BSETI` instructions when the
`Xqcibm` vendor extension is enabled. This enables the generation of the
compressed `QC_C_BEXTI/QC_C_BSETI` instructions when possible.
DeltaFile
+65-0llvm/test/CodeGen/RISCV/xqcibm-regalloc-hints.ll
+5-0llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+70-02 files

LLVM/project a5d7611mlir/include/mlir/Interfaces ControlFlowInterfaces.td ControlFlowInterfaces.h, mlir/lib/Analysis/DataFlow SparseAnalysis.cpp

[mlir][Interfaces] Add `RegionBranchOpInterface` helper for forwarded values
DeltaFile
+21-29mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
+22-23mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+44-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+6-31mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp
+9-14mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+13-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+115-976 files

LLVM/project 50645a9mlir/include/mlir/Interfaces ControlFlowInterfaces.td ControlFlowInterfaces.h, mlir/lib/Analysis/DataFlow SparseAnalysis.cpp

[mlir][Interfaces] Add `RegionBranchOpInterface` helper for forwarded values
DeltaFile
+21-29mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
+22-23mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+44-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+6-31mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp
+13-18mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+13-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+119-1016 files

LLVM/project 60606b2mlir/include/mlir/Interfaces ControlFlowInterfaces.td, mlir/lib/Interfaces ControlFlowInterfaces.cpp

[mlir][Interfaces] Add `RegionBranchOpInterface::getSuccessorOperands` helper (#173971)

Add a helper for querying the successor operands for a region branch
`src -> dst`. Both `src` and `dst` may be the region branch op itself or
a terminator.

This helper allows users to query successor operands for the region
branch op and the terminators in a uniform way. This is similar to
`getSuccessorRegions(RegionBranchPoint)`, which works both for region
branch ops and terminators.
DeltaFile
+19-21mlir/lib/Transforms/RemoveDeadValues.cpp
+10-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+9-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+38-213 files

LLVM/project d72a2f9llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximum.ll simplify-demanded-fpclass-minimum.ll

InstCombine: Introduce nsz flag on minimum/maximum in SimplifyDemandedFPClass

Alive isn't particularly happy with this in the case where
one of the inputs could be zero, but I think
it's wrong: https://alive2.llvm.org/ce/z/dF7V6k

nsz shouldn't permit introducing a -0 result where
there wasn't one in the input here.
DeltaFile
+30-30llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+30-30llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+18-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+78-623 files

LLVM/project 86aace1llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-minimumnum.ll simplify-demanded-fpclass-maximumnum.ll

InstCombine: Handle minimumnum/maximumnum in SimplifyDemandedFPClass
DeltaFile
+36-59llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+34-55llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+64-12llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+134-1263 files

LLVM/project 87371adllvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximumnum.ll simplify-demanded-fpclass-minimumnum.ll

InstCombine: Add baseline minimumnum/maximumnum SimplifyDemandedFPClass tests
DeltaFile
+1,625-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+1,625-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+3,250-02 files

LLVM/project 2ba4cb9llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Handle minimum/maximum in SimplifyDemandedFPClass
DeltaFile
+51-80llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+49-76llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+26-87llvm/lib/Analysis/ValueTracking.cpp
+94-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+92-0llvm/lib/Support/KnownFPClass.cpp
+14-0llvm/include/llvm/Support/KnownFPClass.h
+326-2446 files

LLVM/project bb4c880libcxx/include/__ranges iota_view.h, libcxx/test/libcxx/ranges/range.factories/range.iota.view nodiscard.verify.cpp

[libc++][ranges] Applied `[[nodiscard]]` to `iota_view` (#173612)

`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.iota

Towards #172124
DeltaFile
+125-0libcxx/test/libcxx/ranges/range.factories/range.iota.view/nodiscard.verify.cpp
+19-16libcxx/include/__ranges/iota_view.h
+144-162 files

LLVM/project fc30dc4libcxx/include/__ranges drop_view.h, libcxx/test/libcxx/ranges/range.adaptors/range.drop nodiscard.verify.cpp

[libc++][ranges] Applied `[[nodiscard]]` to `drop_view` (#173557)

`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.drop

Towards #172124
DeltaFile
+144-0libcxx/test/libcxx/ranges/range.adaptors/range.drop/nodiscard.verify.cpp
+8-8libcxx/include/__ranges/drop_view.h
+152-82 files

LLVM/project 437ae34libcxx/include/__numeric gcd_lcm.h

[libc++][NFC] Simplify `gcd` a bit (#173570)

1. With `if constexpr` we can avoid partial specializations of
`__ct_gcd`. This patch changes it to a function template and renames it
to `__abs_in_type` to slightly improve readability.
2. `__gcd` was made non-recursive by
27a062e9ca7c92e89ed4084c3c3affb9fa39aabb, so this patch simply inlines
it into `gcd`.
DeltaFile
+24-34libcxx/include/__numeric/gcd_lcm.h
+24-341 files

LLVM/project baf029cllvm/lib/Transforms/Utils CloneFunction.cpp

remove outdated comment
DeltaFile
+0-3llvm/lib/Transforms/Utils/CloneFunction.cpp
+0-31 files

LLVM/project 8be2c19mlir/lib/Dialect/Tensor/IR TensorOps.cpp, mlir/test/Dialect/Tensor invalid.mlir

[MLIR] Fix mlir-opt crash in ReshapeOpsUtils.cpp when collapse_shape index is invalid (#173791)

This patch fixes a crash occurring in mlir-opt when running
collapse_shape with an invalid index configuration. Instead of crashing,
an error message is returned to the user.
Fixes: #173567

---------

Co-authored-by: Bazinga! <akparmar004>
DeltaFile
+9-0mlir/test/Dialect/Tensor/invalid.mlir
+5-0mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
+14-02 files