workflows/release-binaries.yml: Only dump the wix logs on failure (#218810)
There is currently a bug in the path on ARM64 Windows, so this step
always fails. Running it after a successful build doesn't make much
sense anyway since since we don't need to see the logs for a good build.
Also, we risk having it fail the whole job even after a successful build
(like what is currently happening on ARM64 Windows), so that's another
reason only to run this when the bulid fails.
[mlir:tblgen] Qualify access to `getContext` to fix #218872. (#218951)
With #218872, some code generated by `tblgen` containing `getContext()`
now uses `OpTyp::getContext()` if that op has a `context` property
instead of the intendend `Operation::getContext()`. This PR qualifies
the access such that the intended function is always called.
Signed-off-by: Ingo Müller <ingomueller at google.com>
[AArch64] Remove extra fmov after half-vector Neon LD instruction (#216758)
Currently, after a load instruction resulting in a half-vector tuple,
LLVM emits an extra fmov for explicitly zeroing the upper-half of the
vector register when returning a value in the tuple as the full 128 bit
vector.
This is unneeded as the load instruction already zeros the upper half of
the registers in the tuple.
Add special case to existing peephole function that can recognize the D
sub-reg tuple defining opcode and allow removing the extra FMOV
Full List of Load Instructions Tested:
LD1Twov: 8b, 4h, 2s, 1d
LD1Twov_POST: 8b, 4h, 2s, 1d
LD1Threev: 8b, 4h, 2s, 1d
LD1Threev_POST: 8b, 4h, 2s, 1d
LD1Fourv: 8b, 4h, 2s, 1d
LD1Fourv_POST: 8b, 4h, 2s, 1d
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[MemCpyOpt] Extend call slot optimization for non-dereferenceable destinations. (#217436)
Allow call slot optimization for non-dereferenceable destinations when
execution is guaranteed to reach the store. For this, check if the call
has both willreturn and nounwind attributes, and there are no
instructions between the call and the store that might trap or throw.
Since the store would trap anyway if the destination pointer was not
dereferenceable, we can forward the pointer to the call.
[CIR] Address review comments, drop one more test's opt-out
Update a couple of review comments to either stand alone instead of referencing
what classic does or clarify what they say.
The test case that was discussed already exists in the CIR lit suite. It was
just opting out of the pass until this PR allowed it to run. Dropped the flag
and confirmed the test passes with the pass on and no CHECK changes are needed.
Assisted-by: Cursor / claude-opus-5
[CIR] Regenerate CHECK lines for 8 more callconv opt-out tests (#218931)
These 8 CIR tests compile clean with x86_64 calling-convention lowering
on, but their CHECK lines still pinned the pre-coercion CIR: raw record
types in signatures, plain by-value loads for temporaries with a
non-trivial destructor, and matching store/load pairs for empty records.
The pass now emits the ABI-correct shape instead: sret return
parameters, a dropped or byref-marked argument for records that carry no
data or that need pass-by-reference, and a `#cir.poison` placeholder
where a value the pass ignores used to be stored.
Assisted-by: Cursor / claude-opus-5
Revert "[CodeGen] Take the executable stack from a module flag" (#218964)
Reverts llvm/llvm-project#215152
This change breaks -Wl,-z,execstack for target offload.
Reapply "[clang-repl] Honor -emit-llvm to print incremental IR" (#218735)
Relands #217870 with a fix for the failure in `clang/test/Interpreter/emit-llvm.cpp` seen on ppc64le
[clang][CIR][AArch64] Add lowering for conversion intrinsics (#217263)
This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
It continues the work started in #190961, #193273, #199990, #209252,
, #211609, #216757 and #217017.
This PR implements the conversions for the following:
1) "int to float" intrinsics:
* vcvt_f32_s32
* vcvtq_f32_s32
* vcvt_f32_u32
* vcvtq_f32_u32
* vcvts_f32_s32
* vcvts_f32_u32
* vcvt_f64_s64
* vcvtq_f64_s64
* vcvt_f64_u64
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[mlir] Remove dead forward declarations (#218863)
This patch removes forward declarations of classes and structs that
are no longer referenced anywhere in MLIR.
[DWARFLinker] Resolve a module import through the module's anchor (#218575)
An importing compile unit emits its own DW_TAG_module skeleton, and that
skeleton can name a different DW_AT_LLVM_include_path than the unit
built from the .pcm. For example, a Swift unit names the .swiftmodule
while the companion Clang module names the framework bundle.
The classic linker gets this from DeclContext uniquing. f03b9d709525
made the parallel linker's type pool pick the right copy, but the type
pool only covers ODR languages. This addresses the non-ODR case.
Add a link-global ModulePool, using the dotted module path as the key. A
module unit records where it put each DW_TAG_module, either as a type
entry or as a section + offset. Because the import may not exist during
cloning, we emit a placeholder and only emit it when the anchor is fully
resolved.
A .pcm holds the description of the module it was built for, and also a
partial copy of every module that it imports. Only the first is the
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[mlir][Tosa] Use split discardable/inherent attribute APIs (#218912)
Use typed operation accessors and explicit discardable attribute APIs in
the Tosa dialect, conversions, target handling, and validation.
Assisted-by: Codex
[SCEV] Fix dead CHECK lines in ptrtoint.ll (NFC) (#218932)
There is no CHECK prefix; remove and regenerate with X32/X86 check
lines.
As suggested in https://github.com/llvm/llvm-project/pull/217378.
[MergeFunctions] Fix merging functions with different KCFI type identifiers (#217665)
MergeFunctions currently merges functions with identical bodies even
when
their function-level !kcfi_type metadata contains different type
identifiers.
This can redirect calls or function pointers to a function with a
mismatched
KCFI type identifier, potentially causing KCFI checks to fail at
runtime.
Compare function-level !kcfi_type metadata in FunctionComparator so that
functions with different KCFI type identifiers are not merged.
Add a minimal regression test covering two identical functions with
different
KCFI type identifiers.
Fixes #217629
[AArch64] Suboptimal assembly for u128 x * x (#214796)
This PR optimizes the AArch64 backend for 128-bit integer squaring
(`u128 x * x`).
It updates the instruction selection logic to combine `(A + B) + B` into
`A + (B << 1)`. This allows the compiler to emit a single, optimal `add
... lsl #1` instruction instead of multiple separate `add` instructions.
A baseline test was added in the first commit, and the optimization is
provided in the second commit to clearly highlight the codegen
improvements.
Fixes #213775
[MLIR][X86] Track shuffled write operand updates (#218936)
Notify pattern rewrite listeners while replacing the operands of both
write-like users after accumulator shuffling.
Add focused coverage that does not depend on the separate accumulator
rewrite.
Assisted-by: Codex
