LLVM/project 7063365clang/docs ReleaseNotesTemplate.txt ReleaseNotes.rst

[clang][docs] Redirect folks from CSA sections for usual Clang crashes (#175935)

Almost in every release there are contributors adding non-CSA entries to
the CSA release docs sections due to confusion.
To reduce the temptation in the future, let's add a reminder.

Note that it's not the end of the world if entries are put in the wrong
section, because I always moved them in the past. It would be simply
more convenient to avoid this.
DeltaFile
+7-11clang/docs/ReleaseNotesTemplate.txt
+7-11clang/docs/ReleaseNotes.rst
+14-222 files

LLVM/project d45fafaclang-tools-extra/clang-tidy/misc ConstCorrectnessCheck.cpp, clang-tools-extra/docs/clang-tidy/checks/misc const-correctness.rst

[clang-tidy] Add AnalyzeParameters option to misc-const-correctness (#171215)

Closes https://github.com/llvm/llvm-project/issues/170445.
DeltaFile
+511-0clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-parameters.cpp
+105-33clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
+22-6clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
+27-0clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-parameters-header.cpp
+11-0clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/const-correctness/correctness.h
+11-0clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/const-correctness/correctness-fixed.h
+687-393 files not shown
+698-399 files

LLVM/project dbba4edflang/lib/Lower/OpenMP Clauses.cpp ClauseProcessor.cpp, flang/test/Lower/OpenMP thread-limit-dims.f90

[Flang] Add lowering for flang to mlir for thread_limit
DeltaFile
+62-0flang/test/Lower/OpenMP/thread-limit-dims.f90
+10-3flang/lib/Lower/OpenMP/Clauses.cpp
+3-1flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+3-1llvm/include/llvm/Frontend/OpenMP/ClauseT.h
+78-54 files

LLVM/project de40ef2bolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Passes LongJmp.cpp

[BOLT][BTI] Patch LLD-generated PLTs to contain BTI landing pad (#173245)

This patch adds the patchPLTEntryForBTI to enable patching PLT entries
generated by LLD.

## Context:

To keep BTI consistent, targets of stubs inserted in LongJmp need to be
patched. As PLTs are not optimized and emitted by BOLT, this patch adds
a helper for patching them in the original .plt section.

For PLTs generated by LLD, this is safe as LLD inserts extra nops to
PLTs which don't already contain a BTI.

PLT entry before patching:
```
   adrp x16, Page(&(.got.plt[n]))
   ldr  x17, [x16, Offset(&(.got.plt[n]))]
   add  x16, x16, Offset(&(.got.plt[n]))

    [26 lines not shown]
DeltaFile
+64-0bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+33-4bolt/test/runtime/AArch64/long-jmp-bti-plt.c
+5-0bolt/lib/Passes/LongJmp.cpp
+4-0bolt/include/bolt/Core/MCPlusBuilder.h
+106-44 files

LLVM/project c91fbbdllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 combine-pclmul.ll

[X86] SimplifyDemandedVectorEltsForTargetNode - add basic X86ISD::PCLMULQDQ handling (#176142)

Now that we're creating X86ISD::PCLMULQDQ nodes in DAG, we need to
handle basic vector simplification - a minor first step towards adding
ISD::CLMUL vector handling

X86ISD::PCLMULQDQ uses the lower/upper i64 element from each 128-bit
lane depending on whether bit0/bit4 are set (for lhs/rhs operands)

These tests were copied from InstCombine which already did something
similar for the pclmulqdq intrinsics
DeltaFile
+16-61llvm/test/CodeGen/X86/combine-pclmul.ll
+50-0llvm/lib/Target/X86/X86ISelLowering.cpp
+66-612 files

LLVM/project fb2c62cllvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstCombine select-cmp-cttz-ctlz.ll

[InstSimplify] Avoid poison value for ctz/abs in simplifyWithOpsReplaced() (#176168)

If we drop flags, we'll set the zero_is_poison/int_min_is_poison flag to
false as part of the transform. However, the constant folding was still
performed with the value true, which made constant folding return
poison. This resulted in the pattern failing to match, as the poison
value is not equal to the other select arm.

To avoid this, add some special handling to set the argument to false
during constant folding as well.

Fixes https://github.com/llvm/llvm-project/issues/175282.
DeltaFile
+117-0llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
+18-2llvm/lib/Analysis/InstructionSimplify.cpp
+135-22 files

LLVM/project 9bbea75llvm/cmake/modules AddLLVM.cmake, llvm/tools/llvm-config CMakeLists.txt

[cmake] Restore exception flags in llvm-config --cxxflags (#176195)

https://github.com/llvm/llvm-project/pull/173869 accidentally dropped
rtti and eh flags from `llvm-config --cxxflags`. Then
https://github.com/llvm/llvm-project/pull/174084 restored the rtti
flags. The eh flags were not included with the rationale that they are
not ABI relevant.

This PR restores the eh flags as well. While they are not strictly
necessary, I believe that code that directly interfaces with LLVM almost
certainly does not want to build with exceptions if LLVM is not built
with exceptions. Building in the peculiar `-fexceptions -fno-rtti`
configuration is rarely useful and likely not intended.

On MacOS, this is also relevant because it's not possible to use C++17
headers without `-fno-exceptions` when using older deployment targets.
In that configuration, `-fno-exceptions` is required to interact with
LLVM.
DeltaFile
+21-15llvm/cmake/modules/AddLLVM.cmake
+5-0llvm/tools/llvm-config/CMakeLists.txt
+26-152 files

LLVM/project e2eba60llvm/lib/CodeGen/SelectionDAG StatepointLowering.cpp

Revert StatepointLowering
DeltaFile
+8-6llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
+8-61 files

LLVM/project 7e9fd81clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files

LLVM/project d8aa09allvm/lib/Target/AMDGPU SIISelLowering.cpp

Use pseudo opcode for switch statements
DeltaFile
+10-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10-101 files

LLVM/project d9138b0llvm/lib/Target/AMDGPU SIISelLowering.cpp

Use enum values for src modifiers.
DeltaFile
+8-8llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8-81 files

LLVM/project c4b5dc2llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,115-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,102-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+80-19llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,299-194 files

LLVM/project b138906llvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+72-4llvm/docs/AMDGPUUsage.rst
+72-41 files

LLVM/project 8a78f0dllvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU v_sub_f64_pseudo.mir

[AMDGPU] Introduce `v_sub_f64_pseudo` instruction
DeltaFile
+104-0llvm/test/CodeGen/AMDGPU/v_sub_f64_pseudo.mir
+26-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-0llvm/lib/Target/AMDGPU/SIInstructions.td
+134-03 files

LLVM/project ea19ee9llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

Remove NAN Canonicalization
DeltaFile
+142-199llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+142-199llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+2-26llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+286-4243 files

LLVM/project 8024723clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files

LLVM/project 8d331d5llvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+72-4llvm/docs/AMDGPUUsage.rst
+72-41 files

LLVM/project 019caaellvm/lib/Target/AMDGPU SIISelLowering.cpp

Use pseudo opcode for switch statements
DeltaFile
+10-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10-101 files

LLVM/project 99ec779llvm/lib/Target/AMDGPU SIISelLowering.cpp

Use enum values for src modifiers.
DeltaFile
+8-8llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8-81 files

LLVM/project 28d75bcllvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,115-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,102-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+80-19llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,299-194 files

LLVM/project d607129llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU v_sub_f64_pseudo.mir

[AMDGPU] Introduce `v_sub_f64_pseudo` instruction
DeltaFile
+104-0llvm/test/CodeGen/AMDGPU/v_sub_f64_pseudo.mir
+26-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-0llvm/lib/Target/AMDGPU/SIInstructions.td
+134-03 files

LLVM/project 8b2c247llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

Remove NAN Canonicalization
DeltaFile
+142-199llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+142-199llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+2-26llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+286-4243 files

LLVM/project ddb8385flang/lib/Lower/OpenMP ClauseProcessor.cpp Clauses.cpp, flang/test/Lower/OpenMP num-teams-dims.f90

[FLANG] Add flang to mlir lowering for num_teams
DeltaFile
+52-0flang/test/Lower/OpenMP/num-teams-dims.f90
+25-9flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+23-4flang/lib/Lower/OpenMP/Clauses.cpp
+14-3flang/lib/Lower/OpenMP/OpenMP.cpp
+114-164 files

LLVM/project c30c2f4llvm/lib/Target/AMDGPU GCNRegPressure.cpp GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU swdev-549940.ll

[AMDGPU] Rematerialize VGPR candidates when SGPR spills results in VGPR Excess (#168079)

Before, when selecting candidates to rematerialize, we would only
consider SGPR candidates when there was an excess of SGPR registers.

Failing to eliminate the excess would result in spills to VGPRs.
This is normally not an issue, unless spilling to VGPRs results in
excess VGPRs.

This patch does 2 things:
* It relaxes the GCNRPTarget success criteria: now we accept regions
  where we spill SGPRs to VGPRs, as long as this does not end up in
  excess VGPRs.
* It changes isSaveBeneficial to consider the excess VGPRs (which
  includes the SGPRs that would be spilled to VGPR).

With these changes, the compiler rematerializes VGPRs when the excess
SGPRs would result in VGPR excess.


    [4 lines not shown]
DeltaFile
+609-0llvm/test/CodeGen/AMDGPU/swdev-549940.ll
+66-54llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+12-1llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+6-0llvm/lib/Target/AMDGPU/GCNRegPressure.h
+693-554 files

LLVM/project 3b1d7edclang/lib/CIR/Dialect/IR CIRDialect.cpp, mlir/include/mlir/Interfaces ControlFlowInterfaces.h

[mlir][Interfaces] Split successor inputs from region successor
DeltaFile
+52-12clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+43-20mlir/lib/Dialect/SCF/IR/SCF.cpp
+43-12mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+12-30mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+28-11mlir/lib/Dialect/Transform/IR/TransformOps.cpp
+36-3mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+214-8836 files not shown
+446-20742 files

LLVM/project ce93961llvm/docs/CommandGuide llvm-readobj.rst llvm-readelf.rst, llvm/test/tools/llvm-readobj/ELF call-graph-info.test call-graph-info-warn-malformed.test

Revert "[llvm-readobj] Dump callgraph section info for ELF" (#176221)

Reverts llvm/llvm-project#157499

Following up on discourse post. Reverting this patch and will attempt a
reland addressing post merge comments.

(cherry picked from commit 97576a86eb25696a2b57cd42370991b172c08405)
DeltaFile
+0-521llvm/test/tools/llvm-readobj/ELF/call-graph-info.test
+0-366llvm/test/tools/llvm-readobj/ELF/call-graph-info-warn-malformed.test
+1-277llvm/tools/llvm-readobj/ELFDumper.cpp
+17-25llvm/docs/CommandGuide/llvm-readobj.rst
+4-12llvm/docs/CommandGuide/llvm-readelf.rst
+0-4llvm/tools/llvm-readobj/llvm-readobj.cpp
+22-1,2052 files not shown
+22-1,2078 files

LLVM/project 42d7ed3flang/include/flang/Optimizer/Dialect/MIF MIFOps.td, flang/lib/Lower Bridge.cpp MultiImageFortran.cpp

[flang] Fix crash with coarray teams #171048 (#172259)

This PR updates the `CHANGE TEAM` construct to fix the bug mentioned in
the issue #171048.
When a construct such as `IfConstruct` was present in the `CHANGE TEAM`
region, several BB were created but outside the region.

(cherry picked from commit 1d4f9ac37c043198d823e85e3cd777dc970d8b75)
DeltaFile
+40-20flang/lib/Lower/Bridge.cpp
+29-0flang/test/Lower/MIF/change_team2.f90
+6-11flang/lib/Lower/MultiImageFortran.cpp
+6-7flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
+6-6flang/include/flang/Optimizer/Dialect/MIF/MIFOps.td
+5-3flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+92-471 files not shown
+95-497 files

LLVM/project 777e29dlldb/test/API/tools/lldb-dap/attach TestDAP_attach.py, lldb/test/API/tools/lldb-dap/startDebugging TestDAP_startDebugging.py

[lldb-dap] Move targetId and debuggerId into a session property (#175930)

This makes it clear the fields required for attaching to an existing
debug session.

It also makes it easier to check mutually exclusive fields required to
attach.

(cherry picked from commit 6977e6812c3e2027f0f427506ee151011f1e55bb)
DeltaFile
+13-11lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
+15-3lldb/tools/lldb-dap/extension/package.json
+8-9lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
+9-8lldb/test/API/tools/lldb-dap/startDebugging/TestDAP_startDebugging.py
+11-5lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
+7-5lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
+63-415 files not shown
+86-6011 files

LLVM/project d16413allvm/lib/ExecutionEngine/JITLink MachO_x86_64.cpp MachO_arm64.cpp

[JITLink][CompactUnwind] Explicitly enumerate mergeable encodings. NFCI. (#176317)

Updates CompactUnwindTraits_MachO_arm64 and
CompactUnwindTraits_MachO_x86_64 encodingCanBeMerged methods to use
switch statements that clearly list mergeable encodings, and have a
default "false" case.

Since the new scheme explicitly covers DWARF modes (always
non-mergeable), this patch removes the separate DWARF mode check from
mergeRecords in CompactUnwindSupport.h.
DeltaFile
+14-3llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
+14-2llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
+2-3llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
+30-83 files

LLVM/project 12c4749flang/lib/Lower/OpenMP OpenMP.cpp, mlir/include/mlir/Dialect/OpenMP OpenMPClauses.td

Remove dims(N) syntax and use list of vals for num_threads
DeltaFile
+13-38mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+22-27mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
+0-31mlir/test/Dialect/OpenMP/invalid.mlir
+11-15mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+6-8flang/lib/Lower/OpenMP/OpenMP.cpp
+9-2mlir/test/Dialect/OpenMP/ops.mlir
+61-1213 files not shown
+74-1249 files