TableGen: Parenthesize negated predicate-dag leaves with operators
Allows writing more general expressions in the predicate code. Previously
not ("a == b") would be emitted as !a == b.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
RuntimeLibcalls: Rename RuntimeLibcallPredicate to RuntimeLibcallAvailability
Rename to avoid confusing partial name collisions in future changes.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
RuntimeLibcalls: Reuse AssemblerPredicate's operators for libcalls
Allow specifying RuntimeLibcall's availability in terms of individual
triple properties composed with logical operators.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[lldb][AArch64][Linux][NFC] Move RegisterSetType enum into header (#207145)
I will be using this later to replace all the register specific
functions this class has (WriteSVE/ReadSVE and so on) with single
functions that use RegisterSetType to decide what to do.
While I'm here, I've made some sizeof and casts use RegisterSetType in
case the underlying type changes later.
[RISCV][P-ext] Generalize lowerVECTOR_SHUFFLEAsRV32PNarrowingShift (#210522)
The previous implementation only matches
`shuffle(extract_subvector(src), extract_subvector(src), mask)`.
This patch generalizes it to `shuffle(a, b, mask)`, so we can now lower
it to `PNSRL(concat(a,b), element_bits)` if it is a deinterleave
shuffle. And we use `foldConcatVector` to handle the original pattern
with `extract_subvector`.
[GVN] Remove the "private" `llvm::gvn` namespace (NFC) (#210323)
Move `AvailableValue` and `AvailableValueInBlock` into GVNPass, similar
to other helper types.
Retain `llvm::gvn::GVNLegacyPass` as just `llvm::GVNLegacyPass` -
"legacy" is already a sufficent hint and it is not going to become more
"private" by stacking "gvn" prefixes to the name.
Ideally, `GVNLegacyPass` should be defined in an anonymous namespace,
but that is not possible because it is declared as a friend of GVNPass.
[LSROA] Add logical SROA pass (#192058)
This commit adds a logical-pointer compatible SROA pass. As-is, the pass
does not optimizes nested structs, arrays, or usages of structured
alloca with non-structured GEP instructions.
Adding support for both is not complex, but increase the size of the PR,
hence we can start with this.
Next step will be to allow mem2reg to apply on logical alloca/ptr, and
to add support for nesting/arrays.
---------
Co-authored-by: Nikita Popov <npopov at redhat.com>
[lldb][docs] Remove image links from trace doc (#210664)
The document was first added in https://reviews.llvm.org/D105741 but
that did not include the images (they were not in the RFC or discussions
either).
[Driver,FreeBSD] Fix -pie for -r and -no-pie links (#210663)
Port Gnu.cpp changes ae623d16d50c and cac82e26c642 to FreeBSD and
Serenity: -r should suppress -pie. -nopie, OpenBSD specific, should not
be used by other OSes.
Group the options selecting the link mode and place them after -m, as
gnutools::Linker does, so that -r suppresses -export-dynamic and
--hash-style as well, and -no-pie overrides the -fsanitize PIE default.
Drop --enable-new-dtags: default in modern linkers.
Change -Bstatic to -static to follow Gnu.cpp (identical in lld and older
GNU ld).
Reapply "[libc++][NFC] Inline std::function members into the class body" (#209555) (#210260)
This caused LLDB to fail, which has been fixed now.
This reverts commit 7618426138aae95561da676a1d1e10ee0392bf78.
[ConstraintSys] Solve sub-system with variables needed for query (#210432)
Update ConstraintSystem to only solve the sub-system containing all
variables relevant to a given query.
The sub-system contains the transitive closure of all variables in rows
involving the variables in the constraint to prove.
The iterative collection loop only needs very few iterations to
complete. The pruned system can significantly speed up Fourier–Motzkin
elimination and reduce the cost of copying the system.
This helps to notably decrease compile-time in cases when there are
larger numbers of variables & rows (especially during (Thin)LTO).
Highlights include
* stage1-ReleaseThinLTO: -0.16%
* stage1-ReleaseLTO-g: -0.19%
* stage1-aarch64-O3: -0.04%
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[libc][bazel] Add missing arpa/inet functions and tests (#210310)
Add bazel build targets for the remaining arpa/inet functions
(inet_addr, inet_aton, inet_ntoa, and inet_ntop) along with their unit
tests and supporting targets (__support_net_address, headers, and proxy
types).
Assisted by Gemini.
[libc][cmake] Remove proxy header XXX_macros -> XXX.h deps (#210008)
In the full build mode, these headers do not include the main XXX.h
header, which makes sense, because they exist to allow us only to expose
a part of it. They do include it in the overlay mode, but in this case,
they are referring to the header from the libc being overlaid, which
exists outside of the build system.
Also fix float_macros by moving
libc.include.llvm-libc-macros.float_macros from DEPENDS to
FULL_BUILD_DEPENDS, as llvm-libc-macros/float-macros.h is only included
under LIBC_FULL_BUILD.
[Driver][test] Unwrap freebsd-mips-as.c RUN lines (#210658)
Collapse 3-line RUN blocks to 2 lines and move -### immediately after
%clang, matching the prevailing style for new tests.
[flang][PFT-to-MLIR] Wrap unstructured Fortran constructs in scf.execute_region (#208635)
Extend the PFT-to-MLIR (HLFIR/FIR) lowering so unstructured DO and IF
constructs are emitted inside scf.execute_region, hiding their
multi-block CFG behind a single op. OpenACC lowerings that reject
multi-block content (e.g. the "unstructured do loop in combined acc
construct" TODO in OpenACC.cpp) now see a structured op instead.
The main goal is to prevent propagating the "unstructured" property up
the evaluation tree just because one nested evaluation is unstructured;
which is the current behavior.
Flag: -mmlir --wrap-unstructured-constructs-in-execute-region (default
on).
An evaluation is wrappable iff all of the following hold:
* wrap flag on
* eval is parser::DoConstruct or parser::IfConstruct
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[AArch64] Fold vector shifts guarded against oversized amounts into USHL (#207628)
`select(icmp ult(amt, EltSize), shl(x, amt), 0)`, where EltSize is the
{8, 16, 32, 64} lane size, is the usual way to guard a variable vector
shift against shl poison. On AArch64 the guard is unnecessary because
USHL already returns zero once the shift amount reaches the lane size.
For v4i32:
Before:
```
movi v2.4s, #63
movi v3.4s, #32
and v1.16b, v1.16b, v2.16b
ushl v0.4s, v0.4s, v1.4s
cmhi v1.4s, v3.4s, v1.4s
and v0.16b, v1.16b, v0.16b
```
After:
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[libc] Port process utilities to hermetic mode and enable some tests (#209999)
This is achieved by calling internal libc functions in hermetic mode. In
the overlay mode I keep calling the system functions so that the tests
work even on systems which don't have these implemented.
I also needed to implement the delete operators as both the libc proper
and the test framework uses them nowadays.
This is sufficient to enable all stdlib tests in hermetic mode, except
for one, which actually exposes a bug in the implementation. I'll deal
with that in a separate patch.
[LLD][RISCV][Zicfilp] Generate unlabeled landing pad-style PLT (#145461)
To support dynamic linking when Zicfilp is enabled, lpad insns are
inserted into PLTs. This patch generates the unlabeled landing pad-style
PLT, in which all the lpads have label `0`, when ZICFILP-unlabeled is
enabled:
--- PLT Header:
```
1: auipc t3, %pcrel_hi(.got.plt)
sub t1, t1, t2
l[w|d] t2, %pcrel_lo(1b)(t3)
addi t1, t1, -(hdr size + 16)
addi t0, t3, %pcrel_lo(1b)
srli t1, t1, log2(16/PTRSIZE)
l[w|d] t0, PTRSIZE(t0)
jr t2
```
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[mlir] Fix mem2reg crash on scalable vector store/load with matching type (#209426)
Fixes #209065
`createInsertAndCast/createExtractAndCast` in `LLVMMemorySlot.cpp`
queried the bit size of the source/target types before checking whether
they were already identical. For scalable vector types (e.g.
`vector<[4]xi1>`), this size query implicitly converts a scalable
TypeSize to a scalar, which aborts. `mem2reg` hits this path for any
store or load whose value type exactly matches the slot's element type,
since `getStored/removeBlockingUses` run even when no cast is needed.
This fix adds an early return when the types are already equal, skipping
the size query, consistent with the existing short-circuit in
`areConversionCompatible/castSameSizedTypes`.
[RFC][LangRef] Specify that the accessed bytes of concurrent atomics must be either disjoint or the same
So far, the LangRef hasn't been clear on the semantics of partially overlapping
concurrent atomics in LLVM IR (specifically: a set of accesses marked as
`atomic` that would be in a data race if they weren't `atomic` and not all of
them access the exact same set of bytes).
What loads read is defined in terms of individual bytes, but the memory
ordering constraints are formulated closely to the C/C++ (and Java for
`unordered`) memory model, where partially overlapping atomics are not
possible. It's not obvious how concepts like C/C++'s per-location total
modification order for `monotonic` accesses map to accesses that can partially
overlap. While C/C++ relies on the modification order to ensure that atomics
cannot tear (i.e., atomic reads return bytes from two or more atomic writes),
our IR semantics (as written) currently does not guarantee this in the presence
of partially overlapping accesses.
This PR proposes a solution to this problem: It specifies that concurrent
overlapping atomics must access the exact same set of bytes to act atomically.
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