[LLE][LoopDistribution][LoopVersioning] Form LCSSA at Caller Invoking LoopVersioning Utility (#202296)
LoopVersioning utility `versionLoop()` expects the input form to be
LCSSA. However, passes like Loop distribution, Loop-load-elimination,
may invoke versioning with a non-LCSSA IR. Versioning updates exit-block
PHIs to handle both the original loop and the cloned loop. However, a
raw non-LCSSA use in the exit block (such as `switch i1 %C`) still
points to the original loop’s `%C`. On the cloned-loop path, control
reaches the exit block without executing the original `%C`, resulting in
error: `Instruction does not dominate all uses!`.
The fix is to form LCSSA at the caller pass.
[NFC][SPIRV] Use `StringRef` by value (no `const`, no `&`) (#207940)
A `StringRef` is non-modifiable and it acts as a reference, so there is
no need to declare it as `const` nor `&`.
---------
Co-authored-by: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
[lldb][Linux] Show si_addr for SIGBUS signals (#207718)
The general rule is if si_addr is the same as the PC, we don't show it
because it doesn't add any new information.
SIGBUS signals are caused by an instruction trying to do something, but
si_addr is not the address of the instruction. It's some virtual
address, which is the important bit so add it to the description.
https://man7.org/linux/man-pages/man7/signal.7.html
> SIGBUS <...> Bus error (bad memory access)
Before:
```
* thread #1, name = 'test.o', stop reason = signal SIGBUS: illegal address
* frame #0: 0x0000aaaaaaaa0b80 test.o`main at test.c:42:13
```
After:
```
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[libc] Add auxiliary vector and note macros to elf.h (#207914)
Added missing macros to elf.h:
* sys-auxv-macros.h: Added AT_RSEQ_FEATURE_SIZE and AT_RSEQ_ALIGN.
* elf.yaml: Added PT_AARCH64_MEMTAG_MTE, PN_XNUM, ELFCLASSNUM, EV_NUM,
and AT_* macros (via sys-auxv-macros.h). Also added NN_* and NT_* note
macros (including NT_FPREGSET and NT_SIGINFO) to match system headers.
* CMakeLists.txt: Added sys_auxv_macros dependency to elf target.
Assisted-by: Automated tooling, human reviewed.
[RISCV] Fix interleaved + strided costs for e64 elements on rv32 (#207927)
This is the same fix as #176105 for interleaved + strided memory op
costs.
We currently compute the cost of interleaved + strided ops as N *
scalar element memory ops, but on rv32 the scalar memory access will
be on an illegal type for 64 bit elements, even with zve64x. Prevent
it from overcosting by just using TCC_Basic.
[NFC][SPIRV] Correct misuses of `StringRef`
A `StringRef` is non-modifiable and it acts as a reference, so there is
no need to declare it as `const` or `&`.
[clang] Fix constant-evaluator crash on array new with no size (#207730)
An array new-expression whose bound is neither specified nor deducible
from its initializer (for example `new int[]()`) is ill-formed and is
already diagnosed by Sema with `error: cannot determine allocated array
size from initializer`. However, the constant evaluator still tried to
evaluate the recovery expression. In
`PointerExprEvaluator::VisitCXXNewExpr`
the array size is unavailable (`E->getArraySize()` is `nullopt`), so the
allocation fell through to the scalar-new path, producing an array
`APValue` stored under a scalar type. Reading that object later asserted
in `Type::castAsArrayTypeUnsafe()` (`isa<ArrayType>(CanonicalType)`)
from
`CheckEvaluationResult`.
This patch detects an array new-expression whose size could not be
determined and bails out of constant evaluation.
Fixes #200139
[GVN] Add tests for loop-load PRE into a multi-successor block
Precommit tests for loop-load PRE when the loaded pointer cannot be freed (a gc-managed address-space pointer and a nofree function). PRE currently fires but sinks the reload into a cold block with multiple successors, so it also runs on the loop-exit edge.
[GVN] Support critical-edge splitting in loop-load PRE
When the only in-loop blocker of a loop-load PRE candidate has multiple successors, the reload was placed at the end of that block, so it also ran on the loop-exit edge. Split the critical edge to the unique in-loop successor and insert the reload there, so it runs only on the path back to the header. Bail out on indirectbr or multiple in-loop successors, and keep backedge splitting gated behind the existing flag. Also refresh the stale TODO comments on the freeable-pointer tests, which stay un-PRE'd because the pointer may be freed.
clang/AMDGPU: Fix double linking opencl libs with --libclc-lib
Noticed by inspection. If using an explicit --libclc-lib flag,
do not attempt to also link the rocm device libs which will contain
different implementations of the same opencl symbols.
Co-Authored-By: Claude <noreply at anthropic.com>
clang/AMDGPU: Remove driver restriction on --gpu-max-threads-per-block
Previously this flag was only handled for HIP, and would produce an unused
argument warning. There is a custom warning produced by cc1 that the
argument isn't supported, but practically speaking that was unreachable
due to not forwarding the argument. Also add a test for the untested warning.
Also use a simpler method for forwarding the flag to cc1.
[LV][RISCV] Enable FSub reduction for scalable VFs (#207698)
#197134 introduced a change to FAdd reduction recognition, causing fsub
instructions to be classified as FSub reductions instead of FAdd
reductions. This patch fixes the regression by enabling FSub reduction
support for scalable VFs in TTI.
[Hexagon] Optimize sext + mul pattern for splatted scalar sext i16 (#206893)
Extend the existing vmpyh pattern to handle the case where one operand
of a v2i32 nsw mul is a splatted scalar sext i16 value. When the splat
is hoisted out of a loop, it arrives as assertsext v2i32, i16 in the DAG
rather than sext v2i16. The existing pattern did not match this form,
causing the multiply to expand to two scalar mpyi instructions.
Add a PatFrag assertsext_v2i32_i16 to match assertsext nodes of type
v2i32 extended from i16, and two new patterns (both operand orderings)
that recover the v2i16 using A2_combine_ll before feeding into
M2_vmpy2s_s0.
[AArch64] C1-Nano scheduler cleanup in preparation for SME [NFC] (#207738)
Change are in preparation for a forthcoming addition of SME to the
C1-Nano scheduling model. This is restructuring of the code which does
not involve the actual SME changes. By separating out these NFC changes
it will make review of the SME specific changes easier.
- Defined resource names to match the form now used in the C1-Ultra
scheduling model which has the throughput information on the end of the
name rather than in the middle:
C1NanoWrite_1c_1r_2ALU => C1NanoWrite_1c_2ALU_1rc
- Moved definitions so that they more closely match the order they are
defined in the C1-Nano SWOG. This make it easier to match entries in the
code to the tables in the SWOG.
These changes also make the C1-Nano scheduling model more closely match
the forms and layout used in the C1-Ultra scheduling model.
[clang][AST] Qualify DeclRefExpr printing (#206041)
I updated DeclRefExpr printing so fully-qualified printing consistently
uses declaration ownership rather than only the written qualifier. This
also preserves existing behavior for local names and cleaned parameter
names.
The added tests cover both the direct expression printer behavior and
the original type-printing scenario that exposed the missing
qualification.
Fixes #205925
clang/AMDGPU: Merge toolchain subclasses
Simplify the toolchain implementations by collapsing
them into one. Previously we had a confusing split. The
AMDGPUToolChain base class implemented much of the base
support. It was subclassed by ROCMToolChain, which would
have been more accurately described as the offloading subclass.
That was further subclassed into HIP and OpenMP specific subclasses.
Deleting those two is the important part of this change. There was
code duplication, and features arbitrarily handled in one but not
the other. The offload kind is passed in almost everywhere if you
really need to know the original language. However, I consider
this an antifeature, and it is really poor QoI to have the HIP
and OpenMP toolchains behave differently in any way. The platform
should be consistent and the driver behaviors should not depend
on the language.
There is additional mess in the handling of spirv, which this
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