[ELF][AArch64][PAC] Replace R_AARCH64_AUTH_ABS64 addend hack
Rather than trying to infer deep down in AArch64::relocate whether we
need to actually write anything or not, we should instead mark the
relocations that we no longer want so we don't actually apply them. This
is similar to how X86_64::deleteFallThruJmpInsn works, although given
the target is still valid we don't need to mess with the offset, just
the expr.
This is mostly NFC, but if the addend ever exceeded 32-bits but then
came back in range then previously we'd pointlessly write it, but now we
do not. We also validate that the addend is actually 32-bit so will
catch errors in our implementation rather than silently assuming any
relocations where that isn't true have been moved to .rela.dyn.
Reviewers: kovdan01, MaskRay
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/171192
[NFC][ELF][AArch64][MTE] Replace addend hack with less-confusing code
The current implementation in addRelativeReloc makes it look like we're
writing the symbol's VA + addend to the section, because that's what the
given relocation will evaluate to, but we're supposed to be writing the
negated original addend (since the relative relocation's addend will be
the sum of the symbol's VA and the original addend). This only works
because deep down in AArch64::relocate we throw away the computed value
and peek back inside the relocation to extract the addend and negate it.
Do this properly by having a relocation that evaluates to the right
value instead.
Reviewers: kovdan01, MaskRay
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/171182
[NFC][ELF][AArch64][PAC] Use existing addSymbolReloc for R_AARCH64_AUTH_ABS64
The only difference between these calls is whether rel or type is passed
as the first argument, but AArch64::getDynRel returns type unchanged for
R_AARCH64_AUTH_ABS64, so they are the same.
Reviewers: MaskRay, kovdan01
Pull Request: https://github.com/llvm/llvm-project/pull/171179
[StackProtector] Add metadata to opt-out (#170229)
This is the LLVM piece of this work. There is also a clang piece, which
adds this metadata to AllocaInst when the source does
`__attribute__((no_stack_protector))` on a variable.
We already have `__attribute__((no_stack_protector))` on functions, but
opting out the whole function might be too heavy a hammer. Instead this
allows us to opt out of stack protectors on specific allocations we
might have audited an know to be safe, but still allow the function to
generate a stack protector if other allocations necessitate it.
[lldb] Use ReadCStringsFromMemory to speed-up AppleObjCClassDescriptorV2::method_t lookup (#172031)
With this improvement, compiling a simple Objective-C program like:
```
int main() {
@autoreleasepool {
NSDictionary *mapping = @{ @"one": @1, @"two": @2, @"three": @3 };
return 0; //breakhere
}
}
```
And running `expr -O -- mapping[@"one"]`, we can observe the following
packet count for the expression evaluation:
```
Before:
multi mem read ($MultiMemRead) : 94
[12 lines not shown]
[AArch64][llvm] Add codegen for simd fpcvt intrinsics
Add tablegen patterns to provide codegen for SCVTF and UCVTF
operating purely on SIMD & FP registers, using explicit bitcasts.
[lldb][windows] skip TestPlatformProcessLaunchGDBServer.test_launch_with_unusual_process_name (#173250)
This patch skips
TestPlatformProcessLaunchGDBServer.test_launch_with_unusual_process_name
on Windows which is flaky.
The test will be reenabled once it has been fixed.
Revert "[SLP]Enable float point math ops as copyables elements."
This reverts commit e644f06c2ffc23b3415f3478b05c627303aef614 to fix
crashes found during internal testing
[Flang][Docs] Formatting change (#173257)
The flang.llvm.org page listed two entries (Testing, Resources) from the
Debug generation document in the table of contents. Change the
formatting to only include the top-level title.
[AArch64][GlobalISel] Added test coverage for sri intrinsic
Previously, generation of sri intrinsics was tested during the ACLE -> IR stage, but not in the IR -> MIR stage. Now, correct generation of sri intrinsics is tested in both stages.
