LLVM/project 1c0c9aellvm/include/llvm/CAS OnDiskGraphDB.h

[llvm][CAS] Fixed build with -D_LIBCPP_REMOVE_TRANSITIVE_INCLUDES (#173797)

DeltaFile
+1-0llvm/include/llvm/CAS/OnDiskGraphDB.h
+1-01 files

LLVM/project e7f23b4llvm/lib/Target/SystemZ SystemZISelLowering.h, llvm/test/CodeGen/SystemZ fmuladd-soft-float.ll

[SystemZ] Remove the `softPromoteHalfType` override (#175410)

`softPromoteHalfType` is being phased out because it is prone to
miscompilations (further context at [1]). SystemZ is one of the few
remaining platforms to override the default, so remove it here.

This only affects SystemZ when the `soft-float` option is used.

[1]: https://github.com/llvm/llvm-project/pull/175149
DeltaFile
+13-9llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll
+0-1llvm/lib/Target/SystemZ/SystemZISelLowering.h
+13-102 files

LLVM/project 8877491llvm/include/llvm/Support KnownBits.h, llvm/lib/Analysis ValueTracking.cpp

[ValueTracking] Support horizontal vector add in computeKnownBits (#174410)

Alive2 proofs:
* Leading zeros - [4vi32](https://alive2.llvm.org/ce/z/w--S2D),
[16vi8](https://alive2.llvm.org/ce/z/hEdVks)
* Leading ones - [4vi16](https://alive2.llvm.org/ce/z/RyPdBS),
[16vi8](https://alive2.llvm.org/ce/z/UTFFt9)
DeltaFile
+45-0llvm/test/Transforms/InstCombine/vector-reduce-add-known-bits.ll
+40-0llvm/lib/Support/KnownBits.cpp
+34-0llvm/unittests/Support/KnownBitsTest.cpp
+10-10llvm/test/Transforms/PhaseOrdering/AArch64/udotabd.ll
+8-0llvm/lib/Analysis/ValueTracking.cpp
+5-0llvm/include/llvm/Support/KnownBits.h
+142-106 files

LLVM/project 3448695llvm/include/llvm/BinaryFormat/ELFRelocs LoongArch.def, llvm/test/tools/llvm-readobj/ELF reloc-types-loongarch64.test

[llvm][LoongArch] Add reloc types for LA32R/LA32S (#175352)

This patch introduces the relocation types added in la-abi-sepcs v2.50.

Link: https://github.com/loongson/la-abi-specs/pull/16
DeltaFile
+28-0llvm/unittests/Object/ELFTest.cpp
+26-0llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test
+18-0llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def
+72-03 files

LLVM/project f25ddefclang/lib/Interpreter Interpreter.cpp, clang/tools/clang-repl ClangRepl.cpp

[clang-repl] Fix OrcRuntime lookup for Solaris and unit tests. (#175435)

The out-of-process execution in the interpreter depends on the orc
runtime. It is generally easy to discover as it is in the clang runtime
path. However, the clang runtime path is relative to clang's resource
directory which is relative to the clang binary. That does not work well
if clang is linked into a different binary which can be in a random
place in the build directory structure.

This patch performs a conservative approach to detect the common
directory structure and correctly infer the paths. That fixes the
out-of-process execution unittests. The patch also contains a small
adjustment for solaris.

Another take on trying to fix the issue uncovered by #175322.
DeltaFile
+48-64clang/lib/Interpreter/Interpreter.cpp
+13-9clang/unittests/Interpreter/OutOfProcessInterpreterTests.cpp
+2-2clang/tools/clang-repl/ClangRepl.cpp
+63-753 files

LLVM/project dcdcc3dclang/lib/CIR/Dialect/IR CIRDialect.cpp, mlir/include/mlir/Interfaces ControlFlowInterfaces.td ControlFlowInterfaces.h

[mlir][Interfaces] Simplify and align `RegionSuccessor` API
DeltaFile
+36-27mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+11-13mlir/lib/Dialect/SCF/IR/SCF.cpp
+9-15clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+10-6mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+5-5mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+5-5mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+76-7116 files not shown
+108-10522 files

LLVM/project 363903eclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp CIRGenFunction.h, clang/test/CIR/CodeGenBuiltins/AArch64 acle_sve_dup.c

[CIR][AArch64] Add lowering for unpredicated svdup builtins (#174433)

This PR adds CIR lowering support for unpredicated `svdup` SVE builtins.
The corresponding ACLE intrinsics are documented at:
* https://developer.arm.com/architectures/instruction-sets/intrinsics

(search for svdup).

Since LLVM provides a direct intrinsic for svdup with a 1:1 mapping, CIR
lowers these builtins by emitting a call to the corresponding LLVM
intrinsic.

DESIGN NOTES
------------
With this change, ACLE intrinsics that have a corresponding LLVM intrinsic can
generally be lowered by CIR by reusing LLVM intrinsic metadata, avoiding
duplicated intrinsic-name definitions, unless codegen-relevant SVETypeFlags are
involved. As a consequence, CIR may no longer emit NYI diagnostics for
intrinsics that (a) have a known LLVM intrinsic mapping and (b) do not use such

    [47 lines not shown]
DeltaFile
+211-0clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c
+114-1clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+4-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+329-13 files

LLVM/project a779fdfllvm/include/llvm/Support KnownBits.h, llvm/unittests/Support KnownBitsTest.cpp

[Support] Add KnownBits::isNonPositive() helper and exhaustive test coverage for sign predicates (#175284)

This patch adds:

1. KnownBits::isNonPositive() - Returns true if this value is known to
be non-positive (i.e., the signed maximum value is <= 0). This is
implemented using getSignedMaxValue().isNonPositive().

2. SignPredicatesExhaustive test - An exhaustive test that validates the
correctness of isNegative(), isNonNegative(), isStrictlyPositive(),
isNonPositive(), and isNonZero() by iterating through all possible
KnownBits combinations for 1-bit and 4-bit widths and verifying that the
predicates return true if and only if all possible values represented by
the KnownBits satisfy the predicate.

Fixes #175203
DeltaFile
+41-0llvm/unittests/Support/KnownBitsTest.cpp
+3-0llvm/include/llvm/Support/KnownBits.h
+44-02 files

LLVM/project 76ce034clang/unittests/Basic CMakeLists.txt

[clang] [unittest] Fix linking against dylib (#175317)

Fix a regression introduced in #174513 that would cause `BasicTests` to
link directly to static `LLVMTargetParser` library instead of using the
component linking, to respect dylib.

Signed-off-by: Michał Górny <mgorny at gentoo.org>
DeltaFile
+1-1clang/unittests/Basic/CMakeLists.txt
+1-11 files

LLVM/project 362b653llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine umin_cttz_ctlz.ll

[InstCombine] Fold Minimum over trailing or leading zeros (#173768)

Add support for
`umin(clz(x), clz(y)) => clz(x | y)`
`umin(ctz(x), ctz(y)) => ctz(x | y)`

[C++ source](https://godbolt.org/z/E8abbjT7G)
[alive proof](https://alive2.llvm.org/ce/z/mh94_n)

Fixes #173691
DeltaFile
+152-0llvm/test/Transforms/InstCombine/umin_cttz_ctlz.ll
+16-8llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+168-82 files

LLVM/project 3920bc6llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/Target/MSP430 MSP430ISelLowering.h

[TargetLowering] Change the `softPromoteHalfType` default to `true` (#175149)

The default `f16` lowering has some issues that result in incorrect
float behavior, so over time most targets have switched to use
`softPromoteHalfType`. Swap to soft promotion by default and add
overrides for SystemZ and AMDGPU, which are the two remaining backends
that still depend on this behavior.

All basic `f16` op tests now pass on all remaining experimental arches.

Fixes: https://github.com/llvm/llvm-project/issues/97981
Fixes: https://github.com/llvm/llvm-project/issues/97975
DeltaFile
+56-59llvm/test/CodeGen/Generic/half-op.ll
+13-5llvm/include/llvm/CodeGen/TargetLowering.h
+2-6llvm/lib/Target/MSP430/MSP430ISelLowering.h
+0-2llvm/lib/Target/VE/VEISelLowering.h
+0-2llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
+0-2llvm/lib/Target/X86/X86ISelLowering.h
+71-7616 files not shown
+74-10322 files

LLVM/project 99ab1ddllvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Implement SimplifyDemandedFPClass for sqrt (#173883)

DeltaFile
+38-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+10-19llvm/lib/Analysis/ValueTracking.cpp
+24-0llvm/lib/Support/KnownFPClass.cpp
+9-14llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
+4-0llvm/include/llvm/Support/KnownFPClass.h
+85-335 files

LLVM/project 1cb9b79llvm/test/tools/UpdateTestChecks/update_test_checks keep-label-name.test, llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs keep-label-name.ll keep-label-name.ll.expected

[UTC] Align label var handling of old lines to new lines (#173850)

BB labels have been treated as variables in newer UTC versions. 

However, UTC previously handled BB labels in old lines differently from
new lines, causing incorrect `remap_metavar_names`.

E.g., 
- New lines var `exit:` and `label %exit`: UTC generalized them as
`[[@@]]` and `[[@@]]`.
- Old lines var `[[EXIT]]:` and `label %[[EXIT]]`: UTC generalized them
as `[[@@]]:` and `label %[[@@]]`, which mismatched with the
generalization of new lines.

This mismatch might cause unexpected variable name remappings, even if
the new lines are indeed equivalent to the old lines.

This PR aligns label var handling of old lines to new lines, i.e.,
generalizes `[[EXIT]]:` and `label %[[EXIT]]` as `[[@@]]` and `[[@@]]`.
DeltaFile
+57-0llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/keep-label-name.ll
+57-0llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/keep-label-name.ll.expected
+8-2llvm/utils/UpdateTestChecks/common.py
+3-0llvm/test/tools/UpdateTestChecks/update_test_checks/keep-label-name.test
+125-24 files

LLVM/project d620ea7llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize epilog-vectorization-reductions.ll

[LV] Handle live-ins in findRecipe.

Skip live-ins in findRecipe to prevent a crash for cases with degenerate
reductions (where the backedge value is a live-in). Such reductions
should be removed, but this requires further changes.

Fixes https://github.com/llvm/llvm-project/issues/175229.
DeltaFile
+99-0llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
+3-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+102-12 files

LLVM/project 9eac606llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-rounding-intrinsics.ll

ceil to -0
DeltaFile
+2-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+3-32 files

LLVM/project bf5cc66llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Zero implies normal
DeltaFile
+2-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+2-21 files

LLVM/project 0c33852llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Remove parentheses
DeltaFile
+1-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-11 files

LLVM/project 69b5dd1llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

format
DeltaFile
+3-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+3-21 files

LLVM/project da9e433llvm/lib/Analysis ValueTracking.cpp

getScalarType()->isMultiUnitFPType()
DeltaFile
+3-2llvm/lib/Analysis/ValueTracking.cpp
+3-21 files

LLVM/project 6a568cellvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

VTy->getScalarType()->isMultiUnitFPType()
DeltaFile
+1-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-11 files

LLVM/project 633a6bbllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

also zero
DeltaFile
+1-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-11 files

LLVM/project d96b09cllvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Handle rounding intrinsics in SimplifyDemandedFPClass
DeltaFile
+55-89llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+66-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+28-0llvm/lib/Support/KnownFPClass.cpp
+2-20llvm/lib/Analysis/ValueTracking.cpp
+7-0llvm/include/llvm/Support/KnownFPClass.h
+158-1095 files

LLVM/project 5551b48llvm/test/Transforms/InstCombine simplify-demanded-fpclass-rounding-intrinsics.ll

InstCombine: Add SimplifyDemandedFPClass tests for round

Add tests for the family of rounding intrinsics
DeltaFile
+1,073-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+1,073-01 files

LLVM/project 5e11888llvm/lib/Support KnownFPClass.cpp, llvm/test/Transforms/Attributor nofpclass-sqrt.ll

ValueTracking: sqrt never returns subnormal
DeltaFile
+52-52llvm/test/Transforms/Attributor/nofpclass-sqrt.ll
+14-14llvm/unittests/Analysis/ValueTrackingTest.cpp
+2-5llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
+1-0llvm/lib/Support/KnownFPClass.cpp
+69-714 files

LLVM/project 59163d8llvm/test/Transforms/InstCombine simplify-demanded-fpclass-rounding-intrinsics.ll

Tests for 0 result implying normal input
DeltaFile
+144-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+144-01 files

LLVM/project 0b7c8ccllvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Implement SimplifyDemandedFPClass for sqrt
DeltaFile
+38-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+10-19llvm/lib/Analysis/ValueTracking.cpp
+24-0llvm/lib/Support/KnownFPClass.cpp
+9-14llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
+4-0llvm/include/llvm/Support/KnownFPClass.h
+85-335 files

LLVM/project 12cccb9mlir/lib/Dialect/MemRef/IR MemRefOps.cpp, mlir/test/Dialect/MemRef ops.mlir

Reapply [mlir][memref]: Allow collapse of strided unit dim even if strides are dynamic (#171039)

DeltaFile
+14-1mlir/test/Dialect/MemRef/ops.mlir
+5-5mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
+19-62 files

LLVM/project 7e4f390llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Handle fpext in SimplifyDemandedFPClass (#174849)

DeltaFile
+13-26llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll
+22-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+22-0llvm/lib/Support/KnownFPClass.cpp
+3-14llvm/lib/Analysis/ValueTracking.cpp
+6-0llvm/include/llvm/Support/KnownFPClass.h
+66-405 files

LLVM/project 007d2dcmlir/include/mlir/Dialect/SCF/IR SCFOps.td, mlir/lib/Dialect/SCF/IR SCF.cpp

Implement RegionBranchTerminatorOpInterface for scf.forall.in_parallel
DeltaFile
+18-13mlir/lib/Dialect/SCF/IR/SCF.cpp
+1-7mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
+19-202 files

LLVM/project a0c091bmlir/include/mlir/Interfaces ControlFlowInterfaces.h ControlFlowInterfaces.td, mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir][draft] Consolidate patterns into RegionBranchOpInterface patterns

fix some tests

reorganize code

address comments
DeltaFile
+17-813mlir/lib/Dialect/SCF/IR/SCF.cpp
+496-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+47-13mlir/test/Dialect/SCF/canonicalize.mlir
+9-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+4-4mlir/test/Transforms/remove-dead-values.mlir
+5-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+578-8306 files