LLVM/project 22d90e4clang/lib/Basic Cuda.cpp, llvm/include/llvm/TargetParser NVPTXTargetParser.h NVPTXTargetParser.def

NVPTX: Add target names in TargetParser

Track the canonical sm name and other target information.
This will eventually be used to reduce the pain of maintaining
OffloadArch in clang; all of the dijoint targets share an
enum which makes target specific covered switches annoying.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+24-156clang/lib/Basic/Cuda.cpp
+73-0llvm/lib/TargetParser/NVPTXTargetParser.cpp
+72-0llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
+71-0llvm/include/llvm/TargetParser/NVPTXTargetParser.def
+69-0llvm/include/llvm/TargetParser/NVPTXTargetParser.h
+1-0llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
+310-1563 files not shown
+313-1569 files

LLVM/project 9c9e12cllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIProgramInfo.cpp

[AMDGPU] Fix typos SGRP and VGRP. NFC. (#212732)
DeltaFile
+4-4llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
+4-4llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+3-3llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
+2-2llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
+1-1llvm/docs/AMDGPUUsage.rst
+14-145 files

LLVM/project 3757c5dllvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-trunc.ll clmul-fixed.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)

FIXED_REGS is not used for register allocation, but since it overlaps
the GPR classes via FP and SP, TableGen merges VG and FFR into the GPR
pressure set, giving it a static limit of 35.

The underlying GPR32all class has 33 registers: W0-W30, WZR, and WSP.
WZR and WSP are always reserved, leaving up to 31 allocatable registers
depending on whether W29 (FP) and W30 (LR) are reserved.

Marking FIXED_REGS non-allocatable removes VG and FFR from the pressure
set, reducing its static limit from 35 to 33 and its dynamic limit from
33 to 31. The corrected limit changes scheduling decisions made by the
register-pressure heuristics, which explains the test churn.

Assisted-by: codex
DeltaFile
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+727-755llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+611-614llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
+606-611llvm/test/CodeGen/AArch64/clmul-fixed.ll
+453-453llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
+4,568-4,5867 files not shown
+5,328-5,34613 files

LLVM/project d036f0aclang/lib/Basic Cuda.cpp, llvm/include/llvm/TargetParser NVPTXTargetParser.h NVPTXTargetParser.def

NVPTX: Add target names in TargetParser

Track the canonical sm name and other target information.
This will eventually be used to reduce the pain of maintaining
OffloadArch in clang; all of the dijoint targets share an
enum which makes target specific covered switches annoying.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+24-156clang/lib/Basic/Cuda.cpp
+73-0llvm/lib/TargetParser/NVPTXTargetParser.cpp
+72-0llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
+71-0llvm/include/llvm/TargetParser/NVPTXTargetParser.def
+63-0llvm/include/llvm/TargetParser/NVPTXTargetParser.h
+1-0llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
+304-1563 files not shown
+307-1569 files

LLVM/project e7db113llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/MachineVerifier/AMDGPU verify-ds-vdata-vdst-both-agpr-or-vgpr.mir

[AMDGPU] Remove redundant AGPR/VGPR register class verification (#212721)
DeltaFile
+1-14llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-11llvm/test/MachineVerifier/AMDGPU/verify-ds-vdata-vdst-both-agpr-or-vgpr.mir
+1-252 files

LLVM/project 462602dllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU soft-waitcnt-deletion.mir

[AMDGPU] Fix incorrect VM_VSRC simplification after async instruction (#212481)

Add ASYNC_CNT to the list of VMEM counters. The implication is that only
if all these counters are zero can we know that there are no outstanding
VMEM instructions, so VM_VSRC must be zero.
DeltaFile
+432-0llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
+1-1llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+433-12 files

LLVM/project 3120980llvm/lib/Transforms/Vectorize LoopVectorize.cpp

[LV][NFC]: Use CostCtx.CM instead of CM in precomputeCosts (#212287)
DeltaFile
+2-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+2-21 files

LLVM/project 9df6ca1llvm/lib/Target/AArch64 SVEInstrFormats.td, llvm/test/CodeGen/AArch64 sve-ptrue-coalesce.mir

[LLVM][CodeGen][SVE] Add ElementSize information to fp compare, continuous/replicating load and store instructions (#204821)

This information was originally used to implement MOVPFRX support.
However https://github.com/llvm/llvm-project/pull/204820 uses the same
information to determine which bits of an instruction's predicate
operand are used so that PTRUE instructions can be coalesced.
MOVPRFXable instructions are a subset of all predicated instructions, so
this patch extends some non-MOVPRFXable instructions with ElementSize
information.
DeltaFile
+334-1llvm/test/CodeGen/AArch64/sve-ptrue-coalesce.mir
+33-19llvm/lib/Target/AArch64/SVEInstrFormats.td
+367-202 files

LLVM/project e17d910llvm/test/MC/AMDGPU mcexpr_amd.s data.s

AMDGPU: Manually convert some MC tests to subarch triples

Many are switches from using the dummy amdgcn triple to a concrete
subarch.
DeltaFile
+7-7llvm/test/MC/AMDGPU/hsa-metadata-kernel-attrs-v3.s
+6-6llvm/test/MC/AMDGPU/hsa-metadata-kernel-args-v3.s
+3-3llvm/test/MC/AMDGPU/s_endpgm.s
+3-3llvm/test/MC/AMDGPU/hsa-metadata-kernel-code-props-v3.s
+2-2llvm/test/MC/AMDGPU/mcexpr_amd.s
+2-2llvm/test/MC/AMDGPU/data.s
+23-2328 files not shown
+55-5534 files

LLVM/project 7c20e1dllvm/include/llvm/CodeGen SelectionDAG.h, llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp DAGCombiner.cpp

DAG: Use poison in getLoad/getStore for offsets

The painful part of this is due to a few unfortunate things.

1. poison is legalized to undef
2. Non-indexed load/store encode the offset as an undef (which is
   not like a TargetConstant, and does get legalized)
3. 2 asserts in DAGCombiner expect identical load/store nodes,
   which assumes the offset will be preserved and not converted
   between poison and undef
4. The getLoad/getStore overloads are a mess, and a path was missing
   to recreate the store case with the original offset.
DeltaFile
+36-20llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+11-10llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+7-7llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+12-0llvm/include/llvm/CodeGen/SelectionDAG.h
+4-4llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
+2-2llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+72-432 files not shown
+74-458 files

LLVM/project 0cce7a0llvm/test/CodeGen/AMDGPU mixed-vmem-types.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-sub.mir regbankselect-add.mir

AMDGPU/GlobalISel: Fix Vcc reg bank apply method for sgpr i1 input (#212532)

Need to clean up high bits on sgpr bool use, simlar to Sgpr32AExtBoolInReg.
G_AMDGPU_COPY_VCC_SCC assumes clean (zero) high bits in sgpr i32 input.
This should be combined away in most cases, for example if input is result
of a compare. But should stay for example for truncated input from s_load.
DeltaFile
+106-72llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
+60-20llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
+13-12llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
+14-10llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
+16-8llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
+8-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
+217-12615 files not shown
+292-15121 files

LLVM/project e062a29libcxx/docs/Status Cxx20Issues.csv, libcxx/test/std/numerics/numarray/template.valarray/valarray.access const_access.pass.cpp access.pass.cpp

[libc++] Mark LWG3133 as Complete and add valarray operator[] safety tests (#208145)

This verifies that libc++ has implemented the resolution of LWG3133,
which modernizes the requirements on `T` for `std::complex<T>` and
`std::valarray<T>` in [numeric.requirements].
- No code changes were needed for `std::valarray<T>`: its `operator[]`
already indexes through a raw pointer and never relies on a
user-overloadable `operator&`, so it already conforms to the revised
wording.
- Added o`perator_hijacker`-based tests to `valarray`'s
`access.pass.cpp`/`const_access.pass.cpp`, confirming `operator[]`
doesn't rely on a user-overloadable `operator&`.
DeltaFile
+6-0libcxx/test/std/numerics/numarray/template.valarray/valarray.access/const_access.pass.cpp
+6-0libcxx/test/std/numerics/numarray/template.valarray/valarray.access/access.pass.cpp
+1-1libcxx/docs/Status/Cxx20Issues.csv
+13-13 files

LLVM/project 61d6e49mlir/include/mlir/Dialect/Quant/IR QuantTypes.h, mlir/lib/Dialect/Quant/IR QuantTypes.cpp

QuantileType relax quantileType conditions and inheritance issue (#204793)

# Recategorize QuantileType as Storage Format, Not Quantization Scheme

## Summary

Reclassify `QuantileType` from inheriting `QuantizedType` to functioning
as a pure storage type.

## Motivation

### QuantileType is a Storage Format, Not a Quantization Scheme

After careful consideration, there was a conclusion reached that
**QuantileType should not be registered as a subtype of QuantizedType**.
The architectural distinction is critical:

- **QuantizedType** represents different quantization schemes (uniform,
per-axis, etc.), semantic operations that map values into a

    [25 lines not shown]
DeltaFile
+21-5mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h
+14-0mlir/test/Dialect/Quant/quantile-types.mlir
+3-3mlir/test/Dialect/Quant/invalid-quantile-types.mlir
+3-2mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
+41-104 files

LLVM/project 0878b66flang/include/flang/Optimizer/Transforms Passes.td, flang/lib/Optimizer/Passes CommandLineOpts.cpp

[flang] Remove legacy stack-arrays and memory-allocation-opt passes

The unified allocation-placement pass now supersedes both the heap-to-stack
stack-arrays pass and the stack-to-heap memory-allocation-opt pass, and is the
default in the FIR optimizer pipeline. Remove the two legacy passes: their
TableGen definitions, the MemoryAllocation.cpp source, the memory-allocation-opt
command-line options, the enable-allocation-placement fallback switch, and the
addMemoryAllocationOpt pipeline helper. The pass-only portions of
StackArrays.cpp are dropped while its analysis and rewrite pattern, now shared
with allocation-placement, are kept.

The legacy tests are retargeted onto allocation-placement to show it reproduces
both prior behaviors: the stack-arrays tests use "stack-arrays=true", and the
memory-allocation-opt tests use the default policy (runtime-sized and big
constant-size temporaries go on the heap).
DeltaFile
+0-150flang/lib/Optimizer/Transforms/MemoryAllocation.cpp
+0-71flang/lib/Optimizer/Transforms/StackArrays.cpp
+0-28flang/include/flang/Optimizer/Transforms/Passes.td
+0-22flang/lib/Optimizer/Passes/CommandLineOpts.cpp
+12-5flang/test/Fir/memory-allocation-opt.fir
+5-11flang/test/Fir/allocation-placement-pipeline.fir
+17-28713 files not shown
+33-32719 files

LLVM/project b95ce5ellvm/include/llvm/CodeGenTypes MachineValueType.h

[LLVM] Disambiguate MVT and SVT comparisons (#212711)

[LLVM] Disambiguate MVT and SVT comparisons

Without this:
```
error: use of overloaded operator '==' is ambiguous (with operand types 'MVT' and 'llvm::MVT::SimpleValueType')
  167 |       if (VT == MVT::Untyped)
      |           ~~ ^  ~~~~~~~~~~~~
llvm/include/llvm/CodeGenTypes/MachineValueType.h:62:10: note: candidate function
   62 |     bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
      |          ^
llvm/include/llvm/CodeGen/ValueTypes.h:598:15: note: candidate function (with reversed parameter order)
  598 |   inline bool operator==(MVT::SimpleValueType SVT, EVT VT) { return VT == SVT; }
      |               ^
1 error generated.
```

Fixes 52f6c88c2c1b6f0c10b9c8fb09ec35e147c593e3
DeltaFile
+4-0llvm/include/llvm/CodeGenTypes/MachineValueType.h
+4-01 files

LLVM/project 66cc921flang/docs fstack-arrays.md, flang/include/flang/Optimizer/Passes CommandLineOpts.h

[flang] Enable allocation-placement pass by default

Make the unified allocation-placement pass the default in the FIR optimizer
pipeline in place of the legacy stack-arrays and memory-allocation-opt passes,
by defaulting -enable-allocation-placement to true. Passing
-enable-allocation-placement=false restores the legacy passes for comparison.

Add a -disable-allocation-placement switch that skips the pass entirely (wired
through addAllocationPlacement like the other optimizer passes), so codegen
tests can opt out of placement policy independently of the legacy fallback.

Update the pipeline-dump tests to expect AllocationPlacement, and disable the
pass in the alloca/allocmem codegen tests (alloc.fir, coordinateof.fir) so they
keep testing lowering rather than placement policy. Document the unified pass,
its policy, thresholds, and options in fstack-arrays.md.
DeltaFile
+64-0flang/docs/fstack-arrays.md
+8-5flang/lib/Optimizer/Passes/Pipelines.cpp
+10-3flang/lib/Optimizer/Passes/CommandLineOpts.cpp
+6-6flang/test/Fir/allocation-placement-pipeline.fir
+6-2flang/include/flang/Optimizer/Passes/CommandLineOpts.h
+4-2flang/test/Fir/alloc.fir
+98-185 files not shown
+104-2311 files

LLVM/project 922d639flang/include/flang/Optimizer/Passes Pipelines.h CommandLineOpts.h, flang/lib/Optimizer/Passes Pipelines.cpp CommandLineOpts.cpp

[flang] Wire allocation-placement into the optimizer pipeline (experimental)

Add a hidden -enable-allocation-placement flag that, when set, replaces the
stack-arrays and memory-allocation-opt passes in the default FIR optimizer
pipeline with the unified allocation-placement pass. The flag is off by
default, so the legacy passes remain the default path and behavior is
unchanged.

When enabled, the pass runs with its default byte-size thresholds; the
-fstack-arrays strategy is forwarded through the new stackArrays option.
DeltaFile
+21-0flang/test/Fir/allocation-placement-pipeline.fir
+16-0flang/lib/Optimizer/Passes/CommandLineOpts.cpp
+11-1flang/lib/Optimizer/Passes/Pipelines.cpp
+12-0flang/include/flang/Optimizer/Passes/CommandLineOpts.h
+2-2flang/lib/Optimizer/Transforms/AllocationPlacement.cpp
+2-0flang/include/flang/Optimizer/Passes/Pipelines.h
+64-36 files

LLVM/project ebc5778offload/test CMakeLists.txt

[Offload] Enable offload test on Windows (#212480)

Description:
This change enables the offload test build on Windows by adding
compatibility guards around libomptarget test suites.

Why:
libomptarget is not available on Windows. Without these guards, CMake
fails when referencing the missing omptarget target. With these guards,
Windows builds complete successfully and run available tests (using
check-offload-unit), while Linux/macOS builds remain unaffected.
DeltaFile
+36-30offload/test/CMakeLists.txt
+36-301 files

LLVM/project 005c18eflang/include/flang/Optimizer/Transforms Passes.td AllocationPlacementPolicy.h, flang/lib/Optimizer/Transforms AllocationPlacement.cpp

[flang] Add policy-driven allocation-placement pass - memory passes unification [2/5] (#210742)

Introduce a new function-level pass, allocation-placement, that unifies
the stack/heap placement decisions currently split between the
stack-arrays and memory-allocation-opt passes. For each array allocation
it consults a policy to decide whether it should live on the stack
(fir.alloca) or the heap (fir.allocmem) and rewrites it accordingly,
reusing fir::replaceAllocas for stack-to-heap and the StackArrays
analysis/rewrite for heap-to-stack (so heap-to-stack only happens where
it is provably safe).

The default policy (AllocationPlacementPolicy.h) is threshold-driven:
- small constant-size arrays go on the stack within a per-function stack
budget, otherwise on the heap;
- big constant-size arrays: user variables stay on the stack,
temporaries go on the heap;
  - runtime-sized arrays go on the heap;
- an aggressive mode places all arrays on the stack (best effort). User
variables are distinguished from compiler temporaries via the presence

    [6 lines not shown]
DeltaFile
+324-0flang/lib/Optimizer/Transforms/AllocationPlacement.cpp
+90-0flang/include/flang/Optimizer/Transforms/AllocationPlacementPolicy.h
+84-0flang/test/Transforms/allocation-placement.fir
+29-0flang/test/Transforms/allocation-placement-budget.fir
+26-0flang/include/flang/Optimizer/Transforms/Passes.td
+24-0flang/test/Transforms/allocation-placement-stack-arrays-mode.fir
+577-02 files not shown
+586-08 files

LLVM/project 8cf39a9llvm/include/llvm/Frontend/OpenMP ConstructDecompositionT.h

[OpenMP] Fix ambiguous namespace lookup with delayed template parsing
DeltaFile
+1-1llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
+1-11 files

LLVM/project c90f91allvm/docs AMDGPUUsage.rst AMDGPUMemoryModel.md

add addrspace names, also update intrinsics to match AMDGPU Usage Manual
DeltaFile
+18-19llvm/docs/AMDGPUMemoryModel.md
+2-0llvm/docs/AMDGPUUsage.rst
+20-192 files

LLVM/project a6614eeclang/include/clang/APINotes Types.h, clang/lib/APINotes APINotesFormat.h APINotesReader.cpp

[APINotes] Diagnose invalid Where.Parameters selectors (#209408)

This PR adds diagnostics for exact `Where.Parameters` selectors on top
of the existing parsing, serialization, and Sema matching support.

It diagnoses duplicate exact selectors during API notes conversion,
including duplicate `Where.Parameters: []`, while still allowing broad
name-only entries and same-name entries with different selectors.

It also adds reader/Sema support to warn under `-Wapinotes` when an
exact selector in API notes does not match any visible overload. The
reader can now enumerate stored exact selectors for global functions and
C++ methods, and Sema compares those against the selector candidates
derived from the visible overload set.

The diagnostic path follows the same matching policy as Sema, including
the desugared alias fallback, so valid matched selectors do not produce
false warnings.


    [9 lines not shown]
DeltaFile
+239-0clang/test/APINotes/where-parameters-diagnostics.cpp
+135-0clang/lib/APINotes/APINotesReader.cpp
+121-0clang/include/clang/APINotes/Types.h
+108-0clang/lib/Sema/SemaAPINotes.cpp
+98-0clang/lib/Sema/SemaAPINotesInternal.h
+0-61clang/lib/APINotes/APINotesFormat.h
+701-615 files not shown
+792-6311 files

LLVM/project 17df429clang/test/AST/ByteCode builtin-object-size-codegen.cpp

[clang][bytecode][NFC] Add CHECK markers for functions in test (#212699)

We aren't testing the existence of the function in the output here, but
without these markers, debugging test failures here can become very
cumbersome.
DeltaFile
+7-2clang/test/AST/ByteCode/builtin-object-size-codegen.cpp
+7-21 files

LLVM/project 1a0baa2llvm/docs AMDGPUMemoryModel.md

fix copy-pasta
DeltaFile
+1-1llvm/docs/AMDGPUMemoryModel.md
+1-11 files

LLVM/project 9cd13c1llvm/lib/Target/X86 X86.td

[X86] Remove TuningFastSHLDRotate from BMI2 targets (#211217)

This flag has no effect at `x86-64-v3` or `v4`. It only enables a pseudo
that lowers `rotl`/`rotr` by immediate to `shld $imm, %reg, %reg`, but a
higher-priority `RORX` pattern matches the same case and always wins the
iSel tie.

Both patterns match `rotl(GR64, imm)`; only their `AddedComplexity`
differs:

```
// X86InstrShiftRotate.td:507 -- SHLD-rotate pseudo, complexity 5
let Predicates = [HasFastSHLDRotate], AddedComplexity = 5, ... in {
  def SHLDROT64ri : ... [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
}

// X86InstrShiftRotate.td:602 -- RORX pattern, complexity 10, only needs BMI2
let AddedComplexity = 10 in {
  def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),

    [7 lines not shown]
DeltaFile
+0-7llvm/lib/Target/X86/X86.td
+0-71 files

LLVM/project c6ea16dllvm/docs AMDGPUMemoryModel.md

[Docs][AMDGPU] availability/visibility in addrspace(3)

addrspace(3) on AMDGPU corresponds to LDS, which is a fast memory directly
accessed by all threads in a workgroup (there is no intervening cache). Thus,
any accesses to this addrspace have built-in availability and visibility at
"workgroup" scope.
DeltaFile
+50-17llvm/docs/AMDGPUMemoryModel.md
+50-171 files

LLVM/project f7d75bfllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel atomic_optimizations_mul_one.ll

Add missed optimization: Remove redundant S_MUL instrs
DeltaFile
+366-30llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
+66-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+432-322 files

LLVM/project 98d4a86llvm/lib/Target/AMDGPU GCNSubtarget.h AMDGPU.td

AMDGPU: Add supports-wgp subtarget feature

Whether the hardware supports WGP (work-group processor) execution mode is a
fixed per-GPU capability, distinct from the per-kernel cumode selection. Add
a dedicated feature instead of inferring from the generation and instructions.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+10-0llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
+4-4llvm/lib/Target/AMDGPU/AMDGPU.td
+0-6llvm/lib/Target/AMDGPU/GCNSubtarget.h
+14-103 files

LLVM/project acd22eeclang/lib/AST/ByteCode Record.h Interp.cpp

[clang][bytecode][NFC] Add Record::findField to look up fields by offset (#212697)
DeltaFile
+9-0clang/lib/AST/ByteCode/Record.cpp
+1-7clang/lib/AST/ByteCode/Pointer.cpp
+1-4clang/lib/AST/ByteCode/Interp.cpp
+3-0clang/lib/AST/ByteCode/Record.h
+14-114 files

LLVM/project b2b5c13clang-tools-extra/docs/clang-tidy/checks/modernize redundant-void-arg.md

[clang-tidy][docs] Fix broken redundant-void-arg documentation. NFC. (#212692)
DeltaFile
+9-8clang-tools-extra/docs/clang-tidy/checks/modernize/redundant-void-arg.md
+9-81 files