LLVM/project aa31efc — libclc/opencl/lib/clspv/shared vstore_half.cl

by Romaric Jodin via GitHub on ⎇
[libclc] use clc functions in clspv/shared/vstore_half.cl (#171770)
DeltaFile
+18-12libclc/opencl/lib/clspv/shared/vstore_half.cl
+18-121 files

LLVM/project 2ce17ba — llvm/lib/Analysis CmpInstAnalysis.cpp, llvm/lib/Transforms/InstCombine InstCombineAndOrXor.cpp InstCombineCompares.cpp

by Tirthankar Mazumder via GitHub on ⎇
[InstCombine][CmpInstAnalysis] Use consistent spelling and function names. NFC. (#171645)

Both `decomposeBitTestICmp` and `decomposeBitTest` have a parameter
called `lookThroughTrunc`. This was spelled in full (i.e. `lookThroughTrunc`)
in the header. However, in the implementation, it's written as `lookThruTrunc`.

I opted to convert all instances of `lookThruTrunc` into
`lookThroughTrunc` to reduce surprise while reading the code and for
conformity.

---

The other change in this PR is the renaming of the wrapper around
`decomposeBitTest()`. Even though it was a wrapper around
`CmpInstAnalysis.h`'s `decomposeBitTest`, the function was called
`decomposeBitTestICmp`. This is quite confusing because such a function
_also_ exists in `CmpInstAnalysis.h`, but it is _not_ the one actually
being used in `InstCombineAndOrXor.cpp`.
DeltaFile
+6-6llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+4-4llvm/lib/Analysis/CmpInstAnalysis.cpp
+1-1llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+11-113 files

LLVM/project 39a723e — mlir/lib/Dialect/Linalg/Transforms Specialize.cpp, mlir/lib/Dialect/Linalg/Utils Utils.cpp

by Abhishek Varma via GitHub on ⎇
[Linalg] Add *Conv2D* matchers (#168362)

-- This commit is the fourth in the series of adding matchers
for linalg.*conv*/*pool*. Refer:
https://github.com/llvm/llvm-project/pull/163724
-- In this commit all variants of Conv2D convolution ops have been
   added.
-- It also refactors the way these matchers work to make adding more
matchers concise.

Signed-off-by: Abhishek Varma <abhvarma at amd.com>

---------

Signed-off-by: Abhishek Varma <abhvarma at amd.com>
Signed-off-by: hanhanW <hanhan0912 at gmail.com>
Co-authored-by: hanhanW <hanhan0912 at gmail.com>
DeltaFile
+558-11mlir/lib/Dialect/Linalg/Utils/Utils.cpp
+218-4mlir/test/Dialect/Linalg/convolution/roundtrip-convolution.mlir
+15-0mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
+791-153 files

LLVM/project 6a25e45 — llvm/lib/Analysis ConstantFolding.cpp, llvm/test/Transforms/InstSimplify ptrtoaddr.ll

by Nikita Popov via GitHub on ⎇
[ConstantFolding] Support ptrtoaddr in ConstantFoldCompareInstOperands (#162653)

This folds `icmp (ptrtoaddr x, ptrtoaddr y)` to `icmp (x, y)`, matching
the existing ptrtoint fold. Restrict both folds to only the case where
the result type matches the address type.
    
I think that all folds this can do in practice end up actually being
valid for ptrtoint to a type large than the address size as well, but I
don't really see a way to justify this generically without making
assumptions about what kind of folding the recursive calls may do.

This is based on the icmp semantics specified in
https://github.com/llvm/llvm-project/pull/163936.
DeltaFile
+82-0llvm/test/Transforms/InstSimplify/ptrtoaddr.ll
+12-10llvm/lib/Analysis/ConstantFolding.cpp
+94-102 files

LLVM/project c9648d7 — llvm/lib/IR Verifier.cpp, llvm/test/Assembler ptrtoaddr-invalid-constexpr.ll

by Nikita Popov via GitHub on ⎇
[Verifier] Make sure all constexprs in instructions are visited (#171643)

Previously this only happened for constants of some types and missed
incorrect ptrtoaddr.
DeltaFile
+17-3llvm/test/Assembler/ptrtoaddr-invalid-constexpr.ll
+5-8llvm/lib/IR/Verifier.cpp
+22-112 files

LLVM/project 4882029 — llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/InstCombine mul.ll

by Adar Dagan via GitHub on ⎇
[ValueTracking] Enhance overflow computation for unsigned mul (#171568)

Changed the range computation in computeOverflowForUnsignedMul to use
computeConstantRange as well.

This expands the patterns that InstCombine manages to narrow a mul that
has values that come from zext, for example if a value comes from a div
operation then the known bits doesn't give the narrowest possible range
for that value.

---------

Co-authored-by: Adar Dagan <adar.dagan at mobileye.com>
DeltaFile
+28-0llvm/test/Transforms/InstCombine/mul.ll
+5-5llvm/lib/Analysis/ValueTracking.cpp
+33-52 files

LLVM/project cb4b6ad — clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

by Jasmine Tang via GitHub on ⎇
[CIR] Add the ability to detect if SwitchOp covers all the cases (#171246)
DeltaFile
+35-13clang/test/CIR/CodeGen/switch.cpp
+0-38clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+31-1clang/test/CIR/IR/switch.cir
+13-4clang/include/clang/CIR/Dialect/IR/CIROps.td
+5-5clang/test/CIR/Transforms/switch-fold.cir
+3-3clang/test/CIR/CodeGen/atomic.c
+87-642 files not shown
+90-658 files

LLVM/project 45e7dab — mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

by skc7 on ⎇
Mark mlir->llvmir translation for num_threads with dims as NYI
DeltaFile
+14-1mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+14-11 files

LLVM/project 3d4264e — mlir/include/mlir/Dialect/OpenMP OpenMPClauses.td, mlir/lib/Conversion/SCFToOpenMP SCFToOpenMP.cpp

by skc7 on ⎇
[OpenMP][MLIR] Add num_threads clause with dims modifier support
DeltaFile
+72-7mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+47-3mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
+32-1mlir/test/Dialect/OpenMP/invalid.mlir
+10-5mlir/test/Dialect/OpenMP/ops.mlir
+2-0mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
+163-165 files

LLVM/project 4f9d5a8 — llvm/lib/Target/RISCV RISCVLoadStoreOptimizer.cpp, llvm/test/CodeGen/RISCV xqcilsm-lwmi-swmi.mir

by Sudharsan Veeravalli via GitHub on ⎇
[RISCV] Generate Xqcilsm LWMI/SWMI load/store multiple instructions (#171079)

This patch adds support for generating the Xqcilsm load/store multiple
instructions as a part of the RISCVLoadStoreOptimizer pass. For now we
only combine two load/store instructions into a load/store multiple.
Support for converting more loads/stores will be added in follow-up
patches. These instructions are only applicable for 32-bit loads/stores
with an alignment of 4-bytes.
DeltaFile
+315-0llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir
+112-10llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+427-102 files

LLVM/project 426cedc — llvm/lib/Target/LoongArch LoongArchInstrInfo.td LoongArchInstrFormats.td, llvm/lib/Target/LoongArch/Disassembler LoongArchDisassembler.cpp

by hev via GitHub on ⎇
[LoongArch] Add support for the ud macro instruction (#171583)

This patch adds support for the `ud ui5` macro instruction. The `ui5`
operand must be inthe range `0-31`. The macro expands to:

`amswap.w $rd, $r1, $rj`

where `ui5` specifies the register number used for `$rd` in the expanded
instruction, and `$rd` is the same as `$rj`.

Relevant binutils patch:

https://sourceware.org/pipermail/binutils/2025-December/146042.html
DeltaFile
+23-0llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
+10-7llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+13-1llvm/test/MC/LoongArch/Basic/Integer/misc.s
+13-0llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
+1-1llvm/test/CodeGen/LoongArch/trap.ll
+60-95 files

LLVM/project 71bfdd1 — clang/lib/CodeGen CGStmt.cpp, clang/test/CodeGen defer-ts.c defer-ts-nested-cleanups.c

by Sirraide via GitHub on ⎇
[Clang] Add support for the C `_Defer` TS (#162848)

This implements WG14 N3734 (https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3734.pdf),
aka `_Defer`; it is currently only supported in C if `-fdefer-ts` is passed.
DeltaFile
+652-0clang/test/CodeGen/defer-ts.c
+179-0clang/test/CodeGen/defer-ts-nested-cleanups.c
+172-0clang/test/Sema/defer-ts.c
+85-0clang/lib/CodeGen/CGStmt.cpp
+58-0clang/test/Parser/defer-ts.c
+52-0clang/test/Sema/defer-ts-sjlj.c
+1,198-040 files not shown
+1,667-846 files

LLVM/project 3b04094 — llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVISelDAGToDAG.cpp

by Craig Topper via GitHub on ⎇
[RISCV] Add Xsfmm vlte and vste intrinsics to getTgtMemIntrinsics. (#171747)

Replace dyn_cast with cast. The dyn_cast can never fail now. Previously
it never succeeded.
DeltaFile
+54-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-2llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+56-22 files

LLVM/project e795b8b — llvm/lib/Target/RISCV RISCVInstrInfoA.td

by Craig Topper via GitHub on ⎇
[RISCV] Use GPR instead of ixlenimm for sextshamt in PseudoMaskedAMOMinMax. NFC (#171736)

This operand is always a register.
DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+2-21 files

LLVM/project a19badb — clang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst

by Florian Mayer on ⎇
doc

Created using spr 1.3.7
DeltaFile
+3-2clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+3-21 files

LLVM/project 0c934ba — llvm/test/tools/llvm-mca/AArch64/Neoverse V2-neon-instructions.s V3-neon-instructions.s

by Florian Mayer on ⎇
address comments

Created using spr 1.3.7
DeltaFile
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s
+5,340-7,2931,495 files not shown
+44,622-34,7501,501 files

LLVM/project 43c78d0 — llvm/test/tools/llvm-mca/AArch64/Neoverse V3AE-neon-instructions.s V3-neon-instructions.s

by Florian Mayer on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s
+1,000-1,084llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s
+5,340-7,2931,491 files not shown
+44,480-34,6081,497 files

LLVM/project 18b6137 — clang/lib/Basic/Targets PPC.h, llvm/include/llvm/TargetParser Triple.h

by Harald van Dijk via GitHub on ⎇
[NFC] isOSGlibc: musl is not glibc. (#171734)

Previously, `isOSGlibc()` was returning true for musl triples as well.
This commit changes `isOSGlibc()` to return false for musl triples, and
updates all existing `isOSGlibc()` checks to call `isOSGlibc() ||
isMusl()`, in order to preserve existing behaviour.
DeltaFile
+2-2llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+2-2llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+2-2clang/lib/Basic/Targets/PPC.h
+2-1llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+1-1llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+1-1llvm/include/llvm/TargetParser/Triple.h
+10-91 files not shown
+11-97 files

LLVM/project fa92475 — llvm/lib/Target/RISCV RISCVInstrInfoA.td RISCVInstrInfo.cpp, llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.h

by Craig Topper via GitHub on ⎇
[RISCV] Add an OperandType for ordering for atomic pseudos. (#171744)
DeltaFile
+14-6llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+3-0llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+2-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+19-63 files

LLVM/project d7c3021 — llvm/lib/Target/LoongArch/Disassembler LoongArchDisassembler.cpp, llvm/test/MC/LoongArch/Basic/Integer misc.s

by WANG Rui on ⎇
Address weining's comments
DeltaFile
+9-9llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
+6-1llvm/test/MC/LoongArch/Basic/Integer/misc.s
+15-102 files

LLVM/project a8f6c51 — mlir/lib/Dialect/XeGPU/Transforms XeGPUWgToSgDistribute.cpp XeGPUPropagateLayout.cpp, mlir/test/Dialect/XeGPU xegpu-wg-to-sg.mlir

by Jianhui Li on ⎇
adjust the layout for expandedUnitDims and wg-to-sg distribution shapecast op
DeltaFile
+46-29mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+17-0mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
+0-4mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+1-1mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+64-344 files

LLVM/project 2614af0 — clang/lib/Tooling Tooling.cpp, clang/unittests/Tooling ToolingTest.cpp

by mitchell via GitHub on ⎇
[Tooling] Fix misleading progress report when files have multiple compile commands (#169640)

This patch fixes an issue in progress reporting where the processed item
counter could exceed the total item count, leading to confusing outputs
like [22/18].

Closes [#169168](https://github.com/llvm/llvm-project/issues/169168)
DeltaFile
+133-0clang/unittests/Tooling/ToolingTest.cpp
+19-12clang/lib/Tooling/Tooling.cpp
+152-122 files

LLVM/project 3fdce79 — libunwind/src UnwindCursor.hpp

by Brad Smith via GitHub on ⎇
[libunwind] fix building on Haiku i386 (#171586)

Co-authored-by: Jérôme Duval <jerome.duval at gmail.com>
DeltaFile
+3-2libunwind/src/UnwindCursor.hpp
+3-21 files

LLVM/project 76ae530 — compiler-rt/test/builtins/Unit/ppc fixunstfti_test.c fixtfti_test.c

by Wael Yehia on ⎇
[PPC] XFAIL ppc/fixtfti_test.c and ppc/fixunstfti_test.c and track them under issue 171751
DeltaFile
+1-0compiler-rt/test/builtins/Unit/ppc/fixunstfti_test.c
+1-0compiler-rt/test/builtins/Unit/ppc/fixtfti_test.c
+2-02 files

LLVM/project 1f07f7c — flang-rt/lib/cuda allocatable.cpp pointer.cpp, flang/lib/Lower Allocatable.cpp

by Valentin Clement (バレンタイン クレメン) via GitHub on ⎇
[flang][cuda] Add support for allocate with device source (#171743)

Add support for allocate statement with a source that is a device
variable.
DeltaFile
+16-8flang-rt/lib/cuda/allocatable.cpp
+8-6flang-rt/lib/cuda/pointer.cpp
+10-3flang/lib/Lower/Allocatable.cpp
+9-0flang/test/Lower/CUDA/cuda-allocatable.cuf
+0-9flang/test/Lower/CUDA/TODO/cuda-allocate-source-device.cuf
+5-2flang/test/Fir/CUDA/cuda-allocate.fir
+48-284 files not shown
+63-3610 files

LLVM/project ba73d60 — llvm/lib/Target/RISCV RISCVInstrInfoXRivos.td

by Craig Topper via GitHub on ⎇
[RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)

This enables MachineVerifier and MachineIR printing support for these
operands.
DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+2-21 files

LLVM/project 16e6055 — llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/DebugInfo/X86 selectionDAG-load-sext-trunc.ll selectionDAG-load-sext.ll

by Shubham Sandeep Rastogi via GitHub on ⎇
Revert "[SelectionDAG] Salvage debuginfo when combining load and sext… (#171745)

… instrs. (#169779)"

This reverts commit 2b958b9ee24b8ea36dcc777b2d1bcfb66c4972b6.

I might have broken the sanitizer-x86_64-linux bot


/home/b/sanitizer-x86_64-linux/build/llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_linux.cpp
clang++:
/home/b/sanitizer-x86_64-linux/build/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:248:
const T &llvm::ArrayRef<llvm::DbgValueLocEntry>::operator[](size_t)
const [T = llvm::DbgValueLocEntry]: Assertion `Index < Length &&
"Invalid index!"' failed.
DeltaFile
+0-70llvm/test/DebugInfo/X86/selectionDAG-load-sext-trunc.ll
+0-61llvm/test/DebugInfo/X86/selectionDAG-load-sext.ll
+2-39llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+2-1703 files

LLVM/project 1dd78d7 — lldb/source/Interpreter CommandInterpreter.cpp, lldb/test/API/functionalities/breakpoint/breakpoint_command TestRegexpBreakCommand.py

by Alex Richardson on ⎇
rebase after fix landed

Created using spr 1.3.8-beta.1
DeltaFile
+88-0lldb/source/Interpreter/CommandInterpreter.cpp
+29-18llvm/utils/TableGen/Common/InfoByHwMode.cpp
+22-6lldb/test/API/functionalities/breakpoint/breakpoint_command/TestRegexpBreakCommand.py
+21-0llvm/test/TableGen/RegClassByHwModeErrors.td
+7-7llvm/test/CodeGen/AArch64/tbi.ll
+6-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+173-322 files not shown
+175-348 files

LLVM/project 055bfc4 — lldb/source/Interpreter CommandInterpreter.cpp, lldb/test/API/functionalities/breakpoint/breakpoint_command TestRegexpBreakCommand.py

by Alex Richardson on ⎇
clang-format

Created using spr 1.3.8-beta.1
DeltaFile
+88-0lldb/source/Interpreter/CommandInterpreter.cpp
+29-18llvm/utils/TableGen/Common/InfoByHwMode.cpp
+22-6lldb/test/API/functionalities/breakpoint/breakpoint_command/TestRegexpBreakCommand.py
+21-0llvm/test/TableGen/RegClassByHwModeErrors.td
+7-7llvm/test/CodeGen/AArch64/tbi.ll
+6-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+173-322 files not shown
+175-348 files

LLVM/project 62aaa3a — llvm/runtimes CMakeLists.txt

by Wael Yehia via GitHub on ⎇
[compiler-rt] follow-up to 166837, rename COMPILER_RT_FORCE_TEST_BUILTINS_DIR to COMPILER_RT_TEST_BUILTINS_DIR (#171741)

Co-authored-by: David Tenty <daltenty at ibm.com>
DeltaFile
+2-2llvm/runtimes/CMakeLists.txt
+2-21 files