[llubi] Reset retval for noop inline asm (#230849)
When a call is followed by a call to noop inline asm, `setResult` inside
`returnFromCallee` will reuse the previous return value (moved) and
trigger assertions.
The test is generated by DeepSeek-V4.1-Flash.
[llubi] Use correct tag bitwidth to recover provenances (#230852)
Tag always uses the pointer width rather than the padded one. Previously
the tag lookup always missed due to the width mismatch.
The test is generated by DeepSeek-V4.1-Flash.
[llubi] Fix wrong assert when writing `poison` at an unaligned bit offset (#230819)
Writing `poison` that starts at a bit offset not a multiple of 8 and
spans more than one byte could trigger an assert, even though each write
stayed within a single byte.
- `Context::toBytes` marks bits as `poison` one byte at a time, from
`OffsetInBits + I`.
- The assert checked the bits from `OffsetInBits` instead, missing the
offset `I`.
[libc++][chrono][threading] Implement LWG 3504: `condition_variable::wait_for` is overspecified (#222443)
Implement the relative-to-absolute conversion mandated by LWG 3504 using
`ceil<steady_clock::duration>` to avoid precision loss with
floating-point
durations.
- Add internal `chrono::__ceil` (usable in all dialects) and make
`chrono::ceil`
forward to it.
- Introduce `__rel_to_abs` helper and update all `wait_for` overloads on
`condition_variable` / `condition_variable_any`.
- Move the previous nanosecond conversion into `__do_timed_wait` to
avoid recursion after the change.
- Add regression tests for floating-point durations.
Fixes #189807
[Analysis][ARM] Remove unused getNumBytesToPadGlobalArray (NFC) (#230912)
The last caller of TargetTransformInfo::getNumBytesToPadGlobalArray was
removed on June 30, 2025 in commit
183acdd27985afd332463e3d9fd4a2ca46d85cf1, leaving
TargetTransformInfoImplBase::getNumBytesToPadGlobalArray,
ARMTTIImpl::getNumBytesToPadGlobalArray, and the command-line option
UseWidenGlobalArrays unused as well.
Assisted-by: Antigravity
TwoAddressInstructions: Keep undef INSERT_SUBREG lanes defined
%reg = INSERT_SUBREG undef %reg, %subreg, subidx defines all of %reg, so
reading the lanes outside subidx afterwards is valid. Rewriting it to
undef %reg.subidx = COPY %subreg narrows the definition to subidx and
leaves those reads without a live subrange, failing the "No live subrange
at use"
machine verifier check.
When a subrange outside subidx is still live past the def, insert an
IMPLICIT_DEF of the full register and drop the undef flag. In the common
case, where the lanes the INSERT_SUBREG left undefined are dead, keep the
undef flag and avoid an IMPLICIT_DEF that survives to the end of codegen
when the COPY is not coalesced.
Co-authored-by: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
CodeGen: Remove stale last-block case when splitting a critical edge
Before f264f9ad7df5, a new block at the end of the function began at the
old end index, so the isLastMBB case had to extend live-out intervals
over it. Now the new block always ends at the old end index, so they
already cover it. The extension became a no-op, and the case also
skipped trimming registers not live into the successor, leaving a dead
segment.
block-placement.ll needs a volatile store to keep its nested loop.
common-chain.ll gets shrink-wrapped.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[GlobalISel] [AArch64] Support ROTR shift amount masking in SelectShiftMask (#226579)
The RORV instructions already use the Shift multiclass, so they inherit
the shiftMask32/shiftMask64 ComplexPattern patterns added in the earlier
patches, giving them AND/ADD/SUB/NEG/MVN shift-amount optimization for
free.
This patch adds one additional pattern for the 32-bit rotate case, where
GlobalISel legalizes the shift amount with a zext to i64. The pattern
peeks through the zext to apply the 32-bit shift-amount masking:
(i32 (rotr GPR32, (i64 (zext (i32 shiftMask32)))))
This completes the set of shift-amount optimizations (AND mask, ADD/SUB
mod, NEG, MVN, ROTR) needed to eventually replace tryShiftAmountMod, as
tracked in #224245.
Depends on https://github.com/llvm/llvm-project/pull/226273
[AMDGPU] Limit the fmul fusion discount to a matching context type
The fmul is free when its context instruction feeds a fusable fadd or
fsub. A vector fmul priced with a scalar lane as the context inherits
that fusion only when it is emitted lane by lane. On a packed type the
scalar user does not show that the vector fmul feeds a vector fadd, and
products extracted into a scalar fadd chain keep the packed fmul while
the fma is lost.
CodeGen: Merge TargetLoweringObjectFile::getModuleMetadata into initialize
getModuleMetadata had a single caller, which invoked it immediately after
Initialize. Pass the module to Initialize and fold it in. Also lowercase the
name while touching all the uses.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
CodeGen: Initialize TargetLoweringObjectFile from MachineModuleInfo (#226836)
MachineModuleInfo passes TLOF to the MCContext but nothing initialized it until the
AsmPrinter pass ran, so every codegen pass in between saw it uninitialized. Initialize
it from MachineModuleInfo, and drop the calls llc and SPIRVTranslate used to work
around this.
SPIRVTranslate's MachineModuleInfoWrapperPass was never passed on to
addPassesToEmitFile, so it was initializing a throwaway context.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
[RISCV] Fix FP properties for Zvbdota instructions (#228737)
Mark floating-point Zvbdota instructions as potentially raising FP
exceptions. Add an implicit FRM use to vfbdota.vv, which uses the
dynamic rounding mode.
AI Usage: Assisted by AmpCode (6.1 Sol)
Co-authored-by: Amp <amp at ampcode.com>
[clang] Replace PointerUnion::dyn_cast with llvm::dyn_cast (NFC) (#230911)
PointerUnion::dyn_cast has been soft-deprecated in favor of
llvm::dyn_cast and llvm::dyn_cast_if_present. This patch replaces the
former with llvm::dyn_cast where the operand is guaranteed to be
nonnull.
Note that PlaceholderBase::ParamOrMethod is always initialized to a
nonnull pointer in LoanManager::getOrCreatePlaceholderBase and never
modified afterward.
Assisted-by: Antigravity
[libc++] Implement LWG2991: variant copy constructor missing noexcept(see below) (#230241)
LWG2991 adds a conditional `noexcept` to the variant's copy constructor.
A small example to illustrate the issue:
```cpp
static_assert(!std::is_trivially_copy_constructible_v<std::shared_ptr<int>>);
static_assert(std::is_copy_constructible_v<std::shared_ptr<int>>);
static_assert(std::is_nothrow_copy_constructible_v<std::shared_ptr<int>>);
static_assert(!std::is_trivially_move_constructible_v<std::shared_ptr<int>>);
static_assert(std::is_move_constructible_v<std::shared_ptr<int>>);
static_assert(std::is_nothrow_move_constructible_v<std::shared_ptr<int>>);
using Variant = std::variant<int,std::shared_ptr<int>>;
static_assert(std::is_nothrow_copy_constructible_v<Variant>); // false, should be true
static_assert(std::is_nothrow_move_constructible_v<Variant>);
```
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[llubi] Check UB before handling ret attributes (#230842)
Some code paths return AnyValue() on UB (e.g., calling function
declarations not recognized as libfunc). Check this before handling ret
attributes to avoid operating on incompatible values.
The test is generated by DeepSeek-V4.1-Flash.
[AMDGPU] Insert wmma coexec aware anti-hints rules (#226397)
This patch ports the downstream coexec anti-hint insertion to upstream
as rule-based insertion in the AMDGPU pre-ra anti-hints framework. It
adds gfx1250x anti-hint rules for wmma coexec hazards such as A/B source
war, swmmac index war, dest waw), trans source war, memory-address war
etc. Each rule builds anti-hints relationship for the register allocator
to keep hazardous registers in different physical registers so the
hazard recognizer and waitcnt inserter need less nop and waits.
Co-authored-by: Jeffrey Byrnes <jrbyrnes1989 at gmail.com>
Depends on #218075
AMDGPU: Don't use PressureDiffs with implicit allocatable physregs
canUsePressureDiffs skipped all implicit operands, so instructions
reading an allocatable physreg implicitly (e.g., vcc on v_cndmask_b32)
used the cached PressureDiff. PressureDiffs assume a single use for
physregs (see the FIXME in ScheduleDAGMILive::updatePressureDiffs), so
the pressure was added for each user. With several users in a region, the
SGPR pressure was overestimated and failed the expensive checks pressure
validation.
Fall back to the RegPressureTracker for implicit operands of
allocatable physregs, which are the ones it tracks.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[ARM] Implement CRC32 const folding (#230751)
This implements constant folding for __crc32 intrinsics in 32-bit ARM
targets when both the arguments are compile time known constants.
This is a follow up of https://github.com/llvm/llvm-project/pull/228985
which does the same for AArch64.
[Support] Fix SpecificBumpPtrAllocator move assignment leak (#230480)
Move assignment releases the destination's storage without destroying
its objects, leaking resources they own.
Call `DestroyAll()` before replacing the destination's storage.
Testing on Linux with GCC 11.4.0, Release with assertions enabled:
- `AllocatorTest.*`: 15 passed. The new regression test fails with the
original header and passes with the fix.
- Support unit tests via `llvm-lit`: 1842 passed, 13 skipped, no
failures.
- ASan/LSan reproducer: a 512-byte leak with the original header; no
sanitizer report with the fix.
- Additional ASan/LSan checks for destruction, move construction, empty
and
populated destinations, multiple slabs, and custom-sized slabs passed.
Assisted-by: Codex
[ProfileData] Move ProfCorrelatorKind out of InstrProfCorrelator (#230883)
For coverage and PGO, `clang -mllvm
-profile-correlate={debug-info,binary}` moves the per-function profile
metadata out of the memory image at runtime.
After the cl::opt to TableGen migration (#230746),
InstrumentationOptions.h includes InstrProfCorrelator.h only for this
enum, adding about 0.25s to each Instrumentation TU. Fix the compile
time regression by moving the type to its own header as a scoped enum.
LLM-aided
Simplify iterator lowering and trim duplicate tests
Use capture-only iterator callbacks and bind induction variables as block
arguments are created, eliminating the temporary induction-value vector.
Remove unused-iterator HLFIR cases covered by the per-locator and LLVM
checks. Reduce repeated stride diagnostics and remove unused declarations
from the positive AFFINITY tests.
[CIR] Implement ViewLikeOpInterface for multiple Ops
We implement ViewLikeOpInterface for dyn_cast, ptr_stride, get_member,
get_element, get_runtime_member, base_class_addr, derived_class_addr,
and memonic. Although there is no user for CIR internally as
decouplePointer returns the base and offset instead of the base
directly, it is still useful for external project to do aliasing
analysis for MemRef.
[AMDGPU] Use 8-bit barrier member count on GFX13
GFX13 widens the barrier member count in M0 to 8 bits for cluster
named barriers. s_barrier_init and s_barrier_signal_var lowering
masked it to 6 bits, truncating counts above 63.
Change-Id: I33571d2ed499ebe168571c6b4cd5d0e3340f8a0f
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[flang][cuda] share runtime type info between host and device under managed memory (#229213)
With -gpu=mem:managed, descriptors can live in managed memory, so a
descriptor built on the device may be read on the host. The type
descriptor address in its addendum then pointed at the device copy of
the type info, and host code dereferencing it crashed.
Make the host copy of the type info the single shared copy:
- Add the cuf-shared-type-info pass. It makes host type-info globals
writable, places them in the __nv_type_info section, and drops
acc.declare from type info on both host and device so that OpenACC
declare constructors no longer copy it to the device. For each type
descriptor used in the GPU module, it creates a managed pointer
global <dt>Xhostaddr<tag>. The tag is a per-unit hash, which keeps
the name unique when each unit has its own device module. The GPU
module gets a cuf.shared_type_descs dictionary mapping each type
descriptor to its pointer.
- CUFAddConstructor: add the cuda-managed-type-info option. It
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