LLVM/project 32dcaa6llvm/lib/Target/AMDGPU GCNSubtarget.h AMDGPUSubtarget.h

[NFCI][AMDGPU] Use `GET_SUBTARGETINFO_MACRO` in `GCNSubtarget.h`
DeltaFile
+9-295llvm/lib/Target/AMDGPU/GCNSubtarget.h
+18-44llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+14-11llvm/lib/Target/AMDGPU/R600Subtarget.h
+7-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-3llvm/lib/Target/AMDGPU/R600Processors.td
+1-1llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
+52-3592 files not shown
+53-3628 files

LLVM/project 2192fb2clang/lib/CIR/CodeGen CIRGenModule.cpp

le format monseiur
DeltaFile
+3-4clang/lib/CIR/CodeGen/CIRGenModule.cpp
+3-41 files

LLVM/project 3d2b769clang/lib/CIR/CodeGen CIRGenModule.cpp TargetInfo.cpp, clang/test/CIR/CodeGen/CUDA filter-decl.cu nvptx-basic.cu

[CIR][CUDA] Add NVPTX target info and CUDA/HIP global emission filtering
DeltaFile
+66-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+37-0clang/test/CIR/CodeGen/CUDA/filter-decl.cu
+30-0clang/test/CIR/CodeGen/CUDA/nvptx-basic.cu
+19-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+4-0clang/lib/CIR/CodeGen/CIRGenModule.h
+2-0clang/lib/CIR/CodeGen/TargetInfo.h
+158-06 files

LLVM/project 402ee51llvm/lib/Target/AMDGPU SILowerControlFlow.cpp, llvm/test/CodeGen/AMDGPU si-lower-control-flow-preserve-dom-tree.mir

[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are removed (#176691)

I would think the "applyUpdates" API should also take care of deleting
the nodes from the analyses objects but this does not seem to be the
case. https://godbolt.org/z/38a7rfzjd shows an example where
SILowerControlFlow removes a basic block which is not removed in the
Post dominator tree.
DeltaFile
+65-0llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
+5-0llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+70-02 files

LLVM/project cf9adf5clang/lib/Format FormatTokenLexer.cpp, clang/unittests/Format TokenAnnotatorTest.cpp FormatTestJava.cpp

[clang-format] Handle \\""" at end of Java text block (#177736)

DeltaFile
+8-3clang/lib/Format/FormatTokenLexer.cpp
+9-0clang/unittests/Format/TokenAnnotatorTest.cpp
+7-0clang/unittests/Format/FormatTestJava.cpp
+24-33 files

LLVM/project 3c4ce40llvm/lib/Target/RISCV RISCVInstrInfoV.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Use decodeVMaskReg for VMaskCarryInOp. NFC (#177742)

After #177678 we don't need DecodeVMV0RegisterClass to reject vm=1
cases. All instructions that use VMaskCarryInOp have set vm=0 in their
tablegen classes.
DeltaFile
+0-10llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+4-0llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+4-102 files

LLVM/project 0515a5dllvm/lib/Target/AArch64 MachineSMEABIPass.cpp

[AArch64][SME] Use LibcallLoweringInfo in the MachineSMEABIPass (#177762)

This adds a new helper to add calls to SME routines (addSMELibCall) and
check they are using the expected CC.

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+50-30llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+50-301 files

LLVM/project f255beclibc/shared/math tanf.h, libc/src/__support/math tanf.h CMakeLists.txt

[libc][math] Refactor tanf implementation to header-only in src/__support/math folder. (#177730)

Part of #147386

in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
DeltaFile
+164-0libc/src/__support/math/tanf.h
+2-138libc/src/math/generic/tanf.cpp
+17-8utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+23-0libc/shared/math/tanf.h
+16-0libc/src/__support/math/CMakeLists.txt
+1-10libc/src/math/generic/CMakeLists.txt
+223-1563 files not shown
+226-1569 files

LLVM/project 49d464cclang-tools-extra/clang-tidy/llvm UseVectorUtilsCheck.cpp UseVectorUtilsCheck.h, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Add llvm-use-vector-utils (#177722)

This new check suggests the following replacements:
* `llvm::to_vector(llvm::map_range(X, Fn))` -> `llvm::map_to_vector(X,
Fn)`
* `llvm::to_vector(llvm::make_filter_range(X, Fn))` ->
`llvm::filter_to_vector(X, Fn)`
and add the `SmallVectorExtras.h` include when necessary.

The check is called `vector-utils` because we may want to handle more
cases in the future, like turning explicit calls to SmallVector
constructor to `llvm::to_vector` (which lives in `SmallVector.h`, not
`SmallVectorExtras.h`).

Assisted-by: claude
DeltaFile
+149-0clang-tools-extra/test/clang-tidy/checkers/llvm/use-vector-utils.cpp
+97-0clang-tools-extra/clang-tidy/llvm/UseVectorUtilsCheck.cpp
+42-0clang-tools-extra/clang-tidy/llvm/UseVectorUtilsCheck.h
+31-0clang-tools-extra/docs/clang-tidy/checks/llvm/use-vector-utils.rst
+7-0clang-tools-extra/docs/ReleaseNotes.rst
+2-0clang-tools-extra/clang-tidy/llvm/LLVMTidyModule.cpp
+328-02 files not shown
+330-08 files

LLVM/project 24be429llvm/lib/Target/SystemZ SystemZISelLowering.cpp

SystemZ: Use correctly offset MachinePointerInfo in CC lowering (#177793)

Previously this was just using the original base address as
the pointer info.
DeltaFile
+5-3llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+5-31 files

LLVM/project 8387237lldb/include/lldb/API SBDebugger.h

[lldb] improve Doxygen rendering of an existing comment (#177785)

This commit improves the way how the example code attached to
`SBDebugger::GetSetting` method is rendered by Doxygen.

Co-authored-by: Matej Košík <matej.kosik at codasip.com>
DeltaFile
+2-0lldb/include/lldb/API/SBDebugger.h
+2-01 files

LLVM/project f7d7897clang Maintainers.rst

[clang] Add NagyDonat to the Clang Static Analyzer maintainers (#174595)

I was nominated for this role at
https://discourse.llvm.org/t/nominate-new-static-analyzer-maintainers/89362
DeltaFile
+4-0clang/Maintainers.rst
+4-01 files

LLVM/project 1650782llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanConstruction.cpp

[VPlan] Share and re-use logic to find FindIVResult (NFC).

Move logic to look for FindIVResult pattern out of LoopVectorize to
allow for re-use in current code and follow-up patches.
DeltaFile
+3-35llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+17-8llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+22-0llvm/lib/Transforms/Vectorize/VPlanUtils.h
+11-0llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
+53-434 files

LLVM/project fe71ea4mlir/lib/Dialect/XeGPU/Transforms XeGPUBlocking.cpp, mlir/test/Dialect/XeGPU xegpu-blocking.mlir

[MLIR][XeGPU] Preserve Leading dimension when blocking rank-sensitive operations (#177489)

This PR preserves leading dimensions for
xegpu.load_matrix/store_matrix/atomic_rmw/convert_layout, and vector
operations which have impact on shapes:
broadcast/multi-reduction/shape_cast/transpose.
Rank-sensitive operations are operations whose semantics depend on the
tensor rank (and consequently its shape), and therefore must not alter
the input tile rank or shape, such as by dropping leading dimensions.
DeltaFile
+18-13mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
+3-3mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
+21-162 files

LLVM/project 460e19bllvm/lib/Target/SystemZ SystemZISelLowering.cpp

SystemZ: Use correctly offset MachinePointerInfo in CC lowering

Previously this was just using the original base address as
the pointer info.
DeltaFile
+5-3llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+5-31 files

LLVM/project 1892d27clang/test/CIR/CodeGen/CUDA kernel-stub-name.cu

make test include cleaner
DeltaFile
+2-2clang/test/CIR/CodeGen/CUDA/kernel-stub-name.cu
+2-21 files

LLVM/project 51d5865llvm/test/TableGen MacroFusion.td ResolveSchedClass.td, llvm/utils/TableGen SubtargetEmitter.cpp

TableGen: Emit subtarget generated methods as final (#177781)

DeltaFile
+9-9llvm/utils/TableGen/SubtargetEmitter.cpp
+1-1llvm/test/TableGen/MacroFusion.td
+1-1llvm/test/TableGen/ResolveSchedClass.td
+11-113 files

LLVM/project 2f1b1f3flang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP declare-simd.f90

[flang][mlir][OpenMP] Support inbranch and notinbranch clause (#177310)

Support inbranch and notinbranch clause for OpenMP declare simd
directive.
DeltaFile
+44-0mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
+37-0mlir/test/Dialect/OpenMP/ops.mlir
+27-2flang/test/Lower/OpenMP/declare-simd.f90
+18-0flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+6-3mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+7-0mlir/test/Dialect/OpenMP/invalid.mlir
+139-53 files not shown
+145-69 files

LLVM/project 3c3aec2llvm/test/Instrumentation/HWAddressSanitizer use-after-scope.ll

update

Created using spr 1.3.6
DeltaFile
+404-0llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
+404-01 files

LLVM/project 0c6a094llvm/test/Instrumentation/HWAddressSanitizer use-after-scope.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6

[skip ci]
DeltaFile
+403-0llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
+403-01 files

LLVM/project 8e1733cllvm/test/Instrumentation/HWAddressSanitizer use-after-scope.ll

add test

Created using spr 1.3.6
DeltaFile
+403-0llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
+403-01 files

LLVM/project f703a61clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenFunction.cpp, clang/test/CIR/CodeGen/CUDA kernel-stub-name.cu

[CIR][CUDA] Upstream device stub mangling
DeltaFile
+74-0clang/test/CIR/CodeGen/inputs/cuda.h
+22-0clang/test/CIR/CodeGen/CUDA/kernel-stub-name.cu
+8-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+3-1clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+107-34 files

LLVM/project aefd87dllvm/lib/Target/RISCV RISCVInstrInfoZfa.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Remove decodeRTZArg. NFC (#177744)

We can set the frm field in tablegen class which makes the disassembler
only accept that fixed value without needing to reject it with
decodeRTZArg.
DeltaFile
+0-10llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+2-1llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+2-112 files

LLVM/project 6d7c12cllvm/lib/CodeGen/SelectionDAG InstrEmitter.cpp

DAG: Replace legal type check in EmitCopyFromReg

It doesn't make sense that an illegal type would get here; a
CopyFromReg cannot be illegally typed. The only exception that
was hit here is in a handful of SystemZ inline assembly tests
for i128, which use untyped. They shouldn't; it should treat
v2i64 as legal instead. Just leave the untyped check for now.
DeltaFile
+5-4llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+5-41 files

LLVM/project dcb6e15polly/test/CodeGen/OpenMP matmul-parallel.ll

[Polly] Avoid dependence on x86 backend

Unbreak the polly-arm-linux buildbot.
DeltaFile
+32-57polly/test/CodeGen/OpenMP/matmul-parallel.ll
+32-571 files

LLVM/project 5dec140llvm/include/llvm/Analysis IR2Vec.h, llvm/lib/Analysis IR2Vec.cpp

[IR2Vec] Changes to support programmatic creation of Vocabulary (#177348)

These changes would help create `ir2vec::Vocabulary` in Python bindings
(or any other *tool*) without having to run `IR2VecVocabAnalysis` which
reads the Vocab path via command line.
DeltaFile
+268-0llvm/unittests/Analysis/IR2VecTest.cpp
+54-35llvm/lib/Analysis/IR2Vec.cpp
+17-5llvm/include/llvm/Analysis/IR2Vec.h
+339-403 files

LLVM/project 217731ellvm/test/TableGen MacroFusion.td ResolveSchedClass.td, llvm/utils/TableGen SubtargetEmitter.cpp

TableGen: Emit subtarget generated methods as final
DeltaFile
+9-9llvm/utils/TableGen/SubtargetEmitter.cpp
+1-1llvm/test/TableGen/MacroFusion.td
+1-1llvm/test/TableGen/ResolveSchedClass.td
+11-113 files

LLVM/project 8dcc9b6polly/lib/External/isl isl_map.c isl_map_simplify.c, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

[Polly] Update isl to isl-0.27 (#177776)

Fixes: #177527

Updated test cases:

* CodeGen/OpenMP/matmul-parallel.ll, ScheduleOptimizer/pattern-matching-based-opts.ll
  Before the update, ISL bailed out the dependency computation due to
  hitting the max operation limit. The commit
  https://repo.or.cz/isl.git/commit/4bdfe2567715c5d1a8287c07d8685eb3db281e32
  seems to have reduced the complexity needed of the dependency
  computation, thus now being able to recognize some loops as parallel.
  The tests were checking that the outer loop is not parallel, but some
  inner loops can be parallized, particularly the array packing loops.

 * DeLICM/reduction_looprotate_hoisted.ll
   changes in how isl generates expressions

 * ScheduleOptimizer/pattern-matching-based-opts_5.ll
   changes in how isl generates expressions, and AST node changes
DeltaFile
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+21,192-0polly/lib/External/isl/include/isl/cpp-checked.h
+19,097-0polly/lib/External/isl/interface/isl.py.core
+1,681-148polly/lib/External/isl/isl_map.c
+772-161polly/lib/External/isl/isl_map_simplify.c
+126,366-309141 files not shown
+131,425-2,485147 files

LLVM/project 4623ccallvm/include/llvm-c Core.h, llvm/lib/IR Core.cpp

Add C API to set this
DeltaFile
+34-0llvm/include/llvm-c/Core.h
+30-0llvm/unittests/IR/AttributesTest.cpp
+16-0llvm/lib/IR/Core.cpp
+80-03 files

LLVM/project f5de162llvm/test/Assembler denormal_fpenv.ll, llvm/test/Bitcode compatibility.ll auto_upgrade_denormal_fp_math.ll

bar syntax and only print input if different from output.

Breaks update_test_checks Function Attrs comment check in the rare
case where the modes mismatch.
DeltaFile
+72-72llvm/test/Bitcode/compatibility.ll
+70-72llvm/test/Assembler/denormal_fpenv.ll
+57-57llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+48-48llvm/test/Transforms/InstSimplify/canonicalize.ll
+40-44llvm/test/Transforms/Attributor/denormal-fp-math.ll
+42-42llvm/test/Bitcode/auto_upgrade_denormal_fp_math.ll
+329-335156 files not shown
+861-848162 files