[AMDGPU] Allow independent WMMA to resolve WMMA coexecution hazards
When counting the wait states that separate a WMMA from a later dependent
instruction, every VALU in between is credited with one wait state. An
intervening XDL WMMA clears the hazard.
[AArch64] Avoid factor-4 deinterleaved loads feeding uitofp (#210894)
Avoid generating ld4 when all values produced by the deinterleaved load
are fed into uitofp. Keeping the loads separate allows the backend to
optimize them into shifts and masks.
AMDGPU: Add missing atomic-fmin-fmax-global to gfx13 feature map
fillAMDGCNFeatureMap omitted atomic-fmin-fmax-global-f32 and
atomic-fmin-fmax-global-f64 for gfx1310/gfx13-generic, so clang wrongly
rejected the raw_ptr_buffer_atomic_f{min,max}_f{32,64} builtins on those
targets even though the backend enables the features. Add them to the
gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
ARM: Read float ABI from the "float-abi" module flag
Use the value from the module flag if present, otherwise
fall back on the legacy TargetOptions field until that is
removed.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[Sema] Fix crash in __builtin_dump_struct with -Werror -Wformat-pedantic (#212377)
`DiagnosticErrorTrap::hasErrorOccurred()` treats warnings promoted to
errors by `-Werror` as real errors, causing `BuiltinDumpStructGenerator`
to bail out before building the `PseudoObjectExpr` wrapper. CodeGen then
encounters the untransformed `CallExpr` with a placeholder builtin type
and hits `llvm_unreachable` in `CodeGenTypes::ConvertType`.
Use `hasUnrecoverableErrorOccurred()` instead, which ignores `-Werror`
promoted warnings and only bails on genuine compilation errors.
Fixes #211943
[clang] perf_helper.py ignore clang warning/note when parsing cc1 command (#212401)
Parsing cc1 command fails in `perf_helper` when `clang: note:` or
`clang: warning:` due to driver warnings. As an example, harmless macOS
sdk mismatch and `-Wunused-command-line-argument`.
[NVPTX] Move NVPTXAsmPrinter and NVPTXDAGToDAGISel out of headers (NFC) (#213162)
Both headers were only included by their own `.cpp` file, so move the
class definitions into anonymous namespaces there and delete the
headers.
`getFromTypeWidthForLoad` was the only thing `NVPTXISelLowering.cpp`
needed from the ISel class, so it moves to `NVPTXUtilities` as a free
function.
[ELF] Remove -z sort-thunks (#213074)
The option was added by #211721 (sort forward thunks by descending
destination to prevent convergence failures) as a temporary opt-out.
Tests have been migrated to the default order.
Reland "[msan] Apply handleGenericVectorConvertIntrinsic() to fptrunc/fpext" (#213161)
Reverts llvm/llvm-project#204221 i.e., reapplies
https://github.com/llvm/llvm-project/pull/204197. The original patch was
reverted was due to a buildbot failure in vararg_shadow.cpp that relied
on undefined behavior as well as an unwarranted assumption that the
shadow is preserved when round-tripping from float->double->float. The
UB cases have been disabled in
https://github.com/llvm/llvm-project/pull/204246.
Original commit message:
The current instrumentation uses handleShadowOr(), which effectively
truncates or zero-extends the shadows for fptrunc/fpext respectively;
this is overly lax because floating-point has both mantissa and exponent
components (e.g., if the mantissa is initialized but the exponent is
uninitialized, an fptrunc might end up with a fully initialized shadow,
which is incorrect; conversely, if a floating-point value is fully
uninitialized, we want the fpext'ed shadow to be fully uninitialized,
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[ADT] Introduce SetVector::reserve (NFC) (#209951)
This patch introduces SetVector::reserve to allocate capacity in the
underlying containers.
We also adopt SetVector::reserve across Attributor.cpp where the exact
number of unique functions being inserted is known ahead of time.
Assisted-by: Antigravity
[DebugInfo] Make DW_AT_LLVM_stmt_seq work with split DWARF (#213128)
Before this change, we would end up with a relocation in the dwo, which
would then result in an error.
[ORC] Generalize RTBridge callers over signature types. (#213179)
Recast the RTBridge callers as templates parameterized on the call
signature, so future executor accessors can be added as thin
declarations rather than hand-written classes.
rt::Caller<RetT(ArgTs...)> is the runtime-agnostic caller interface for
a given signature, providing the asynchronous and synchronous call
operators and the associated result types. rt::MainCaller is now an
alias for rt::Caller<int64_t(ArrayRef<std::string>)>.
rt::sps::Caller<BaseT, SPSSigT, CIName> implements any such interface by
invoking an executor-side SPS wrapper in the runtime's controller
interface, deducing the argument and result types from BaseT. A concrete
caller is a typedef supplying the interface, its SPS signature, and the
CI entry-point name; see rt::sps::MainCaller.
MainCaller's observable behavior is unchanged (the existing
SPSCallersTest still passes). The out-of-line destructor anchor in
OrcRTBridge.cpp is dropped, as the templated base now provides an inline
defaulted destructor.
[libc++][pstl] Implementation of parallel std::lexicographical_compare() based on std::mismatch() (#212366)
This PR adds an implementation of parallel
`std::lexicographical_compare()` based on parallel `std::mismatch()`.
The implementation is close to a one-liner:
```c++
auto __res = _Mismatch()(__policy, __first1, __last1, __first2, __last2, [&](_Ref1 __lhs, _Ref2 __rhs) {
return !__comp(__lhs, __rhs) && !__comp(__rhs, __lhs);
});
```
Included tests check that:
- Semantics of the iterator-only version is correct.
- Semantics of the predicated version is correct.
- The functions correctly SFINAE out when the first argument is not an
execution policy.
- The `noexcept` policy is followed.
- The `nodiscard` policy is followed.
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[SPIRV] Legalize Cast Instructions for Matrix Types (#212619)
fixes #186864
This is a more limited fix. that doesn't require us to change the whole
legalization strategy for SPIR-V.
To get the last fix to work it looks like I would have to have changed
every global opcode to no longer use power of 2 based legalization.
This change with power of 2 fixed the transpose case in the offload
testsuite when we do the conversion of bools to i32s before we call
transpose.
There remains an issue when a i1 makes it into a transpose intrinsic.
That said I can only trigger that case via llvmir and not HLSL so will
move on for now.
[lldb] Ask the reporter what happened in a bug report (#213173)
A diagnostics bundle records the state of the debugger, never what the
user was doing or what they expected instead, so reports arrive with a
generic title and no description of the problem. Pre-fill the report
with the questions only the person filing it can answer, and print a
checklist when the bundle is written so an incomplete report doesn't get
shared as-is.
rdar://183356348
Reapply "[NFC][clang][Driver] Add tests for --driver-mode=flang" (#211724)
This reapplies #207658.
Some targets do not support flang_rt or clang_rt.
It seems difficult to create a blocklist, so the tests are now
configured to explicitly specify the known-working targets.
The specified targets are extracted from tests in flang/test/Driver.
-----
The original commit message:
This patch intends to clarify the current behaviors, not to state the
expected/desirable behaviors.
[CIR] Pointer and vptr width from a CIR-native data-layout entry (#204185)
PointerType and VPtrType have hard-coded sizes and alignments of 64/8
bits. On targets with 32-bit pointers (e.g., nvptx, spirv32), this trips
the record layout builder. Any record containing a pointer hit the
insertPadding assertion (offset >= size)
because the pointer was sized at 8 bytes while the following field was
placed at the AST-mandated 4-byte offset.
### Changes:
- CIRGenerator: attaches a CIR-native cir.ptr data-layout entry at
module setup, storing {size-in-bits, abi-align-in-bits} read
from the target DataLayout (only for the default address space).
- CIRTypes: PointerType reads its size/alignment from that entry
(falling back to 64/8 when absent); VPtrType routes through a cir.ptr so
it picks up the same width.
- LowerToLLVM: strips the cir.ptr entry during CIR→LLVM lowering, since
cir.ptr has no meaning in LLVM IR.
- Unit test: checking 4-byte pointer/vptr layout on nvptx, verified
across CIR, CIR→LLVM.
