[X86] Fix assertion failure for tail call on i686+pic (#210302)
The pattern for TCRETURNmi has a IsNotPIC predicate, but the
checkTCRetEnoughRegs() predicate that's part of the X86tcret_enough_regs
PatFrag is evaluated first, so we can't assert that PIC is disabled
here. We should just return false in that case.
Fixes https://github.com/llvm/llvm-project/issues/210300.
clang: Use TargetID parsing from AMDGPUTargetParser
We had grown 2 parallel parsing implementations for
triple+gpu name+feature flag target ID strings. Mostly
eliminate the redundant clang version.
Co-authored-by: Claude (Opus 4.8)
[AArch64][PAC] Rework the expansion of AUT/AUTPAC pseudos
Refactor `AArch64AsmPrinter::emitPtrauthAuthResign` to improve
readability and fix the conditions when `emitPtrauthDiscriminator` is
allowed to clobber AddrDisc.
* do not clobber `AUTAddrDisc` when computing `AUTDiscReg` on resigning
if `AUTAddrDisc == PACAddrDisc`, as it would prevent passing raw,
64-bit value as the new discriminator
* move the code computing `ShouldCheck` and `ShouldTrap` conditions to a
separate function
[LV] Add additional SCEV expansion tests with AddRecs. (NFC) (#210159)
Add additional test coverage for SCEV expansion of AddRecs, including
cases where extends are needed, different start and steps, as well as
cases where the outer header is not the plan's entry block.
clang: Use TargetID parsing from AMDGPUTargetParser
We had grown 2 parallel parsing implementations for
triple+gpu name+feature flag target ID strings. Mostly
eliminate the redundant clang version.
Co-authored-by: Claude (Opus 4.8)
AMDGPU: Remove now-unused splitTargetID
splitTargetID was a syntactic-only target-ID splitter used solely by
clang's getConflictTargetIDCombination, which now parses through the
canonical llvm::AMDGPU::TargetID::parse instead. With that last user
gone, drop the function, its declaration, and its unit test.
AMDGPU: Add TargetID::printCanonicalTargetIDString
Factor the canonical feature-string formatting into a raw_ostream print
method so callers can stream directly without a temporary std::string.
getCanonicalFeatureString now delegates to it.
AMDGPU: Validate processor and features in TargetID parsing
TargetID::parseTargetIDString previously only checked that the string was
structurally a 4-component triple followed by a processor field. It
accepted unrecognized processors and silently ignored malformed or
unsupported feature modifiers. Work towards improving validation so in
the future clang's copy of TargetID can be replaced.
Co-authored-by: Claude (Opus 4.8)
[Clang][Driver] Fix compiler-rt library directory for cygwin (#208925)
If compiler-rt is built with `LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=OFF`,
its search directory is incorrect.
Specifically, `ToolChain::getOSLibName()` returns `windows` instead of
`cygwin` in a Cygwin environment, due to falling back to getOS(). This
results in a link error against compiler-rt.
This patch makes `getOSLibName()` return `cygwin`, ensuring that
compiler-rt is linked correctly.
---------
Signed-off-by: Takashi Yano <takashi.yano at nifty.ne.jp>
[KnownBits] Use X < Y identity and umin(MaxX, MaxY - 1) bound in urem (#210262)
Tightens `KnownBits::urem` with the two facts `ConstantRange::urem`
already uses:
- `L % R == L` when `MaxL < MinR`: return the LHS bits unchanged. This
can propagate known one bits, which the current leading-zeros-only
reasoning never produces.
- `L % R <= umin(MaxL, MaxR - 1)`, since a zero divisor is UB: keep that
bound's leading zeros. This is one bit stronger than the per-operand
leading-zero count when `MaxR` is a power of two, and together with
`remGetLowBits` it subsumes the power-of-two-constant special case,
which is removed.
Soundness is covered by the existing exhaustive unit test (widths 1 and
4; additionally brute-forced at width 5). Across all 6480 valid width-4
KnownBits pairs, non-optimal results drop from 3332 to 2090. The
residual is number-theoretic (e.g. the exact value of `10 % 3`), out of
reach of leading-bit/range reasoning, so `CheckOptimality` stays off for
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[AArch64][GlobalISel] Add sign bits for G_VASHR (#210269)
Ports the `AArch64ISD::VASHR` case from
`ComputeNumSignBitsForTargetNode` to the GlobalISel hook: an arithmetic
right shift by K adds K copies of the sign bit, so the result has
`min(SignBits(Src) + K, ScalarSizeInBits)` sign bits. `G_VASHR`'s shift
amount is always an immediate in `[1, ElementBits]`.
Follow-up to #198314, which added the `G_FCM*` cases.
Assisted by Claude (Anthropic).
Revert "[LLD] [COFF] Fix linking directly against an ARM64X DLL without import library (#210080)" (#210299)
This reverts commit a3bcc010c7b7d5fa43ab7928a88312841c4322dd, which
breaks in asan build.
