[RFC][AMDGPU][InsertWaitcnts] Move `WaitcntBrackets` to a separate file
My previous stack of patches de-tangled quite a bit of InsertWaitcnt,
and now `WaitcntBrackets` can be moved into a separate file fairly
easily. I'm proposing this as a RFC. While I think this is a net
positive, I don't want to force this through if others feel it's unnecessary.
Implementation:
This pretty much moves `WaitcntBrackets` as-is, with a few changes:
- Instead of having a pointer to `SIInsertWaitcnts` for the "context"
there is now a "Info" class that `SIInsertWaitcnts` implements.
This enforces a small separation between the classes, not enough to
force a massive redesign, but enough that we can't just access the
entire state of `InsertWaitcnts` at will.
- Some unused/unnecessary functions were removed or made private.
- I reorganized the code a bit: moved all private functions together,
moved method implementations to the .cpp if they had more than 2 lines of code.
The goal is to keep things somewhat organized so it's easy to glance at the
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[CodeView] Encode signed enumerators as signed integers (#210352)
In #210338 I noticed that enumerator constants were always encoded as
unsigned integers. MSVC (usually) uses the correct signedness
(comparison: https://godbolt.org/z/rbrchhjTT). It only uses signed
values for 64 bit unsigned values (probably a bug).
We know the signedness in `DIEnumerator` and we should use it.
The change in `llvm/lib/DebugInfo/CodeView/CodeViewRecordIO.cpp` was
needed, because the max/min values need all the bits to encode their
value - otherwise we hit an assertion.
This also encodes the saturated value (`INT64_MIN = 0x8000000000000000`)
in the int128 test correctly (initially added in
https://reviews.llvm.org/D105320).
Revert "[libc++][test] XFAIL `text/text_encoding/environment.pass.cpp` test on Armv7/Linux Ubuntu targets." (#211112)
Reverts #206188
XFAIL'ed wrong test
[AMDGPU] Remove some unneeded waits for VA_VDST (#210741)
Add some internal consistency checks on WaitcntBrackets before and after
processing each instruction. In particular, check that VA_VDST_RD and
VA_VDST_WR agree on the range of values of the underlying hardware
counter. Fix some cases where this was not true, which has the effect of
removing some unneeded waits for VA_VDST where it was already known to
be zero.
[MachO] Preserve weak linkage for aliases (#198148)
Mach-O aliases with weak or linkonce linkage were emitted as weak
references, which is appropriate for undefined references but not for
alias definitions. Emit Mach-O aliases through the same linkage path as
other global definitions so weak aliases get .weak_definition.
When writing aliased symbols, keep the aliasee flags and include the
alias symbol's own flags so N_WEAK_DEF is preserved in the Mach-O n_desc
field.
Fixes #111321
#196047 was closed as a duplicate of #111321.
[AArch64][SVE] Fix v16i8 -> v2i64 partial_reduce for VL > 128 (#204938)
A fixed-length `llvm.vector.partial.reduce.add` reducing `<16 x i8>`
into `<2 x i64>` is lowered on `+sve` by converting the reduction to a
scalable one and finishing with `convertFromScalableVector`. The i8 ->
i64 fold splits the `(nx)v4i32` dot before converting it back to fixed
length, but splitting a scalable container is not equivalent to
splitting the fixed vector it holds: at vscale=2 an `nxv4i32` container
splits into two `nxv2i32`, each holding four i32s, not the two-lane
halves of the underlying `v4i32`. The high partial sums land in lanes
that `convertFromScalableVector` then discards, so any runtime VL > 128
silently drops them — on a 256-bit machine (e.g. Neoverse V1) exactly
half the result is lost (#204939; downstream miscompile
rust-lang/rust#158144).
Convert the dot back to a fixed-length i32 vector before splitting, so
the split, widen and accumulate all happen in fixed length and no lanes
are dropped. The fixed dot width is derived from the result (two i32
lanes per i64 result lane) so the wider, VL-pinned `<4 x i64> <- <32 x
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[LV] Vectorize uncountable early exit store loops with combined conditions
Support the case where both the countable and uncountable exit conditions
have been combined by earlier passes.
AMDGPU: Reland: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3 (#196516)
For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark
them with usesCustomInserter which will be used to add pre-RA register
allocation hints to preferably assign dst and src2 to the same physical
register. When the hint is satisfied, canMapVOP3PToVOPD recognises the
instruction as eligible for VOPD pairing by checking if it is VOP2 like:
dst==src2, no source modifiers, no clamp, and src1 is a register.
Mark both instructions as commutable to allow a literal in src1 to be
moved to src0, since VOPD only permits a literal in src0.
Original patch had a bug where it did not check if physical src
registers match register class of appropriate operand in fullVOPD
instructions, check is now done via isValidVOPDSrc.
AMDGPU: Validate VOPD/VOPD3 physical source registers against operand RC (#196515)
Replace isVGPR checks with isValidVOPDSrc that validates physical source
registers against the actual combined VOPD/VOPD3 instruction's operand
register classes. Now we also validate operands for VOPD instructions.
clang: Emit "long-double-type" module flag generically
Move emission of the "long-double-type" module flag out of PowerPC
and into generic code, so it describes the long double format for all
targets.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Triple: Add query for the default long double format
The long double format changes the library call info, which needs
to be computed independently of codegen. Implement this based on the
clang target code.
IR: Accept x86_fp80 and float as a long-double-type value
Prepare to emit long-double-type for all targets.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[CIR][CUDA] Add support for scoped NVVM atomic builtins (#210863)
Adds codegen support for the block and system-scoped NVVM atomic
builtins: add, and, or, xor, min, max, inc and dec.
These are lowered to the corresponding CIR `cir.atomic.fetch` operations
and subsequently lowered to LLVM `atomicrmw` instructions.
[Docs] Remove dead Phabricator link from DeveloperPolicy (#210934)
The Phabricator committing-a-change anchor no longer resolves since
Phabricator has been discontinued, so drop the reference and keep the
GitHub Issues guidance for linking reviewed/closed bugs.
IR: Introduce "float-abi" module flag
This is intended to eliminate the FloatABIType TargetOptions field.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
PowerPC: Rename "float-abi" module flag to "long-double-type"
PPC was emitting a "float-abi" module flag for indicating the type of long
double. The "float ABI" naming is already widely taken by soft vs. hard
float controls (e.g., the clang flag is called -mfloat-abi), so this shouldn't
have taken it. This should also not be PPC specific; x86 has the same problem.
Rename the flag to the more specific long-double-type, and add appropriate
verification and documentation (which was also missing). Also changes the value
names to match the IR type names.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[MLIR][WASM] Introduce full support for raising WASM MLIR to other dialects (#205990)
Following https://github.com/llvm/llvm-project/pull/164562 where
RaiseWasm was introduced.
This PR completes the support for rewriting the currently supported Wasm
MLIR operators to arith, math, cf and memref.
---------
Co-authored-by: Ferdinand Lemaire <ferdinand.lemaire at woven-planet.global>
