LLVM/project 81c35c7llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ISelLowering.h

[AArch64][SVE] Enable known bits for predicated shifts (#200347)

Allow SelectionDAG to query target known-bits information for scalable
vector nodes, and known-bits cases for SVE predicated SHL, SRL and SRA
nodes.

This enables DAG combines to prove disjointness for ORs involving
scalable vector shifts, enabling USRA/SSRA instruction selection.
DeltaFile
+222-8llvm/test/CodeGen/AArch64/sve2-sra.ll
+22-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+16-8llvm/test/CodeGen/AArch64/sve2-sli-sri.ll
+0-5llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.h
+261-245 files

LLVM/project 024c82aclang/test/CodeGen/AArch64 neon-intrinsics.c, clang/test/CodeGen/AArch64/neon subtraction.c

Merge branch 'main' into users/kparzysz/single-check
DeltaFile
+632-322llvm/test/Transforms/GVN/PRE/pre-loop-load-through-select.ll
+215-109llvm/test/Transforms/GVN/PRE/pre-load-through-select.ll
+0-230clang/test/CodeGen/AArch64/neon-intrinsics.c
+199-1clang/test/CodeGen/AArch64/neon/subtraction.c
+110-81llvm/lib/IR/IRBuilder.cpp
+96-51llvm/test/Transforms/GVN/load-select-addr-store-fwd.ll
+1,252-79475 files not shown
+2,424-1,27581 files

LLVM/project a1c3370llvm/test/Transforms/GVN load-select-addr-store-fwd.ll opaque-ptr.ll, llvm/test/Transforms/GVN/PRE pre-loop-load-through-select.ll pre-load-through-select.ll

[GVN] Regenerate check lines (NFC) (#204341)

Test check lines have been regenerated while enabling MemorySSA as well.
DeltaFile
+632-322llvm/test/Transforms/GVN/PRE/pre-loop-load-through-select.ll
+215-109llvm/test/Transforms/GVN/PRE/pre-load-through-select.ll
+96-51llvm/test/Transforms/GVN/load-select-addr-store-fwd.ll
+58-41llvm/test/Transforms/GVN/opaque-ptr.ll
+54-29llvm/test/Transforms/GVN/pr69301.ll
+45-21llvm/test/Transforms/GVN/debugloc-load-select.ll
+1,100-5731 files not shown
+1,147-5857 files

LLVM/project 564e831clang/docs ReleaseNotes.rst, clang/include/clang/Sema Overload.h

[clang][Sema][CUDA] Restrict immediate template resolution to host-device functions (#200662)

Since overload resolution gives higher priority to `__host__` and
`__device__` attributes, HD functions may favor template candidates even
when a non‑template candidate would be a perfect match. This patch
resolves templates eagerly only for HD functions, not for all code
compiled with `-x cuda`, thus preventing valid host code from being
rejected.

Close #200545
DeltaFile
+109-0clang/test/SemaCUDA/pr200545.cu
+26-4clang/lib/Sema/SemaOverload.cpp
+1-17clang/include/clang/Sema/Overload.h
+1-0clang/docs/ReleaseNotes.rst
+137-214 files

LLVM/project ddad3caclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c

[CIR][AArch64] Lower NEON Widen && Widening subtraction intrinsics (#204088)

## summary

This is a part of : https://github.com/llvm/llvm-project/issues/185382

follow up of : https://github.com/llvm/llvm-project/pull/202857

Lower part of Widen and Widening subtraction intrinsics

### why implement two sets of intrinsics in one PR?

Widening subtraction depends on the widen intrinsics during lowering, so
I implemented them in the same PR.
DeltaFile
+0-230clang/test/CodeGen/AArch64/neon-intrinsics.c
+199-1clang/test/CodeGen/AArch64/neon/subtraction.c
+98-0clang/test/CodeGen/AArch64/neon/widen.c
+12-1clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+309-2324 files

LLVM/project 41aed9bllvm/lib/Transforms/Scalar GVN.cpp, llvm/test/Transforms/GVN load-select-addr-store-fwd.ll debugloc-load-select.ll

[GVN][NFC] Use InsertPt in MaterializeAdjustedValue (#204335)
DeltaFile
+18-18llvm/test/Transforms/GVN/PRE/pre-loop-load-through-select.ll
+8-8llvm/test/Transforms/GVN/load-select-addr-store-fwd.ll
+7-7llvm/test/Transforms/GVN/PRE/pre-load-through-select.ll
+6-6llvm/test/Transforms/GVN/debugloc-load-select.ll
+5-5llvm/test/Transforms/GVN/opaque-ptr.ll
+2-2llvm/lib/Transforms/Scalar/GVN.cpp
+46-462 files not shown
+48-488 files

LLVM/project 12f405dflang/lib/Semantics check-omp-structure.cpp check-omp-structure.h, flang/test/Semantics/OpenMP single04.f90 single03.f90

[flang][OpenMP] Refactor semantic check of SINGLE construct

Extract it into a separate function and simplify the code. Avoid making
the distinction between a clause appearing on the "begin" and the "end"
directives for the purposes of emitting diagnostic messages.

One change in behavior is that using the same list item multiple times
in COPYPRIVATE clause(s) is an error regardless of the placement of the
clauses. Previously in some cases it was treated as a warning.

Part of the motivation is the goal of eliminating explicit definitions
of end-directives for directives that are not delimited, e.g.
"end single", but not "end declare_variant".
DeltaFile
+73-57flang/lib/Semantics/check-omp-structure.cpp
+15-20flang/test/Semantics/OpenMP/single04.f90
+5-10flang/test/Semantics/OpenMP/single03.f90
+0-2flang/test/Semantics/OpenMP/clause-validity01.f90
+1-0flang/lib/Semantics/check-omp-structure.h
+94-895 files

LLVM/project 22e1561mlir/lib/Dialect/Tosa/Transforms TosaConvertIntegerTypeToSignless.cpp, mlir/test/Dialect/Tosa tosa-convert-integer-type-to-signless.mlir

[mlir][tosa] Preserve raw const data in signless conversion (#204324)

Use DenseElementsAttr::getFromRawBuffer when rebuilding tosa.const
attributes in TosaConvertIntegerTypeToSignless. The previous
DenseElementsAttr::get(type, ArrayRef<char>) call interpreted raw bytes
as i8 elements, which asserted for integer constants wider than 8 bits.

Add regression coverage for ui16, ui32, and ui48 constants.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+27-0mlir/test/Dialect/Tosa/tosa-convert-integer-type-to-signless.mlir
+2-1mlir/lib/Dialect/Tosa/Transforms/TosaConvertIntegerTypeToSignless.cpp
+29-12 files

LLVM/project d7e30d2llvm/include/llvm/IR IRBuilder.h, llvm/lib/IR IRBuilder.cpp

[IRBuilder] Refactor for intrinsics const-folding (NFC) (#202738)

In preparation to const-fold intrinsic calls, refactor the IRBuilder
API, generalizing it to return possibly constant-folded values.
DeltaFile
+110-81llvm/lib/IR/IRBuilder.cpp
+86-54llvm/include/llvm/IR/IRBuilder.h
+50-42llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+39-42llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
+20-20llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+19-20llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+324-25948 files not shown
+498-43054 files

LLVM/project f14737fllvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

AMDGPU: Refactor AMDGPUTargetID to not store MCSubtargetInfo

Store the triple string and GPUKind instead. The dependence
on checking AMDHSA seems like an anti-feature, but maintain the
behavior of not printing the modifiers for other OSes. Start
parsing the target ID instead of performing a direct string
comparison. Also improve test coverage for the treatment of the
environment component of the triple. The main behavioral change
is this will now produce normalized triples in the output and
diagnostics. Practially, this means all of the places that
currently emit "--" will be expanded into "-unknown-".

Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+102-102llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
+79-36llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+36-10llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+22-22llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll
+27-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+17-0llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
+283-17136 files not shown
+371-24742 files

LLVM/project 12b7754mlir/include/mlir/Dialect/WasmSSA/IR WasmSSAOps.td, mlir/test/Target/Wasm trunc_si.mlir trunc_ui.mlir

[MLIR][WasmSSA] Add f32/f64.nearest and trapped float to int trunc operations (#193873)

- `f32.nearest` (wasmssa.nearest)
- `f64.nearest` (wasmssa.nearest)
- `i32.trunc_f32_s` (wasmssa.trunc_si)
- `i32.trunc_f64_s` (wasmssa.trunc_si)
- `i64.trunc_f32_s` (wasmssa.trunc_si)
- `i64.trunc_f64_s` (wasmssa.trunc_si)
- `i32.trunc_f32_u` (wasmssa.trunc_ui)
- `i32.trunc_f64_u` (wasmssa.trunc_ui)
- `i64.trunc_f32_u` (wasmssa.trunc_ui)
- `i64.trunc_f64_u` (wasmssa.trunc_ui)
DeltaFile
+45-0mlir/test/Target/Wasm/inputs/trunc_si.yaml.wasm
+45-0mlir/test/Target/Wasm/inputs/trunc_ui.yaml.wasm
+45-0mlir/test/Target/Wasm/trunc_si.mlir
+45-0mlir/test/Target/Wasm/trunc_ui.mlir
+38-0mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAOps.td
+33-0mlir/test/Target/Wasm/inputs/nearest.yaml.wasm
+251-03 files not shown
+298-09 files

LLVM/project b160d1dllvm/include/llvm/CodeGen MachineRegionInfo.h, llvm/include/llvm/Passes MachinePassRegistry.def

[CodeGen][NewPM] Port machine-region-info to new pass manager (#203848)

- Make `MachineRegionInfo` movable, like `RegionInfo`.
- Add printer pass.
DeltaFile
+40-0llvm/include/llvm/CodeGen/MachineRegionInfo.h
+33-0llvm/lib/CodeGen/MachineRegionInfo.cpp
+3-2llvm/include/llvm/Passes/MachinePassRegistry.def
+1-0llvm/test/CodeGen/X86/machine-region-info.mir
+1-0llvm/lib/Passes/PassBuilder.cpp
+78-25 files

LLVM/project f63d8d6libc/src/__support/OSUtil/linux/syscall_wrappers prlimit.h CMakeLists.txt, libc/src/sys/resource/linux setrlimit.cpp getrlimit.cpp

[libc][NFC] wrap prlimit64 and refactor getrlimit/setrlimit (#204306)

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+38-0libc/src/__support/OSUtil/linux/syscall_wrappers/prlimit.h
+10-7libc/src/sys/resource/linux/setrlimit.cpp
+10-7libc/src/sys/resource/linux/getrlimit.cpp
+15-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+2-4libc/src/sys/resource/linux/CMakeLists.txt
+75-185 files

LLVM/project d5918ceflang/include/flang/Optimizer/Dialect FIROps.td FIROps.h, flang/lib/Optimizer/Dialect FIROps.cpp

Revert "[flang][mem2reg] promote memory slots through declares" (#204332)

Reverts llvm/llvm-project#196975

This patch is causing regressions on some of our downstream testing. I
am not sure the logic here is directly to blame, but I'd rather revert
and investigate for now.
DeltaFile
+16-195flang/test/Fir/mem2reg.mlir
+24-111flang/lib/Optimizer/Dialect/FIROps.cpp
+3-10flang/include/flang/Optimizer/Dialect/FIROps.td
+0-1flang/include/flang/Optimizer/Dialect/FIROps.h
+43-3174 files

LLVM/project 85ec3afflang/include/flang/Optimizer/Dialect FIROps.td FIROps.h, flang/lib/Optimizer/Dialect FIROps.cpp

Revert "[flang][mem2reg] promote memory slots through declares (#196975)"

This reverts commit c1ec4b3c79967ae5ef824f7194540f6529405a03.
DeltaFile
+16-195flang/test/Fir/mem2reg.mlir
+24-111flang/lib/Optimizer/Dialect/FIROps.cpp
+3-10flang/include/flang/Optimizer/Dialect/FIROps.td
+0-1flang/include/flang/Optimizer/Dialect/FIROps.h
+43-3174 files

LLVM/project f8fea59clang/lib/Basic LangOptions.cpp

[Clang][NFC] Change if-else to switch for OpenCL/HLSL version mapping (#204288)

Address https://github.com/llvm/llvm-project/pull/204043#discussion_r3419702862
DeltaFile
+34-15clang/lib/Basic/LangOptions.cpp
+34-151 files

LLVM/project 1f9f4f8lldb/test/API/api/listeners main.c, lldb/test/API/commands/expression/radar_9673664 main.c

[lldb] Remove several system header includes from tests (#204072)

System includes slow down test compilation and create unnecessary
dependencies on system header code.

This patch removes system headers from tests that do not test their
functionality. For the most part, this just removes the dummy 'printf'
we had in many tests.
DeltaFile
+11-10lldb/test/API/commands/expression/weak_symbols/main.c
+1-8lldb/test/API/functionalities/object-file/bin/hello.c
+1-8lldb/test/API/functionalities/object-file/bin/hello.cpp
+3-5lldb/test/API/commands/expression/radar_9673664/main.c
+1-7lldb/test/API/python_api/breakpoint/main.c
+1-7lldb/test/API/api/listeners/main.c
+18-4522 files not shown
+38-12128 files

LLVM/project 4d2342fllvm/docs LangRef.rst

[RFC][LangRef] Specify that the accessed bytes of concurrent atomics must be either disjoint or the same

So far, the LangRef hasn't been clear on the semantics of partially overlapping
concurrent atomics in LLVM IR (specifically: a set of accesses marked as
`atomic` that would be in a data race if they weren't `atomic` and not all of
them access the exact same set of bytes).

What loads read is defined in terms of individual bytes, but the memory
ordering constraints are formulated closely to the C/C++ (and Java for
`unordered`) memory model, where partially overlapping atomics are not
possible. It's not obvious how concepts like C/C++'s per-location total
modification order for `monotonic` accesses map to accesses that can partially
overlap. While C/C++ relies on the modification order to ensure that atomics
cannot tear (i.e., atomic reads return bytes from two or more atomic writes),
our IR semantics (as written) currently does not guarantee this in the presence
of partially overlapping accesses.

This PR proposes a solution to this problem: It specifies that concurrent
overlapping atomics must access the exact same set of bytes to act atomically.

    [7 lines not shown]
DeltaFile
+6-2llvm/docs/LangRef.rst
+6-21 files

LLVM/project 21f3248llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU waitcnt-debug.mir

[RFC][AMDGPU] Remove DebugCounter-based WaitCnt debugging (#202937)

It's 8 years old, only used by a handful of tests, and has not been
updated
in a while except for maintenance as far as I can see.

I don't mind keeping it in if there are users of it, but right now it
looks like a dead feature. If we want some more elaborate waitcnt
debugging,
we should have a modern, generic system that works on any waitcnt, not
something specific to 3 GFX9 counters.
DeltaFile
+1-50llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+0-44llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir
+1-942 files

LLVM/project 68c947fllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUWaitcntUtils.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

[NFC][AMDGPU][InsertWaitCnts] Move some simple functions into Utils (#202936)

Move really trivial functions into helpers to declutter InsertWaitCnt a
bit more.
I had to move HardwareLimits into a different header but it's only used
in InsertWaitCnt so it doesn't matter.
DeltaFile
+26-90llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+75-0llvm/lib/Target/AMDGPU/AMDGPUWaitcntUtils.cpp
+32-0llvm/lib/Target/AMDGPU/AMDGPUWaitcntUtils.h
+0-20llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+0-20llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+133-1305 files

LLVM/project 1bea228libc/src/unistd/linux ftruncate.cpp link.cpp

[libc][NFC] Migrate unistd entrypoints to syscall wrappers (#204176)

Migrated link, ftruncate, and getentropy entrypoints to use their
corresponding syscall wrappers instead of direct syscall_impl calls.
Updated CMake dependencies accordingly.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+4-18libc/src/unistd/linux/ftruncate.cpp
+5-15libc/src/unistd/linux/link.cpp
+6-8libc/src/unistd/linux/getentropy.cpp
+3-11libc/src/unistd/linux/CMakeLists.txt
+18-524 files

LLVM/project ec7235eclang/lib/CodeGen CGStmt.cpp, clang/test/CodeGenCXX noreturn-init-stmt.cpp

[clang][CodeGen] Fix crash on if/switch init-statement ending in noreturn (#201047)

EmitStmt may `ClearInsertionPoint()` to mark dead code, EmitDecl is not
prepared to handle it. Fix by `EnsureInsertPoint()` in transition from
EmitStmt to EmitDecl. If/Switch body may contain a label which makes
them not dead.

Fixes #115514.
DeltaFile
+98-0clang/test/CodeGenCXX/noreturn-init-stmt.cpp
+12-2clang/lib/CodeGen/CGStmt.cpp
+110-22 files

LLVM/project 4995c6eclang/include/clang/Basic LangOptions.def

[LifetimeSafety] Mark lifetime safety LangOptions as `Benign` (#204316)

Without this, we cannot load modules built without lifetime safety.
Analysis options are in general benign and does not effect AST
construction.

See doc:
```cpp
  /// For ASTs produced with different option value, signifies their level of
  /// compatibility.
  enum class CompatibilityKind {
    /// Does affect the construction of the AST in a way that does prevent
    /// module interoperability.
    NotCompatible,
    /// Does affect the construction of the AST in a way that doesn't prevent
    /// interoperability (that is, the value can be different between an
    /// explicit module and the user of that module).
    Compatible,
    /// Does not affect the construction of the AST in any way (that is, the

    [4 lines not shown]
DeltaFile
+4-4clang/include/clang/Basic/LangOptions.def
+4-41 files

LLVM/project 0dda20cllvm/test/Transforms/LoopVectorize/AArch64 replicating-load-store-costs-apple.ll induction-costs.ll, llvm/test/Transforms/LoopVectorize/WebAssembly memory-interleave.ll

[LV] Add initial cost model for VPScalarIVSteps (#203347)

This PR currently only adds a cost model for integer types in
non-replicating regions in order to limit the scope of impact.
We can also support replicating regions, but that requires
looking for a recipe with an underlying value in the same
region in order to get a BasicBlock to pass in to the
getPredBlockCostDivisor function. This can be done in a future
PR.
DeltaFile
+18-130llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
+54-73llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
+16-67llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+30-43llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+46-17llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+31-31llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
+195-3617 files not shown
+299-40913 files

LLVM/project b9f8eeellvm/include/llvm/BinaryFormat DXContainer.h

[DirectX][ObjectYAML][NFC] Remove unused function (#204019)

A small follow-up for #202761.
`updateSize()` function added there is a rebase artifact. It is never
actually used. This change removes it.
DeltaFile
+0-5llvm/include/llvm/BinaryFormat/DXContainer.h
+0-51 files

LLVM/project 55ea182llvm/lib/Transforms/IPO FunctionSpecialization.cpp, llvm/test/Transforms/FunctionSpecialization interposable.ll

[FuncSpec] Do not specialize interposable functions (#204314)

We cannot specialize interposable functions, because the definition we
see may not be prevailing one. The prevailing definition can have
arbitrary different behavior.

We *can* still specialize inexact definitions like linkonce_odr, similar
to inlining.
DeltaFile
+40-0llvm/test/Transforms/FunctionSpecialization/interposable.ll
+3-0llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
+43-02 files

LLVM/project 6f73bc2llvm/lib/Support Parallel.cpp

[llvm] Fix unused function warning in Parallel (#204114)

When llvm is built without threading support:
<...>/llvm-project/llvm/lib/Support/Parallel.cpp:230:13: warning: unused
function 'isNested' [-Wunused-function]
  230 | static bool isNested() {
      |             ^~~~~~~~

The function is only used once, so I've put the code into the caller,
which is itself guarded with `#if LLVM_ENABLE_THREADS`.

Function added in 8daaa26efdda3802f73367d844b267bda3f84cbe / #189293.
DeltaFile
+2-9llvm/lib/Support/Parallel.cpp
+2-91 files

LLVM/project 8c3d2e9llvm/docs Passes.rst, llvm/include/llvm InitializePasses.h

[Passes] Remove deadarghaX0r pass (#204310)

This was a pass internally used by bugpoint. Bugpoint has been removed,
so remove the pass as well.
DeltaFile
+7-30llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp
+0-7llvm/include/llvm/Transforms/IPO/DeadArgumentElimination.h
+0-6llvm/docs/Passes.rst
+0-1llvm/lib/Transforms/IPO/IPO.cpp
+0-1llvm/include/llvm/InitializePasses.h
+7-455 files

LLVM/project 7d92d40mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc TosaOps.td, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Add row_gather operator (#202895)

Adds support for the row_gather operator defined by the TOSA
specification, see https://github.com/arm/tosa-specification/pull/60.

This includes:
- Operator definition
- Verification logic for the operator
- Output shape inference for the operator
- Validation checks to ensure compliance with the TOSA specification
including profile compliance and level checks.
- Canonicalization to replace row_gather with gather when row_count is
statically known to be 1.

It does not yet cover support for MXFP types. This will be added once
block scaled types are supported.
DeltaFile
+88-16mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+63-0mlir/test/Dialect/Tosa/verifier.mlir
+59-0mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+49-0mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+47-0mlir/test/Dialect/Tosa/ops.mlir
+36-0mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+342-1612 files not shown
+506-1618 files

LLVM/project b59f965lldb/test/API/lang/objc/hidden-ivars TestHiddenIvars.py

[lldb][test] Cleanup and modernize TestHiddenIvars.py (#202023)

This is simple rewrite of the test. The patch improves three things:

* It replaces old expect tests with the new expect_* variants that no
longer rely on substring matching.

* It unifies the strip/non-stripped checks as we actually produce
identical SBValues in both cases (by fetching data from the Objective-C
runtime).

* It builds this test with a shared build directory. Our stripping logic
generates a new stripped binary in a subdirectory and doesn't touch the
shared build files. This also halves the test runtime to 6s.
DeltaFile
+79-187lldb/test/API/lang/objc/hidden-ivars/TestHiddenIvars.py
+79-1871 files