LLVM/project 108df06clang/lib/AST DeclTemplate.cpp, clang/test/SemaTemplate GH181062.cpp

[clang] Backport: fix transformation of substituted constant template parameters of partial specializations

This fixes a helper so it implements retrieval of the argument replaced
for a template parameter for partial spcializations.

This was left out of the original patch, since it's quite hard to actually test.

This helper implements the retrieval for variable templates, but only for
completeness sake, as no current users rely on this, and I don't think a similar
test case is possible to implement with variable templates.

This fixes a regression introduced in #161029 which will be backported to llvm-22,
so there are no release notes.

Backport from #183348

Fixes #181062
Fixes #181410
DeltaFile
+24-0clang/test/SemaTemplate/GH181062.cpp
+10-10clang/lib/AST/DeclTemplate.cpp
+34-102 files

LLVM/project cb79aaeclang/lib/AST ASTContext.cpp, clang/test/SemaTemplate GH183075.cpp

[clang] Backport: allow canonicalizing assumed template names

Assumed template names are part of error recovery and encode just a
declaration name, making them always canonical. This patch allows
them to be canonicalized, which is trivial.

Backport from #183222

Fixes #183075
DeltaFile
+13-0clang/test/SemaTemplate/GH183075.cpp
+5-2clang/lib/AST/ASTContext.cpp
+18-22 files

LLVM/project ee4e391clang/lib/Sema SemaCXXScopeSpec.cpp, clang/test/SemaCXX GH167120.cpp

[clang] Backport: NestedNameSpecifier typo correction fix

This stops typo correction from considering template parameters
as candidates for a NestedNameSpecifier when it has a prefix itself.

I think this is better than the alternative of accepting these candidates,
but otherwise droping the prefix, because it seems more far-fetched that
someone would actually try to refer to a template parameter this way.

Since this regression was never released, there are no release notes.

Backport from #181239

Fixes #167120
DeltaFile
+11-4clang/lib/Sema/SemaCXXScopeSpec.cpp
+5-0clang/test/SemaCXX/GH167120.cpp
+16-42 files

LLVM/project 698202dclang/lib/Sema SemaOverload.cpp, clang/test/SemaTemplate temp_arg_nontype_cxx11.cpp

[clang] Backport: stop error recovery in SFINAE for narrowing in converted constant expressions

A narrowing conversion in a converted constant expression should produce an
invalid expression so that [temp.deduct.general]p7 is satisfied, by stopping
substitution at this point.

Fixes #167709
DeltaFile
+10-1clang/test/SemaTemplate/temp_arg_nontype_cxx11.cpp
+8-0clang/lib/Sema/SemaOverload.cpp
+18-12 files

LLVM/project b1b0bb9clang/lib/Sema SemaTemplateDeduction.cpp, clang/test/SemaTemplate temp_arg_template_p0522.cpp

[clang] create local instantiation scope for matching template template parameters

This fixes a bug where a partial substitution from the enclosing scope
is used to prepopulate an unrelated template argument deduction.

Backport from #183219

Fixes #181166
DeltaFile
+7-0clang/test/SemaTemplate/temp_arg_template_p0522.cpp
+2-0clang/lib/Sema/SemaTemplateDeduction.cpp
+9-02 files

LLVM/project a9a4c1eclang/docs ReleaseNotes.rst

fixup! [analyzer] Fix crash in MallocChecker when a function has both ownership_returns and ownership_takes (#183583)

Mention in the release docs
DeltaFile
+3-0clang/docs/ReleaseNotes.rst
+3-01 files

LLVM/project c82ee13clang/lib/StaticAnalyzer/Checkers MallocChecker.cpp, clang/test/Analysis malloc-annotations.c

[analyzer] Fix crash in MallocChecker when a function has both ownership_returns and ownership_takes (#183583)

When a function was annotated with both `ownership_returns` and
`ownership_takes` (or `ownership_holds`), MallocChecker::evalCall would
fall into the freeing-only branch (isFreeingOwnershipAttrCall) and call
checkOwnershipAttr without first calling MallocBindRetVal. That meant no
heap symbol had been conjured for the return value, so
checkOwnershipAttr later dereferenced a null/invalid symbol and crashed.

Fix: merge the two dispatch branches so that MallocBindRetVal is always
called first whenever ownership_returns is present, regardless of
whether the function also carries ownership_takes/ownership_holds.

The crash was introduced in #106081
339282d49f5310a2837da45c0ccc19da15675554.
Released in clang-20, and crashing ever since.

Fixes #183344.


    [2 lines not shown]
DeltaFile
+93-0clang/test/Analysis/malloc-annotations.c
+3-7clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
+96-72 files

LLVM/project 1e66cb3clang/docs ReleaseNotes.rst, clang/lib/Sema SemaExpr.cpp

[Clang] Don't diagnose missing members when looking at the instantiating class template

This backports https://github.com/llvm/llvm-project/pull/180725 to Clang
22.

The perfect matching patch revealed another bug where recursive
instantiations could lead to the escape of SFINAE errors, as shown in
the issue.
DeltaFile
+81-0clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
+1-1clang/lib/Sema/SemaExpr.cpp
+1-0clang/docs/ReleaseNotes.rst
+83-13 files

LLVM/project 55f9cf3llvm/lib/Target/RISCV/MCTargetDesc RISCVMCAsmInfo.cpp

RISCVMCAsmInfo: Remove redundant `UseAtForSpecifier = false`. NFC (#183890)

UseAtForSpecifier defaults to false in MCAsmInfo, and RISCVMCAsmInfo
never calls initializeAtSpecifiers (which sets it to true).
DeltaFile
+0-1llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
+0-11 files

LLVM/project cd6e5a6llvm/lib/Target/Hexagon HexagonISelLoweringHVX.cpp, llvm/test/CodeGen/Hexagon extract-hvx-subvector-pred-small.ll

[Hexagon] Fix extractHvxSubvectorPred shuffle mask for small predicates (#181364)

The loop generating the shuffle mask in extractHvxSubvectorPred used
HwLen/ResLen as the iteration count, but each iteration produces 8
elements (ResLen * Rep where Rep = 8/ResLen). This means the total mask
size was (HwLen/ResLen) * 8, which only equals HwLen when ResLen == 8.
For smaller predicate subvectors (e.g., <4 x i1> or <2 x i1>), the mask
was too large, causing an assertion failure in getVectorShuffle.

Fix by using HwLen/8 as the loop bound, which correctly produces HwLen
elements regardless of ResLen.

(cherry picked from commit c3a86ff2d0b397d757345fad7e29c2a6e7dbc823)
DeltaFile
+28-0llvm/test/CodeGen/Hexagon/extract-hvx-subvector-pred-small.ll
+1-1llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+29-12 files

LLVM/project c9160c2mlir/include/mlir/IR BuiltinTypeInterfaces.td BuiltinAttributes.td, mlir/lib/AsmParser AttributeParser.cpp

[mlir][IR] Generalize `DenseElementsAttr` to custom element types (#179122)

`DenseElementsAttr` supports only a hard-coded list of element types:
`int`, `index`, `float`, `complex`. This commit generalizes the
`DenseElementsAttr` infrastructure: it now supports arbitrary element
types, as long as they implement the new `DenseElementTypeInterface`.

The `DenseElementTypeInterface` has the following helper functions:
- `getDenseElementBitSize`: Query the size of an element in bits. (When
storing an element in memory, each element is padded to a full byte.
This is an existing limitation of the `DenseElementsAttr`; with an
exception for `i1`.)
- `convertToAttribute`: Attribute factory / deserializer. Converts bytes
into an MLIR attribute. The attribute provides the assembly format /
printer for a single element.
- `convertFromAttribute`: Serializer. Converts an MLIR attribute into
bytes.

Note: `convertToAttribute` / `convertFromAttribute` are mainly for

    [23 lines not shown]
DeltaFile
+124-1mlir/lib/AsmParser/AttributeParser.cpp
+25-92mlir/lib/IR/BuiltinAttributes.cpp
+87-0mlir/lib/IR/BuiltinTypes.cpp
+83-0mlir/test/IR/dense-elements-type-interface.mlir
+74-1mlir/include/mlir/IR/BuiltinTypeInterfaces.td
+32-13mlir/include/mlir/IR/BuiltinAttributes.td
+425-1078 files not shown
+579-11914 files

LLVM/project 1ff1e5fllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Stop applying nofpclass from use nofpclass attribute (#183835)

Functionally reverts a80d4329ce96856a02bd279c800c3d08619da4c9, with new
test.
This should be applied somewhere, but this is the wrong place.

Fixes regression reported after #182444
DeltaFile
+21-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+0-5llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+21-72 files

LLVM/project 32eb450llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

Update coexec-sched-effective-stall.mir
DeltaFile
+0-2llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+0-21 files

LLVM/project 702e4eclldb/test/API/macosx/delay-init-dependency TestDelayInitDependency.py

[lldb/test] Skip TestDelayInitDependency on remote platforms (#183885)

This test exercises macOS-specific linker functionality (-delay_library)
and uses a hardcoded local working directory for the launch info. It
should not run against a remote platform where neither condition holds.

Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
DeltaFile
+1-0lldb/test/API/macosx/delay-init-dependency/TestDelayInitDependency.py
+1-01 files

LLVM/project 1eb9bd8clang/lib/AST DeclTemplate.cpp, clang/test/SemaTemplate GH181062.cpp

[clang] Backport: fix transformation of substituted constant template parameters of partial specializations

This fixes a helper so it implements retrieval of the argument replaced
for a template parameter for partial spcializations.

This was left out of the original patch, since it's quite hard to actually test.

This helper implements the retrieval for variable templates, but only for
completeness sake, as no current users rely on this, and I don't think a similar
test case is possible to implement with variable templates.

This fixes a regression introduced in #161029 which will be backported to llvm-22,
so there are no release notes.

Backport from #183348

Fixes #181062
Fixes #181410
DeltaFile
+24-0clang/test/SemaTemplate/GH181062.cpp
+10-10clang/lib/AST/DeclTemplate.cpp
+34-102 files

LLVM/project f977b46llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

[AMDGPU] Add structural stall heuristic to scheduling strategies

Implements a structural stall heuristic that considers both resource
hazards and latency constraints when selecting instructions. In coexec,
this changes the pending queue from a binary “not ready to issue”
distinction into part of a unified candidate comparison. Pending
instructions still identify structural stalls in the current cycle, but
they are now evaluated directly against available instructions by stall
cost, making the heuristics both more intuitive and more expressive.

- Add getStructuralStallCycles() to GCNSchedStrategy that computes the
number of cycles an instruction must wait due to:
  - Resource conflicts on unbuffered resources (from the SchedModel)
  - Sequence-dependent hazards (from GCNHazardRecognizer)

- Add getHazardWaitStates() to GCNHazardRecognizer that returns the number
of wait states until all hazards for an instruction are resolved,
providing cycle-accurate hazard information for scheduling heuristics.
DeltaFile
+35-0llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+26-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+7-2llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+6-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+4-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+2-2llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+80-71 files not shown
+82-77 files

LLVM/project d09cd35llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir amdgpu-workload-type-scheduler-debug.mir

[AMDGPU] Add ML-oriented coexec scheduler selection and queue handling

This patch adds the initial coexec scheduler scaffold for machine
learning workloads on gfx1250.

It introduces function and module-level controls for selecting the
AMDGPU preRA and postRA schedulers, including an `amdgpu-workload-type`
module flag that maps ML workloads to coexec preRA scheduling and a nop
postRA scheduler by default.

It also updates the coexec scheduler to use a simplified top-down
candidate selection path that considers both available and pending
queues through a single flow, setting up follow-on heuristic work.
DeltaFile
+275-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+124-0llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+114-0llvm/test/CodeGen/AMDGPU/amdgpu-workload-type-scheduler-debug.mir
+64-5llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+43-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+22-0llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+642-53 files not shown
+663-149 files

LLVM/project 3b30dcdclang/include/clang/Basic CodeGenOptions.h, clang/include/clang/Options Options.td

[Driver] Add -Wa,--reloc-section-sym= to control section symbol conversion (#183472)

Wire the llvm-mc --reloc-section-sym={all,internal,none} option through
the clang driver (-Wa,--reloc-section-sym=) and cc1as
(--reloc-section-sym=). The option is only valid for ELF targets.

GNU Assembler will add the option as well.
DeltaFile
+27-0clang/test/Misc/cc1as-reloc-section-sym.s
+16-0clang/lib/Driver/ToolChains/Clang.cpp
+9-0clang/test/Driver/reloc-section-sym.c
+9-0clang/tools/driver/cc1as_main.cpp
+6-0clang/include/clang/Options/Options.td
+2-0clang/include/clang/Basic/CodeGenOptions.h
+69-02 files not shown
+72-08 files

LLVM/project 27d654cllvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU vgpr-lowering-gfx1250.mir

[AMDGPU] Fix piggybacking after commute in AMDGPULowerVGPREncoding (#183778)

After successfully commuting an instruction to be compatible with the
current VGPR MSB mode, update CurrentMode with the commuted
instruction's mode requirements. This locks in the mode bits the
commuted instruction relies on, preventing later instructions from
piggybacking and corrupting those bits.

Without this fix, a subsequent instruction needing a different mode
could piggyback onto the preceding s_set_vgpr_msb and change mode bits
that the commuted instruction depends on. For example, a nullopt src1
position (treated as 0) could be overwritten to a different value,
causing incorrect register encoding for the commuted instruction.

The fix still allows compatible piggybacking - instructions that only
add new mode bits without changing existing ones can still piggyback.
DeltaFile
+47-1llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
+9-2llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+56-32 files

LLVM/project bed8997lld/test/ELF aarch64-reloc-gotpcrel32.s, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

AArch64: Replace @plt/%gotpcrel in data directives with %pltpcrel %gotpcrel (#155776)

Similar to #132569 for RISC-V, replace the unofficial `@plt` and
`@gotpcrel` relocation specifiers, currently only used by clang
-fexperimental-relative-c++-abi-vtables, with %pltpcrel %gotpcrel. The
syntax is not used in humand-written assembly code, and is not supported
by GNU assembler.

Also replace the recent `@funcinit` with `%funcinit(x)`.
DeltaFile
+40-32llvm/test/MC/AArch64/data-directive-specifier.s
+24-8llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+22-5llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+18-1llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
+9-9llvm/test/CodeGen/AArch64/ptrauth-irelative.ll
+5-5lld/test/ELF/aarch64-reloc-gotpcrel32.s
+118-6011 files not shown
+137-7617 files

LLVM/project ce6a3d9clang-tools-extra/clang-tidy/misc UnusedUsingDeclsCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Teach `misc-unused-using-decls` that exported using-decls aren't unused (#183638)

Fixes #162619.
DeltaFile
+69-0clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls-module.cpp
+6-0clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+79-03 files

LLVM/project 620a754bolt/test/AArch64 skip-non-vfuncptr-reloc-in-relative-vtable.s

update bolt test

Created using spr 1.3.5-bogner
DeltaFile
+1-1bolt/test/AArch64/skip-non-vfuncptr-reloc-in-relative-vtable.s
+1-11 files

LLVM/project fe76e90llvm/lib/CodeGen MachineBlockPlacement.cpp, llvm/test/CodeGen/X86 code_placement_ext_tsp_size_and_perf.ll

[CodeGen] Allow `-enable-ext-tsp-block-placement` and `-apply-ext-tsp-for-size`  passed together (#183642)

Currently, the asserts fires when both `UseExtTspForPerf` and
`UseExtTspForSize` are true on a given function.

Ideally, we should allow `-enable-ext-tsp-block-placement` and
`-apply-ext-tsp-for-size` passed together, meaning run the block
placement for performance on hot functions, while run the placement for
size on cold functions.

The diff makes `UseExtTspForPerf` and `UseExtTspForSize` mutually
exclusive per-function: functions with the `OptForSize` attribute use
ext-tsp block placement for size, while the others use ext-tsp block
placement for perf.

Co-authored-by: Sharon Xu <sharonxu at fb.com>
DeltaFile
+91-0llvm/test/CodeGen/X86/code_placement_ext_tsp_size_and_perf.ll
+3-3llvm/lib/CodeGen/MachineBlockPlacement.cpp
+94-32 files

LLVM/project d72e95bclang/test/CIR/CodeGenHLSL matrix-element-expr-load.hlsl

[CIR] Use `-verify` on clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl (#182817)

Update clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl to use
`-verify` with expected CIR NYI diagnostics.
DeltaFile
+7-6clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl
+7-61 files

LLVM/project 0b88ee1clang/include/clang/CIR/Dialect/IR CIRAttrs.td CIRTypes.h, clang/lib/CIR/Dialect/IR CIRTypes.cpp CIRAttrs.cpp

[CIR] Infrastructure and MemorySpaceAttrInterface for Address Spaces (#179073)

Related: https://github.com/llvm/llvm-project/issues/175871,
https://github.com/issues/assigned?issue=llvm%7Cllvm-project%7C179278,
https://github.com/issues/assigned?issue=llvm%7Cllvm-project%7C160386

- Introducing the LangAddressSpace enum with offload address space kinds
(offload_private, offload_local, offload_global, offload_constant,
offload_generic) and the LangAddressSpaceAttr attribute.


- Generalizes CIR AS attributes as MemorySpaceAttrInterface and Attaches
it to `PointerType`. Includes test coverage for valid IR roundtrips and
invalid address space parsing.

This starts a series of patches with the purpose of bringing complete
address spaces support features for CIR. Most of the test coverage is
provided in subsequent patches further down the stack. note that most of
these patches are based on: https://github.com/llvm/clangir/pull/1986
DeltaFile
+163-39clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+104-4clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
+52-3clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+41-0clang/test/CIR/IR/address-space.cir
+29-3clang/test/CIR/IR/invalid-addrspace.cir
+17-3clang/include/clang/CIR/Dialect/IR/CIRTypes.h
+406-5212 files not shown
+474-7918 files

LLVM/project 6f9c68dllvm/test/Transforms/LoopVectorize/AArch64 scalable-strict-fadd.ll sve-interleaved-masked-accesses.ll

[VPlan] Don't adjust trip count for DataAndControlFlowWithoutRuntimeCheck (#183729)

Previously, the canonical IV increment may have overflowed to a non-zero
value due to vscale being a non power-of-two. So we used to emit a
runtime check for this.

If you didn't want the runtime check,
DataAndControlFlowWithoutRuntimeCheck skipped it and instead tweaked the
trip count so it wouldn't overflow.

However #144963 stopped the check from ever being emitted because vscale
is always a power-of-two on AArch64 and RISC-V, so it never overflowed
to a non-zero value. And in #183292 the code to emit the check was
removed. But we never restored the trip count back to normal when the
target's vscale was a power-of-two.

Now that vscale is always a power-of-two, this PR avoids adjusting it. A
follow up NFC can then remove DataAndControlFlowWithoutRuntimeCheck.
DeltaFile
+174-195llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+78-90llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
+61-66llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
+13-43llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
+40-2llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+14-20llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
+380-41622 files not shown
+438-63728 files

LLVM/project 6f27060clang/lib/CIR/Dialect/IR CIRTypes.cpp

fix fmt
DeltaFile
+4-4clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+4-41 files

LLVM/project 5f22decclang/docs LanguageExtensions.rst ReleaseNotes.rst, clang/lib/Sema SemaChecking.cpp

Clang: Deprecate float support from __builtin_elementwise_max (#180885)

Now we have
  __builtin_elementwise_maxnum
  __builtin_elementwise_maximum
  __builtin_elementwise_maximumnum
DeltaFile
+17-0clang/test/Sema/builtins-elementwise-math.c
+13-1clang/lib/Sema/SemaChecking.cpp
+6-2clang/test/SemaCXX/builtins-elementwise-math.cpp
+4-4clang/docs/LanguageExtensions.rst
+3-0clang/docs/ReleaseNotes.rst
+1-1libclc/clc/lib/generic/math/clc_fdim.inc
+44-81 files not shown
+46-87 files

LLVM/project cc9f25dclang/include/clang/CIR/Dialect/IR CIRTypes.td CIRTypes.h, clang/lib/CIR/Dialect/IR CIRTypes.cpp

rename normalize AS function
DeltaFile
+3-3clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+2-2clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+1-1clang/include/clang/CIR/Dialect/IR/CIRTypes.h
+6-63 files

LLVM/project 62cfe16libc/src/__support/math acospif.h asinpif.h, libc/test/src/math acospif_test.cpp

[libc][math][c23] implement C23 `acospif` math function (#183661)

Implementing C23 `acospi` math function for single-precision with the
header-only approach that is followed since #147386
DeltaFile
+100-0libc/src/__support/math/acospif.h
+51-0libc/test/src/math/smoke/acospif_test.cpp
+8-41libc/src/__support/math/asinpif.h
+37-0libc/src/__support/math/inv_trigf_utils.h
+33-0libc/test/src/math/exhaustive/acospif_test.cpp
+29-0libc/test/src/math/acospif_test.cpp
+258-4125 files not shown
+429-6131 files