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[libc][math] Refactor hypotf16 to Header Only (#180511).

closes #175337
part of #175336

Reapply "[msan] Switch switch() from strict handling to (icmp eq)-style handling" (#180636) (#181112)

This reverts https://github.com/llvm/llvm-project/pull/180636 i.e.,
relands https://github.com/llvm/llvm-project/pull/179851.

It was originally reverted because of buildbot failures. When compiling
switch statements with many cases (e.g., AMDGPUGenMCCodeEmitter.inc has
>30,000 cases), MSan's instrumentation created an extremely long chained
expression for the shadow computation. Although that was legal LLVM IR,
it caused the subsequent JumpThreadingPass to have a stack overflow.

This reland avoids the issue by limiting the number of cases considered
(`-msan-switch-precision`), with the tradeoff of niche false negatives
(only in the case where the condition is partly uninitialized and the
first x cases still have a defined comparison, but a case # > x does not
have a fully-defined comparison).

This reland also adds some TODOs for possible improvements.


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[libc][math] Refactor ffma implementation to header-only in src/__support/math folder (#175304).

Part of #147386

in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450

[libc][math] Refactor tanhf implementation to header-only in src/__support/math folder. (#178554)

Part of https://github.com/llvm/llvm-project/issues/147386
closes https://github.com/llvm/llvm-project/issues/178493

[Clang][RISCV] Add Zvabd intrinsics

Doc:

* https://github.com/riscv/integer-vector-absolute-difference
* https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/424

Authored-by: Zhenxuan Sang <sang at bytedance.com>
Co-Authored-by: Pengcheng Wang <wangpengcheng.pp at bytedance.com>

Reviewers: preames, topperc, kito-cheng

Pull Request: https://github.com/llvm/llvm-project/pull/180929

[libc][math] Refactor bf16addf128 to header only (#181058)

Resolves #181018
Part of #147386

[ELF] Move RISCV scanSectionImpl next to getRelExpr. NFC

Move scanSectionImpl and scanSection to right after getRelExpr and
before relocate, matching the ordering used in X86_64.cpp and PPC64.cpp.

Revert "[LLD] Add support for statically resolved vendor-specific RISCV relocations. (#169273)" (#181336)

This reverts commit 0c6d7a40187e5e6cbdff1cf5dbdb6fe91054bef4 and
follow-up 7dfa132936a89a966befb6045f306cb9905c6dab.

It landed prematurely with multiple issues in the implementation and
tests.

[lldb/API] Add __getitem__ subscript support to python SBAPI list class (#181457)

This patch adds __getitem__ method to the SBAPI list classes that were
missing subscript support, enabling Pythonic index access (e.g.,
list[0], list[-1]) in Python bindings.

The implementation adds __getitem__ to the following classes:
- SBStringList
- SBFileSpecList
- SBProcessInfoList
- SBMemoryRegionInfoList
- SBThreadCollection
- SBBreakpointList
- SBModuleSpecList
- SBTypeList

Each implementation follows the same pattern:
- Type validation (raises TypeError for non-integer indices)
- Range validation with negative index support (raises IndexError for

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[RISCV] Calculate max call frame size in RISCVTargetLowering::finalizeLowering. (#181302)

I want to enable the frame pointer when the call frame size is too large
to access emergency spill slots. To do that I need to know the call
frame size early enough to reserve FP.

The code here is copied from AArch64. ARM does the same. I did not check
other targets.

Splitting this off separately because it stops us from unnecessarily
reserving the base pointer in the some RVV tests. That appears to due to
this check

(!hasReservedCallFrame(MF) && (!MFI.isMaxCallFrameSizeComputed() ||
MFI.getMaxCallFrameSize() != 0))) &&

By calculating early !MFI.isMaxCallFrameSizeComputed() is no longer true
and the size is zero.

[RISCV] Convert some multiclasses in RISCVInstrInfoV.td to classes if they only have one child def. NFC (#181408)

The child def requires an empty string which looks odd. Use classes and
inheritance instead.

[GlobalISel] Fix type mismatch in LegalizerHelper ternary (#180865)

### Summary

Fix type mismatch in ternary expression that causes GCC `-Werror=extra`
to fail.

### Details

GCC's `-Werror=extra` enforces stricter type consistency in ternary
expressions, in this case unsigned and an enum literal.

### Tested

- Built with ToT clang and GCC 13.3.0 on Linux x86_64 (not really
because there are other warnings, but this one is gone).
- All existing tests pass

Rebase before commit

Created using spr 1.3.6-beta.1

[RISCV] Add SpacemiT A100 processor definition (#174052)

[clang][NFC] Add missing indentation for expected-notes in C++ DR tests

[clang] Ensure -mno-outline adds attributes

Before this change, `-mno-outline` and `-moutline` only controlled the
pass pipelines for the invoked compiler/linker.

The drawback of this implementation is that, when using LTO, only the
flag provided to the linker invocation is honoured (and any files which
individually use `-mno-outline` will have that flag ignored).

This change serialises the `-mno-outline` flag into each function's
IR/Bitcode, so that we can correctly disable outlining from functions in
files which disabled outlining, without affecting outlining choices for
functions from other files. This matches how other optimisation flags
are handled so the IR/Bitcode can be correctly merged during LTO.

Release Note

[clang] Add clang::no_outline Attribute (#163666)

This change:

- Adds a `[[clang::no_outline]]` function attribute for C and C++. There
is no equivalent GNU syntax for this attribute, so no `__attribute__`
syntax.
- Uses the presence of `[[clang::no_outline]]` to add the `nooutline`
attribute to IR function definitions.
- Adds test for the above.

The `nooutline` attribute disables both the Machine Outliner (enabled at
Oz for some targets), and the IR Outliner (disabled by default).

Fixes #144135

[RISCV] Simplify Extension Predicates, Compatibility (#181255)

This pushes some of our simplifications to extension dependencies into
other parts of RISCVISAInfo and into the tablegen predicates.

The key affected pieces are:
- Error messages around Zcd incompatibilities now reference only `zcd`.
- We now have a big list of extensions that are rv32-only.

[mlir] Fix #176920 Add MLIRBindingsPythonLibHeaders library (#181447)

MLIRBindingsPythonLibHeaders includes internal headers.

Revert "[TableGen] Introduce MatcherList to manage a linked list of Matchers. NFC (#177875)"

This reverts commit 39613943855e6a82b1bb4c3d16fbaf2289a5d739.

It's failing across multiple build bots.

[flang][cuda] Add entry point for set/get default stream (#181440)

[TableGen] Introduce MatcherList to manage a linked list of Matchers. NFC (#177875)

The previous memory management involved passing around references to the
std::unique_ptr next pointer in each Matcher. Scopes and
SwitchOpcode/SwitchType did not use std::unique_ptr internally, but
would sometimes need to have the pointers to their children moved to
temporary std::unique_ptrs that may be modified and then put back into
the Scope/Switch. Other code used manual deletion.

This patch introduces a MatcherList object that encapsulates list
management and ownership. The interface is based on std::forward_list
using the libcxx implementation for reference.

Once a Matcher is added to a MatcherList it can only be in that list or
spliced into another list. This ensures it is always owned by a list
that will be responsible for deleting it.

Scope and SwitchOpcode/Type children are now MatcherLists rather than
Matcher*. A nice side effect of this is that we no longer need a Size

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Revert "[libclc] replace float remquo with amd ocml implementation" (#181443)

Reverts llvm/llvm-project#177131
It broke SPIRV target: error in backend: unable to legalize instruction:
%88:fid(s32) = G_FCANONICALIZE

[libclc] Fix memory_scope and memory_order of *mem_fence builtins (#181311)

See OpenCL spec 6.15.12.5.
https://registry.khronos.org/OpenCL/specs/3.0-unified/html/OpenCL_C.html#fences

// Older syntax memory fences are equivalent to atomic_work_item_fence
with the // same flags parameter, memory_scope_work_group scope, and
ordering as follows:
void mem_fence(cl_mem_fence_flags flags)        // memory_order_acq_rel
void read_mem_fence(cl_mem_fence_flags flags)   // memory_order_acquire
void write_mem_fence(cl_mem_fence_flags flags)  // memory_order_release

---------

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>

Revert "[libclc] replace float remquo with amd ocml implementation (#177131)"

This reverts commit 20c15c7afe97a546d339a5500d3fa273412e2fda.

[Hexagon] Fix APInt assertion in getBuildVectorConstInts (#181202)

Truncate the ConstantSDNode APInt value to the element bit width before
creating the ConstantInt. After type legalization, a ConstantSDNode may
have a wider type than the vector element (e.g., i32 constant for an i16
element).

[SYCL][Driver] Pass path to libsycl.so by default for SYCL compilation. (#174877)

This patch updates the default behavior for `SYCL` offload compilations.

Specifically, we now pass the path to the SYCL runtime library,
`libsycl.so`, by default to the `clang-linker-wrapper` tool, which is
responsible for linking the `SYCL` runtime library. We also add the SYCL
header include paths by default to both the SYCL host and device
compilations.

[lldb][macOS] Don't fetch settings in Host, to keep layering (#181406)

I introduced a dependency from Host on Core without realizing it in an
earlier PR, while adding a setting to disable the new shared cache
binary blob scanning/reading in HostInfoMacOSX, which caused build
problems. Thanks to Alex for figuring out the build failure I caused.

Add a bool to the methods in HostInfoMacOSX, and have the callers (in
Core and various plugins etc) all fetch the
symbols.shared-cache-binary-loading setting from ModuleList, and pass
the result in.

The least obvious part of this is in ProcessGDBRemote where we first
learn the shared cache filepath & uuid, it calls
HostInfoMacOSX::SharedCacheIndexFiles() - this is only called when the
shared cache binary loading is enabled, so I conditionalize the call to
this method based on the setting.

rdar://148939795

Update callback to return TargetOptions