[lldb][test] Allow LLDB_TEST_EXTRA_TSAN_OPTION (#237331)
Some platforms require additional ThreadSanitizer options. For example,
is macOS we need a workaround to make race conditions in some standard
library containers visible (as libc++ on our bot is not instrumented).
This patch adds LLDB_TEST_EXTRA_TSAN_OPTIONS which allows specifying
additional TSAN_OPTIONS that are appended to the standard TSAN_OPTIONS
used in the lldb tests.
[libc++] Added a benchmark for std::reduce with a trivial reduction operator (std::plus) (#236853)
This PR adds benchmarks for serial reductions with a trivial operator,
to specifically capture the cases where the compiler can do a good job
optimising the loop. This includes cases where the compiler can already
perform reordering without an explicit permission (e.g. with `int`s) and
where it requires an opt-int like `clang loop vectorize(enable)
interleave(enable)` (e.g. with `float`s, which libc++ currently doesn't
do).
Part of #234887.
[lldb] Test that unterminated DW_FORM_strp names are rejected (#237354)
c38a7054a1d8 bounded DataExtractor::PeekCStr and converted
DWARFFormValue::AsCString, but only tested the DataExtractor and Mach-O
paths. Add a DWARF test so AsCString can't regress to returning a
pointer into a .debug_str string with no terminator.
RuntimeLibcalls: Use explicit types for F80, F128 and PPCF128 libcalls (#235145)
LDbl only makes sense for encoding the long double libm functions. Other
functions have need of the specific type. Separately, LDbl brokenly
assumes
double instead of checking the module's long double format. Some
functions
are inappropriately using a specific type instead of LDbl. I'll fix both
of these issues separately.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CodeGen] Use shared RegClassInfo in basic, greedy and fast allocators (#226523)
Make RegAllocBase use the MachineRegisterClassInfo analysis and publish
the
newly frozen set to it with updateReservedRegs. This reuses the set
computed by
freezeReservedRegs() instead of calling TRI->getReservedRegs() again, so
the
shared state becomes correct for everyone without an additional
reserved-set
computation.
No allocator should keep a private RegisterClassInfo after this.
A pass that changes the reserved set and is followed by an allocator no
longer
has to publish it by hand.
AI-assisted.
[SDAG] Improve bf16 converts with fast-math flags. (#231044)
This is a SDAG equivalent of #200741, where given NoNan flags we can
avoid creating for nan inputs.
[AArch64][MTE] Tag dynamic allocas in AArch64StackTagging
Instrument dynamic allocas in the memtag-stack pass, more or less
following the the way AddressSanitizer does: by instrumenting
stackrestore to un(poison/tag) allocas when free'd.
- Dynamic allocas are given 16-byte alignment and padded to 16-bytes.
- At lifetime.start (or at the alloca if no lifetimes), the dynamic
alloca is tagged.
- The most recently executed dynamic alloca is tracked in an extra
per-func static alloca. The address of this static alloca is used
as the bottom (highest address) of the dynamic alloca section of
the frame, while the value stored there is treated as the current
top (lowest address) of the frame.
- At llvm.stackrestores, memory is untagged from the restored sp
to the last executed dynamic alloca.
- At function returns, memory is untagged from the last executed
dynamic alloca to the bottom of the (dynamic alloca section of) the
frame.
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[AMDGPU] Bundle counter layouts as features
Generation feature lists stay plain lists: the shared gfx11 and gfx12
counter layouts become features implying their fields, instead of
defvars spliced in with !listconcat.
Change-Id: Id1656a599f7d9b4fa43c82bb811ca311881dd603
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[AArch64][MTE] Fix bit width in variable-size settag loop expansion
expandSetTagLoopVar peels a single STG granule when the size is an odd
multiple of 16 (bit 4 set). It built this test with TBZX, the bit-32..63
form (which checks bit 36), when it should have used the TBZW form, which
actually tests bit 4.
Assisted-By: Claude
[AMDGPU] Keep wait counter layout in the backend
Counter field layouts only matter for instruction encoding; no
frontend needs them. Drop the TargetParser copy, the GPU table column
and the emitter changes, and move CounterLayout and its encode/decode
helpers back into AMDGPUBaseInfo, replacing the IsaVersion parameter.
Unit tests now check per-GPU masks and encodings through
MCSubtargetInfo.
Change-Id: Iaa0d100af5e3f1885da9261fb97340709955488a
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
X86: Remove kill argument from addRegOffset (#237316)
This is now unused / always false. A few were true but had no tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
PeepholeOptimizer: Fix value tracking through SUBREG_TO_REG
The tracked source of a SUBREG_TO_REG was reported as the subregister
index of the inserted value, rather than the full inserted value. The
inserted value is never a register class supporting that index, so
this never found a usable source.
Some of the tests are regressions but I have a separate patch which
recovers those.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Revert "[ValueTracking] Check noundef before applying square (fmul_self)" (#237161)
This reverts commit 05404cec67c67215394d2253002961a1d97a2f20.
It reintroduces the performance regression reported in #174763 where the
same check was previously reverted. Also as mentioned on #232178 the
policy is not to fix pre-existing multi-use undef issues without a
real-world miscompile.
[MachineLICM] Cache regmask clobbered register units per function
HoistRegionPostRA calls applyBitsNotInRegMaskToRegUnitsMask for every
regmask operand (i.e. every call) in a loop, and again for each enclosing
loop. Each call walks every physical register and its register units,
which is expensive on targets with many registers (about 700 on AArch64),
even though the result depends only on the mask, and calls almost always
use one of a few calling-convention masks.
Compute the clobbered register units once per mask and function and OR
the cached set into RUClobbers. The result is identical by construction.
[RISCV][P-ext] Improve codegen for funnel shifts (#235245)
This patch improves RV32 code generation for 64-bit funnel shifts. It
splits them into 32-bit slx/srx operations and uses merge instructions
to select the appropriate halves.
This removes branches and reduces the worst-case dynamic instruction
count.
[SystemZ][z/OS] Add missing ADA reference to DWARF sections (#237276)
Labels marked as DATA needs a reference to the ADA. However, this is
missing for the DWARF sections, which can lead to crashes in certain
scenarios. Fix is to set the ADA reference.
Assisted by: IBM Bob
[gn][NFC] Remove obsolete macro definition (#219000)
The _LIBCPP_DISABLE_NEW_DELETE_DEFINITIONS macro is not honoured anymore
since afc5cca0d401, 3 years ago. This has been dead code since then.
[libc++] Link to CI jobs instead of overall runs in LNT reports (#237340)
We were including a link to the Github workflow run which produced a
report, but what we really want is the specific job, since a run can
contain multiple jobs.
[AMDGPU] Load the inputs of any_extend_to_perm_wide_src
Do not depend on the kernel argument lowering: load the vector and the
byte in a non-kernel function, like the other tests in permute_i8.ll.
AI-assisted.
[AMDGPU] Check whitespace in roundtripped disassembler tests (#237301)
This has been useful in the past for catching unintended extra
whitespace between operands.
CodeGen: Finally delete LiveVariables
This is about 12 years overdue.
The extra workaround run in PPC was last removed in #222416, but
reverted by #225816. There was never a reproducer or specific patch to
fix this, though it's possible the now consistent dead flag handling
fixed or at least hid the LiveRangeCalc error.
[ci] Run the LLVM test-suite LNT pipeline on a schedule (#237286)
This adds a workflow that runs twice a day using the latest Clang /
LLVM, and submits the results of the LLVM Test Suite to LNT. In the
future we could decide to set up advanced triggering to backfill history
and automatically bisect regressions like we do for libc++, if that's
desired.
Assisted by Claude
[DAGCombine] Fold (abdu x, y) -> (sub x, y) iff x >= y (#237314)
Drop the equivalent fold from TargetLowering expansion.
This allows us to the optimize these cases even when we don't go through
expansion.
Assisted-by: Claude
[ci] Fix timing of the LLVM test-suite LNT runs (#237310)
The test-suite was run with `--use-perf time`, but we were not
installing perf on the runners. As a drive-by cleanup, also stop passing
`--benchmarking-only` redundantly from machines.json, since the workflow
always passes it.
