LLVM/project 755f3e4llvm/lib/Target/ARM ARMAsmPrinter.cpp ARMISelLowering.cpp, llvm/test/CodeGen/ARM elf-preemption.ll weak-hidden-pic.ll

[ARM] Use .reloc for dso_local weak symbols in PIC mode instead of GOT indirection (#209660)

In ARM ELF PIC mode, weak symbols referenced via the constant pool use a
PC-relative expression like `.long sym-(.LPC+8)`. The assembler eagerly
resolves this when the symbol and reference are in the same section,
which prevents the linker from overriding a weak definition with a
non-weak one from another object file.

The previous approach forced *all* weak symbols through GOT indirection.
That works, but `dso_local` weak symbols with hidden/protected
visibility are non-preemptible — they don't need GOT indirection, and
the extra load is wasteful. This patch emits a `.reloc` directive for
such symbols instead, forcing the assembler to produce an `R_ARM_REL32`
relocation while keeping a direct PC-relative reference from the
constant pool.

Default-visibility weak symbols (even `dso_local`) remain routed through
the GOT because they stay exported and preemptible in shared objects,
and `R_ARM_REL32` against an external symbol cannot be used when making

    [2 lines not shown]
DeltaFile
+103-4llvm/test/CodeGen/ARM/elf-preemption.ll
+34-0llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+8-6llvm/test/CodeGen/ARM/weak-hidden-pic.ll
+3-8llvm/lib/Target/ARM/ARMISelLowering.cpp
+0-9llvm/lib/Target/ARM/ARMTargetMachine.h
+1-2llvm/lib/Target/ARM/ARMFastISel.cpp
+149-291 files not shown
+150-317 files

LLVM/project fac6cddllvm/lib/Target/ARM ARMISelLowering.cpp ARMConstantPoolValue.cpp, llvm/test/CodeGen/ARM subtarget-features-long-calls.ll

[ARM] support -mlong-calls -fPIC on arm32 (#147313)

support -mlong-calls -fPIC on arm32
try fixing issuse https://github.com/llvm/llvm-project/issues/39970 and
maybe helpful for soving the problem encourted in
https://github.com/llvm/llvm-project/pull/142982
DeltaFile
+235-27llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
+43-5llvm/lib/Target/ARM/ARMISelLowering.cpp
+5-4llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
+4-2llvm/lib/Target/ARM/ARMConstantPoolValue.h
+287-384 files

LLVM/project 0ee40c5llvm/test/Analysis/CostModel/AArch64 sve-intrinsics.ll, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-64-128bit-loads.ll sve-fixed-length-masked-64-128bit-stores.ll

[AArch64][SVE] Prefer SVE over scalarization for masked load/store of bf16 vectors (#210986)

During lowering of masked load/store for bf16 fixed-length vectors,
prefer emitting SVE instructions instead of scalarized branching code
whenever "+sve" is enabled in "target-features", regardless of whether
"+bf16" is present. The resulting changes can be seen in the following
test cases.
- llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
- llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll

The direct cause of generating scalarized branching code is that the
"scalarize-masked-mem-intrin" optimization uses isLegalMaskedLoadStore
to determine whether the target natively supports masked load/store
operations. In AArch64TTIImpl::isLegalMaskedLoadStore,
isElementTypeLegalForScalableVector only treats bf16 vector operations
as legalizable when "+bf16" is enabled in "target-features". This
introduces an unnecessary restriction.

Therefore, this patch removes this restriction from

    [3 lines not shown]
DeltaFile
+217-0llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always-bf16.ll
+10-86llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
+9-83llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll
+68-0llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+4-5llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
+4-5llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
+312-1791 files not shown
+314-1837 files

LLVM/project c45be99llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize select-cmp-blend-chain.ll debugloc.ll

[LV] Simplify Blend/Select chain for tail folding outer loop reductions (#209659)

Predicated tail-folding outer loop reductions will generate a `Blend`
recipe for the predicate in-loop op and a `select` for tail-folding.

E.g.
```llvm
%blend = select %pred.mask, %inloop.op, %red.phi
%sel   = select %header.mask, %blend, %red.phi
```

This patch simplifies this Blend/Select chain to
```llvm
%logical.and = select %header.mask, %pred.mask, false
%sel         = select %logical.and, %inloop.op, %red.phi
```

This enables further optimization opportunities from CSE and further
simplification since the `%header.mask` will become an all-true-mask in

    [3 lines not shown]
DeltaFile
+82-4llvm/test/Transforms/LoopVectorize/select-cmp-blend-chain.ll
+46-0llvm/test/Transforms/LoopVectorize/debugloc.ll
+16-16llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
+6-12llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
+7-7llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
+14-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+171-396 files not shown
+184-5712 files

LLVM/project 99992e5flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-reduction-remapping.f90

[flang][acc] fix array-section reductions on boxed arrays (#211648)

Reduction lowering (genReductions in flang/lib/Lower/OpenACC.cpp) only
remapped the reduced symbol to the acc.reduction result when the object
was a whole array (`isWholeSymbol` guard). For sections, the remap was
skipped, so hlfir.designate for element accesses inside the compute
region kept resolving through the original host declare's box instead of
the private reduction copy — the reduction ran on a private buffer that
never got read back.

Checked and confirmed dropping the boolean is safe for: non-1-starting
sections (recipe already compensates via a deliberate base-pointer
shift), SIZE/UBOUND/LBOUND inside privatized sections (intended
semantics), OPTIONAL dummies (pre-existing TODO, now fails loudly
instead of silently), combined constructs.
DeltaFile
+87-0flang/test/Lower/OpenACC/acc-reduction-remapping.f90
+22-0flang/test/Lower/OpenACC/Todo/acc-reduction-component.f90
+7-10flang/lib/Lower/OpenACC.cpp
+116-103 files

LLVM/project 3a418e3clang/lib/Sema SemaOverload.cpp, clang/test/SemaCXX deleted-function-deduction-failure.cpp

[clang][sema] Call expressions are constructed for undeduced deleted functions (#208488)

The deleted function path of overload resolution always constructed a CallExpr node
for the called function even if the function could not be deduced.
This case is handled in other paths by DiagnoseUseOfDecl which does perform that
test. The delete path cannot use that path though, as DiagnoseUseOfDecl rejects
deleted functions, and the entire point of this code is to permit the continued
evaluation of code even if the resolved function was deleted.

To fix this we now manually check for a complete type before continuing to construct
a potentially bogus CallExpr.
DeltaFile
+49-0clang/test/SemaCXX/deleted-function-deduction-failure.cpp
+4-0clang/lib/Sema/SemaOverload.cpp
+53-02 files

LLVM/project 31f6ba3llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp

Fix error reported by -Wrange-loop-construct (#211657)

One system I'm building on adds -Wrange-loop-construct to the list of
-W<group> options. This results in the compile error:

```
/home/perry/llvm/Woz/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp:37:19: error: loop variable '[ID, N]' creates a copy from type 'std::pair<unsigned int, llvm::MDNode *> const' [-Werror,-Wrange-loop-construct]
  for (const auto [ID, N] : MD) {
                  ^
/home/perry/llvm/Woz/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp:37:8: note: use reference type 'std::pair<unsigned int, llvm::MDNode *> const &' to prevent copying
  for (const auto [ID, N] : MD) {
       ^~~~~~~~~~~~~~~~~~~~
                  &
1 error generated.
```
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+1-11 files

LLVM/project 725737bllvm/lib/IR AutoUpgrade.cpp, llvm/test/Assembler auto_upgrade_coro_end_result.ll

[LLVM] Auto-upgrade legacy coro.end results (#211081)

When `llvm.coro.end` and `llvm.coro.end.async` changed from returning
`i1`
to returning `void` in #159278, the bitcode auto-upgrader continued to
handle
only the older two-argument `llvm.coro.end` form.

As a result, valid bitcode produced before that transition fails
verification
when a current LLVM ThinLTO backend materializes a module containing
either:

* the three-argument, `i1`-returning `llvm.coro.end`; or
* the `i1`-returning `llvm.coro.end.async`.

Teach `AutoUpgrade` to recognize both legacy declarations and rebuild
their
calls with the current `void`-returning intrinsics. If the legacy result

    [15 lines not shown]
DeltaFile
+49-0llvm/test/Assembler/auto_upgrade_coro_end_result.ll
+24-4llvm/lib/IR/AutoUpgrade.cpp
+73-42 files

LLVM/project 257e81fmlir/include/mlir/Dialect/Tosa/IR TosaTypesBase.td, mlir/test/Conversion/TosaToLinalg tosa-to-linalg-pipeline.mlir

Revert "[mlir][tosa] Combine unranked/ranked tensor types into single type" (#211701)

Reverts llvm/llvm-project#209737

Breaks bots, see
https://github.com/llvm/llvm-project/pull/209737#issuecomment-5064857765
DeltaFile
+68-40mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
+20-20mlir/test/Dialect/Tosa/invalid.mlir
+5-5mlir/test/Dialect/Tosa/verifier.mlir
+1-1mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
+94-664 files

LLVM/project 125113ellvm/test/CodeGen/AMDGPU soft-waitcnt-deletion.mir soft-waitcnt-loop-deletion.ll

Rebase

Change-Id: I5f8b91764af1964f6b4b68f07f08170546a5c83b
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
+2-2llvm/test/CodeGen/AMDGPU/soft-waitcnt-loop-deletion.ll
+9-92 files

LLVM/project 1538937mlir/include/mlir/Dialect/Tosa/IR TosaTypesBase.td, mlir/test/Conversion/TosaToLinalg tosa-to-linalg-pipeline.mlir

Revert "[mlir][tosa] Combine unranked/ranked tensor types into single type (#…"

This reverts commit aab7e0b08d30ddca5858069a4c14c1ea3da042e6.
DeltaFile
+68-40mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
+20-20mlir/test/Dialect/Tosa/invalid.mlir
+5-5mlir/test/Dialect/Tosa/verifier.mlir
+1-1mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
+94-664 files

LLVM/project 5acf75dllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU expert_scheduling_gfx12.mir soft-waitcnt-deletion.mir

[AMDGPU] Check all incoming edges before deleting soft waits

Change-Id: I92ca9784405e53f46aa4c8701e417d32f00bbff7
DeltaFile
+724-1llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
+431-0llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
+128-38llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+118-0llvm/test/CodeGen/AMDGPU/soft-waitcnt-loop-deletion.ll
+46-0llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+36-0llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+1,483-3910 files not shown
+1,607-6116 files

LLVM/project 31b6ee9llvm/lib/Target/AArch64 AArch64PointerAuth.cpp, llvm/test/CodeGen/AArch64 pauth-lr-tail-call-fpdiff.ll sign-return-address-pauth-lr.ll

[llvm][AArch64] Enable .cfi_set_ra_state by default for PAuth_LR (#211698)
DeltaFile
+48-24llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
+35-35llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
+34-34llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr-mir.ll
+18-9llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
+4-4llvm/test/CodeGen/AArch64/sign-return-address-pauthlr-slh.ll
+1-1llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+140-1076 files

LLVM/project 1ec7a13clang/include/clang/AST ExprCXX.h, clang/lib/Sema TreeTransform.h

[Sema] Fix assertion in TreeTransform when rebuilding CXXParenListInitExpr (#203715)
DeltaFile
+13-0clang/test/SemaTemplate/instantiate-member-initializers.cpp
+4-0clang/include/clang/AST/ExprCXX.h
+2-1clang/lib/Sema/TreeTransform.h
+19-13 files

LLVM/project 490b49flldb/source/Plugins/Process/gdb-remote GDBRemoteCommunicationClient.cpp ProcessGDBRemote.cpp

[lldb] Fix qSpeedTest radix mistake, make number parsings explicit (#211495)

The documentation for qSpeedTest says

```
send packet: qSpeedTest:response_size:response-size;
read packet: data:<response data>

response-size is a hex encoded unsigned number up to 64 bits in size.
```

debugserver implements qSpeedTest as per this documentation, but lldb
sends the number in decimal (base 10), and lldb-server parses it as base
10. I changed lldb and lldb-server to base 16. This is a maintenance
command used by lldb developers exclusivley, so IMO I'm not handling a
migration for old/new servers or defining a new packet or key. I was
running some packet transmission tests with debugserver and noticed
debugserver was sending much larger packets than requested; that's the
kind of failure you see when there is a mismatch.

    [21 lines not shown]
DeltaFile
+32-32lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+20-20lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+9-8lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
+5-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
+1-1lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerPlatform.cpp
+67-615 files

LLVM/project bee0671clang/include/clang/Basic AArch64CodeGenUtils.h, clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp

[CIR][AArch64] Lower Vector saturating shift and narrow intrinsics (#209389)

### summary

part of : https://github.com/llvm/llvm-project/issues/185382

lower all intrinsics in :
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-right-and-narrow
DeltaFile
+344-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-331clang/test/CodeGen/AArch64/neon-intrinsics.c
+99-28clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+20-11clang/include/clang/Basic/AArch64CodeGenUtils.h
+463-3704 files

LLVM/project 93740f6clang/test/OpenMP target_map_nested_ptr_member_mapper_codegen.cpp, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[OpenMP] Propagate PRESENT to pointee entries in mapper codegen

Extend mapper map-type-modifier propagation to include PRESENT, gated to entries
that have an attach pointer (HasAttachPtr): the pointee data, whose storage
differs from the struct being mapped. A present modifier on the outer map/motion
clause must require that pointee to be present on the device; the present-check
on the struct's own storage does not cover it.

The propagation is gated on a new PropagatePresentToPointee argument to
emitUserDefinedMapper, set by callers only for OpenMP >= 6.0. Before 6.0 the
present modifier is treated as not applying to the pointee: the spec committee
confirmed the divergence between the present 'motion' modifier (to/from) and the
present map-type modifier (map) was unintentional, to be fixed as an OpenMP 6.0
erratum, so for 5.2 present is ignored for the pointee for both map and to/from.

Regular struct members receive only ALWAYS/DELETE/CLOSE; attach-ptr/pointee
entries additionally receive PRESENT at OpenMP >= 6.0. ATTACH entries receive no
modifier bits.


    [8 lines not shown]
DeltaFile
+202-0clang/test/OpenMP/target_map_nested_ptr_member_mapper_codegen.cpp
+65-0offload/test/mapping/mapper_map_mbr_then_present_mbr_ptee.c
+58-0offload/test/mapping/mapper_map_present_ptee.c
+37-11llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+46-0offload/test/mapping/mapper_map_mbr_ptee_then_present_mbr_ptee.c
+15-8offload/test/mapping/mapper_target_update_present_ptee.c
+423-192 files not shown
+446-278 files

LLVM/project 475ddabclang/lib/CodeGen CGOpenMPRuntime.cpp, clang/test/OpenMP target_map_nested_ptr_member_mapper_codegen.cpp declare_mapper_codegen.cpp

[OpenMP] Track attach-ptr entries in mapper codegen (HasAttachPtr)

Add a per-entry HasAttachPtr flag to MapInfosTy. It is set for entries that
have an attach pointer (and thus an accompanying ATTACH entry linking that ptr
to its pointee): pointee/combined entries whose storage differs from the struct
being mapped. It is NOT set for the ATTACH entries themselves.

In emitUserDefinedMapper, entries with HasAttachPtr (or the ATTACH bit, or the
Flang/MLIR PreserveMemberOfFlags) do not receive a new outer MEMBER_OF: pointee
data occupies a different storage block than the struct, and ATTACH entries
just link a ptr to its ptee. Existing inner MEMBER_OF bits are still shifted.

Clang (CGOpenMPRuntime) and the MLIR translator populate HasAttachPtr in
parallel with the other per-entry arrays; the MLIR/Flang side currently pushes
false with a TODO to set it for pointee-storage entries (e.g. s%p(0:10)) and
eventually drop PreserveMemberOfFlags in favor of it.

Co-Authored-By: Claude Opus 4.8 <noreply at anthropic.com>
DeltaFile
+98-80clang/test/OpenMP/target_map_nested_ptr_member_mapper_codegen.cpp
+68-60clang/test/OpenMP/declare_mapper_codegen.cpp
+66-5clang/lib/CodeGen/CGOpenMPRuntime.cpp
+52-15llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+18-24offload/test/mapping/mapper_enter_data_always_present_ptee.c
+20-0mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+322-1846 files not shown
+345-21412 files

LLVM/project d61e7edclang/test/OpenMP target_map_array_section_of_structs_with_nested_mapper_codegen.cpp target_map_array_of_structs_with_nested_mapper_codegen.cpp, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[OpenMP] Propagate ALWAYS/DELETE/CLOSE map-type modifiers to mapper entries

Per OpenMP 6.0:281:34, when a map/motion clause uses a mapper modifier, any
map-type-modifying modifier on that clause applies to each map the declared
mapper specifies. Propagate the ALWAYS, DELETE, and CLOSE bits from the outer
clause's map type into every entry emitted by emitUserDefinedMapper, except
ATTACH entries (ATTACH|ALWAYS is reserved for attach(always), and the other
bits have no meaning for an ATTACH entry).

PRESENT is intentionally NOT propagated here: it requires distinguishing
pointee entries from the struct's own storage and is handled in a follow-up.

Co-Authored-By: Claude Opus 4.8 <noreply at anthropic.com>
DeltaFile
+87-77clang/test/OpenMP/target_map_array_section_of_structs_with_nested_mapper_codegen.cpp
+87-77clang/test/OpenMP/target_map_array_of_structs_with_nested_mapper_codegen.cpp
+76-68clang/test/OpenMP/target_map_nested_ptr_member_mapper_codegen.cpp
+37-2llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+27-9clang/test/OpenMP/declare_mapper_codegen.cpp
+4-12offload/test/mapping/mapper_map_ptee_only_always_array.c
+318-2453 files not shown
+334-2529 files

LLVM/project f854d3ellvm/test/CodeGen/AMDGPU maximumnum.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

Merge remote-tracking branch 'upstream/main' into add-mapper-tests-that-need-attach-type-codegen
DeltaFile
+23,904-12llvm/test/CodeGen/RISCV/clmul.ll
+9,414-9,234llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+7,009-6,937llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,819-5,824llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+5,588-5,406llvm/test/CodeGen/AMDGPU/maximumnum.ll
+64,802-27,41312,038 files not shown
+498,341-321,66612,044 files

LLVM/project 89b8429clang/bindings/python/clang cindex.py, clang/bindings/python/tests/cindex test_code_completion.py

[libclang/python] Remove global SPELLING_CACHE alias (#210677)

This completes the second step of
https://github.com/llvm/llvm-project/issues/156680
This change is a follow-up to
https://github.com/llvm/llvm-project/pull/177586, following the release
branching, to ensure a one release-cycle deprecation period.

---------

Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
DeltaFile
+0-29clang/bindings/python/clang/cindex.py
+0-25clang/bindings/python/tests/cindex/test_code_completion.py
+4-0clang/docs/ReleaseNotes.md
+4-543 files

LLVM/project c517346llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer VecUtils.cpp

Pass Claimed by ref to getNextUserBundles

A user should not be claimed by multiple successful
bundles. Added a test for this.
DeltaFile
+60-7llvm/test/Transforms/SandboxVectorizer/topdown_vec.ll
+3-3llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
+3-1llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
+2-1llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+68-124 files

LLVM/project 64bc006mlir/lib/CAPI/IR IR.cpp

braces

The 1:N conversion callback returned MlirLogicalResult, which the binding
could only map to success or nullopt (try-another), leaving the C++
failure() state (fail without trying another conversion) unreachable.

Return a MlirTypeConverterConversionStatus enum instead, with Success,
Failure, and Declined states mapped to success(), failure(), and
std::nullopt respectively. Add a test covering the hard-failure path.
DeltaFile
+2-1mlir/lib/CAPI/IR/IR.cpp
+2-11 files

LLVM/project 6e70cfbmlir/test/CAPI ir.c

[mlir-c] Strengthen testGetParentWithName coverage

Address review feedback: the previous IR chain
(arith.constant -> func.func -> builtin.module) had each queried name
appear exactly once, so an implementation returning the outermost match
instead of the nearest would still pass. Use nested modules so
builtin.module appears twice in the ancestor chain, assert the walk
returns the inner (nearest) module, and add a boundary case for a
top-level op whose parent is null.
DeltaFile
+33-8mlir/test/CAPI/ir.c
+33-81 files

LLVM/project 516a328llvm/lib/Target/NVPTX NVPTXFrameLowering.cpp NVPTXAsmPrinter.cpp, llvm/test/CodeGen/NVPTX peephole-cvta-local-short-ptr.mir short-ptr.ll

[NVPTX] Respect local pointer width for %SPL (#211656)
DeltaFile
+22-13llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp
+26-0llvm/test/CodeGen/NVPTX/peephole-cvta-local-short-ptr.mir
+17-0llvm/test/CodeGen/NVPTX/short-ptr.ll
+6-7llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+3-3llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
+5-0llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
+79-231 files not shown
+81-257 files

LLVM/project 936e081mlir/include/mlir-c IR.h, mlir/lib/CAPI/IR IR.cpp

[mlir-c] Add mlirOperationGetParentWithName
DeltaFile
+50-0mlir/test/CAPI/ir.c
+10-0mlir/lib/CAPI/IR/IR.cpp
+6-0mlir/include/mlir-c/IR.h
+66-03 files

LLVM/project 2e32c6cclang-tools-extra/clang-tidy/performance ExpensiveValueOrCheck.cpp ExpensiveValueOrCheck.h, clang-tools-extra/docs/clang-tidy/checks/performance expensive-value-or.md

[clang-tidy] Add performance-expensive-value-or check (#200166)

Finds calls to `value_or` (and alternative spellings `valueOr`,
`ValueOr`) on optional types where the return type is expensive to copy.
Objects not trivially copyable, or larger than a configurable size threshold
are treated as expensive.
Rationale: While `value` and `operator*` return references, `value_or` for
these types always returns by value.
DeltaFile
+246-0clang-tools-extra/test/clang-tidy/checkers/performance/expensive-value-or.cpp
+182-0clang-tools-extra/clang-tidy/performance/ExpensiveValueOrCheck.cpp
+71-0clang-tools-extra/docs/clang-tidy/checks/performance/expensive-value-or.md
+42-0clang-tools-extra/clang-tidy/performance/ExpensiveValueOrCheck.h
+41-0clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/std/optional
+24-0clang-tools-extra/test/clang-tidy/checkers/performance/expensive-value-or-size-threshold.cpp
+606-07 files not shown
+627-013 files

LLVM/project 68d7f7bmlir/include/mlir/Dialect/EmitC/Transforms Passes.td Transforms.h, mlir/lib/Dialect/EmitC/Transforms WrapFuncInClass.cpp

[mlir][EmitC] Add `class-name-format` option to `wrap-emitc-func-in-class` pass (#211147)

Added the `class-name-format` option that takes a format string used to
generate the wrapper class name.

This provides greater control over the generated `ClassOp` name. When
multiple identically structured IR files need to be programmatically
lowered with this pass and linked, there will be naming conflicts which
this patch provides a method of resolution for.
DeltaFile
+14-6mlir/lib/Dialect/EmitC/Transforms/WrapFuncInClass.cpp
+17-0mlir/test/Dialect/EmitC/wrap-func-in-class.mlir
+5-1mlir/include/mlir/Dialect/EmitC/Transforms/Passes.td
+1-1mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h
+37-84 files

LLVM/project 525aa54llvm/test/CodeGen/AMDGPU maximumnum.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

Merge branch 'main' into users/ziqingluo/PR-171209196
DeltaFile
+23,904-12llvm/test/CodeGen/RISCV/clmul.ll
+9,414-9,234llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+7,009-6,937llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,819-5,824llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+5,588-5,406llvm/test/CodeGen/AMDGPU/maximumnum.ll
+64,802-27,41314,592 files not shown
+565,466-358,54514,598 files

LLVM/project fee5637clang/lib/Analysis ThreadSafety.cpp

address comments
DeltaFile
+7-5clang/lib/Analysis/ThreadSafety.cpp
+7-51 files