LLVM/project 8b96ddb — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 trimmed-node-matching-gather-emitted-first.ll

[SLP]Do not reuse transformed nodes in gathers emitted before their user

Gathers of the users with all scalars used outside the block are emitted
before the user, while the transformed nodes are emitted with the user.
Reusing such a transformed node postponed the gather and moved only the
last instruction of the transformed node buildvector, breaking dominance.

Fixes #226674

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/226687
DeltaFile
+69-0llvm/test/Transforms/SLPVectorizer/X86/trimmed-node-matching-gather-emitted-first.ll
+4-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+73-22 files

LLVM/project f432cba — mlir/include/mlir/Transforms GreedyPatternRewriteDriver.h, mlir/lib/Transforms/Utils GreedyPatternRewriteDriver.cpp

[mlir] Avoid rewriting unreachable blocks in the greedy driver

A rewrite can disconnect a block after the iteration's initial CFG sweep.
Track reachability through rewriter notifications and skip worklist
operations in unreachable blocks until the next iteration removes them.

Cache reachability per region and compare final successors after each
rewrite. Preserve the cache for successor-equivalent changes, added edges,
and block merges that keep surviving blocks reachable. Recompute for other
CFG changes, including entry changes and cross-region block moves.

Keep cache updates separate from reachability queries, returning failure
when a full traversal is required. Collect each successor set once for
validation and retain compact vector snapshots in the cache. Check
containing blocks when querying operations in nested regions, caching the
ancestor result until listener notifications invalidate it.

Cover inserted and redirected blocks, blocks connected before rewrite
completion, nested regions, block moves and merges, and explicit op lists.

    [6 lines not shown]
DeltaFile
+259-1mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
+206-0mlir/test/Transforms/greedy-cfg-reachability.mlir
+94-4mlir/test/lib/Dialect/Test/TestPatterns.cpp
+51-5mlir/test/Transforms/test-strict-pattern-driver.mlir
+41-0mlir/test/Transforms/canonicalize-dce.mlir
+9-3mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
+660-136 files

LLVM/project 1916c2c — clang/lib/AST/ByteCode EvaluationResult.cpp, libcxx/test/std/algorithms/alg.modifying.operations/alg.swap pstl.swap_ranges.pass.cpp

Rebase, address comments, improvements

Created using spr 1.3.7
DeltaFile
+733-228llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
+389-0llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
+1-381clang/lib/AST/ByteCode/EvaluationResult.cpp
+252-26orc-rt/test/unit/support/bind-test.cpp
+187-0libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
+164-0llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
+1,726-635334 files not shown
+6,348-2,420340 files

LLVM/project 10872fe — llvm/test/Transforms/SLPVectorizer/AArch64 reduced-value-next-to-fused-fmul.ll, llvm/test/Transforms/SLPVectorizer/AMDGPU fmul-sunk-into-fadd-block.ll

[SLP][NFC]Add extra FMA candidates tests, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/226684
DeltaFile
+52-0llvm/test/Transforms/SLPVectorizer/AMDGPU/fmul-sunk-into-fadd-block.ll
+42-0llvm/test/Transforms/SLPVectorizer/AArch64/reduced-value-next-to-fused-fmul.ll
+94-02 files

LLVM/project 9f8d812 — clang/lib/CodeGen BackendConsumer.h CodeGenAction.cpp, clang/lib/Interpreter Interpreter.cpp DeviceOffload.h

Revert "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation" (#226679)

Reverts llvm/llvm-project#218337 buildbot failures
DeltaFile
+8-209clang/lib/Interpreter/DeviceOffload.cpp
+9-55clang/lib/Interpreter/DeviceOffload.h
+0-50clang/unittests/Basic/TargetIDTest.cpp
+0-9clang/lib/CodeGen/CodeGenAction.cpp
+0-8clang/lib/CodeGen/BackendConsumer.h
+6-1clang/lib/Interpreter/Interpreter.cpp
+23-3323 files not shown
+25-3409 files

LLVM/project c495a9b — mlir/docs ReleaseNotes.md, mlir/docs/DefiningDialects Operations.md _index.md

[mlir] Enable strict properties in assembly formats by default (#225742)

Make strict property assembly formats the default and remove redundant
per-dialect settings. Keep legacy test fixtures explicitly opted out and
update the documentation.

Downstream can opt out for now using `let
useStrictPropertiesInAssemblyFormat = 0;` ; This will be removed in a
future release.

Part of #155475 

Assisted-by: Codex
DeltaFile
+11-13mlir/docs/DefiningDialects/_index.md
+8-12mlir/docs/DefiningDialects/Operations.md
+12-0mlir/docs/ReleaseNotes.md
+6-5mlir/include/mlir/IR/DialectBase.td
+2-1mlir/test/mlir-tblgen/op-format.td
+2-1mlir/test/mlir-tblgen/op-format-invalid.td
+41-3260 files not shown
+54-8066 files

LLVM/project 8228ace — mlir/include/mlir/Transforms GreedyPatternRewriteDriver.h, mlir/lib/Transforms/Utils GreedyPatternRewriteDriver.cpp

[mlir] Avoid rewriting unreachable blocks in the greedy driver

A rewrite can disconnect a block after the iteration's initial CFG sweep.
Track reachability through rewriter notifications and skip worklist
operations in unreachable blocks until the next iteration removes them.

Cache reachability per region and compare final successors after each
rewrite. Preserve the cache for successor-equivalent changes, added edges,
and block merges that keep surviving blocks reachable. Recompute for other
CFG changes, including entry changes and cross-region block moves.

Keep cache updates separate from reachability queries, returning failure
when a full traversal is required. Collect each successor set once for
validation and retain compact vector snapshots in the cache. Check
containing blocks when querying operations in nested regions.

Cover inserted and redirected blocks, blocks connected before rewrite
completion, nested regions, block moves and merges, and explicit op lists.
Use observer diagnostics to check whether affected operations are processed

    [5 lines not shown]
DeltaFile
+187-1mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
+171-0mlir/test/Transforms/greedy-cfg-reachability.mlir
+83-4mlir/test/lib/Dialect/Test/TestPatterns.cpp
+51-5mlir/test/Transforms/test-strict-pattern-driver.mlir
+41-0mlir/test/Transforms/canonicalize-dce.mlir
+9-3mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
+542-136 files

LLVM/project e9e2743 — llvm/lib/Target/AVR AVRRegisterInfo.cpp TODO.md

[AVR][NFC] Improve some comment messages (#226423)
DeltaFile
+10-9llvm/lib/Target/AVR/AVRInstrInfo.td
+7-6llvm/lib/Target/AVR/AVRISelLowering.cpp
+5-5llvm/lib/Target/AVR/AVRInstrInfo.cpp
+4-4llvm/lib/Target/AVR/AVRDevices.td
+0-7llvm/lib/Target/AVR/TODO.md
+2-2llvm/lib/Target/AVR/AVRRegisterInfo.cpp
+28-334 files not shown
+33-3910 files

LLVM/project fbbf217 — clang/lib/CodeGen BackendConsumer.h CodeGenAction.cpp, clang/lib/Interpreter Interpreter.cpp DeviceOffload.h

Revert "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device comp…"

This reverts commit 0b4f72d00bdd2ef1707c5098d12936bfa159b414.
DeltaFile
+8-209clang/lib/Interpreter/DeviceOffload.cpp
+9-55clang/lib/Interpreter/DeviceOffload.h
+0-50clang/unittests/Basic/TargetIDTest.cpp
+0-9clang/lib/CodeGen/CodeGenAction.cpp
+0-8clang/lib/CodeGen/BackendConsumer.h
+6-1clang/lib/Interpreter/Interpreter.cpp
+23-3323 files not shown
+25-3409 files

LLVM/project fccc863 — orc-rt/include/orc-rt/bedrock/sps SimpleRemoteCAOverSocket.h, orc-rt/lib/bedrock/sys/posix/sps SimpleRemoteCAOverSocket.cpp

[orc-rt] SimpleRemoteCAOverSocket: require a stream socket. (#226676)

SimpleRemote framing reads each message in as many parts as the socket
delivers it, which a socket that preserves message boundaries (datagram,
seqpacket) would truncate. Check SO_TYPE up front and reject anything
but SOCK_STREAM; the socket is owned by then, so it is closed on
failure.

Assisted-by: Claude
DeltaFile
+16-0orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
+10-0orc-rt/lib/bedrock/sys/posix/sps/SimpleRemoteCAOverSocket.cpp
+2-1orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCAOverSocket.h
+28-13 files

LLVM/project e8e4a54 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-shuffle-reverse.ll

[AArch64] Use SVE rev for full reverse shuffles with SVE128 (#224589)

When the vscale_range is always 1, we can make use of the SVE rev
instruction to perform a full 128bit vector reverse.

Sidesteps #223597 for SVE128
DeltaFile
+18-12llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
+11-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+29-132 files

LLVM/project babcc2b — clang/lib/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage UnsafeBufferUsageAnalysis.cpp, clang/unittests/ScalableStaticAnalysis/WholeProgramAnalysis UnsafeBufferReachableAnalysisTest.cpp

[SSAF] Close unsafe-buffer reachability over override families

An unsafe pointer reaching one override's parameter is equally unsafe in every
sibling and base override of that method, because the call site picks the
target dynamically. Without closing over the families, reachability depended
on which override the extractor happened to see the flow through, so a fix
suggested for the base could be contradicted by a derived override.

- Mirroring is level-preserving: families relate slot entities, so a reachable
  EPL propagates only to the same pointer level on its family members.
- Mirroring happens inside the pointer-flow search, so flows out of a mirrored
  EPL are followed too.
- Type-constrained slots are never mirrored onto, so C3 still holds.

§4 of rdar://179151603

Assisted-By: claude
DeltaFile
+240-0clang/unittests/ScalableStaticAnalysis/WholeProgramAnalysis/UnsafeBufferReachableAnalysisTest.cpp
+55-14clang/lib/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage/UnsafeBufferUsageAnalysis.cpp
+295-142 files

LLVM/project e7019f8 — mlir/lib/Dialect/IRDL/IR IRDL.cpp, mlir/lib/Target/IRDLToCpp IRDLToCpp.cpp

[MLIR][IRDL] Instantiate "." in IRDL-defined names as nested namespaces (#207035)

In PR #187911, it was revealed that the constraints on IRDL op names
placed by irdl-to-cpp were too restrictive.
This PR will address that by allowing "." in operation names to denote
nested namespaces, but not "$".

To discuss:
- ops like `wmma.f16.16x16x64.bf8_bf` cannot be registered as C++
identifiers cannot begin with a number. In discussions, we have opted to
prefix the generated namespaces with _.

Codex was used to generate the lit tests.

Close #187911.

Assisted-by: OpenAI Codex (GPT-5 and 6)
DeltaFile
+110-12mlir/test/lib/Dialect/TestIRDLToCpp/test_irdl_to_cpp.irdl.mlir
+89-23mlir/lib/Target/IRDLToCpp/IRDLToCpp.cpp
+17-12mlir/lib/Dialect/IRDL/IR/IRDL.cpp
+216-473 files

LLVM/project f696114 — clang/include/clang/ScalableStaticAnalysis BuiltinAnchorSources.def, clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamily.h

[SSAF] Serialize virtual method summaries and families

Per-TU summaries and whole-program results cross process boundaries, and the
JSON layer refuses to write a summary kind it has no format for. Register both
sides so --ssaf-extract-summaries=VirtualMethod becomes usable and the family
result survives a round trip.

Deserialization tolerates a missing override list, since a root virtual method
legitimately has none.

§3 of rdar://179151603
DeltaFile
+379-0clang/unittests/ScalableStaticAnalysis/Serialization/JSONFormatTest/VirtualMethodFamilyFormatTest.cpp
+186-0clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyFormat.cpp
+22-0clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysis.cpp
+5-0clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
+1-0clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
+1-0clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
+594-01 files not shown
+595-07 files

LLVM/project 520f960 — clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamily.h, clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamilyAnalysis.cpp

[SSAF] Drop the unused OwnerMethodId from method families

The only consumer, the unsafe-buffer reachability closure, needs just the family
a slot belongs to.
- Recording the owning method cost a map per analysis and a field per slot for
  nothing.
- With only the family left, the per-slot `Data` collapses into a plain
  slot-to-family map.

Assisted-By: claude
DeltaFile
+42-86clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysisTest.cpp
+7-46clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysis.cpp
+5-25clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
+54-1573 files

LLVM/project 8905b8c — clang/include/clang/ScalableStaticAnalysis BuiltinAnchorSources.def, clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamily.h

[SSAF] Group virtual method slots into override families

A virtual call site can dispatch to any override, so the parameter and return
slots that occupy the same vtable slot across an override chain are
indistinguishable to a caller. Whole-program consumers therefore have to treat
them as one unit or they will reason about a slot that a call never actually
reaches.

Compute those units up front, keyed per slot, so consumers only need a map
lookup rather than their own traversal of the override relation. Overloads
occupy distinct vtable slots and stay in distinct families.

The family representative is the smallest EntityId in the class, which keeps
the result stable across runs.

§2 of rdar://179151603
DeltaFile
+336-0clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysisTest.cpp
+201-0clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysis.cpp
+46-0clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
+11-0clang/include/clang/ScalableStaticAnalysis/Core/Model/EntityId.h
+1-0clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
+1-0clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
+596-01 files not shown
+597-07 files

LLVM/project 86c6d28 — clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamily.h, clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamilyAnalysis.cpp

[SSAF] Drop the dead MethodFamilyUnionFind::seed overloads

Nothing calls either overload; they are scaffolding left over from the
prototype this analysis was extracted from.

- `Roots` is populated entirely by the lazy self-rooting in `find()`,
  reached via `unionSets()`.
- `seed(E, Owner)` ignored `Owner` altogether. The parameter only existed
  because `seed(Owner, S)` was copy-pasted from
  `Owners::recordOwner(Owner, S)`, which does need it.
- Where the prototype did call `seed`, it ran immediately above
  `unionSets()` over the same entities, so it was a no-op there too.

Also document that a virtual method with no override relation contributes
no entries, so the omission reads as deliberate rather than as a gap.

Assisted-By: claude
DeltaFile
+0-11clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysis.cpp
+1-0clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
+1-112 files

LLVM/project 2b29a81 — clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamilyExtractorTest.cpp

tmp - Test that three-level chain records only direct override edges

`overridden_methods()` is not transitive. This means that it describes
the directly overridden methods - which is usually a single method
(unless it overrides the same function from multiple parents).

This test case demonstrates that A::f overrides B::f which overrides C::f.
And that it's not that A::f overrides C::f without overriding B::f first.

Assisted-By: claude
DeltaFile
+36-0clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyExtractorTest.cpp
+36-01 files

LLVM/project f0842d8 — clang/include/clang/ScalableStaticAnalysis BuiltinAnchorSources.def, clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily VirtualMethodFamily.h

[SSAF] Extract the virtual method override relation per TU

A virtual call may dispatch to any override of its callee, so a whole-program
analysis cannot reason about a method's parameters and return value in
isolation. It needs to know which method overrides which, and which slots
that relates. Collect this per TU, so a later pass can join the related
slots into families.

JSON serialization lands separately, so the summary is not writable via
--ssaf-extract-summaries yet.

§1 of rdar://179151603
DeltaFile
+228-0clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyExtractorTest.cpp
+155-0clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyTestSupport.h
+145-0clang/unittests/ScalableStaticAnalysis/ParsedAST.h
+92-0clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodEntityExtractor.cpp
+51-0clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
+1-0clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
+672-02 files not shown
+674-08 files

LLVM/project 0407861 — llvm/lib/Target/Mips MipsSERegisterInfo.cpp MipsRegisterInfo.cpp

Mips: Route ABI queries through the subtarget (#226667)
DeltaFile
+4-8llvm/lib/Target/Mips/MipsMachineFunction.cpp
+4-4llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+2-4llvm/lib/Target/Mips/MipsCallLowering.cpp
+1-4llvm/lib/Target/Mips/MipsFastISel.cpp
+1-3llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
+1-3llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+13-264 files not shown
+17-3310 files

LLVM/project a4e311d — llvm/lib/ExecutionEngine/Orc MachOPlatform.cpp ELFNixPlatform.cpp

[ORC] Call createPThreadKey through a Proxy in MachO/ELFNixPlatform (#226656)

Replace the callSPSWrapper calls in MachOPlatform::createPThreadKey and
ELFNixPlatform::createPThreadKey with a Proxy built over the address
recorded during bootstrap, using a local CI descriptor for each
platform's create_pthread_key wrapper. The address stays in the
platforms' RuntimeFunction table, which is filled uniformly by the
bootstrap recording pass.
DeltaFile
+17-5llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
+17-5llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
+34-102 files

LLVM/project d94f3a5 — orc-rt/test/unit CMakeLists.txt, orc-rt/test/unit/bedrock SocketTestUtils.h SocketConnectorTest.cpp

[orc-rt] Make socket unit tests portable; build them on POSIX. (#226662)

SimpleRemoteCAOverSocketTest.cpp tests a POSIX-only implementation, so
move it to the POSIX source list. Its tests are portable, so move the
fixture's POSIX code into SocketTestUtils (makeStreamSocketPair,
sendAll, recvAll, makeNativeNonStreamSocket) rather than moving the file
under sys/posix; a Windows transport will need only Windows definitions
of those helpers.

makeStreamSocketPair documents the properties the tests rely on beyond a
connected stream pair: neither direction buffers StallingPayloadSize
bytes, and closing an end delivers what it already sent even if it has
unread data. AF_UNIX provides both; a loopback TCP pair may not.

SocketConnectorTest.cpp tests fd adoption with pipe and fcntl, so it is
a test of the POSIX implementation: move it to sys/posix/.

Assisted-by: Claude
DeltaFile
+0-89orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
+89-0orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
+14-58orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
+56-0orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
+30-0orc-rt/test/unit/bedrock/SocketTestUtils.h
+10-6orc-rt/test/unit/CMakeLists.txt
+199-1536 files

LLVM/project 97e9558 — llvm/lib/CodeGen DetectDeadLanes.cpp, llvm/test/CodeGen/AMDGPU detect-dead-lanes-reg-sequence-narrow-slot.mir true16-uniform-f16-phi-copysign.ll

Revert "[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths" (#226665)

Reverts llvm/llvm-project#226556

This is handling malformed IR and adding size based instead of register
class based reasoning
DeltaFile
+1,052-1,538llvm/test/CodeGen/AMDGPU/frem.ll
+0-72llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
+0-24llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
+2-13llvm/lib/CodeGen/DetectDeadLanes.cpp
+1,054-1,6474 files

LLVM/project 3cde605 — llvm/lib/Target/Mips MipsSERegisterInfo.cpp MipsRegisterInfo.cpp

Mips: Route ABI queries through the subtarget

MipsSubtarget::getABI() already forwards to the target machine, so every
direct MipsTargetMachine::getABI() reader can use the subtarget instead.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+4-8llvm/lib/Target/Mips/MipsMachineFunction.cpp
+4-4llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+2-4llvm/lib/Target/Mips/MipsCallLowering.cpp
+1-4llvm/lib/Target/Mips/MipsFastISel.cpp
+1-3llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
+1-3llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+13-264 files not shown
+17-3310 files

LLVM/project 96b5cc3 — llvm/include/llvm/Analysis BranchProbabilityInfo.h, llvm/lib/Analysis BranchProbabilityInfo.cpp

[BPI] Add getEdgeProbabilitiesFromWeights (NFC). (#226560)

Move computing edge probabilities from branch weights to a static
helper. This allows re-using the core logic when computing execution
frequencies in VPlan, fixing a number of subtle differences.

While touching the code, also modernize the code slightly.

Note that the helper does not handle the case where all successors are
unreachable. This would need additional info and is not needed for the
VPlan case.

PR: https://github.com/llvm/llvm-project/pull/226560
DeltaFile
+33-28llvm/lib/Analysis/BranchProbabilityInfo.cpp
+6-0llvm/include/llvm/Analysis/BranchProbabilityInfo.h
+39-282 files

LLVM/project 406b232 — llvm/lib/CodeGen DetectDeadLanes.cpp, llvm/test/CodeGen/AMDGPU detect-dead-lanes-reg-sequence-narrow-slot.mir true16-uniform-f16-phi-copysign.ll

Revert "[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched w…"

This reverts commit 201e76d4559e9d8acdfec1c202df8f2269acbd8b.
DeltaFile
+1,052-1,538llvm/test/CodeGen/AMDGPU/frem.ll
+0-72llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
+0-24llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
+2-13llvm/lib/CodeGen/DetectDeadLanes.cpp
+1,054-1,6474 files

LLVM/project c0b6ee1 — llvm/test/CodeGen/AArch64 sve-fixed-length-shuffle-reverse.ll

[AArch64] Add tests for sve fixed length reverse shuffles. NFC (#226661)
DeltaFile
+158-0llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
+158-01 files

LLVM/project 5f609f9 — llvm/docs CommandLine.md, llvm/include/llvm/Support CommandLine.h

[Support] Remove cl::bits (#226628)

cl::list covers the same use, and cl::bits would block migration to
TableGen based representation.

LLM-aided
DeltaFile
+0-145llvm/include/llvm/Support/CommandLine.h
+0-66llvm/docs/CommandLine.md
+5-10llvm/unittests/Support/CommandLineTest.cpp
+5-2213 files

LLVM/project 46f2d1c — clang/lib/CIR/CodeGen CIRGenAsm.cpp CIRGenExpr.cpp, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Propagate the record address space to get_member
DeltaFile
+71-0clang/test/CIR/CodeGen/get-member-addrspace.cpp
+24-0clang/test/CIR/CodeGenHIP/inline-asm-multi-output-addrspace.hip
+14-0clang/test/CIR/IR/invalid-struct.cir
+6-3clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+3-1clang/lib/CIR/CodeGen/CIRGenAsm.cpp
+3-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+121-43 files not shown
+125-79 files

LLVM/project 4ad5c70 — clang/lib/CIR/CodeGen CIRGenModule.h CIRGenDecl.cpp, clang/test/CIR/CodeGen amdgpu-array-addrspace.cpp

[CIR] Cast global addresses to their declared address space
DeltaFile
+95-0clang/test/CIR/CodeGenCUDA/global-addrspace-cast.cu
+26-11clang/test/CIR/CodeGen/amdgpu-array-addrspace.cpp
+18-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+3-9clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+3-2clang/test/CIR/CodeGenCUDA/address-spaces.cu
+4-0clang/lib/CIR/CodeGen/CIRGenModule.h
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+151-267 files