[Object] Extract format-agnostic BBAddrMap decoder (#188435)
[Object] Extract format-agnostic BBAddrMap decoder
This is part of patches to port BBAddrMap to COFF.
Move format-agnostic BBAddrMap decode logic out of ELF.cpp into
BBAddrMap.cpp, and expose a shared decodeBBAddrMapPayload helper in
BBAddrMap.h.
Keep ELF-specific steps (section decompression and relocation
translation) in ELF.cpp, and delegate payload decoding to the
shared helper.
Error messages in the decoder are updated to use the generic
"BB address map" instead of the ELF-specific "SHT_LLVM_BB_ADDR_MAP"
since the decoder is now shared across object formats.
This refactor prepares follow-up work to let COFF and ELF share
the same BBAddrMap decoding logic.
[lldb] Fix ScriptedFrame thread member init assignment (#191297)
This patch fixes a typo in the `ScriptedFrame` base class initializer
where we used a thread id with `GetThreadByIndexID` instead of the
thread index.
This could lead to issues where derived classes wouldn't be initialized
properly, which could cause crashes down the line.
The patch addresses the issue by calling `GetThreadByID` with the thread
id.
rdar://174432881
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
[MLIR][XeGPU] Add uArch defintion for CRI - Crescent Island (#191024)
XeGPU lowering relies on uArch definition and lowering fails if a chip
does not have uArch definition entry.
Add preliminary uArch definition for CRI.
This is a place holder for now and current defintion is identical to
BMG.
[WebAssembly][GlobalISel] Add legalization & selection of most integer ops (#190234)
Allows many ops/instructions working solely on integers to be fully
selected (legalize, regbankselect, isel).
Split from #157161
Revert "[X86][APX] Add copy instruction to LiveInterval of SrcReg (#191102) (#191330)
This reverts commit 16f02c0940d6ee783c38ca27b44fc158d77e7567.
This caused a bot failure when building with expensive checks.
https://ci.swift.org/job/llvm.org/job/clang-stage1-RA-expensive/job/main/409/testReport/junit/Clang/CodeGen_X86/pr190962_ll/
The test case included in the original commit fails with:
```
| *** Bad machine code: Two-address instruction operands must be identical ***
| - function: foo
| - basic block: %bb.0 (0x7fc688853c40) [0B;192B)
| - instruction: 128B %10:gr64 = IMUL64rm %33:gr64(tied-def 0), %fixed-stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s64) from %fixed-stack.1, align 16)
| - operand 1: %33:gr64(tied-def 0)
| fatal error: error in backend: Found 1 machine code errors.
```
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[RISCV][P-ext] Add mul*.h00 and mul*.w00 patterns. (#191313)
The instructions take the low halfword/word from each input, extends
them and multiplies to produce a word/dword result.
We can use these instead of plain MUL if it would allow us to avoid
a sext/zext for at least one of the operands.
Tests were written by Claude Sonnet 4.5.
[llvm-profgen] Read build ID from binary for perfscript address filtering (#190862)
For shared libraries (.so), read the binary's build ID during load()
using object::getBuildID() and store it as FilterBuildID. Main
executables keep FilterBuildID empty, matching the convention that
their perfscript addresses have no buildid prefix.
This enables automatic build ID-based filtering of perfscript
addresses in [buildid:]0xaddr format without requiring a CLI option.
[BOLT] Use identify_magic for shared library detection (#190902)
Replace the fragile filename-based check (ends_with(".so")) with
identify_magic()/file_magic::elf_shared_object to reliably detect
shared libraries when filtering pre-aggregated profile data by
build ID.
Test Plan: pre-aggregated-perf-shlib.test
[orc-rt] Add Session::attach convenience overload. (#191199)
This overload enables one-line attach in the common case where the
ControllerAccess implementation does not require any configuration after
construction.
[CIR] Implement variable size array cleanup (#191247)
This implements partial array destruction for variable sized arrays. The
cir.array.dtor operation already had support for variable length, so
this change only needs to add the variable handling in
`emitArrayDestroy` and `emitArrayLength`.
Assisted-by: Cursor / claude-4.6-opus-high
[clang][modules] Add warning for symlinks to modular headers (#188059)
Symlinks that are not covered by a module that point to a header owned
by a module create situations where if a header is owned by a module
depends on which headers were included prior.
This adds a diagnostic for such cases when they can be detected, and
informs the user to use a textual forwarding header instead.
This bypasses Clang's FileManager and VFS as they don't know about
symlinks. The diagnostic is worded as "may" because of this.
[llvm-lit] Ignore malformed `.lit_test_times` entries
When running `llvm-lit`, I sometimes hit a traceback, because a
`.lit_test_times.txt` file has got corrupted (not sure how).
However, it's non-obvious what the issue is (you just get a traceback),
so I've fixed this as follows:
`read_test_times()` currently assumes every line in .lit_test_times.txt
contains a floating-point time followed by a test path. If the file
contains a blank line, a line without a path, or a non-numeric time,
lit raises during discovery instead of skipping the bad entry.
Fix this by parsing each line defensively. Split once, ignore lines
that do not produce both fields, and ignore entries whose time cannot
be parsed as a float. This keeps the existing behavior for valid lines
while making malformed timing files non-fatal.
Add a new `malformed-test-times.py` regression test and a checked-in
lit_test_times fixture containing both valid and malformed entries. The
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[AArch64][clang] Fix `__arm_atomic_store_with_stshh` ordering and lowering
`__builtin_arm_atomic_store_with_stshh` must satisfy two constraints:
- preserve release/seq_cst ordering in LLVM IR
- keep `stshh` immediately adjacent to the final store in codegen
The original target-intrinsic lowering preserved the final `stshh` + store
sequence, but it did not model ordering strongly enough in LLVM IR, so the
optimizer could sink earlier stores across the builtin.
Fix this by inserting a `release` or `seq_cst` fence before the intrinsic
call. This preserves ordering in optimized IR while still letting the
backend emit the required final instruction sequence. This means we now
get a `dmb ish` instruction before the `stshh` instruction.
Also relax Sema for the builtin to accept storing 8/16/32/64-bit
floating-point and pointer values in addition to integers, and update
the diagnostic text accordingly.
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Reapply "[clang][ModulesDriver] Add support for Clang modules to -fmodules-driver" (#191258)
This relands #187606 (reverted with #191122).
In the initial PR, the Clang module precompile jobs were created as
`CC1Command` objects instead of regular `Command` objects, which
introduced a memory leak.
(See discussion in https://reviews.llvm.org/D74447)
This has been fixed in this reland.
[RISCV][P-ext] Recognize (select (X >u ((1 << C) - 1), sext(X >s -1), trunc(X)) as usati (#190810)
Where the result is a type with C bits. The unsigned compare on the
select treats negative values as large positive values so any value
that isn't in the range [0, (1 << C) - 1] will use the True operand
of the select. The sext(X >s -1) creates all ones for positive values
of X and 0 for negative values of X.
This pattern appears in the picojpeg workload of embench-iot with
an i8 result type.
Assisted-by: Claude Sonnet 4.5
[clang] implement CWG2064: ignore value dependence for decltype
The 'decltype' for a value-dependent (but non-type-dependent) should be known,
so this patch makes them non-opaque instead.
Readds a few test cases from da98651
Fixes #8740
Fixes #61818
Fixes #190388
[Analysis][NFC] Remove BPI::getEdgeProbability(iterator) (#191286)
Now that successor iterators are Use iterators, it is no longer cheap to
get the successor index. Replace uses with the variant that takes the
successor index, which in all cases is easily available.
This is primarily cleanup after the somewhat recent successor changes.
There's also a minor (barely measurable) performance improvement here.
