LLVM/project fb4b133llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/InstCombine/RISCV riscv-vsetvlimax-ispow2.ll

[ValueTracking] Treat RISC-V vsetvlimax as a power of two (#218831)

VLMAX = VLEN * LMUL / SEW is always a non-zero power of two for any valid
vtype, so llvm.riscv.vsetvlimax is a power of two regardless of SEW/LMUL or
whether a vscale_range is present. Report this in isKnownToBeAPowerOfTwo
so that consumers such as ctpop and the x & (x - 1) idiom can fold.

Assisted-by: TRAE CLI (Opus 4.8)
DeltaFile
+63-0llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvlimax-ispow2.ll
+4-0llvm/lib/Analysis/ValueTracking.cpp
+67-02 files

LLVM/project f79da0allvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Transforms/Scalar ExpandMemCmp.cpp

[ExpandMemCmp] Apply NumLoadsPerBlock to ordering compares (#215186)

Make NumLoadsPerBlock control both equality and ordering memcmp
expansions. For ordering comparisons, pack consecutive legal loads
in memory order into a value no wider than the target preferred
load width, then compare the packed values. This preserves
lexicographic semantics while reducing conditional branches.

BPF uses groups of eight byte-load pairs, so an align-1 32-byte
comparison forms four i64 compare blocks instead of 32 byte compare
blocks.

Other targets retain their existing default ordering behavior unless
grouping is explicitly requested.

Assisted-by: TRAE CLI (GPT-5)
DeltaFile
+898-0llvm/test/Transforms/ExpandMemCmp/BPF/memcmp.ll
+190-107llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
+168-75llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
+56-75llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
+14-14llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
+5-3llvm/include/llvm/Analysis/TargetTransformInfo.h
+1,331-2748 files not shown
+1,342-28014 files

LLVM/project 2c972ab.github/workflows/containers/github-action-ci-tooling Dockerfile

[Github] Bump formatting/tools container to 23.1.0 (#218815)

Now that 23.1.0 has been released, we should update the container to
ensure we're using the latest released version of the tooling.
DeltaFile
+2-2.github/workflows/containers/github-action-ci-tooling/Dockerfile
+2-21 files

LLVM/project 16852a1.github/workflows pr-code-format.yml

[Github] Hash pin ci-format container (#218816)

This follows our own CI best practices and ensures zizmor/CodeQL will
not complain about this when people inevitably touch it in the future.
DeltaFile
+1-1.github/workflows/pr-code-format.yml
+1-11 files

LLVM/project cfe9defllvm/lib/IR Verifier.cpp, llvm/test/Verifier/RISCV vsetvli.ll

[RISCV][Verifier] Check operands and result type of RISC-V vsetvli/vsetvlimax (#218594)

The result of `llvm.riscv.vsetvli/vsetvlimax` models VLMAX (or a VL bounded
by it) and is only defined for XLen, so the result type must be i32 or i64.
Narrower types cannot represent the architectural VLMAX range of [1, 65536]
that value analyses rely on.

Also check that the VSEW and VLMUL immediate operands encode a valid
SEW/LMUL pair (VSEW <= 3, VLMUL != reserved), so that consumers can
assume a well-formed vtype.

Assisted-by: TRAE CLI (Opus 4.8)
DeltaFile
+25-0llvm/test/Verifier/RISCV/vsetvli.ll
+22-0llvm/lib/IR/Verifier.cpp
+47-02 files

LLVM/project 106601aclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen arm-neon-vld.c

[CIR][AArch64] Upstream load (vld1_*/vld1q_*) NEON builtins (#218319)

Related to https://github.com/llvm/llvm-project/issues/185382

CIR lowering for load intrinsics (`vld1_*`/`vld1q_*`)

(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#stride)

Port tests:
- `clang/test/CodeGen/AArch64/neon-intrinsics.c`
- `clang/test/CodeGen/AArch64/neon-ldst-one.c`
- `clang/test/CodeGen/AArch64/poly64.c`
- `clang/test/CodeGen/arm-neon-vld.c`

to `clang/test/CodeGen/AArch64/neon/load.c`
DeltaFile
+2,240-0clang/test/CodeGen/AArch64/neon/load.c
+365-576clang/test/CodeGen/arm-neon-vld.c
+1-743clang/test/CodeGen/AArch64/neon-ldst-one.c
+0-698clang/test/CodeGen/AArch64/neon-intrinsics.c
+66-14clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+0-20clang/test/CodeGen/AArch64/poly64.c
+2,672-2,0511 files not shown
+2,678-2,0577 files

LLVM/project 63e0da0clang/include/clang/Lex Preprocessor.h, clang/lib/Frontend InitPreprocessor.cpp

[C++][Modules] Don't insert `#include` before GMF when `-include` used (#212533)

Clang currently emits command-line implicit inputs such as `-imacros`,
`-include-pch`/`-include-pth`, and `-include` as part of the predefines
buffer. This causes them to be processed before the main source file.

For a C++20 module unit with a global module fragment:

```cpp
module;
export module M;
```

a force-included header containing declarations was effectively
processed as:

```cpp
#include "Header.h"
module;

    [23 lines not shown]
DeltaFile
+157-0clang/test/Modules/cxx20-force-include.cpp
+56-18clang/lib/Lex/DependencyDirectivesScanner.cpp
+51-0clang/unittests/Lex/DependencyDirectivesScannerTest.cpp
+49-0clang/lib/Lex/Preprocessor.cpp
+23-12clang/lib/Frontend/InitPreprocessor.cpp
+31-1clang/include/clang/Lex/Preprocessor.h
+367-314 files not shown
+412-4410 files

LLVM/project e1ff57eclang/test/CodeGenCXX module-initializer-elision.cpp

[NFC] Skip a test on target={{.*}}-apple-darwin for TLS using (#218824)

Close https://github.com/llvm/llvm-project/pull/218346
DeltaFile
+2-0clang/test/CodeGenCXX/module-initializer-elision.cpp
+2-01 files

LLVM/project f872635llvm/lib/Target/X86 X86InstrFragments.td X86InstrCompiler.td, llvm/test/CodeGen/X86 pr218583.ll

[X86] Limit the result of XOR8rr_NOREX unused (#218640)

In case it may be zero/sign-extended into an REX/REX2 register.

Fixes: #218583

Assisted-by: Claude Opus 4.8
DeltaFile
+77-0llvm/test/CodeGen/X86/pr218583.ll
+10-3llvm/lib/Target/X86/X86InstrCompiler.td
+5-0llvm/lib/Target/X86/X86InstrFragments.td
+92-33 files

LLVM/project 6e7406cllvm/test/MC/AsmParser altmacro-arg.s macro-arg.s

[MCParser,test] Improve macro argument charset test (#218828)

'@', '#', and '?' are assembly identifier characters, but they terminate
a macro argument name.
DeltaFile
+9-0llvm/test/MC/AsmParser/macro-arg.s
+2-0llvm/test/MC/AsmParser/altmacro-arg.s
+11-02 files

LLVM/project b9279f6llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

[AMDGPU] Correct DS FIFO buffer size semantics

There was some ambiguity in how buffersize 0 and 1 are handled. The
correct semantics are:
- `BufferSize == 0`: unlimited, no FIFO stall
- `BufferSize == 1`: unbuffered, only one instruction in flight
- `BufferSize > 1`: buffered FIFO
DeltaFile
+9-7llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+13-102 files

LLVM/project ec585f6llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Handle DS FIFO accounting edge cases

Saturate hardware-unit pressure decrements and treat buffer sizes zero
and one as disabling buffering to avoid underflow and inconsistent stall
costs.
DeltaFile
+4-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+6-72 files

LLVM/project 7ce9975llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

Address Review comments

Change-Id: I6972e887edd5db44ee9bcaed1f79e0c9933f611e
DeltaFile
+17-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+6-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+23-42 files

LLVM/project 6987eb9llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll coexec-hazardrec-preRA.mir

[AMDGPU] Use DS latency for FIFO scheduling

Use instruction latency for DS hardware-unit cycle accounting so the FIFO
model can identify a full buffer. Add focused MIR coverage for the resulting
stall cost and scheduling decision, and regenerate the integration checks.

Change-Id: I2f4df2e97d145af4935872dbd43108e1b55077ab
DeltaFile
+48-0llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+5-5llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
+4-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+61-94 files

LLVM/project 7e85238llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Claude Code review

Change-Id: Id4983ca59270c8bb2d261d38a6e7f2483c9d237e
DeltaFile
+18-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+19-42 files

LLVM/project 7fc26bbllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

[AMDGPU] Add stalls for DS FIFO buffer

Change-Id: I73e56da97a931349e0655e4e20b24aeb97920647
DeltaFile
+41-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+41-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+82-112 files

LLVM/project 1604393llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Typo

Change-Id: I8b8da8a07be84506483f474d0a5e10ad79178c15
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-11 files

LLVM/project 81eb9e0llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Merge conflicts

Change-Id: I33564a1e5d14f3b53577cb463ba2cb3a7993fd24
DeltaFile
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+4-31 files

LLVM/project 5a4214aclang/docs/ScalableStaticAnalysis/user-docs SourceEditGeneration.md, clang/include/clang/Frontend SSAFOptions.h

[SSAF][SourceTransform] Add '--ssaf-link-unit-id=' for specifying link unit identifiers

The source-transformation pass takes WPA results as input, where
entities are named under link-unit and compilation-unit namespaces.
To associate ASTNodes with entities, the source-transformation pass
needs to know both link-unit and compilation-unit IDs. Such information
is provided by the caller.

rdar://185818153
DeltaFile
+8-6clang/test/Analysis/Scalable/source-edit-generation/cli-errors.cpp
+8-3clang/docs/ScalableStaticAnalysis/user-docs/SourceEditGeneration.md
+9-0clang/include/clang/Options/Options.td
+6-0clang/lib/ScalableStaticAnalysis/Frontend/SourceTransformationFrontendAction.cpp
+4-0clang/include/clang/Frontend/SSAFOptions.h
+2-1clang/test/Analysis/Scalable/source-edit-generation/downgradable-errors.cpp
+37-106 files not shown
+46-1112 files

LLVM/project 03fa14allvm/include/llvm/MC MCInstrDesc.h, llvm/include/llvm/Target Target.td

[RISCV][GlobalISel] Legalize and select G_PREFETCH (#215466)

GlobalISel aborted on `llvm.prefetch` ("unable to legalize
`G_PREFETCH`") while SDAG lowers it to `prefetch.r/w/i`. Add a legalizer
rule marking `G_PREFETCH` legal for p0 addresses, and a custom selector
since the SDAG patterns use the `AddrRegImmLsb00000` complex pattern
that the GISel pattern importer does not auto-translate. The selector
picks `prefetch.r/w/i` from the rw/cache-type immediates and folds a
`simm12_lsb00000` offset when present, matching SDAG.
DeltaFile
+556-0llvm/test/CodeGen/RISCV/GlobalISel/prefetch.ll
+192-5llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+3-3llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+4-2llvm/include/llvm/Target/Target.td
+4-2llvm/include/llvm/MC/MCInstrDesc.h
+3-0llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
+762-123 files not shown
+766-149 files

LLVM/project 57fc5aellvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.h RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel legalizer-info-validation.mir readsteadycounter.ll

[RISCV][GlobalISel] Legalize readcyclecounter/readsteadycounter (#217535)

Add a legalizer rule for G_READCYCLECOUNTER/G_READSTEADYCOUNTER. On RV64
they are legal and select via the existing tablegen Pats
(rdcycle/rdtime). On RV32 lower them to the ReadCounterWide target
pseudo, which FinalizeISel expands into the re-read-the-high-half loop
(emitReadCounterWidePseudo) — the same expansion SelectionDAG uses.
DeltaFile
+107-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+24-0llvm/test/CodeGen/RISCV/GlobalISel/readsteadycounter.ll
+24-0llvm/test/CodeGen/RISCV/GlobalISel/readcyclecounter.ll
+5-4llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+2-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+162-45 files

LLVM/project 8ebb4a0clang/lib/StaticAnalyzer/Checkers/WebKit RawPtrRefLambdaCapturesChecker.cpp, clang/test/Analysis/Checkers/WebKit unchecked-lambda-captures.cpp

[alpha.webkit.UncheckedLambdaCapturesChecker] Allow protectedThis of RefPtr (#218723)

Fix a bug that lambda capture checkers were checking for the exact match
for "protectedThis" as opposed to any protective smart pointer.
DeltaFile
+8-0clang/test/Analysis/Checkers/WebKit/unchecked-lambda-captures.cpp
+2-2clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
+10-22 files

LLVM/project 77d2b37llvm/lib/Frontend/OpenMP OMPDescriptors.inc, llvm/test/CodeGen/AArch64 vector-ldst-offset.ll vector-ldst-align.ll

Rebase

Created using spr 1.3.7
DeltaFile
+9,921-0llvm/test/CodeGen/AArch64/vector-ldst-align-float.ll
+8,227-0llvm/test/CodeGen/AArch64/vector-ldst-align.ll
+3,448-2llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
+2,421-285llvm/test/tools/llvm-mca/AArch64/Cortex/A57-forwarding.s
+2,386-0llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+1,217-1,125llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+27,620-1,4121,699 files not shown
+98,366-40,9541,705 files

LLVM/project 6c81b99llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVISelLowering.cpp

[RISCV][P-ext] Custom lower v8i8 mulh* on RV64. NFC (#218160)

Assisted-by: Claude
DeltaFile
+44-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+28-13llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+72-152 files

LLVM/project 994a5ffllvm/utils/TableGen/Common CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h

[TableGen] Simplify PtrAddrSpace handling in TypeSetByHwMode. NFC (#218564)

The PtrAddrSpace field was previously unused and I think it always has
been. The AddrSpace field used to be vector, but was made a single value
in 83507644ed1c59d76ca0b1ffc3e837fcb3677e41.

Replace AddrSpace with PtrAddrSpace for clarity.

Remove unnecessary conversions to ValueTypeByHwMode to get the pointer
address space. The conversion copies the PtrAddrSpace directly from the
TypeSetByHwMode without modification.
DeltaFile
+4-3llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+2-2llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+6-52 files

LLVM/project aa9a5edllvm/utils/TableGen AsmMatcherEmitter.cpp

[TableGen] Fix non-deterministic output from emitGetRegClassFromMatchKindFunc. (#218560)

We were iterating a std::map that uses a pointer for the key which isn't
deterministic.

To fix, dereference the pointer and use operator< from the class.
DeltaFile
+2-1llvm/utils/TableGen/AsmMatcherEmitter.cpp
+2-11 files

LLVM/project 35746b2llvm/lib/Target/BPF BTFDebug.cpp, llvm/test/CodeGen/BPF/BTF func-nocall-reassigned-arg.ll func-nocall-spilled-arg.ll

[BPF] Record an argument's first DBG_VALUE as its entry location (#217991)

Accurate BTF types for DW_CC_nocall functions were added in [1] and work
at -O2. At -O1 the entry block keeps debug locations that -O2 optimizes
away, and two of those patterns defeat the argument-register scan.
Accurate signatures are worth having at -O1 too: transformations move
between optimization levels over time, and some users build at -O1.

collectNocallEntryArgRegs() scans the entry block for DBG_VALUEs to find
which physical register each source argument arrived in. An argument may
have several DBG_VALUEs there, and the map was last-write-wins, so a
later location silently replaced the entry one. The registers then no
longer match the optimized IR signature,
canUseNocallOptimizedSignature() bails, and BTFDebug emits the
unfiltered source prototype -- a FUNC_PROTO that does not describe the
real ABI.

The first pattern is a spilled argument. From
progs/test_l4lb_noinline_dynptr.c in the kernel BPF selftests, with the

    [45 lines not shown]
DeltaFile
+74-0llvm/test/CodeGen/BPF/BTF/func-nocall-spilled-arg.ll
+52-0llvm/test/CodeGen/BPF/BTF/func-nocall-reassigned-arg.ll
+3-2llvm/lib/Target/BPF/BTFDebug.cpp
+129-23 files

LLVM/project 863f70ellvm/lib/Target/AMDGPU SIInsertHardClauses.cpp, llvm/test/CodeGen/AMDGPU hard-clauses-gfx1250.mir

[AMDGPU] Prevent clauses with incompatible scopes on gfx1250-strict
DeltaFile
+168-8llvm/test/CodeGen/AMDGPU/hard-clauses-gfx1250.mir
+20-1llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
+188-92 files

LLVM/project 7e65276offload/test/offloading/CUDA blocking_stream_semantics.cu, offload/test/offloading/HIP blocking_stream_semantics.hip

unify tests
DeltaFile
+0-131offload/test/offloading/CUDA/blocking_stream_semantics.cu
+129-0offload/test/offloading/language/blocking_stream_semantics.cpp
+0-125offload/test/offloading/HIP/blocking_stream_semantics.hip
+110-0offload/test/offloading/language/stream_api.cpp
+102-0offload/test/offloading/language/get_errs.cpp
+100-0offload/test/offloading/language/devicesync_streams.cpp
+441-25646 files not shown
+1,116-1,95352 files

LLVM/project 90e874foffload/languages/include/kernel LanguageRuntime.h, offload/languages/kernel/src LanguageRuntime.cpp

add Memset
DeltaFile
+87-0offload/test/offloading/CUDA/memset.cu
+85-0offload/test/offloading/HIP/memset.hip
+14-0offload/languages/kernel/src/LanguageRuntime.cpp
+1-2offload/test/offloading/HIP/basic_launch_blocks_and_threads.hip
+1-2offload/test/offloading/CUDA/basic_launch_blocks_and_threads.cu
+2-0offload/languages/include/kernel/LanguageRuntime.h
+190-42 files not shown
+192-48 files