FreshBSD

   remove unneeded variables in uchcom_softc

   omit irrelevant #includes

[InstCombine] Fix negative GEP offset evaluation for 32-bit pointers

This fixes https://bugs.llvm.org/show_bug.cgi?id=39908.

The evaluateGEPOffsetExpression() function simplifies GEP offsets for
use in comparisons against zero, basically by converting X*Scale+Offset==0
to X+Offset/Scale==0 if Scale divides Offset. However, before this is done,
Offset is masked down to the pointer size. This results in incorrect
results for negative Offsets, because we basically end up dividing the
32-bit offset *zero* extended to 64-bit bits (rather than sign extended).

Fix this by explicitly sign extending the truncated value.

Differential Revision: https://reviews.llvm.org/D55449

Merge remote-tracking branch 'origin/hardened/11-stable/master' into 
hardened/11-stable/unstable

* origin/hardened/11-stable/master:
  MFC r339873:

Merge branch 'freebsd/11-stable/master' into hardened/11-stable/master

* freebsd/11-stable/master:
  MFC r339873:

[hwasan] Link ubsan_cxx to shared runtime library.

Summary: This is needed for C++-specific ubsan and cfi error reporting to work.

Reviewers: kcc, vitalybuka

Subscribers: srhines, kubamracek, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D55589

[llvm-objcopy] Change Segment::Type from uint64_t to uint32_t

Summary:
In both Elf{32,64}_Phdr, the field Elf{32,64}_World p_type is uint32_t.

Also reorder the fields to be similar to Elf64_Phdr (which is different
from Elf32_Phdr but quite similar).

Reviewers: rupprecht, jhenderson, jakehehrlich, alexshap, espindola

Reviewed By: rupprecht

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D55618

Switch Android from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)

Summary:
The TLS_SLOT_TSAN slot is available starting in N, but its location (8)
is incompatible with the proposed solution for implementing ELF TLS on
Android (i.e. bump ARM/AArch64 alignment to reserve an 8-word TCB).

Instead, starting in Q, Bionic replaced TLS_SLOT_DLERROR(6) with
TLS_SLOT_SANITIZER(6). Switch compiler-rt to the new slot.

Reviewers: eugenis, srhines, enh

Reviewed By: eugenis

Subscribers: ruiu, srhines, kubamracek, javed.absar, kristof.beyls, delcypher, 
llvm-commits, #sanitizers

Differential Revision: https://reviews.llvm.org/D55581

[hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)

Summary:
The change is needed to support ELF TLS in Android. See D55581 for the
same change in compiler-rt.

Reviewers: srhines, eugenis

Reviewed By: eugenis

Subscribers: srhines, llvm-commits

Differential Revision: https://reviews.llvm.org/D55592

Revert "Declares __cpu_model as dso local"

This reverts r348978

Update the approvers file to share custody of releng/12.0 between
so@ and re@ until re@ is comfortable turning over releng/12.0
entirely.

Approved by:    re (implicit)
Sponsored by:   The FreeBSD Foundation

x11-fonts/plex-ttf: Update to 1.2.2

Changes:        https://github.com/IBM/plex/releases

mv_thermal: Add thermal driver for AP806 and CP110 thermal sensor

Sponsored by:   Rubicon Communications, LLC ("Netgate")

   p11-kit: Use `+=' to append to DEPENDS (not `=') (NFC)

   +DYAC

Avoid code duplication in the SEH version of UnwindCursor::getRegisterName. NFC.

This requires making Registers_*::getRegisterName static.

Differential Revision: https://reviews.llvm.org/D55610

arm64: mv_cp110_icu: Fix build

Remove duplicate port (of devel/dcmtk)

Pointy hat:     yuri

[PhaseOrdering] add test for funnel shift (rotate); NFC

As mentioned in D55604, there are 2 bugs here:
1. The new pass manager is speculating wildly by default.
2. The old pass manager is not converting this to funnel shift.

[hwasan] Verify Android TLS slot at startup.

Summary:
Add a check that TLS_SLOT_TSAN / TLS_SLOT_SANITIZER, whichever
android_get_tls_slot is using, is not conflicting with
TLS_SLOT_DLERROR.

Reviewers: rprichard, vitalybuka

Subscribers: srhines, kubamracek, llvm-commits

Differential Revision: https://reviews.llvm.org/D55587

mv_gpio: Since it's also an interrupt controller, attach sooner

Sponsored by:   Rubicon Communications, LLC ("Netgate")

sdhci_xenon: Add Marvell 8k compatible string

Sponsored by:   Rubicon Communications, LLC ("Netgate")

arm64: Add mv_cp110_icu and mv_cp110_gicp

icu is a interrupt concentrator in the CP110 block and gicp
is a gic extension to allow interrupts in the CP block to be turned
into GIC SPI interrupts

Sponsored by:   Rubicon Communications, LLC ("Netgate")

twsi: Clean up marvell part and add support for Marvell 7k/8k

Sponsored by:   Rubicon Communications, LLC ("Netgate")

arm64: marvell: Add cp110 clock controller support

The cp110 clock controller controls the clocks and gate of the CP110
hardware block.

Every clock/gate are implemented except the NAND clock.

Sponsored by:   Rubicon Communications, LLC ("Netgate")

Declares __cpu_model as dso local

__builtin_cpu_supports and __builtin_cpu_is use information in __cpu_model to decide cpu 
features. Before this change, __cpu_model was not declared as dso local. The generated 
code looks up the address in GOT when reading __cpu_model. This makes it impossible to use 
these functions in ifunc, because at that time GOT entries have not been relocated. This 
change makes it dso local.

Differential Revision: https://reviews.llvm.org/D53850

arm64: mv_gpio: Add Marvell 8K support

While here put the interrupts setup in it's own function

Sponsored by:   Rubicon Communications, LCC ("Netgate")

arm64: marvell: Add driver for Marvell Ap806 System Controller

The first two clocks are for the clusters and their frequencies can be
found reading a register. Then a fixed 1200Mhz clock is present and two
fixed clocks, 'mss' which is 1200 / 6 and 'sdio' which is 1200 / 3.

Sponsored by:   Rubicon Communications, LLC ("Netgate")

arm64: mvebu_pinctrl: Add driver for Marvell Pinmux Controller

Add a driver compatible with Marvell mvebu-pinctrl and add ap806-pinctrl
support.

Sponsored by:   Rubicon Communications, LCC ("Netgate")

arm64: Add new SoC type MARVELL_8K

Sponsored by:   Rubicon Communications, LLC ("Netgate")

accessibility/accerciser: fix packaging with python 3.7

Add upstream patch to fix packaging/runtime with python 3.7

PR:            233770
With hat:       gnome

pull https://reviews.freebsd.org/D17896 to fix netmap tx / bpf packet tap hook, closes 
https://github.com/opnsense/core/issues/1632

tested locally with intel igb driver, seems to be working fine, lets give this some time 
in our dev version.

Enable devcryptoeng for OpenSSL.

Since OpenSSL 1.1.1, the good old BSD-specific cryptodev engine has been
deprecated in favor of this new engine.  However, this engine is not
throughly tested on FreeBSD because it was originally written for Linux.

http://cryptodev-linux.org/

Also, the author actually meant to enable it by default on BSD platforms but
he failed to do so because there was a bug in the Configure script.

https://github.com/openssl/openssl/pull/7882

Now they found that it was more generic issue.

https://github.com/openssl/openssl/pull/7885

Therefore, we need to enable this engine on head to give it more exposure.

fdt: Add support for simple-mfd bus

Quoting the binding Documentation :

"These devices comprise a nexus for heterogeneous hardware blocks containing
more than one non-unique yet varying hardware functionality."

Reviewed by:    loos
Sponsored by:   Rubicon Communications, LLC ("Netgate")
Differential Revision:  https://reviews.freebsd.org/D17751

   Cleanup, no functional change:
   No need to expose the tbl(7) syntax tree data structures everywhere.
   Move them to their own include file, "tbl.h", and improve comments.

[AST] Store "UsesADL" information in CallExpr.

Summary:
Currently the Clang AST doesn't store information about how the callee of a CallExpr was 
found. Specifically if it was found using ADL.

However, this information is invaluable to tooling. Consider a tool which renames usages 
of a function. If the originally CallExpr was formed using ADL, then the tooling may need 
to additionally qualify the replacement.
Without information about how the callee was found, the tooling is left scratching it's 
head. Additionally, we want to be able to match ADL calls as quickly as possible, which 
means avoiding computing the answer on the fly.

This patch changes `CallExpr` to store whether it's callee was found using ADL. It does 
not change the size of any AST nodes.


Reviewers: fowles, rsmith, klimek, shafik

Reviewed By: rsmith

Subscribers: aaron.ballman, riccibruno, calabrese, titus, cfe-commits

Differential Revision: https://reviews.llvm.org/D55534

audio/csound: Revert the unintentional change

Reported by:    jbeich

   doc: Updated devel/boehm-gc to 8.0.0nb1

   boehm-gc: update to 8.0.0nb1.

   Disable munmap'ping to work around the regression in 8.0.0 on
   NetBSD.

libxlsxwriter: Installation fails on macOS

   BDEP on intltool

[globalisel] Rename GISelChangeObserver's erasedInstr() to erasingInstr() and related 
nits. NFC

Summary:
There's little of interest that can be done to an already-erased instruction.
You can't inspect it, write it to a debug log, etc. It ought to be notification
that we're about to erase it. Rename the function to clarify the timing of the
event and reflect current usage.

Also fixed one case where we were trying to print an erased instruction.

Reviewers: aditya_nandakumar

Reviewed By: aditya_nandakumar

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D55611

www/phalcon: bump to 3.4.2 again

   remove unused prototypes

   add tx-data reporting event

pwm: Fix some arches by using %ju and casting to uintmax_t

Reported by:    ci.freebsd.org

[X86] Don't emit MULX by default with BMI2

MULX has somewhat improved register allocation constraints compared to the legacy MUL 
instruction. Both output registers are encoded instead of fixed to EAX/EDX, but EDX is 
used as input. It also doesn't touch flags. Unfortunately, the encoding is longer.

Prefering it whenever BMI2 is enabled is probably not optimal. Choosing it should somehow 
be a function of register allocation constraints like converting adds to three address. 
gcc and icc definitely don't pick MULX by default. Not sure what if any rules they have 
for using it.

Differential Revision: https://reviews.llvm.org/D55565

   Simplify mbzero() by using mem_write with a NULL buf which does zero out
   all memory at once without having to use a zero buffer.
   OK mlarkin@

   Set the com speed to 115200 like we do in our bootloader when using SeaBIOS.
   OK mlarkin@

Fix for llvm-dwarfdump changes for subroutine types