FreshBSD

add check for long double for __builtin_dump_struct

[llvm-mca] Remove method Instruction::isZeroLatency(). NFCI

[LoopInterchange] Use getExitBlock()/getExitingBlock instead of manual impl.

This also means we have to check if the latch is the exiting block now,
as `transform` expects the latches to be the exiting blocks too.

https://bugs.llvm.org/show_bug.cgi?id=36586

Reviewers: efriedma, davide, karthikthecool

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D45279

[AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.

This patch adds parsing support for 'vector + shift/extend' and
corresponding asm operand classes, needed for implementing SVE's
gather/scatter addressing modes.

The added combinations of vector (ZPR) and Shift/Extend are:

Unscaled:
  ZPR64ExtLSL8:           signed 64-bit offsets  (z0.d)
  ZPR32ExtUXTW8:        unsigned 32-bit offsets  (z0.s, uxtw)
  ZPR32ExtSXTW8:          signed 32-bit offsets  (z0.s, sxtw)

Unpacked and unscaled:
  ZPR64ExtUXTW8:        unsigned 32-bit offsets  (z0.d, uxtw)
  ZPR64ExtSXTW8:          signed 32-bit offsets  (z0.d, sxtw)

Unpacked and scaled:
  ZPR64ExtUXTW<scale>:  unsigned 32-bit offsets  (z0.d, uxtw #<shift>)
  ZPR64ExtSXTW<scale>:    signed 32-bit offsets  (z0.d, sxtw #<shift>)

Scaled:
  ZPR32ExtUXTW<scale>:  unsigned 32-bit offsets  (z0.s, uxtw #<shift>)
  ZPR32ExtSXTW<scale>:    signed 32-bit offsets  (z0.s, sxtw #<shift>)
  ZPR64ExtLSL<scale>:   unsigned 64-bit offsets  (z0.d,  lsl #<shift>)

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[DebugInfo] Invalidate debug info in ReassociatePass::RewriteExprTree

Summary:
When Reassociate is rewriting an expression tree it may
reuse old binary expression nodes, for new expressions.
Whenever an expression node is reused, but with a non-trivial
change in the result, we need to invalidate any debug info
that is associated with the node.

If for example rewriting
  x = mul a, b
  y = mul c, x
into
  x = mul c, b
  y = mul a, x
we still get the same result for 'y', but 'x' is a new expression.
All debug info referring to 'x' must be invalidated (marked as
optimized out) since we no longer calculate the expected value.

As a side-effect this patch avoid (at least some) problems where
reassociate could end up creating IR with debug-use before def.
Earlier the dbg.value nodes where left untouched in the IR, while
the reused binary nodes where sinked to just before the root node
of the rewritten expression tree. See PR27273 for more info about
such problems.

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Fix buildbot problems after rC330794

Avoiding
  error: no matching function for call to 'makeArrayRef'
at
  ../tools/clang/lib/Parse/ParseTemplate.cpp:373:17

By using a local C array as input to makeArrayRef.

Not sure if this is the best solution, but it makes the code
compile again.

[TableGen] Fix bad indentation in tablegen output file.

Merging r46043:
------------------------------------------------------------------------

[NFC] Make dependent parameter non-deducible, so that we are forced to use the default 
template parameter.

This might provide users with more graceful diagnostics if they should ever try and call 
this function with non-ConceptDecls.

[X86] Auto-generate complete checks. NFC

Fix rC330794 - a parameter that should have been dependent was inadvertently not -
 and compiled in MSVC - but not so for the other bots.

The fix was to make it dependent as intended.

Fix lit test kernel-call.cu failure on ps4 due to dso_local

[c++2a] [concepts] Add rudimentary parsing support for template concept declarations


This patch is a tweak of changyu's patch: https://reviews.llvm.org/D40381. It differs in 
that the recognition of the 'concept' token is moved into the machinery that recognizes 
declaration-specifiers - this allows us to leverage the attribute handling machinery more 
seamlessly.

See the test file to get a sense of the basic parsing that this patch supports. 

There is much more work to be done before concepts are usable...

Thanks Changyu!

Fix failure in lit test kernel-call.cu

There is signext on ppc64. Just remove check for function argument.

[DivRemPairs] Fix non-determinism in use list order.

Summary:
Use a MapVector instead of a DenseMap for RemMap since it is iteratated
over and the order of iteration can effect the order that new
instructions are created.  This can in turn effect the use list order of
div/rem input values if multiple new instructions are created that share
any input values.

Reviewers: spatel

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D45858

[libcxx] [test] Remove nonportable that errc::is_a_directory produces "Is a directory" 
from ios_base::failure tests

These io_error asserts that std::errc::is_a_directory has message "Is a directory". On 
MSVC++ it reports "is a directory" (with a lowercase I). That doesn't matter for the 
ios_failure component being tested, so just implement in terms of 
system_category().message().

Reviewed as https://reviews.llvm.org/D45715

[HIP] Add hip input kind and codegen for kernel launching

HIP is a language similar to CUDA 
(https://github.com/ROCm-Developer-Tools/HIP/blob/master/docs/markdown/hip_kernel_language.md 
).
The language syntax is very similar, which allows a hip program to be compiled as a CUDA 
program by Clang. The main difference
is the host API. HIP has a set of vendor neutral host API which can be implemented on 
different platforms. Currently there is open source
implementation of HIP runtime on amdgpu target 
(https://github.com/ROCm-Developer-Tools/HIP).

This patch adds support of input kind and language standard hip.

When hip file is compiled, both LangOpts.CUDA and LangOpts.HIP is turned on. This allows 
compilation of hip program as CUDA
in most cases and only special handling of hip program is needed LangOpts.HIP is checked.

This patch also adds support of kernel launching of HIP program using HIP host API.

When -x hip is not specified, there is no behaviour change for CUDA.

Patch by Greg Rodgers.
Revised and lit test added by Yaxun Liu.

Differential Revision: https://reviews.llvm.org/D44984

[ODRHash] Hash template arguments of methods.

Bring r329960 back.

The fix is to copy Used when replacing the symbol.

Original message:

Do not keep shared symbols created from garbage-collected eliminated DSOs.

If all references to a DSO happen to be weak, and if the DSO is
specified with --as-needed, the DSO is not added to DT_NEEDED.
If that happens, we also need to eliminate shared symbols created
from the DSO. Otherwise, they become dangling references that point
to non-exsitent DSO.

Fixes https://bugs.llvm.org/show_bug.cgi?id=36991

Differential Revision: https://reviews.llvm.org/D45536

[PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use the new
update API for dominators rather than doing manual, hacky updates.

This is just the first step, but in some ways the most important as it
moves the non-trivial unswitching to update the domtree rather than
fully recalculating it each time.

Subsequent patches should remove the custom update logic used by the
trivial unswitch and replace it with uses of the update API.

This also fixes a number of bugs I was seeing when testing non-trivial
unswitch due to it querying the quasi-correct dominator tree. Now the
tree is 100% correct and safe to query. That said, there are still more
bugs I can see with non-trivial unswitch just running over the test
suite, so more bugfix patches are needed as well.

Thanks to both Sanjoy and Fedor for reviews and testing!

Differential Revision: https://reviews.llvm.org/D45943

[COFF] create MemoryBuffers without requiring NUL terminators

Summary:
In a number of places in the COFF linker, we were calling
MemoryBuffer::getFile() with default parameters. This causes LLVM to
NUL-terminate the buffers, which can prevent them from being memory
mapped. Since we operate on binary and do not use NUL as an indicator
of the end of the file content, this change causes us to not require
the NUL terminator anymore.

Reviewers: ruiu, pcc

Reviewed By: ruiu

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45909

Style fix.

Add a test. NFC.

This would have found the issue in r329960.

[MachineOutliner] Check for explicit uses of LR/W30 in MI operands

Before, the outliner would grab ADRPs that used LR/W30. This patch fixes
that by checking for explicit uses of those registers before the special-casing
for ADRPs.

This also adds a test that ensures that those sorts of ADRPs won't be outlined.

[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal

We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during 
X86's promotion of i16->i32. Not sure about other targets.

Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign 
extended operand like we would need for SRA. However, X86 doesn't currently promote i16 
SRA. I was looking into doing that which is how I found this issue.

This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is 
what caused most of the test changes here.

Differential Revision: https://reviews.llvm.org/D45585#inline-402825

Revert "[Driver] Android triples are not aliases for other triples."

Revering while I diagnose the failures.

This reverts commit 82dc3bf2157da280420f80e654292cb05e0dc5f7.

Fix path separator checks on Windows

[X86] Account for partial stack slot spills (PR30821)

Previously, _any_ store or load instruction was considered to be
operating on a spill if it had a frameindex as an operand, and thus
was fair game for optimisations such as "StackSlotColoring". This
usually works, except on architectures where spills can be partially
restored, for example on X86 where a spilt vector can have a single
component loaded (zeroing the rest of the target register). This can be
mis-interpreted and the zero extension unsoundly eliminated, see
pr30821.

To avoid this, this commit optionally provides the caller to
isLoadFromStackSlot and isStoreToStackSlot with the number of bytes
spilt/loaded by the given instruction. Optimisations can then determine
that a full spill followed by a partial load (or vice versa), for
example, cannot necessarily be commuted.

Patch by Jeremy Morse!

Differential Revision: https://reviews.llvm.org/D44782

[llvm-objcopy] Adjust the help message

Capitalize the first letter, 
make the text a bit more consistent.
NFC.

Differential revision: https://reviews.llvm.org/D46025

Bring back APInt self-move assignment check for MSVC only

Summary:
It was removed about a year ago in r300477. Bring it back, along with
its unittest, when the MSVC STL is in use. The MSVC STL performs
self-assignment in std::shuffle. These days, llvm::sort calls
std::shuffle when expensive checks are enabled to help find
non-determinism bugs.

Reviewers: craig.topper, chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46028

AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic

Summary: This is no longer used by mesa since its 18.0.0 release.

Reviewers: nhaehnle

Reviewed By: nhaehnle

Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D45988

AMDGPU/GlobalISel: Fall-back to SelectionDAG for non-void functions

Reviewers: arsenm, nhaehnle

Reviewed By: nhaehnle

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, 
t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45843

[docs] Add a note on non-deterministic sorting order of equal elements

Reviewers: RKSimon, t.p.northover, dexonsmith

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45831

[X86][AArch64][NFC] Add tests for masked merge unfolding with %y = const

The fold was added in D45733.

This appears to be a regression.

[Driver] Android triples are not aliases for other triples.

Summary:
Android targets should never use tools/libraries for non-Android
targets or vice versa.

Reviewers: srhines, george.burgess.iv, eugenis

Reviewed By: eugenis

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D45597

[CaptureTracking] Fixup const correctness of DomTree arg (NFC)

Summary:
The PointerMayBeCapturedBefore function's DomTree arg should be
const instead of non-const. There are no non-const uses of it
in the function.

[InstCombine] move tests for select with bit-test of condition; NFC

These are all but 1 of the select-of-constant tests that appear 
to be transformed within foldSelectICmpAnd() and the block above 
it predicated by decomposeBitTestICmp().

As discussed in D45862 (and can be seen in several tests here),
we probably want to stop doing those transforms because they
can increase the instruction count without benefitting other
passes or codegen.

The 1 test not included here is a urem test where the bit hackery
allows us to remove a urem. To preserve killing that urem, we 
should do some stronger known-bits analysis or pattern matching of 
'urem x, (select-of-pow2-constants)'.

AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, 
t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45837

[analyzer] Add support for the note diagnostic pieces to plist output format.

Note diagnostic pieces are an additional way of highlighting code sections to
the user. They aren't part of the normal path diagnostic sequence. They can
also be attached to path-insensitive reports.

Notes are already supported by the text output and scan-build.

Expanding our machine-readable plist output format to be able to represent notes
opens up the possibility for various analyzer GUIs to pick them up.

Patch by Umann Kristóf!

Differential Revision: https://reviews.llvm.org/D45407

[wasm] Fix uninitialized memory introduced in r330749.

Found with MSan. This was causing all the WASM MC tests to fail about
10% of the time.

[bugpoint] Fix crash when testing for miscompilation.

Method BugDriver::performFinalCleanups(...) would delete Module object
it worked on, which was also deleted by its caller
(e.g. TestCodeGenerator(...)). Changed the code to avoid double delete
and make Module ownership slightly clearer.

Patch by Andrzej Janik.

[Support] fix countLeadingZeros for types shorter than int

[cmake] Fix libc++ detection

-stdlib=libc++ is added to both the compilation and the link flags, but
the logic for adding it was only checking if it was supported during
compilation and not linking. This could lead to false positives, for
example when using clang with libstdc++ (where the compiler would
support -stdlib=libc++ but then linking would fail because of libc++
actually being unavailable).

[X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.

Improve -Warray-bounds to handle multiple array extents rather than only handling the 
top-most array extent.

Patch by Bevin Hansson.

[test] Update llc checks for CodeGen/X86/avg.ll

The output of update_llc_test_checks.py on this test file has changed,
so the test file should be updated to minimize source changes in future
patches.

The test updates for this file appear to be limited to relaxations of
the form:

  -; SSE2-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill
  +; SSE2-NEXT:    movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill

This was suggested in https://reviews.llvm.org/D45995.

[llvm-mca] Remove unused flag -verbose. NFC

I forgot to remove it at r329794.

[X86] Split off PHMINPOSUW to their own schedule class

This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default.

[lit] Report line number for failed RUN command

When debugging test failures with -vv (or -v in the case of the
internal shell), this makes it easier to locate the RUN line that
failed.  For example, clang's test/Driver/linux-ld.c has 892 total RUN
lines, and clang's test/Driver/arm-cortex-cpus.c has 424 RUN lines
after concatenation for line continuations.

When reading the generated shell script, this also makes it easier to
locate the RUN line that produced each command.

To support reporting RUN line numbers in the case of the internal
shell, this patch extends the internal shell to support the null
command, ":", except pipelines are not supported.

Reviewed By: asmith, delcypher

Differential Revision: https://reviews.llvm.org/D44598

[CUDA] Enable CUDA compilation with CUDA-9.2

Differential Revision: https://reviews.llvm.org/D45827