FreshBSD

[WebAssembly] Add WebAssemblyException information analysis

Summary:
A WebAssemblyException object contains BBs that belong to a 'catch' part
of the try-catch-end structure. Because CFGSort requires all the BBs
within a catch part to be sorted together as it does for loops, this
pass calculates the nesting structure of catch part of exceptions in a
function. Now this assumes the use of Windows EH instructions.

Reviewers: dschuff, majnemer

Subscribers: jfb, mgorny, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D44134

[WebAssembly] Add WebAssemblyLateEHPrepare pass

Summary:
Add WebAssemblyLateEHPrepare pass that does several small jobs for
exception handling. This runs before CFGSort, and is different from
WasmEHPrepare pass that runs before ISel, even though the names are
similar.

Reviewers: dschuff, majnemer

Subscribers: sbc100, jgravelle-google, sunfish, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D46803

[X86] Simplify some code by using isOneConstant. NFC

[X86] Remove the changes to combineScalarToVector made in r335037.

They appear to be untested other than the test case for p37879.ll and I believe we should 
be using SimplifyDemandedElts here to handle these cases.

[X86] Reduce the number of patterns needed for masked scalar ceil/floor isel.

The scalar to vector on the mask register should not be part of the patterns.

[mips][ias] Enable IAS by default for OpenBSD / FreeBSD mips64/mips64el.

Reviewers: atanasyan

Differential Review: https://reviews.llvm.org/D31557

[DAGCombiner] eliminate setcc bool math when input is low-bit of some value

This patch has the same motivating example as D48466:
define void @foo(i64 %x, i32 %c.0282.in, i32 %d.0280, i32* %ptr0, i32* %ptr1) {
    %c.0282 = and i32 %c.0282.in, 268435455
    %a16 = lshr i64 32508, %x
    %a17 = and i64 %a16, 1
    %tobool = icmp eq i64 %a17, 0
    %. = select i1 %tobool, i32 1, i32 2
    %.286 = select i1 %tobool, i32 27, i32 26
    %shr97 = lshr i32 %c.0282, %.
    %shl98 = shl i32 %c.0282.in, %.286
    %or99 = or i32 %shr97, %shl98
    %shr100 = lshr i32 %d.0280, %.
    %shl101 = shl i32 %d.0280, %.286
    %or102 = or i32 %shr100, %shl101
    store i32 %or99, i32* %ptr0
    store i32 %or102, i32* %ptr1
    ret void
}

...but I'm trying to kill the setcc bool math sooner rather than later.

By matching a larger pattern that includes both the low-bit mask and the trailing add/sub, 


    [52 lines not shown]

[FileSpec] Always normalize

Removing redundant components from the path seems pretty harmless.
Rather than checking whether this is necessary and then actually doing
so, always invoke remove_dots to start with a normalized path.

Make testcase classnames unique

Filenames with test results contain only the class name which makes it more
difficult to find it if the same class name is present in multiple *.py files.

packages/Python/lldbsuite/test/functionalities/step-avoids-no-debug/TestStepNoDebug.py
-class ReturnValueTestCase(TestBase):
+class StepAvoidsNoDebugTestCase(TestBase):
as ReturnValueTestCase is already present in:
packages/Python/lldbsuite/test/functionalities/return-value/TestReturnValue.py

packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
-class CreateDuringStepTestCase(TestBase):
+class CrashDuringStepTestCase(TestBase):
as CreateDuringStepTestCase is already present in:
packages/Python/lldbsuite/test/functionalities/thread/create_during_step/TestCreateDuringStep.py

packages/Python/lldbsuite/test/functionalities/thread/step_until/TestStepUntil.py
-class TestCStepping(TestBase):
+class StepUntilTestCase(TestBase):
as TestCStepping is already present in:
packages/Python/lldbsuite/test/lang/c/stepping/TestStepAndBreakpoints.py

[FileSpec] Refactor append and prepend implemenetations. NFC

Replaces custom implementations of append and prepend with calls to
llvm's path library. This is part of a series of patches (started in
D48084) to delegate common operations to llvm::sys::path.

[X86] Regroup some isel patterns. NFC

For some reason the 64-bit patterns were separated from their 8/16/32-bit friends, but 
only for add/sub/mul. For and/or/xor they were together.

[X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include a Z to match 
other EVEX instructions.

Also forward declare BitScanReverse.

With the removal of intrin.h in an earlier patch, the intrinsics
that we were actually using were manually re-declared, however
several of them were missed leading to compilation failures with
MSVC.  Fix those.

Add OpenBSD support to the Threading code

[CMake] Do not use --gc-sections on OpenBSD

[CMake] Support building shared library for OpenBSD

[llc] Fix sanitizer failure.

Store the string on the stack rather than just the StringRef.

Fix sanitizer bots:

  http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19948
  http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/5500

[Coroutines] Less IR for noexcept await_resume

Summary:
In his review of https://reviews.llvm.org/D45860, @GorNishanov suggested
avoiding generating additional exception-handling IR in the case that
the resume function was marked as 'noexcept', and exceptions could not
occur. This implements that suggestion.

Test Plan: `check-clang`

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: cfe-commits, GorNishanov

Differential Revision: https://reviews.llvm.org/D47673

ADT: Use EBO to shrink SmallVector size 1

SmallVectorStorage is empty when its size is 1; use inheritance so that
the empty base class optimization kicks in.

[Sema] isValidCoroutineContext FIXME and citations

Summary:
Add citations to the Coroutines TS to the `isValidCoroutineContext`
function, as well as a FIXME and test for [expr.await]p2, which states
a co_await expression cannot be used in a default argument.

Test Plan: check-clang

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: rsmith, cfe-commits

Differential Revision: https://reviews.llvm.org/D48519

Attempt to fix latent tablegen dependency issue

[llc] Use WithColor for printing errors/warnings

Use the WithColor helper from support to print errors and warnings.

[llvm-config] Use WithColor for printing errors.

Use the WithColor helper from support to print errors.

[llvm-mt] Use WithColor for printing errors.

Use the WithColor helper from support to print errors.

[TableGen] Use WithColor for printing errors/warnings

Use the WithColor helper from support to print errors and warnings.

[X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix some test 
CHECK lines.

[X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is used on a 
rip-relative address.

[X86][AsmParser] Improve base/index register checks.

-Ensure EIP isn't used with an index reigster.
-Ensure EIP isn't used as index register.
-Ensure base register isn't a vector register.
-Ensure eiz/riz usage matches the size of their base register.

Fix invariant fdiv hoisting in LICM

FDiv is replaced with multiplication by reciprocal and invariant
reciprocal is hoisted out of the loop, while multiplication remains
even if invariant.

Switch checks for all invariant operands and only invariant
denominator to fix the issue.

Differential Revision: https://reviews.llvm.org/D48447

[Fuchsia] Enable static libc++, libc++abi, libunwind

This is needed for building Fuchsia drivers.

Differential Revision: https://reviews.llvm.org/D48208

[AMDGPU] Update includes for intrinsic changes :(

[ORC] Fix formatting and list pending queries in VSO::dump.

[IR] Split Intrinsics.inc into enums and implementations

Implements PR34259

Intrinsics.h is a very popular header. Most LLVM TUs care about things
like dbg_value, but they don't care how they are implemented. After I
split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU
from scanning 1.7 MB of source that gets pre-processed away.

It also means we can modify intrinsic properties without triggering a
full rebuild, but that's probably less of a win.

I think the next best thing to do would be to split out the target
intrinsics into their own header. Very, very few TUs care about
target-specific intrinsics. It's very hard to split up the target
independent intrinsics like llvm.expect, assume, and dbg.value, though.

Avoid including intrin.h from MathExtras.h

This is repeatably worth 0.3s compile time on MathExtras.cpp. This is a
very popular header, and it basically pulls all Intel intrinsics into
every LLVM TU. Let's not do that.

[ELF] Change isSectionData to exclude SHF_EXECINSTR

Summary:
This affects what sections are displayed as "DATA" in llvm-objdump.
The other user llvm-size is unaffected.

Before, a "TEXT" section is also "DATA", which seems weird.
The sh_flags condition matches that of bfd's SEC_DATA but the sh_type
condition uses (== SHF_PROGBITS) instead of bfd's (!= SHT_NOBITS).
bfd's SEC_DATA is not appealing as so many sections will be shown as DATA.

Reviewers: jyknight, Bigcheese

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D48472

[ELF] Change llvm-objdump output for D48472: TEXT DATA -> TEXT

Reviewers: jyknight, Bigcheese, espindola

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D48473

[X86][AsmParser] Rework that allows (%dx) to be used in place of %dx with in/out 
instructions.

Previously, to support (%dx) we left a wide open hole in our 16-bit memory address 
checking. This let this address value be used with any instruction without error in the 
parser. It would later fail in the encoder with an assertion failure on debug builds and 
who knows what on release builds.

This patch passes the mnemonic down to the memory operand parsing function so we can allow 
the (%dx) form only on specific instructions.

[RuntimeDyld] Implement the ELF PIC large code model relocations

Prerequisite for https://reviews.llvm.org/D47211 which improves our ELF
large PIC codegen.

Update cmdtemplate.py to use best pratices.

Fixes include:
- fix all lint errors
- add code that will automatically register and LLDB command classes by detecting the 
classes and any classes that have a "register_lldb_command" function
  - automatically fill in the correct module name when registering commands
  - automatically fill in the class name when registering command

[LoopReroll] Rewrite induction variable rewriting.

This gets rid of a bunch of weird special cases; instead, just use SCEV
rewriting for everything.  In addition to being simpler, this fixes a
bug where we would use the wrong stride in certain edge cases.

The one bit I'm not quite sure about is the trip count handling,
specifically the FIXME about overflow.  In general, I think we need to
widen the exit condition, but that's probably not profitable if the new
type isn't legal, so we probably need a check somewhere.  That said, I
don't think I'm making the existing problem any worse.

As a followup to this, a bunch of IV-related code in root-finding could
be cleaned up; with SCEV-based rewriting, there isn't any reason to
assume a loop will have exactly one or two PHI nodes.

Differential Revision: https://reviews.llvm.org/D45191

[MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFC

[X86][AsmParser] Keep track of whether an explicit scale was specified while parsing an 
address in Intel syntax. Use it for improved error checking.

This allows us to check these:
-16-bit addressing doesn't support scale so we should error if we find one there.
-Multiplying ESP/RSP by a scale even if the scale is 1 should be an error because ESP/RSP 
can't be an index.

[llvm-size] Make global variables static

[x86] add more tests for bit hacking opportunities with setcc; NFC

Missed cases where the input and output are the same size in rL335391.

[PowerPC] add more tests for bit hacking opportunities with setcc; NFC

Missed cases where the input and output are the same size in rL335390.

[X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the second register in 
memory expressions like [EAX+ESP].

By default, the second register gets assigned to the index register slot. But ESP can't be 
an index register so we need to swap it with the other register.

There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even 
though its with 1 should force ESP to the index register and trigger an error, but it 
doesn't currently.

[Sema] -Wformat-pedantic only for NSInteger/NSUInteger %zu/%zi on Darwin

Summary:
Pick D42933 back up, and make NSInteger/NSUInteger with %zu/%zi specifiers on Darwin warn 
only in pedantic mode. The default -Wformat recently started warning for the following 
code because of the added support for analysis for the '%zi' specifier.

     NSInteger i = NSIntegerMax;
     NSLog(@"max NSInteger = %zi", i);

The problem is that on armv7 %zi is 'long', and NSInteger is typedefed to 'int' in 
Foundation. We should avoid this warning as it's inconvenient to our users: it's target 
specific (happens only on armv7 and not arm64), and breaks their existing code. We should 
also silence the warning for the '%zu' specifier to ensure consistency. This is acceptable 
because Darwin guarantees that, despite the unfortunate choice of typedef, sizeof(size_t) 
== sizeof(NS[U]Integer), the warning is therefore noisy for pedantic reasons. Once this is 
in I'll update public documentation.

Related discussion on cfe-dev:
http://lists.llvm.org/pipermail/cfe-dev/2018-May/058050.html

<rdar://36874921&40501559>

Reviewers: ahatanak, vsapsai, alexshap, aaron.ballman, javed.absar, jfb, rjmccall


    [3 lines not shown]

[llvm-mca] Remove unnecessary include and forward decl in RCU. NFC.

The DispatchUnit is no longer a dependency of RCU, so this patch removes a
stale include and forward decl.  This patch also cleans up some comments.

[x86] add tests for bit hacking opportunities with setcc; NFC

We likely gave up on folding some select-of-constants patterns in 
IR with rL331486, and we need to recover those in the DAG.

The tests without select are based on our current DAGCombiner 
optimizations for select-of-constants.

[PowerPC] add tests for bit hacking opportunities with setcc; NFC

We likely gave up on folding some select-of-constants patterns in 
IR with rL331486, and we need to recover those in the DAG.

The tests without select are based on our current DAGCombiner 
optimizations for select-of-constants.