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LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll schedule-x86_32.ll

[X86] Add INT/INTO schedule tests

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add IN/OUT schedule tests

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add IDIV schedule tests

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add CMPXCHG schedule tests

LLVM — llvm/trunk/test/CodeGen/X86 clzero-schedule.ll

[X86] Add CLZERO schedule test

LLVM — llvm/trunk/lib/Transforms/Instrumentation MemorySanitizer.cpp

[MSan] Hotfix compilation

For some reason the override directives got removed in r320373.
I suspect this to be an unwanted effect of clang-format.

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add ADCX/ADOX/XADD/XLAT schedule tests

LLVM — llvm/trunk/test/CodeGen/X86 nontemporal.ll avx2-nontemporal.ll

[X86] Modify Nontemporal tests to avoid deadstore optimization.

LLVM — llvm/trunk/docs AMDGPUUsage.rst

[AMDGPU] Rename Bonaire target to be gfx704; update target feature handling

- Rename Bonaire target to be gfx704.
- Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code.
- List target features supported by each processor in the processor table together with 
the default value.
- Add xnack flag to e_flags.
- Remove xnack from kernel metadata and kernel descriptor since it is now a whole code 
object property.

Differential Revision: https://reviews.llvm.org/D40051
Delta File
+143 -138 llvm/trunk/docs/AMDGPUUsage.rst
+143 -138 1 file

LLVM — lldb/trunk/packages/Python/lldbsuite/test lldbinline.py

dotest.py: Correctly annotate lldbinline tests with debug info categories

This enables one to run all dwo tests with dotest.py --category dwo, or
skip them with --skip-category.

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add SETCC/STC/STD/UD2 schedule tests

LLVM — llvm/trunk/lib/Target/AMDGPU SIRegisterInfo.td SIDefines.h, llvm/trunk/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp

[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma

See bugs 35494 and 35559:
https://bugs.llvm.org/show_bug.cgi?id=35494
https://bugs.llvm.org/show_bug.cgi?id=35559

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41007

LLVM — llvm/trunk/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/trunk/test/CodeGen/X86 combine-mul.ll

[DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)
  
At first, I tried to thread the x86 needle and use a target hook 
(isVectorShiftByScalarCheap())
to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only 
some
element types, but...it's difficult.

Here we just avoid the loop with the x86 vector transform that conflicts with the general 
DAG
combine and preserve all of the existing behavior AFAICT otherwise.

Some tests that will probably fail if someone does try to restrict this in a more targeted 
way
for x86-only may be found in:

test/CodeGen/X86/combine-mul.ll
test/CodeGen/X86/vector-mul.ll
test/CodeGen/X86/widen_arith-5.ll

This should prevent the infinite looping seen with:
https://bugs.llvm.org/show_bug.cgi?id=35579

Differential Revision: https://reviews.llvm.org/D41040

LLVM — llvm/trunk/lib/Transforms/Instrumentation MemorySanitizer.cpp

[MSan] introduce getShadowOriginPtr(). NFC.

This patch introduces getShadowOriginPtr(), a method that obtains both the shadow and 
origin pointers for an address as a Value pair.
The existing callers of getShadowPtr() and getOriginPtr() are updated to use 
getShadowOriginPtr().

The rationale for this change is to simplify KMSAN instrumentation implementation.
In KMSAN origins tracking is always enabled, and there's no direct mapping between the app 
memory and the shadow/origin pages.
Both the shadow and the origin pointer for a given address are obtained by calling a 
single runtime hook from the instrumentation,
therefore it's easier to work with those pointers together.

Reviewed at https://reviews.llvm.org/D40835.

LLVM — lld/trunk/test/ELF aarch64-cortex-a53-843419-address.s

[ELF] Improve comments in aarch64 errata fix test [NFC]

Comment improvements split out from review D36749. No changes to any non
comment line.

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add SAR/SHL/SHR schedule tests

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add RCL/RCR schedule tests

LLVM — llvm/trunk/lib/Target/Hexagon HexagonISelLoweringHVX.cpp, llvm/trunk/test/CodeGen/Hexagon/autohvx lower-insert-elt.ll

[Hexagon] Crash in instruction selection for insert_vector_elt for HVX

A wrong type was passed to insertVector, causing an out-of-bounds value
to be added an an operand to HexagonISD::INSERT. This later failed in
instruction selection.

LLVM — llvm/trunk/lib/Target/PowerPC PPCISelLowering.cpp, llvm/trunk/test/CodeGen/PowerPC testComparesigeui.ll testComparesllgeui.ll

[PowerPC] Sign-extend negative constant stores

Second part of https://reviews.llvm.org/D40348.
Revision r318436 has extended all constants feeding a store to 64 bits
to allow for CSE on the SDAG. However, negative constants were zero extended
which made the constant being loaded appear to be a positive value larger than
16 bits. This resulted in long sequences to materialize such constants
rather than simply a "load immediate". This patch just sign-extends those
updated constants so that they remain 16-bit signed immediates if they started
out that way.

LLVM — lldb/trunk/include/lldb/Interpreter Args.h, lldb/trunk/include/lldb/Utility StringList.h

Add a StringList constructor to Args class

Host::GetEnvironment returns a StringList, but the interface for
launching a process takes Args. The fact that we use two classes for
representing an environment is not ideal, but for now we should at least
have an easy way to convert between the two.

LLVM — llvm/trunk/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[DAGCombiner] Add combined indexed load to the work list

This commit is the first part of https://reviews.llvm.org/D40348.
In order to allow target combines to be performed on newly combined
indexed loads, add them back to the worklist. The remainder of the
above patch will be committed in subsequent revisions and will use
this. Test cases will be included with those follow-up commits.

LLVM — libcxx/trunk/include iterator, libcxx/trunk/test/std/iterators/stream.iterators/istream.iterator/istream.iterator.ops equal.pass.cpp

[libcxx] Define istream_iterator equality comparison operators out-of-line

Currently libc++ defines operator== and operator!= as friend functions in the
definition of the istream_iterator class template. Such definition has a subtle
difference from an out-of-line definition required by the C++ Standard: these
functions can only be found by argument-dependent lookup, but not by qualified
lookup.

This patch changes the definition, so that it conforms to the C++ Standard and
adds a check involving qualified lookup to the test suite.

Patch contributed by Mikhail Maltsev.

Differential Revision: https://reviews.llvm.org/D40415

LLVM — llvm/trunk/test/CodeGen/ARM/GlobalISel arm-instruction-select-combos.mir

[ARM GlobalISel] Add test for a MOVTi16 pattern. NFC

Add test for matching an OR with 0xFFFF0000 to a MOVTi16.

LLVM — llvm/trunk/test/CodeGen/X86 fsgsbase-schedule.ll schedule-x86_64.ll

[X86] Add fsgsbase schedule tests.

LLVM — llvm/trunk/include/llvm/CodeGen CallingConvLower.h, llvm/trunk/lib/Target/RISCV RISCVISelLowering.cpp RISCVCallingConv.td

[RISCV] Add custom CC_RISCV calling convention and improved call support

The TableGen-based calling convention definitions are inflexible, while
writing a function to implement the calling convention is very
straight-forward, and allows difficult cases to be handled more easily. With
this patch adds support for:
* Passing large scalars according to the RV32I calling convention
* Byval arguments
* Passing values on the stack when the argument registers are exhausted

The custom CC_RISCV calling convention is also used for returns.

This patch also documents the ABI lowering that a language frontend is 
expected to perform. I would like to work to simplify these requirements over 
time, but this will require further discussion within the LLVM community.

We add PendingArgFlags CCState, as a companion to PendingLocs.

The PendingLocs vector is used by a number of backends to handle arguments 
that are split during legalisation. However CCValAssign doesn't keep track of 
the original argument alignment. Therefore, add a PendingArgFlags vector which 
can be used to keep track of the ISD::ArgFlagsTy for every value added to 
PendingLocs.

Differential Revision: https://reviews.llvm.org/D39898

LLVM — llvm/trunk/lib/Target/RISCV RISCVISelLowering.cpp, llvm/trunk/test/CodeGen/RISCV alloca.ll

[RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore

LLVM — llvm/trunk/lib/Target/RISCV RISCVFrameLowering.cpp RISCVFrameLowering.h, llvm/trunk/test/CodeGen/RISCV sext-zext-trunc.ll bswap-ctlz-cttz-ctpop.ll

[RISCV] Implement prolog and epilog insertion

As frame pointer elimination isn't implemented until a later patch and we make 
extensive use of update_llc_test_checks.py, this changes touches a lot of the 
RISC-V tests.

Differential Revision: https://reviews.llvm.org/D39849

LLVM — llvm/trunk/test/CodeGen/X86 fsgsbase.ll

[X86] Regenerate fsgsbase intrinsic tests. NFCI.

LLVM — llvm/trunk/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/trunk/lib/Target/ARM ARMISelLowering.cpp ARMISelLowering.h

[ARM] Use ADDCARRY / SUBCARRY

This is a preparatory step for D34515.

This change:
 - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
 - lowering is done by first converting the boolean value into the carry flag
   using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
   using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
   operations does the actual addition.
 - for subtraction, given that ISD::SUBCARRY second result is actually a
   borrow, we need to invert the value of the second operand and result before
   and after using ARMISD::SUBE. We need to invert the carry result of
   ARMISD::SUBE to preserve the semantics.
 - given that the generic combiner may lower ISD::ADDCARRY and
   ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
   as well otherwise i64 operations now would require branches. This implies
   updating the corresponding test for unsigned.
 - add new combiner to remove the redundant conversions from/to carry flags
   to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
 - fixes PR34045
 - fixes PR34564
 - fixes PR35103

Differential Revision: https://reviews.llvm.org/D35192

LLVM — cfe/trunk/lib/Basic/Targets Mips.cpp

[mips] Minor update to the comment (NFC)

LLVM — llvm/trunk/include/llvm/CodeGen SelectionDAGISel.h, llvm/trunk/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

[RISCV] Support lowering FrameIndex

Introduces the AddrFI "addressing mode", which is necessary simply because 
it's not possible to write a pattern that directly matches a frameindex.

Ensure callee-saved registers are accessed relative to the stackpointer. This
is necessary as callee-saved register spills are performed before the frame
pointer is set.

Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can 
make use of it in the RISC-V backend.

Differential Revision: https://reviews.llvm.org/D39848

LLVM — llvm/trunk/test/CodeGen/ARM/GlobalISel arm-instruction-select-combos.mir

[ARM GlobalISel] Add tests for PKHBT and PKHTB

Test (some of) the patterns for selecting PKHBT and PKHTB. The others
are just very similar to the ones we're testing and there would be
little value in covering them as well.

LLVM — cfe/trunk/include/clang/Basic DiagnosticCommonKinds.td, cfe/trunk/lib/Basic/Targets Mips.cpp

[mips] Removal of microMIPS64R6

microMIPS64R6 is removed from backend, and therefore frontend
will show an error when target is microMIPS64R6.

This is Clang part of patch.

Differential Revision: https://reviews.llvm.org/D35624

LLVM — llvm/trunk/lib/Target/Mips MicroMips64r6InstrInfo.td MicroMips64r6InstrFormats.td, llvm/trunk/lib/Target/Mips/AsmParser MipsAsmParser.cpp

[mips] Removal of microMIPS64R6

All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.

This is LLVM part of patch.

Differential Revision: https://reviews.llvm.org/D35625

LLVM — lldb/trunk/source/Plugins/Platform/MacOSX PlatformiOSSimulatorCoreSimulatorSupport.mm

Fix osx build broken in r320346

LLVM — llvm/trunk/lib/Target/AVR/MCTargetDesc AVRAsmBackend.cpp AVRMCExpr.cpp, llvm/trunk/test/MC/AVR relocations.s symbol_relocation.s

[AVR] Implement some missing code paths

This has been broken since r320009.

LLVM — llvm/trunk/lib/Target/AVR/MCTargetDesc AVRMCExpr.cpp

[AVR] Fix incorrectly-calculated AVRMCExpr evaluations

This has been broken since r320009.

LLVM — lldb/trunk/include/lldb/Host PseudoTerminal.h, lldb/trunk/include/lldb/Target ProcessLaunchInfo.h

Move PseudoTerminal to the lldb_private namespace

lldb_utility doesn't make sense, as it is no longer even living in the
"utility" module.

LLVM — lldb/trunk/source/Host/common MainLoop.cpp, lldb/trunk/unittests/Host MainLoopTest.cpp

MainLoop: avoid infinite loop when pty slave gets closed

Summary:
For ptys (at least on Linux), the end-of-file (closing of the slave FD)
is signalled by the POLLHUP flag. We were ignoring this flag, which
meant that when this happened, we would spin in a loop, continuously
calling poll(2) and not making any progress.

This makes sure we treat POLLHUP as a read event (reading will return
0), and we call the registered callback when it happens. This is the
behavior our clients expect (and is consistent with how select(2)
works).

Reviewers: eugene, beanz

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D41008

LLVM — llvm/trunk/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/trunk/test/CodeGen/X86 pr34855.ll

[DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.

We should probably also fold (mulhs/u X, 1) for vectors, but that's harder.

LLVM — llvm/trunk/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFC

LLVM — llvm/trunk/test/CodeGen/X86 scalar_widen_div.ll

[X86] Regenerate test with update_llc_test_checks.py

LLVM — lldb/trunk/source/Utility DataEncoder.cpp

Revert "[DataEncoder] Replace buggy versions of write functions."

The commit exposes a bunch of failures in the LLDB testsuite that
I need to analyze more carefully. Reverting for now.

LLVM — llvm/trunk/test/CodeGen/X86 masked_gather_scatter.ll

[X86] Add a test case for masked scatter where the index needs to be legalized from v2i32 
while other types are legal.

LLVM — lld/trunk/test/ELF icf9.s

Fix test to test what it intended to test.

The test was added to test that we don't merge read only data
sections, but the sections in the test were rw.
Delta File
+7 -4 lld/trunk/test/ELF/icf9.s
+7 -4 1 file

LLVM — lldb/trunk/source/Plugins/StructuredData/DarwinLog StructuredDataDarwinLog.cpp

[DarwinLog] Remove other dead code. Found while reading this file.

LLVM — lldb/trunk/source/Plugins/Process/Darwin MachException.cpp

[MachException] Garbage collect unused and dead code.

LLVM — lldb/trunk/source/Utility DataEncoder.cpp

[DataEncoder] Replace buggy versions of write functions.

They cause an ubsan error when ran through the testsuite (store
to misaligned address is UB). This commit kills two birds with
one stone, as we also remove some code while fixing it.

<rdar://problem/35941757>

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add ROL/ROR schedule tests

LLVM — llvm/trunk/test/CodeGen/X86 schedule-x86_64.ll

[X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule tests