LLVM/project b43293allvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AMDGPU extract-insert-i8.ll

VectorCombine: Improve the insert/extract fold in the narrowing case

Keeping the extracted element in a natural position in the narrowed
vector has two beneficial effects:

1. It makes the narrowing shuffles cheaper (at least on AMDGPU), which
   allows the insert/extract fold to trigger.
2. It makes the narrowing shuffles in a chain of extract/insert
   compatible, which allows foldLengthChangingShuffles to successfully
   recognize a chain that can be folded.

There are minor X86 test changes that look reasonable to me. The IR
change for AVX2 in llvm/test/Transforms/VectorCombine/X86/extract-insert-poison.ll
doesn't change the assembly generated by `llc -mtriple=x86_64-- -mattr=AVX2`
at all.

commit-id:c151bb04
DeltaFile
+6-16llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+2-15llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
+8-4llvm/test/Transforms/VectorCombine/X86/extract-insert-poison.ll
+4-4llvm/test/Transforms/VectorCombine/X86/extract-insert.ll
+2-2llvm/test/Transforms/VectorCombine/X86/pr126085.ll
+22-415 files

LLVM/project aaee5f6llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AMDGPU extract-insert-i8.ll

VectorCombine: Fold chains of shuffles fed by length-changing shuffles

Such chains can arise from folding insert/extract chains.

commit-id:a960175d
DeltaFile
+168-0llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+8-33llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
+176-332 files

LLVM/project aa6362bllvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU shufflevector.ll

AMDGPU: Improve getShuffleCost accuracy for 8- and 16-bit shuffles

These shuffles can always be implemented using v_perm_b32, and so this
rewrites the analysis from the perspective of "how many v_perm_b32s does
it take to assemble each register of the result?"

The test changes in Transforms/SLPVectorizer/reduction.ll are
reasonable: VI (gfx8) has native f16 math, but not packed math.

commit-id:8b76e888
DeltaFile
+498-488llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll
+111-34llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+107-20llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
+33-64llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
+17-34llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
+1-31llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll
+767-6716 files

LLVM/project c3fdba0clang/include/clang/Basic Builtins.def, clang/lib/AST ASTContext.cpp

[AMDGPU] Removal of language sensitive option for _Float16 and half( 'e') handling (#168037)

Removing the 'e' handling for the amdgcn builtins as we decided to use
_Float16 for both HIP/C++ and OpenCL
DeltaFile
+2-6clang/lib/AST/ASTContext.cpp
+0-1clang/include/clang/Basic/Builtins.def
+2-72 files

LLVM/project d406c2cllvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel irtranslator-amdgpu_kernel.ll regbankselect-widen-scalar-loads.mir

AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads

This isn't quite a constant pool, but probably close enough for this
purpose. We just need some known invariant value address. The aliasing
queries against the real kernarg base pointer will falsely report
no aliasing, but for invariant memory it probably doesn't matter.
DeltaFile
+216-216llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
+76-76llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
+73-73llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+22-9llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+20-7llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
+415-3894 files not shown
+433-39110 files

LLVM/project 4be9e5bllvm/lib/Target/AMDGPU SIISelLowering.cpp

AMDGPU: Handle invariant when lowering global loads

Global with invariant should be treated identically to
constant.
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-11 files

LLVM/project a8b806cllvm/test/CodeGen/AMDGPU load-global-invariant.ll

AMDGPU: Add baseline test for split/widen invariant loads
DeltaFile
+77-0llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
+77-01 files

LLVM/project 3954df9llvm/test/CodeGen/AMDGPU constant-address-space-32bit.ll

AMDGPU: Convert constant-address-space-32bit test to generated checks (#168975)

DeltaFile
+824-144llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
+824-1441 files

LLVM/project 06eac9flldb/include/lldb/Core SourceManager.h, lldb/include/lldb/Symbol CompileUnit.h

[lldb] Eliminate SupportFileSP nullptr derefs (#168624)

This patch fixes and eliminates the possibility of SupportFileSP ever
being nullptr. The support file was originally treated like a value
type, but became a polymorphic type and therefore has to be stored and
passed around as a pointer.

To avoid having all the callers check the validity of the pointer, I
introduced the invariant that SupportFileSP is never null and always
default constructed. However, without enforcement at the type level,
that's fragile and indeed, we already identified two crashes where
someone accidentally broke that invariant.

This PR introduces a NonNullSharedPtr to prevent that. NonNullSharedPtr
is a smart pointer wrapper around std::shared_ptr that guarantees the
pointer is never null. If default-constructed, it creates a
default-constructed instance of the contained type. Note that I'm using
private inheritance because you shouldn't inherit from standard library
classes due to the lack of virtual destructor. So while the new

    [4 lines not shown]
DeltaFile
+40-41lldb/source/Core/SourceManager.cpp
+80-0lldb/include/lldb/Utility/NonNullSharedPtr.h
+20-20lldb/include/lldb/Core/SourceManager.h
+6-6lldb/include/lldb/Symbol/CompileUnit.h
+5-7lldb/source/Utility/FileSpecList.cpp
+6-4lldb/unittests/Symbol/LineTableTest.cpp
+157-7816 files not shown
+184-10222 files

FreeBSD/ports 114cb6beditors/vscode distinfo pkg-plist

editors/vscode: Update to 1.106.2

Changelog: https://code.visualstudio.com/updates/v1_106

Reported by:    GitHub (watch releases)
DeltaFile
+7-7editors/vscode/distinfo
+5-1editors/vscode/pkg-plist
+2-2editors/vscode/Makefile
+14-103 files

LLVM/project ac55d78llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU twoaddr-wmma.mir

AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)

We previously got a duplicate implicit $exec operand. It didn't really
hurt anything (other than being a slight drag on compile-time
performance). Still, let's keep things clean.
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
+2-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+14-142 files

LLVM/project 754ff45llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

AMDGPU: Try to use zext to implement constant-32-bit addrspacecast

If the high bits are assumed 0 for the cast, use zext. Previously
we would emit a build_vector and a bitcast with the high element
as 0. The zext is more easily optimized. I'm less convinced this is
good for globalisel, since you still need to have the inttoptr back
to the original pointer type.

The default value is 0, though I'm not sure if this is meaningful
in the real world. The real uses might always override the high
bit value with the attribute.
DeltaFile
+24-24llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
+18-18llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
+18-9llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+8-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+90-752 files not shown
+95-778 files

FreeBSD/poudriere 27779dbsrc/man poudriere-jail.8, src/share/poudriere jail.sh common.sh

Merge pull request #1290 from dag-erling/des/pkgbase

Allow creation of pkgbase jails from official repo
DeltaFile
+21-6src/share/poudriere/jail.sh
+10-2src/man/poudriere-jail.8
+5-3src/share/poudriere/common.sh
+36-113 files

LLVM/project 5946d5bllvm/test/CodeGen/AMDGPU constant-address-space-32bit.ll

AMDGPU: Add more tests for 32-bit constant address space

The sub-dword cases just assert now, so comment those out.
DeltaFile
+1,560-19llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
+1,560-191 files

LLVM/project 03d77aellvm/test/CodeGen/AMDGPU constant-address-space-32bit.ll

AMDGPU: Convert constant-address-space-32bit test to generated checks
DeltaFile
+824-144llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
+824-1441 files

LLVM/project 418204dcompiler-rt/lib/ubsan_minimal ubsan_minimal_handlers.cpp, compiler-rt/test/ubsan_minimal/TestCases test-darwin-interface.c

Revert "[UBSan] [compiler-rt] add preservecc variants of handlers" (#168973)

Reverts llvm/llvm-project#168643
DeltaFile
+0-19compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+0-1compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
+0-202 files

FreeBSD/src 4579378sys/conf newvers.sh

15.0: Update to RC3

Approved by:    re (implicit)
DeltaFile
+1-1sys/conf/newvers.sh
+1-11 files

XigmaNAS/svn 10596trunk/boot loader_simp.efi loader_lua.efi

Make boot files executable
DeltaFile
+0-0trunk/boot/loader_simp.efi
+0-0trunk/boot/loader_lua.efi
+0-0trunk/boot/loader_4th.efi
+0-0trunk/boot/loader.efi
+0-04 files

XigmaNAS/svn 10595trunk/boot loader.efi loader_4th.efi

Re-add new boot files(RELEASE-P5)
DeltaFile
+0-0trunk/boot/loader.efi
+0-0trunk/boot/loader_4th.efi
+0-0trunk/boot/efiboot.img
+0-0trunk/boot/loader_lua.efi
+0-0trunk/boot/loader_simp.efi
+0-05 files

FreeNAS/freenas 06b9db0src/middlewared/middlewared/plugins/iscsi_ scst.py

NAS-138637 / 25.10.1 / Fix some locations where failed to call sanitize_extent (by bmeagherix) (#17672)

DeltaFile
+6-4src/middlewared/middlewared/plugins/iscsi_/scst.py
+6-41 files

XigmaNAS/svn 10594trunk/boot loader_4th.efi efiboot.img

Remove boot files before re-add
DeltaFile
+0-0trunk/boot/loader_4th.efi
+0-0trunk/boot/efiboot.img
+0-0trunk/boot/loader.efi
+0-0trunk/boot/loader_lua.efi
+0-0trunk/boot/loader_simp.efi
+0-05 files

LLVM/project 627d5a5clang-tools-extra/clang-doc/assets class-template.mustache namespace-template.mustache, clang-tools-extra/test/clang-doc mustache-index.cpp

[clang-doc] `<ul>` must be nested in `<li>`

The HTML spec states that only `<li>` can be children of `<ul>`. Nested
`<ul>` tags in an unordered list must be children of `<li>`.
DeltaFile
+50-38clang-tools-extra/clang-doc/assets/class-template.mustache
+18-14clang-tools-extra/clang-doc/assets/namespace-template.mustache
+12-10clang-tools-extra/test/clang-doc/mustache-index.cpp
+80-623 files

LLVM/project 2a1852cllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-dwarfdump/X86 simplified-template-names.s

rebase

Created using spr 1.3.7
DeltaFile
+32,115-36,519llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,064-9,431llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+7,387-7,087llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+6,665-6,661llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+5,202-5,039llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+4,588-5,355llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+66,021-70,0922,753 files not shown
+197,908-154,9292,759 files

LLVM/project f04c80fllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-dwarfdump/X86 simplified-template-names.s

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+32,115-36,519llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,064-9,431llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+7,387-7,087llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+6,665-6,661llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+5,202-5,039llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+4,588-5,355llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+66,021-70,0922,753 files not shown
+197,908-154,9292,759 files

LLVM/project 33f6e6ellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-dwarfdump/X86 simplified-template-names.s

rebase

Created using spr 1.3.7
DeltaFile
+32,115-36,519llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,064-9,431llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+7,387-7,087llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+6,665-6,661llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+5,202-5,039llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+4,588-5,355llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+66,021-70,0922,753 files not shown
+197,908-154,9292,759 files

LLVM/project da1d824llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-dwarfdump/X86 simplified-template-names.s

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+32,115-36,519llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,064-9,431llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+7,387-7,087llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+6,665-6,661llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+5,202-5,039llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+4,588-5,355llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+66,021-70,0922,753 files not shown
+197,908-154,9292,759 files

FreeNAS/freenas 7130f7dsrc/middlewared/middlewared/api/v25_10_1 static_route.py, src/middlewared/middlewared/api/v26_04_0 static_route.py

NAS-138635 / 26.04 / Update static routes validation to support auditing. (by mgrimesix) (#17670)

### A forward port with fixup
This is preparation for adding auditing support for static route CRUD.

The static route API uses pydantic IP address types which, when included
in auditing, generate JSON serialization errors.

The fix is to use strings in the pydantic API and add the validation to
the static route CRUD handlers.

---------------------------------
**This has been manually tested with `test_staticroutes.py` CI test on a
halfmoon VM updated with this branch.**

Original PR: https://github.com/truenas/middleware/pull/17669

---------

Co-authored-by: Mark Grimes <mark.grimes at ixsystems.com>
DeltaFile
+23-8src/middlewared/middlewared/plugins/network_/static_routes.py
+0-6src/middlewared/middlewared/api/v25_10_1/static_route.py
+0-6src/middlewared/middlewared/api/v26_04_0/static_route.py
+23-203 files

LLVM/project 49e46a5compiler-rt/lib/ubsan_minimal ubsan_minimal_handlers.cpp, compiler-rt/test/ubsan_minimal/TestCases test-darwin-interface.c

[UBSan] [compiler-rt] add preservecc variants of handlers (#168643)

DeltaFile
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+1-0compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
+20-02 files

FreeNAS/freenas 333cb15src/middlewared/middlewared/plugins/iscsi_ scst.py

NAS-138637 / 26.04 / Fix some locations where failed to call sanitize_extent (#17671)

(cherry picked from commit 6b34a478c741b875ae067757ef63718e20ee3df5)
DeltaFile
+6-4src/middlewared/middlewared/plugins/iscsi_/scst.py
+6-41 files

LLVM/project ec9be2dllvm/lib/Passes PassBuilder.cpp, llvm/test/Instrumentation/BoundsChecking runtimes.ll

moire test

Created using spr 1.3.7
DeltaFile
+3-6llvm/lib/Passes/PassBuilder.cpp
+6-1llvm/test/Instrumentation/BoundsChecking/runtimes.ll
+9-72 files