e1000: Report corrected I350 ECC errors
I350 does not interrupt for corrected internal ECC errors. Instead,
the PCIe, DMA, packet buffer, loopback, and management memories expose
sticky status bits in their region-specific status registers.
Sample those bits with the regular hardware statistics update, preserve
the RX and TX packet buffer ECC enable state while clearing RW1C
indications, and expose counters grouped by memory region. Each counter
records observed indication bits rather than exact error counts because
repeated corrections between samples collapse into one sticky bit.
On an I350 (8086:1521 revision 1), the ECC enables remained set. All
corrected-error status registers remained clear across boot, interface
down/up, three FER recovery resets, and bidirectional line-rate traffic.
The device has no documented corrected error injector. Therefore, the
per-region paths were validated against the register definitions rather
than an injected SRAM error.
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e1000: Recover from I350 memory errors
I350 reports uncorrectable internal memory errors through ICR.FER and
identifies the affected region in PEIND. Depending on the region and
memory, hardware stops transmit, receive, or all PCIe and DMA traffic
until the port is reset and reinitialized.
Enable FER and all regional indication masks. Capture the read-clear
status in the interrupt filter.
Record the fatal PCIe, DMA, and LAN status registers, keep FER masked
while recovery is pending, and expose per-region indication counters.
Use the datasheet required port reset before master disable order for
PCIe parity errors. Reset for PCIe, DMA, and traffic-affecting LAN
errors. Statistics and VF-mailbox parity errors only require their
status to be discarded and cleared; management-memory recovery remains
under firmware control.
Validated on an I350 (8086:1521 revision 1). Three software-set FER
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e1000: Report corrected I210 and I211 ECC errors
I210 and I211 do not interrupt for corrected internal ECC errors.
Instead, the DMA packet-buffer and PCIe memories expose sticky status
bits in PBECCSTS and PCIEECCSTS.
Sample these bits with the regular hardware statistics update, preserve
the I210/I211 PBECCSTS enable state while clearing its RW1C indication,
and expose separate counters for the DMA packet buffer, PCIe transmit
data, and PCIe retry buffer.
The counters represent observed indications rather than exact error
counts because multiple corrections between samples collapse into one
sticky status bit.
Hardware validation used an I210 revision 3. Unlike I225 and I226, the
published I210/I211 register definitions do not expose self-clearing
injectors for these corrected ECC memories. The three counter sysctls
were present and remained zero under line-rate traffic and three fatal
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e1000: Recover from I210 and I211 memory errors
I210 and I211 report uncorrectable internal memory errors through
ICR.FER and identify the affected region in PEIND. Depending on the
region, hardware stops transmit or all PCIe and DMA traffic until the
port is reset and reinitialized.
Enable FER and all regional indication masks. Discard indication state
left by firmware before enabling reactions, capture the read-clear
status in the interrupt filter, and keep the cause masked while recovery
is pending. Report the affected regions and expose per-region
indication counters. Management-only errors remain under firmware
control.
PCIe region parity errors require a different recovery order from the
normal reset path. Assert the port-local CTRL.RST bit, wait at least
3 ms, verify reset completion, disable master requests, clear
PCIEERRSTS, and then enter normal port reinitialization. Do not use the
device-wide CTRL.DEV_RST sequence used by I225 and I226.
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e1000: Report PCH packet buffer ECC statistics
PCH packet buffer ECC status contains read-clear byte counters for
corrected and uncorrected errors. Sample them with the regular
hardware statistics update and account for the snapshot captured by
the fatal error interrupt path.
Expose the counters and the number of reset worthy interrupt
indications under dev.em.N.memory_errors. Keeping the reset counter
separate also preserves evidence when another status reader wins the
read-clear race.
Hardware validation used an I219-LM. Three documented ICS.ECCER
injections advanced fatal_resets from zero to three, exactly once per
reset. corrected_packet_buffer and uncorrected_packet_buffer remained
zero, as expected because ICS does not inject a memory error or alter
PBECCSTS.
MFC after: 2 weeks
Sponsored by: BBOX.io
e1000: Recover from PCH packet buffer ECC errors
PCH LAN controllers beginning with I217 report uncorrectable
packet buffer ECC errors through ICR.ECCER. Descriptor memory errors
stop the MAC and require a reset before traffic can resume.
Enable the interrupt on the PCH generations whose shared code setup
enables packet buffer ECC. Capture the read-clear PBECCSTS value in
the interrupt filter, mask ECCER while recovery is pending, and request
an iflib reset from the admin task. Reenable the cause only after
hardware initialization succeeds.
Hardware validation used an I219-LM and the documented ICS.ECCER bit to
generate the fatal interrupt. This synthesizes the interrupt cause but
does not corrupt packet buffer memory or alter its ECC byte counters.
Three injections in one boot each requested one reset and recovered
traffic without a panic or watchdog. IMS.ECCER and PBECCSTS.ECC_ENABLE
remained set after every reset.
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bsdconfig: add datetime module for live system clock
Provide bsdconfig datetime (menu), date, and time to set the running
system clock via dialog(1)/bsddialog(1) --calendar and --timebox with
mustberoot. Unlike bsdinstall's time helper, this operates on the live
system rather than a CHROOT-staged install target, and calls
adjkerntz(8) after a successful change so the CMOS stays in sync.
Reviewed by: bcr
Differential Revision: https://reviews.freebsd.org/D58487
