powerpc/ddb: Dump more state in `show pcpu`
Add a new CPU-family `show pcpu` handler, cpu_db_show_mdpcpu() to dump
CPU-specific PCPU data. Only Book-E is populated for now, but AIM may
be populated later.
These new field prints: save areas, TLB miss nesting, the new critical
stack pointer. All of them have been very useful for debugging very
esoteric bugs, so make them easier to see from DDB, instead of having to
rummage through hex dumps.
powerpc/pmap(booke): Allocate 64-bit roots from DMAP
When a TLB miss exception occurs the exception handler must walk the
page table from the root. When the root is allocated from KVA the TLB
miss exception may take another exception if the root page(s) aren't in
the TLB.
The 64-bit page table is modeled after the AIM radix page table, with a
64kB root "page", so 16 pages. This makes regular use of UMA
allocations unable to refer back to the DMAP, which itself is mapped in
TLB1. Now we take another page from the radix pmap driver and grab
contiguous pages from the VM system, so that we can simply refer
directly to DMAP and avoid more nested TLB misses. We can still take a
nested miss, though, because the pmap itself may be in KVA, but this
reduces the nesting.
powerpc/pmap(booke): Rework TID reuse
If a pmap is freed and its memory is reused before its TID reference is
taken, then arbitrary memory will be clobbered. Avoid this by never
dereferencing the pmap pointer in the tidbusy array, and instead using
it as a compare sentinel.
powerpc/booke: Reorganize FRAME_LEAVE
There's a small window between when the SRR* registers are restore and
the exception returns, in which a TLB miss exception may be triggered.
Since there are not special SRR* registers for TLB miss exceptions, the
registers from the frame will be ovwritten, and the FRAME_LEAVE block
will effectively be re-entered on exit, leading to a very hard to
diagnose panic or wedge.
Minimize this chance by pushing the SRR* restore to the last possible
moments, caching them in a PCPU save area instead until the end. This
matches what the AIM side already does.
powerpc/booke: Use a dedicated critical exception stack
A critical exception, such as a watchdog, can trigger at any time,
including the middle of a standard exception prologue or epilogue, so
GPRs, including %r1 (the stack pointer) cannot be trusted at all.
Instead, use a private stack pointer for critical interrupts. Each CPU
now has its own critical exception stack, with the boot stack in the
bss.
powerpc/watchdog: Make e500 watchdog action tunable
There are 4 options for e500 watchdog timeout, which may be core- or
even SoC- specific. Add support to tune the behavior via a tunable
(machdep.watchdog_mode). The tunable value is an integer 0-3.
