PR 60412: provide defines for the message files to adapt kernel names
to the various evbmips variants, so the texts can match what the
conditionalized code does.
With lots of help from gson@, thanks!
Enable radeonfb and veritefb by default on EFIKA.
The board can now boot to multi-user with wscons on graphics card.
While here, disable audio, since codec detection is flaky and tends to
cause problems.
Several fixes that help with bringup of non-POSTed Radeon cards.
- Stop preserving sync-disable bits in CRTC_EXT_CNTL
- Unblank path also clears HSYNC_DIS/VSYNC_DIS (for CRTC0)
- Reordered the TMDS transmitter enable after BIOS init
- Skip the FP_SEL_CRTC2 "iBook/XVR-100" restore hack when a BIOS was found
- Program TMDS_PLL_CNTL for internal-TMDS ports
- Skip phantom ports when building the CRTC list (for single-port RV100)
- Pixel clock ungating where appropriate
Tested on RV100 and RV280 with RADEONFB_BIOS_INIT.
Ok macallan@.
various updates for new versions.
define NO_I18N for xclock, we don't have uselocale(3) that it demands.
include xorg-pkg-ver.mk in a few places.
xdpyinfo has present support.
Add Rendition Verite V2100/V2200 (PCI/AGP) wsdisplay driver.
The driver supports:
- Fully accelerated console, provided that the user installs microcode
from the Windows driver (v20002d.uc). The driver runs unaccelerated
until root file system is available, or if the microcode is not present.
- Mode setting and DDC.
Redistribution terms of the original microcode are unclear, therefore
it must be obtained seprarately.
At some point in the future, we may just develop an alternative microcode,
since Verite RISC is documented and reverse engineering efforts have
filled the knowledge gaps.
Cause src/lib/libc/get/sysctl.o to depend upon /dev/null
This is ugly in the extreme, unreliable really, and just bad.
Yet it seems to be reasonably effective in causing sysctl.o to
be rebuilt every time libc is being rebuilt (which is an aim).
There surely must be a better way. If someone knows what that is,
and it actually works, please replace this with that better way.
x86: Redo boot-time XSAVE area size ABI check.
Instead of checking each component's offset+size from
size = CPUID[EAX=0x0d,ECX=i].EAX,
offset = CPUID[EAX=0x0d,ECX=i].EBX,
to make sure it fits in the XSAVE_MAX_BYTES implied by the
MINSIGSTKSZ ABI parameter, just check the total _enabled_ XSAVE area
size from
CPUID[EAX=0x0d,ECX=0].EBX,
which is what we use to allocate the XSAVE area in software anyway.
The Intel documentation[1] is not very clear on exactly what
CPUID[EAX=0x0d,ECX=i] reports for i >= 2, saying `valid bit in the
XCR0 register' without distinguishing `supported' from `enabled'
bits, and the AMD documentation I skimmed didn't have these leaves in
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