gicv3: Stop using ICC_PMR_EL1 to mask interrupts.
Managing ICC_PMR_EL1 with spl changes is too costly, even with lazy PMR
updates. Let's simplify things. We can still take advantage of interrupt
prioritization for delivery but let's do spl filtering in software.
On Ampere eMAG, iperf3 on the loopback interface sees a ~18% performance
improvement with this change.
arm: optimize splx
Skip masking / unmasking interrupts and pic_do_pending_interrupts if
there is another pic_do_pending_interrupts in progress or if there are
no pending unmasked IPLs on the CPU.
arm: Make __HAVE_PIC_PENDING_INTRS state per-CPU.
Move pic_pending_irqs / pic_blocked_irqs / pic_pending_ipls from per-PIC
to per-PIC-per-CPU state. This allows us to defer processor-local
interrupts like SGIs and PPIs that use the same irq number.
mi pmap: Rename two functions for clarity of purpose
tlbinfo_asids_p -> tlbinfo_hasasids_p
This functions indicates if ASIDs are implemented
tlbinfo_noasids_p -> tlbinfo_freeasids_p
The new function indicates if there are free ASIDS in the pool (the
inversion of the previous function)
s/A_BCM1480_SWTRC_MATCH_TAG_MAKS_0/A_BCM1480_SWTRC_MATCH_TAG_MASK_0/ in macro
constant definition.
It is later used with correct name in A_BCM1480_SWTRC_MATCH_TAG_MASK macro.
rdcpcib(4): fix rdcpcib attach/detach handling for function 0 and function 1.
Only function 0 exposes the indirect access registers and the watchdog timer.
Function 1 has a separate register set and does not use these registers.
This resolves the autoconfiguration error seen in boot dmesg:
"rdcpcib1: autoconfiguration error: couldn't map indirect registers"
Attach now maps the indirect access registers and configures the watchdog only
for function 0, and detach only releases resources that were initialized.
reviewed by riastradh@, thanks!
Fill in bus_dmamap_sync() for 68030. Since 68030 caches are write-through,
this is pretty trivial: just invalidate the on-chip + any external D cache
in the PREREAD case. (See comment in code for why PREREAD is preferred
over POSTREAD.)
PR kern/60144
uvm_swap.c: fix /dev/drum regression caused by swap encryption
* decrypt data using a bounce buffer
* reject writes with ENOTSUP for now
https://gnats.netbsd.org/60083
PR/60083
swread/swwrite: hold swap_syscall_lock (cont.)
fix a harmless merge botch i introduced while porting the patch
from git to cvs.
https://gnats.netbsd.org/60147
PR/60147
sw_reg_strategy: do not clobber b_private
this fixes a regression caused by "uvm_swap.c: make the drum mpsafe".
b_private is for the owner of the buffer.
in case of /dev/drum i/o, we are not the owner of the buffer.
kern_physio.c is.
Add b_private2 to struct buf
i plan to use this for swap i/o.
i'm not bumping kernel version as i reused an unused field.
(it used to be softdep b_dep and has been unused since 2009.)
swstrategy: reject non page aligned i/o explicitly
our swap offset calculation logic assumes page aligned i/o.
non aligned requests from /dev/drum silently go to a wrong block.
it has always been this way since the initial uvm import in 1998.
this commit fixes it by simply rejecting non aligned requests.
note: requests from swap and libkvm are always page aligned.
swread/swwrite: hold swap_syscall_lock
to ensure that the list of swap devices is stable
while we are operating on them.
https://gnats.netbsd.org/60147
libkvm _kvm_ureadm: fix an integer overflow
this has been broken since the initial uvm supporT in 1998.
I suppose it was rare to use >2GB swap in that era.
