various updates for new versions.
define NO_I18N for xclock, we don't have uselocale(3) that it demands.
include xorg-pkg-ver.mk in a few places.
xdpyinfo has present support.
Add Rendition Verite V2100/V2200 (PCI/AGP) wsdisplay driver.
The driver supports:
- Fully accelerated console, provided that the user installs microcode
from the Windows driver (v20002d.uc). The driver runs unaccelerated
until root file system is available, or if the microcode is not present.
- Mode setting and DDC.
Redistribution terms of the original microcode are unclear, therefore
it must be obtained seprarately.
At some point in the future, we may just develop an alternative microcode,
since Verite RISC is documented and reverse engineering efforts have
filled the knowledge gaps.
Cause src/lib/libc/get/sysctl.o to depend upon /dev/null
This is ugly in the extreme, unreliable really, and just bad.
Yet it seems to be reasonably effective in causing sysctl.o to
be rebuilt every time libc is being rebuilt (which is an aim).
There surely must be a better way. If someone knows what that is,
and it actually works, please replace this with that better way.
x86: Redo boot-time XSAVE area size ABI check.
Instead of checking each component's offset+size from
size = CPUID[EAX=0x0d,ECX=i].EAX,
offset = CPUID[EAX=0x0d,ECX=i].EBX,
to make sure it fits in the XSAVE_MAX_BYTES implied by the
MINSIGSTKSZ ABI parameter, just check the total _enabled_ XSAVE area
size from
CPUID[EAX=0x0d,ECX=0].EBX,
which is what we use to allocate the XSAVE area in software anyway.
The Intel documentation[1] is not very clear on exactly what
CPUID[EAX=0x0d,ECX=i] reports for i >= 2, saying `valid bit in the
XCR0 register' without distinguishing `supported' from `enabled'
bits, and the AMD documentation I skimmed didn't have these leaves in
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Redo the sysctl user.osrevision (etc) impl method
This is not intended to affect the results, but is a different
method of getting there, without ephemeral generated include files.
It is unlikely that this is the final version, but it seems better
for now (update builds probably don't do what I'd intended for now,
but that's a minor concern - they should still work).
x86: Save and restore all supported extended CPU state on signals.
While here, disable Intel AMX, whose state size (>>8 KiB) exceeds
MINSIGSTKSZ (8 KiB), until we are ready to safely update the ABI for
sigaltstack(2). This isn't a regression: we've never had a release
with Intel AMX support.
Previously, on signal delivery, we would only save and restore at
most what FXSAVE does, which is the x87 and SSE registers that always
exist on amd64.
To save and restore the upper halves of the YMM or ZMM registers
(AVX/AVX2/AVX512), or the AVX512 registers ZMM16..ZMM31, or the
enormous AMX state, we need to do more. And we need to do that even if
the signal handler doesn't use AVX instructions, because an SSE
instruction modifying xmmN (e.g., in a vectorized memcpy) will, as a
side effect, zero the high half of ymmN.
Fortunately, the x86 architecture has an extensible mechanism for
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kqueue(2): Tighten branch in previous change.
If sleepok is true, then kmem_zalloc should never fail, and this
routine is inline with constant arguments at every call site, so
let's let the compiler prune dead branches for the call sites that
can sleep.
PR kern/60436: kqueue(2): random kernel null pointer deref in
EVFILT_PROC NOTE_TRACK
