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   regenerate dtb lists

   sw_reg_strategy: do not clobber b_private

   this fixes a regression caused by "uvm_swap.c: make the drum mpsafe".

   b_private is for the owner of the buffer.
   in case of /dev/drum i/o, we are not the owner of the buffer.
   kern_physio.c is.

   Add b_private2 to struct buf

   i plan to use this for swap i/o.
   i'm not bumping kernel version as i reused an unused field.
   (it used to be softdep b_dep and has been unused since 2009.)

   swstrategy: reject non page aligned i/o explicitly

   our swap offset calculation logic assumes page aligned i/o.
   non aligned requests from /dev/drum silently go to a wrong block.
   it has always been this way since the initial uvm import in 1998.
   this commit fixes it by simply rejecting non aligned requests.
   note: requests from swap and libkvm are always page aligned.

   swread/swwrite: hold swap_syscall_lock

   to ensure that the list of swap devices is stable
   while we are operating on them.

   https://gnats.netbsd.org/60147

   swstrategy: add an assertion

   libkvm _kvm_ureadm: fix an integer overflow

   this has been broken since the initial uvm supporT in 1998.
   I suppose it was rare to use >2GB swap in that era.

   libkvm _kvm_ureadm: fix anon address calculation

   this has been broken since the initial uvm support in 1998.

   libkvm _kvm_ureadm: remove a redundant check

   uvm_swap.c: make the drum mpsafe (cont.)

   mark swapiod WQ_MPSAFE.

   Revert files inadvertently committed in previous.

   Trying again to avoid that 3-second delay on PCI IDE controllers.
   This time, the change is conditionalized so it won't hit old-style wdc.

   back out previous change to wdc.c - broke CF on wdc at obio on landisk

   wiiu: Optimize ahci intr handler.

   The summary interrupt tells us which port the interrupt is for, so we can
   call ahci_intr_port directly (avoiding two extra reads of AHCI_IS).

   Now that oea_dumpsys pauses other CPUs properly, remove the panicstr test.

   powerpc: oea: Pause other CPUs when taking a crash dump.

   evbarm/am18xx: add async-clk clkgate driver

   evbarm/am18xx: choose serial port

   Serial 1 is sensor port 1 on the EV3

   evbarm/am18xx: add pll controller

   evbarm/am18xx: add psc driver

   The PSC is the power and sleep controller.

   evbarm/am18xx: add timer

   evbarm/am18xx: enable interrupt controller in FDT

   evbarm/generic_v5: fix setstatclockrate crash

   setstatclockrate is an optional function for timers that currently cannot be multiplexed through device trees. We don't provide an implementation in the am18 code, but we need to make sure the imx23 driver doesn't crash us.

   evbarm/am18xx: add interrupt controller

   evbarm/am18xx: basic plaform code

   evbarm/am18xx: build lego mindstorms ev3 device tree

   Build cacheops.c if 68020, 68030, 68040, or 68060 is configured.  Adapt
   sun3 to this new reality.

   The 68020 does not have an on-chip data cache, so:
   - Make the comments reflect that.
   - no-op PCIA(), as well, since DC_CLEAR doesn't do anything on a 68020.

   Revert unintended commit.

   We should not be intermingling ATC/TLB and I/D cache operations, but
   for now ensure that the TBI*() functions are only made available for
   Moto and/or HP MMU configurations.

   Decorate all of the legacy pmap_bootstrap1() routines with
   __attribute__((no_instrument_function)) rather than using
   compile-with "${NOPROF_C}".