LLVM/llvm 348986compiler-rt/trunk/lib/hwasan CMakeLists.txt, compiler-rt/trunk/test/hwasan/TestCases cfi.cc

[hwasan] Link ubsan_cxx to shared runtime library.

Summary: This is needed for C++-specific ubsan and cfi error reporting to work.

Reviewers: kcc, vitalybuka

Subscribers: srhines, kubamracek, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D55589

LLVM/llvm 348985llvm/trunk/tools/llvm-objcopy/ELF Object.h

[llvm-objcopy] Change Segment::Type from uint64_t to uint32_t

In both Elf{32,64}_Phdr, the field Elf{32,64}_World p_type is uint32_t.

Also reorder the fields to be similar to Elf64_Phdr (which is different
from Elf32_Phdr but quite similar).

Reviewers: rupprecht, jhenderson, jakehehrlich, alexshap, espindola

Reviewed By: rupprecht

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D55618

LLVM/llvm 348984compiler-rt/trunk/lib/sanitizer_common sanitizer_linux.h

Switch Android from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)

The TLS_SLOT_TSAN slot is available starting in N, but its location (8)
is incompatible with the proposed solution for implementing ELF TLS on
Android (i.e. bump ARM/AArch64 alignment to reserve an 8-word TCB).

Instead, starting in Q, Bionic replaced TLS_SLOT_DLERROR(6) with
TLS_SLOT_SANITIZER(6). Switch compiler-rt to the new slot.

Reviewers: eugenis, srhines, enh

Reviewed By: eugenis

Subscribers: ruiu, srhines, kubamracek, javed.absar, kristof.beyls, delcypher, 
llvm-commits, #sanitizers

Differential Revision: https://reviews.llvm.org/D55581

LLVM/llvm 348983llvm/trunk/lib/Transforms/Instrumentation HWAddressSanitizer.cpp, llvm/trunk/test/Instrumentation/HWAddressSanitizer prologue.ll

[hwasan] Android: Switch from TLS_SLOT_TSAN(8) to TLS_SLOT_SANITIZER(6)

The change is needed to support ELF TLS in Android. See D55581 for the
same change in compiler-rt.

Reviewers: srhines, eugenis

Reviewed By: eugenis

Subscribers: srhines, llvm-commits

Differential Revision: https://reviews.llvm.org/D55592

LLVM/llvm 348982cfe/trunk/lib/CodeGen CGBuiltin.cpp, cfe/trunk/test/CodeGen builtin-cpu-supports.c builtin-cpu-is.c

Revert "Declares __cpu_model as dso local"

This reverts r348978

LLVM/llvm 348981libunwind/trunk/src UnwindCursor.hpp Registers.hpp

Avoid code duplication in the SEH version of UnwindCursor::getRegisterName. NFC.

This requires making Registers_*::getRegisterName static.

Differential Revision: https://reviews.llvm.org/D55610

LLVM/llvm 348980llvm/trunk/test/Transforms/PhaseOrdering rotate.ll

[PhaseOrdering] add test for funnel shift (rotate); NFC

As mentioned in D55604, there are 2 bugs here:
1. The new pass manager is speculating wildly by default.
2. The old pass manager is not converting this to funnel shift.

LLVM/llvm 348979compiler-rt/trunk/lib/hwasan hwasan_linux.cc hwasan.cc

[hwasan] Verify Android TLS slot at startup.

Add a check that TLS_SLOT_TSAN / TLS_SLOT_SANITIZER, whichever
android_get_tls_slot is using, is not conflicting with

Reviewers: rprichard, vitalybuka

Subscribers: srhines, kubamracek, llvm-commits

Differential Revision: https://reviews.llvm.org/D55587

LLVM/llvm 348978cfe/trunk/lib/CodeGen CGBuiltin.cpp, cfe/trunk/test/CodeGen builtin-cpu-supports.c builtin-cpu-is.c

Declares __cpu_model as dso local

__builtin_cpu_supports and __builtin_cpu_is use information in __cpu_model to decide cpu 
features. Before this change, __cpu_model was not declared as dso local. The generated 
code looks up the address in GOT when reading __cpu_model. This makes it impossible to use 
these functions in ifunc, because at that time GOT entries have not been relocated. This 
change makes it dso local.

Differential Revision: https://reviews.llvm.org/D53850

LLVM/llvm 348977cfe/trunk/docs LibASTMatchersReference.html, cfe/trunk/include/clang/AST ExprCXX.h

[AST] Store "UsesADL" information in CallExpr.

Currently the Clang AST doesn't store information about how the callee of a CallExpr was 
found. Specifically if it was found using ADL.

However, this information is invaluable to tooling. Consider a tool which renames usages 
of a function. If the originally CallExpr was formed using ADL, then the tooling may need 
to additionally qualify the replacement.
Without information about how the callee was found, the tooling is left scratching it's 
head. Additionally, we want to be able to match ADL calls as quickly as possible, which 
means avoiding computing the answer on the fly.

This patch changes `CallExpr` to store whether it's callee was found using ADL. It does 
not change the size of any AST nodes.

Reviewers: fowles, rsmith, klimek, shafik

Reviewed By: rsmith

Subscribers: aaron.ballman, riccibruno, calabrese, titus, cfe-commits

Differential Revision: https://reviews.llvm.org/D55534

LLVM/llvm 348976llvm/trunk/include/llvm/CodeGen/GlobalISel GISelChangeObserver.h CombinerHelper.h, llvm/trunk/lib/CodeGen/GlobalISel Legalizer.cpp CombinerHelper.cpp

[globalisel] Rename GISelChangeObserver's erasedInstr() to erasingInstr() and related 
nits. NFC

There's little of interest that can be done to an already-erased instruction.
You can't inspect it, write it to a debug log, etc. It ought to be notification
that we're about to erase it. Rename the function to clarify the timing of the
event and reflect current usage.

Also fixed one case where we were trying to print an erased instruction.

Reviewers: aditya_nandakumar

Reviewed By: aditya_nandakumar

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D55611

LLVM/llvm 348975llvm/trunk/lib/Target/X86 X86ISelDAGToDAG.cpp, llvm/trunk/test/CodeGen/X86 i128-mul.ll pr35636.ll

[X86] Don't emit MULX by default with BMI2

MULX has somewhat improved register allocation constraints compared to the legacy MUL 
instruction. Both output registers are encoded instead of fixed to EAX/EDX, but EDX is 
used as input. It also doesn't touch flags. Unfortunately, the encoding is longer.

Prefering it whenever BMI2 is enabled is probably not optimal. Choosing it should somehow 
be a function of register allocation constraints like converting adds to three address. 
gcc and icc definitely don't pick MULX by default. Not sure what if any rules they have 
for using it.

Differential Revision: https://reviews.llvm.org/D55565

LLVM/llvm 348974llvm/trunk/test/MC/WebAssembly dwarfdump.ll

Fix for llvm-dwarfdump changes for subroutine types

LLVM/llvm 348973libcxx/trunk/test/std/depr/depr.c.headers uchar_h.pass.cpp

[test] [depr.c.headers] XFAIL uchar.h on NetBSD

LLVM/llvm 348972llvm/trunk/test/CodeGen/X86 stack-folding-bmi2.mir stack-folding-bmi2.ll

[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well

A future patch may stop using MULX by default so use MIR to ensure we're always testing 

Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being 
promoted to a 64-bit mul.

LLVM/llvm 348971llvm/trunk/lib/Target/AMDGPU AMDGPUAnnotateKernelFeatures.cpp, llvm/trunk/test/CodeGen/AMDGPU annotate-kernel-features-hsa-call.ll uniform-work-group-recursion-test.ll

[AMDGPU] Support for "uniform-work-group-size" attribute

Updated the annotate-kernel-features pass to support the propagation of uniform-work-group 
attribute from the kernel to the called functions. Once this pass is run, all kernels, 
even the ones which initially did not have the attribute, will be able to indicate weather 
or not they have uniform work group size depending on the value of the attribute. 

Differential Revision: https://reviews.llvm.org/D50200

LLVM/llvm 348970llvm/trunk/include/llvm/Support Threading.h

Support: use internal `call_once` on PPC64le

Use the replacement execute once threading support in LLVM for PPC64le.  It
seems that GCC does not define `__ppc__` and so we would actually call out to
the C++ runtime there which is not what the current code intended.  Check both
`__ppc__` and `__PPC__`.  This avoids the need for checking the endianness.

Thanks to nemanjai for the hint about GCC's behaviour and the fact that the
reviewed condition could be simplified.

Original patch by Sarvesh Tamba!

LLVM/llvm 348969cfe/trunk/lib/CodeGen CodeGenFunction.cpp, cfe/trunk/test/CodeGen builtin-unpredictable.c

Teach __builtin_unpredictable to work through implicit casts.

The __builtin_unpredictable implementation is confused by any implicit
casts, which happen in C++.  This patch strips those off so that
if/switch statements now work with it in C++.

Change-Id: I73c3bf4f1775cd906703880944f4fcdc29fffb0a

LLVM/llvm 348968libcxx/trunk/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions permissions.pass.cpp

[test] [filesystems] NetBSD can do symlink permissions too

LLVM/llvm 348967libcxx/trunk/test/std/input.output/filesystems/fs.op.funcs/fs.op.last_write_time last_write_time.pass.cpp

[test] [filesystems] Extend FreeBSD tv_sec==-1 workaround to NetBSD

NetBSD also uses tv_sec==-1 as error status indicator, and does not
support setting such a value.

LLVM/llvm 348966llvm/trunk/test/CodeGen/X86 copysign-constant-magnitude.ll

[X86] Added missing constant pool checks. NFCI.

So the extra checks in D55600 don't look like a regression.

LLVM/llvm 348965llvm/trunk/lib/DebugInfo/DWARF DWARFDie.cpp, llvm/trunk/test/tools/llvm-dwarfdump/X86 prettyprint_types.s

DebugInfo/DWARF: Pretty print subroutine types

Doesn't handle varargs and other fun things, but it's a start. (also
doesn't print these strictly as valid C++ when it's a pointer to
function, it'll print as "void(int)*" instead of "void (*)(int)")

LLVM/llvm 348964www/trunk/devmtg/2018-10 index.html, www/trunk/devmtg/2018-10/slides Weber-FunnerLLVMDevelopment.pdf

add slides for my lightning talk

LLVM/llvm 348963llvm/trunk/lib/BinaryFormat AMDGPUMetadataVerifier.cpp, llvm/trunk/lib/Target/AMDGPU AMDGPUHSAMetadataStreamer.cpp

[AMDGPU] Emit MessagePack HSA Metadata for v3 code object

Continue to present HSA metadata as YAML in ASM and when output by tools
(e.g. llvm-readobj), but encode it in Messagepack in the code object.

Differential Revision: https://reviews.llvm.org/D48179

LLVM/llvm 348962llvm/trunk/lib/DebugInfo/DWARF DWARFDie.cpp, llvm/trunk/test/tools/llvm-dwarfdump/X86 prettyprint_types.s

DebugInfo/DWARF: Improve dumping of pointers to members ('int foo::*' rather than 'int*')

LLVM/llvm 348961llvm/trunk/lib/DebugInfo/DWARF DWARFDie.cpp

DebugInfo/DWARF: Refactor type dumping to dump types, rather than DIEs that reference 

This lays the foundation for dumping types not referenced by DW_AT_type
attributes (in the near-term, that'll be DW_AT_containing_type for a
DW_TAG_ptr_to_member_type - in the future, potentially dumping the
pretty printed name next to the DW_TAG for the type, rather than only
when the type is referenced from elsewhere)

LLVM/llvm 348960llvm/trunk/include/llvm/DebugInfo/DWARF DWARFDie.h, llvm/trunk/lib/DebugInfo/DWARF DWARFDie.cpp

DebugInfo/DWARF: Refactor getAttributeValueAsReferencedDie to accept a DWARFFormValue

Save searching for the attribute again when you already have the
DWARFFormValue at hand.

LLVM/llvm 348959llvm/trunk/lib/Target/X86 X86InstrCompiler.td X86ISelLowering.cpp, llvm/trunk/test/CodeGen/X86 vector-compare-any_of.ll select.ll

[X86] Emit SBB instead of SETCC_CARRY from LowerSELECT. Break false dependency on the SBB 

I'm hoping we can just replace SETCC_CARRY with SBB. This is another step towards that.

I've explicitly used zero as the input to the setcc to avoid a false dependency that we've 
had with the SETCC_CARRY. I changed one of the patterns that used NEG to instead use an 
explicit compare with 0 on the LHS. We needed the zero anyway to avoid the false 
dependency. The negate would clobber its input register. By using a CMP we can avoid that 
which could be useful.

Differential Revision: https://reviews.llvm.org/D55414

LLVM/llvm 348958llvm/trunk/include/llvm/Transforms/Utils LoopUtils.h

Fix Wdocumentation warning. NFCI.

LLVM/llvm 348957llvm/trunk/lib/IR ConstantFold.cpp, llvm/trunk/test/Transforms/SCCP apint-bigint2.ll

[ConstantFold] Use getMinSignedBits for APInt in isIndexInRangeOfArrayType.

Indices for getelementptr can be signed so we should use
getMinSignedBits instead of getActiveBits here. The function later calls
getSExtValue to get the int64_t value, which also checks

This fixes  https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=11647.

Reviewers: mssimpso, efriedma, davide

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D55536

LLVM/llvm 348956llvm/trunk/test/CodeGen/X86 copysign-constant-magnitude.ll

[X86] Added missing constant pool checks. NFCI.

So the extra checks in D55600 don't look like a regression.

LLVM/llvm 348955lld/trunk/test/wasm debuginfo.test

Update for an llvm-dwarfdump change in output

LLVM/llvm 348954llvm/trunk/lib/DebugInfo/DWARF DWARFDie.cpp, llvm/trunk/test/tools/llvm-dwarfdump/X86 prettyprint_types.s

llvm-dwarfdump: Dump array dimensions in stringified type names

LLVM/llvm 348953llvm/trunk/include/llvm/CodeGen SelectionDAG.h, llvm/trunk/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[SelectionDAG] Add a generic isSplatValue function

This patch introduces a generic function to determine whether a given vector type is known 
to be a splat value for the specified demanded elements, recursing up the DAG looking for 

It also keeps track of the elements that are known to be UNDEF - it returns true if all 
the demanded elements are UNDEF (as this may be useful under some circumstances), so this 
needs to be handled by the caller.

A wrapper variant is also provided that doesn't take the DemandedElts or UndefElts 
arguments for cases where we just want to know if the SDValue is a splat or not 
(with/without UNDEFS).

I had hoped to completely remove the X86 local version of this function, but I'm seeing 
some regressions in shift/rotate codegen that will take a little longer to fix and I hope 
to get this in sooner so I can continue work on PR38243 which needs more capable splat 

Differential Revision: https://reviews.llvm.org/D55426

LLVM/llvm 348952llvm/trunk/lib/Target/NVPTX NVPTXAsmPrinter.cpp NVPTXAsmPrinter.h, llvm/trunk/test/CodeGen/NVPTX nofunc.ll

[NVPTX] do not rely on cached subtarget info.
If a module has function references, but no functions
themselves, we may end up never calling runOnMachineFunction
and therefore would never initialize nvptxSubtarget field
which would eventually cause a crash.

Instead of relying on nvptxSubtarget being initialized by
one of the methods, retrieve subtarget info directly.

Differential Revision: https://reviews.llvm.org/D55580

LLVM/llvm 348951lldb/trunk/source/Plugins/SymbolFile/PDB SymbolFilePDB.cpp

NFC: fix compiler warning about code never being executed when compiling on non windows 

LLVM/llvm 348950cfe/trunk/lib/Analysis CallGraph.cpp, cfe/trunk/test/Analysis debug-CallGraph.cpp

Change CallGraph print to show the fully qualified name

CallGraph previously would just show the normal name of a function,
which gets really confusing when using it on large C++ projects.  This
patch switches the printName call to a printQualifiedName, so that the
namespaces are included.

Change-Id: Ie086d863f6b2251be92109ea1b0946825b28b49a

LLVM/llvm 348949llvm/trunk/include/llvm/Transforms/Vectorize LoopVectorizationLegality.h

[LV] Fix signed/unsigned comparison warning.

LLVM/llvm 348948llvm/trunk/utils/gn/secondary/llvm/lib/Transforms/Scalar BUILD.gn

[gn build] Merge r348944

LLVM/llvm 348947llvm/trunk/docs LangRef.rst

[docs] Use correct ending quotes.

LLVM/llvm 348946llvm/trunk/lib/Target/X86 X86InstrInfo.cpp X86InstrArithmetic.td, llvm/trunk/test/CodeGen/X86 scheduler-backtracking.ll iabs.ll

[x86] allow 8-bit adds to be promoted by convertToThreeAddress() to form LEA

This extends the code that handles 16-bit add promotion to form LEA to also allow 8-bit 
That allows us to combine add ops with register moves and save some instructions. This is 
another step towards allowing add truncation in generic DAGCombiner (see D54640).

Differential Revision: https://reviews.llvm.org/D55494

LLVM/llvm 348945llvm/trunk/utils/gn/secondary/lld/COFF BUILD.gn, llvm/trunk/utils/gn/secondary/lld/Common BUILD.gn

[gn build] Add all non-test build files for lld

Version.inc.in processing has a potentially interesting part which I've punted
on for now (LLD_REVISION and LLD_REPOSITORY are set to empty strings for now).

lld now builds in the gn build. But no symlinks to it are created yet, so it
can't be meaningfully run yet.

Differential Revision: https://reviews.llvm.org/D55593

LLVM/llvm 348944llvm/trunk/docs TransformMetadata.rst LangRef.rst, llvm/trunk/lib/Transforms/Scalar WarnMissedTransforms.cpp

[Unroll/UnrollAndJam/Vectorizer/Distribute] Add followup loop attributes.

When multiple loop transformation are defined in a loop's metadata, their order of 
execution is defined by the order of their respective passes in the pass pipeline. For 
instance, e.g.

    #pragma clang loop unroll_and_jam(enable)
    #pragma clang loop distribute(enable)

is the same as

    #pragma clang loop distribute(enable)
    #pragma clang loop unroll_and_jam(enable)

and will try to loop-distribute before Unroll-And-Jam because the LoopDistribute pass is 
scheduled after UnrollAndJam pass. UnrollAndJamPass only supports one inner loop, i.e. it 
will necessarily fail after loop distribution. It is not possible to specify another 
execution order. Also,t the order of passes in the pipeline is subject to change between 
versions of LLVM, optimization options and which pass manager is used.

This patch adds 'followup' attributes to various loop transformation passes. These 
attributes define which attributes the resulting loop of a transformation should have. For 

    !0 = !{!0, !1, !2}

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LLVM/llvm 348943cfe/trunk/include/clang/Driver Options.td, cfe/trunk/lib/Driver/ToolChains Clang.cpp

[Driver] Add support for -fembed-bitcode for assembly file

Handle -fembed-bitcode for assembly inputs. When the input file is
assembly, write a marker as "__LLVM,__asm" section.

Fix llvm.org/pr39659

Reviewers: compnerd, dexonsmith

Reviewed By: compnerd

Subscribers: rjmccall, dblaikie, jkorous, cfe-commits

Differential Revision: https://reviews.llvm.org/D55525

LLVM/llvm 348942cfe/trunk/include/clang/Analysis CallGraph.h, cfe/trunk/test/Analysis debug-CallGraph.cpp debug-CallGraph.c

Make clang::CallGraph look into template instantiations

Clang's CallGraph analysis doesn't use the RecursiveASTVisitor's setting
togo into template instantiations.  The result is that anything wanting
to do call graph analysis ends up missing any template function calls.

Change-Id: Ib4af44ed59f15d43f37af91622a203146a3c3189

LLVM/llvm 348941lldb/trunk/include/lldb/Symbol ClangASTContext.h, lldb/trunk/source/Plugins/SymbolFile/DWARF DWARFASTParserClang.cpp

[ast] CreateParameterDeclaration should use an appropriate DeclContext.

Previously CreateParameterDeclaration was always using the translation
unit DeclContext.  We would later go and add parameters to the
FunctionDecl, but internally clang makes a copy when you do this, and
we'd end up with ParmVarDecl's at the global scope as well as in the
function scope.

This fixes the issue.  It's hard to say whether this will introduce
a behavioral change in name lookup, but I know there have been several
hacks introduced in previous years to deal with collisions between
various types of variables, so there's a chance that this patch could
obviate one of those hacks.

Differential Revision: https://reviews.llvm.org/D55571

LLVM/llvm 348940llvm/trunk/lib/Analysis ProfileSummaryInfo.cpp, llvm/trunk/test/Transforms/CodeGenPrepare section-samplepgo.ll

[SampleFDO] Extend profile-sample-accurate option to cover isFunctionColdInCallGraph

For SampleFDO, when a callsite doesn't appear in the profile, it will not be marked as 
cold callsite unless the option -profile-sample-accurate is specified.

But profile-sample-accurate doesn't cover function isFunctionColdInCallGraph which is used 
to decide whether a function should be put into text.unlikely section, so even if the user 
knows the profile is accurate and specifies profile-sample-accurate, those functions not 
appearing in the sample profile are still not be put into text.unlikely section right now.

The patch fixes that.

Differential Revision: https://reviews.llvm.org/D55567

LLVM/llvm 348939cfe/trunk/lib/Basic/Targets OSTargets.h, cfe/trunk/test/Preprocessor init.c

Basic: make `int_least64_t` and `int_fast64_t` match on Darwin

The Darwin targets use `int64_t` and `uint64_t` to define the `int_least64_t`
and `int_fast64_t` types.  The underlying type is actually a `long long`.  Match
the types to allow the printf specifiers to work properly and have the compiler
vended macros match the implementation on the target.

LLVM/llvm 348938cfe/trunk/include/clang/Basic DiagnosticASTKinds.td, cfe/trunk/lib/AST ExprConstant.cpp

[ExprConstant] Improve memchr/memcmp for type mismatch and multibyte element types

`memchr` and `memcmp` operate upon the character units of the object
representation; that is, the `size_t` parameter expresses the number of
character units. The constant folding implementation is updated in this
patch to account for multibyte element types in the arrays passed to
`memchr`/`memcmp` and, in the case of `memcmp`, to account for the
possibility that the arrays may have differing element types (even when
they are byte-sized).

Actual inspection of the object representation is not implemented.
Comparisons are done only between elements with the same object size;
that is, `memchr` will fail when inspecting at least one character unit
of a multibyte element. The integer types are assumed to have two's
complement representation with 0 for `false`, 1 for `true`, and no
padding bits.

`memcmp` on multibyte elements will only be able to fold in cases where
enough elements are equal for the answer to be 0.

Various tests are added to guard against incorrect folding for cases
that miscompile on some system or other prior to this patch. At the same
time, the unsigned 32-bit `wchar_t` testing in
`test/SemaCXX/constexpr-string.cpp` is restored.

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LLVM/llvm 348937llvm/trunk/lib/Target/AMDGPU SILoadStoreOptimizer.cpp BUFInstructions.td, llvm/trunk/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Extend the SI Load/Store optimizer to combine more things.

I've extended the load/store optimizer to be able to produce dwordx3
loads and stores, This change allows many more load/stores to be combined,
and results in much more optimal code for our hardware.

Differential Revision: https://reviews.llvm.org/D54042