ixgbe: Avoid a signed shift while assembling the PHY ID
The PHY identifier word is promoted to signed int when the cast is
applied after the shift. Cast the 16-bit register value first so
identifiers with their high bit set are assembled as unsigned data.
(cherry picked from commit f4bf1da7bac80cbe3ec862f395c22a3c5d176312)
igc: Avoid a signed shift while assembling the PHY ID
The PHY identifier word is promoted to signed int when the cast is
applied after the shift. Cast the 16-bit register value first so
identifiers with their high bit set are assembled as unsigned data.
(cherry picked from commit f5fd839fe688181e57171850ce51e4dec71e62fd)
e1000: Avoid signed shifts while assembling PHY IDs
PHY identifier words are promoted to signed int when the cast is applied
after the shift. Cast each 16-bit register value first so identifiers
with their high bit set are assembled as unsigned data.
(cherry picked from commit 13a7470096567480676e24545b3c1d6404f3f2ec)
igc: Export EEE Low Power Idle counters
The driver already accumulates the clear-on-read transmit and receive
LPI event counters. Expose the 64-bit totals under the per-device eee
sysctl node.
(cherry picked from commit 13d78e4b9d0a27128319a1241f00f7ab9aa864bb)
ixl: Avoid a signed PHY capability shift
The PHY capability display examines all 32 bits of the firmware bitmap.
Use an unsigned value so examining bit 31 does not shift a signed
integer into its sign bit.
(cherry picked from commit f7427f890c7f34d0842a35eb9df814adad11a95a)
e1000: Avoid a signed manageability VLAN bitmap shift
A manageability VLAN can select bit 31 of its VFTA register. Use an
unsigned value when constructing the register mask.
(cherry picked from commit 392fbdcf2232f12cb973d00ae931740c72d970c6)
ixgbe: Use unsigned register bitmap shifts
VLAN, VMDq, and VF reset bit indices can reach 31. Use unsigned
values when constructing their 32-bit register masks so the shifts do
not operate on signed integers.
(cherry picked from commit bf6feffef6c16559333048859b24547acea3dba5)
ixgbe: Avoid signed overflow in LED register masks
LED index three shifts the blink bit into bit 31. Convert the base to
the register width before shifting so the operation is unsigned.
This is the ixgbe counterpart of the e1000 correction imported from
DPDK commit 214cb0d7f1.
(cherry picked from commit bbdd3c4692e2869817f77c359b4a2719e716921d)
ixgbe: Avoid a signed shift while assembling the PBA number
The EEPROM word is promoted to signed int before the left shift when
the cast is applied to the complete expression. Cast the word first so
all 16-bit values are shifted as unsigned data.
This is the ixgbe counterpart of the e1000 correction imported from
DPDK commit b932270c66.
(cherry picked from commit baa6e3af8525244e65a404fa13306fbca7feae9c)
igc: Check PHY control register reads
Do not modify a zero-initialized PHY control value when its preceding
read failed. Leave the PHY unchanged when the void power helpers cannot
read its current state.
This follows the defensive checks added to the corresponding e1000
helpers.
(cherry picked from commit 1121aaa0758baf04bed6f16d4157116b49c25000)
igc: fix data type in MAC hash
DPDK commit message
net/e1000/base: fix data type in MAC hash
One of the bit shifts in MAC hash calculation triggers a static analysis
warning about a potential overflow. Fix the data type to avoid this.
Fixes: af75078fece3 ("first public release")
Cc: stable at dpdk.org
Signed-off-by: Barbara Skobiej <barbara.skobiej at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
Obtained from: DPDK (458734aaac)
(cherry picked from commit 3fc1786aa2a3f590453abb6ea2351a12e19f6b45)
igc: fix MAC address hash bit shift
DPDK commit message
net/e1000/base: fix MAC address hash bit shift
In e1000_hash_mc_addr_generic() the expression:
"mc_addr[4] >> 8 - bit_shift", right shifting "mc_addr[4]"
shift by more than 7 bits always yields zero, so hash becomes not so
different. Add initialization with bit_shift = 1, and add a loop
condition to ensure bit_shift will be always in [1..8] range.
Fixes: af75078fece3 ("first public release")
Cc: stable at dpdk.org
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
[5 lines not shown]
igc: fix iterator type
DPDK commit message
net/e1000/base: fix iterator type
Fix static analysis warning about comparison between types of
incompatible width, which might lead to an infinite loop due to
overflow.
Fixes: af75078fece3 ("first public release")
Cc: stable at dpdk.org
Signed-off-by: Amir Avivi <amir.avivi at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
Obtained from: DPDK (3d36053991)
(cherry picked from commit 5587cb18b168f57a4d68c7e58ec660ab2a5ce4da)
ixgbe: Avoid a signed multicast bitmap shift
The multicast vector bit can be 31. Use an unsigned value so setting
the bit cannot shift a signed integer into its sign bit.
(cherry picked from commit 8704d29c6cc86f0780dff3d3d17d744106776ad3)
igc: Avoid a signed multicast bitmap shift
The multicast hash bit can be 31. Use an unsigned value so setting the
bit cannot shift a signed integer into its sign bit.
(cherry picked from commit 275ca86f6abffc4ee6e52a6daab06f5e5c21aa05)
e1000: Verify i210 and i211 multicast table writes
The i210 and i211 can occasionally fail to accept multicast table
writes, particularly while addresses are added and removed rapidly.
Read the table back and rewrite mismatches for up to three passes.
This prevents multicast reception from retaining stale filter state
while keeping the workaround limited to the affected controllers.
(cherry picked from commit bb8d0944b5d53863f00492b69b7bf13d2618fc95)
e1000: Avoid a signed multicast bitmap shift
The multicast hash bit can be 31. Use an unsigned value so setting the
bit cannot shift a signed integer into its sign bit.
(cherry picked from commit a86d65b2c99bab3fe46389b3b51ad27956dccfe9)
e1000: fix data type in MAC hash
DPDK commit message
net/e1000/base: fix data type in MAC hash
One of the bit shifts in MAC hash calculation triggers a static analysis
warning about a potential overflow. Fix the data type to avoid this.
Fixes: af75078fece3 ("first public release")
Cc: stable at dpdk.org
Signed-off-by: Barbara Skobiej <barbara.skobiej at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
Obtained from: DPDK (458734aaac)
(cherry picked from commit a09034d561cbb3792ecc0146b41d4794ab3bda37)
e1000: fix MAC address hash bit shift
DPDK commit message
net/e1000/base: fix MAC address hash bit shift
In e1000_hash_mc_addr_generic() the expression:
"mc_addr[4] >> 8 - bit_shift", right shifting "mc_addr[4]"
shift by more than 7 bits always yields zero, so hash becomes not so
different. Add initialization with bit_shift = 1, and add a loop
condition to ensure bit_shift will be always in [1..8] range.
Fixes: af75078fece3 ("first public release")
Cc: stable at dpdk.org
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
[5 lines not shown]
e1000: fix reset for 82580
DPDK commit message
net/e1000/base: fix reset for 82580
Fix setting device reset status bit in e1000_reset_hw_82580() function
for 82580 by first reading the register value, and then setting the
device reset bit.
Fixes: af75078fece3 ("first public release")
Cc: stable at dpdk.org
Signed-off-by: Barbara Skobiej <barbara.skobiej at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
Obtained from: DPDK (88a1eb79ef)
(cherry picked from commit 53e4711616041a668ab61f2ce86c9fa139ab67a9)
e1000: add LPI counters
DPDK commit message
net/e1000/base: add LPI counters
Add new fields in structure to indicate if EEE LPI entries have been
observed on Tx and Rx path.
Signed-off-by: Sasha Neftin <sasha.neftin at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
Obtained from: DPDK (2e8078ee69)
(cherry picked from commit d1c20195c0fae27b6b1d526c03d8844f200e5c86)
e1000: fix unchecked return
DPDK commit message
net/e1000/base: fix unchecked return
Static analysis has detected a write that is not checked for errors,
leading to ignored error return value. Add a check.
Fixes: edcdb3c5f71b ("e1000/base: fix link flap on 82579")
Cc: stable at dpdk.org
Signed-off-by: Dima Ruinskiy <dima.ruinskiy at intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
Obtained from: DPDK (b0b6b50c20)
(cherry picked from commit c80aface0f4662c7dc46eed3fbb27b64ab931500)
e1000: Check PHY control register reads
Do not modify a zero-initialized PHY control value when its preceding
read failed.
(cherry picked from commit c276a80a4e52c065ed631e498ed2c3d284b45c75)
e1000: Allow more time for PCH ULP exit
Firmware may take up to one second to unconfigure ULP, and affected
Lenovo systems have required nearly two seconds. Allow 2.5 seconds
before treating the transition as a PHY failure.
This extends DPDK commit 7aa4c34581a5 using the field-tested bound
from Linux commit 3cf31b1a9eff.
(cherry picked from commit e49cb7f757f6db8976b0d247e6a897eab5867634)
