Linux/linux eb7c825. MAINTAINERS, Documentation/devicetree/bindings/riscv cpus.yaml sifive.yaml

Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
 "This contains fixes, defconfig, and DT data changes for the v5.2-rc
  series.

  The fixes are relatively straightforward:

   - Addition of a TLB fence in the vmalloc_fault path, so the CPU
     doesn't enter an infinite page fault loop

   - Readdition of the pm_power_off export, so device drivers that
     reassign it can now be built as modules

   - A udelay() fix for RV32, fixing a miscomputation of the delay time

   - Removal of deprecated smp_mb__*() barriers

  This also adds initial DT data infrastructure for arch/riscv, along
  with initial data for the SiFive FU540-C000 SoC and the corresponding
  HiFive Unleashed board.

  We also update the RV64 defconfig to include some core drivers for the
  FU540 in the build"

* tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: remove unused barrier defines
  riscv: mm: synchronize MMU after pte change
  riscv: dts: add initial board data for the SiFive HiFive Unleashed
  riscv: dts: add initial support for the SiFive FU540-C000 SoC
  dt-bindings: riscv: convert cpu binding to json-schema
  dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
  arch: riscv: add support for building DTB files from DT source data
  riscv: Fix udelay in RV32.
  riscv: export pm_power_off again
  RISC-V: defconfig: enable clocks, serial console
DeltaFile
+215-0arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+168-0Documentation/devicetree/bindings/riscv/cpus.yaml
+65-0arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+25-0Documentation/devicetree/bindings/riscv/sifive.yaml
+13-0arch/riscv/mm/fault.c
+9-0MAINTAINERS
+0-5arch/riscv/include/asm/bitops.h
+4-0arch/riscv/configs/defconfig
+2-0arch/riscv/boot/dts/Makefile
+1-1arch/riscv/lib/delay.c
+2-0arch/riscv/boot/dts/sifive/Makefile
+1-0arch/riscv/kernel/reset.c
+505-612 files

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